1 #include "platform.h"
2
3 struct platform platforms[] = {
4 {
5 // item 0
6 CS_ARCH_X86,
7 CS_MODE_32,
8 "X86 32 (Intel syntax)",
9 "x32"
10 },
11 {
12 // item 1
13 CS_ARCH_X86,
14 CS_MODE_64,
15 "X86 64 (Intel syntax)",
16 "x64"
17 },
18 {
19 // item 2
20 CS_ARCH_ARM,
21 CS_MODE_ARM,
22 "ARM",
23 "arm"
24 },
25 {
26 // item 3
27 CS_ARCH_ARM,
28 CS_MODE_THUMB,
29 "THUMB",
30 "thumb"
31 },
32 {
33 // item 4
34 CS_ARCH_ARM,
35 (cs_mode)(CS_MODE_ARM + CS_MODE_V8),
36 "Arm-V8",
37 "armv8"
38 },
39 {
40 // item 5
41 CS_ARCH_ARM,
42 (cs_mode)(CS_MODE_THUMB+CS_MODE_V8),
43 "THUMB+V8",
44 "thumbv8"
45 },
46 {
47 // item 6
48 CS_ARCH_ARM,
49 (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
50 "Thumb-MClass",
51 "cortexm"
52 },
53 {
54 // item 7
55 CS_ARCH_ARM64,
56 (cs_mode)0,
57 "ARM-64",
58 "arm64"
59 },
60 {
61 // item 8
62 CS_ARCH_MIPS,
63 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
64 "MIPS-32 (Big-endian)",
65 "mipsbe"
66 },
67 {
68 // item 9
69 CS_ARCH_MIPS,
70 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO),
71 "MIPS-32 (micro)",
72 "mipsmicro"
73 },
74 {
75 //item 10
76 CS_ARCH_MIPS,
77 CS_MODE_MIPS64,
78 "MIPS-64-EL (Little-endian)",
79 "mips64"
80 },
81 {
82 //item 11
83 CS_ARCH_MIPS,
84 CS_MODE_MIPS32,
85 "MIPS-32-EL (Little-endian)",
86 "mips"
87 },
88 {
89 //item 12
90 CS_ARCH_MIPS,
91 (cs_mode)(CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN),
92 "MIPS-64 (Big-endian)",
93 "mips64be"
94 },
95 {
96 //item 13
97 CS_ARCH_MIPS,
98 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
99 "MIPS-32 | Micro (Big-endian)",
100 "mipsbemicro"
101 },
102 {
103 //item 14
104 CS_ARCH_PPC,
105 CS_MODE_64 | CS_MODE_BIG_ENDIAN,
106 "PPC-64",
107 "ppc64be"
108 },
109 {
110 //item 15
111 CS_ARCH_SPARC,
112 CS_MODE_BIG_ENDIAN,
113 "Sparc",
114 "sparc"
115 },
116 {
117 //item 16
118 CS_ARCH_SPARC,
119 (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
120 "SparcV9",
121 "sparcv9"
122 },
123 {
124 //item 17
125 CS_ARCH_SYSZ,
126 (cs_mode)0,
127 "SystemZ",
128 "systemz"
129 },
130 {
131 //item 18
132 CS_ARCH_XCORE,
133 (cs_mode)0,
134 "XCore",
135 "xcore"
136 },
137 {
138 //item 19
139 CS_ARCH_MIPS,
140 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
141 "MIPS-32R6 (Big-endian)",
142 "mipsbe32r6"
143 },
144 {
145 //item 20
146 CS_ARCH_MIPS,
147 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
148 "MIPS-32R6 (Micro+Big-endian)",
149 "mipsbe32r6micro"
150 },
151 {
152 //item 21
153 CS_ARCH_MIPS,
154 CS_MODE_MIPS32R6,
155 "MIPS-32R6 (Little-endian)",
156 "mips32r6"
157 },
158 {
159 //item 22
160 CS_ARCH_MIPS,
161 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO),
162 "MIPS-32R6 (Micro+Little-endian)",
163 "mips32r6micro"
164 },
165 {
166 //item 23
167 CS_ARCH_M68K,
168 (cs_mode)0,
169 "M68K",
170 "m68k"
171 },
172 {
173 //item 24
174 CS_ARCH_M680X,
175 (cs_mode)CS_MODE_M680X_6809,
176 "M680X_M6809",
177 "m6809"
178 },
179 {
180 //item 25
181 CS_ARCH_EVM,
182 (cs_mode)0,
183 "EVM",
184 "evm"
185 },
186 {
187 //item 26
188 CS_ARCH_MOS65XX,
189 (cs_mode)0,
190 "MOS65XX",
191 "mos65xx"
192 },
193 {
194 //item 27
195 CS_ARCH_TMS320C64X,
196 CS_MODE_BIG_ENDIAN,
197 "tms320c64x",
198 "tms320c64x"
199 },
200 {
201 //item 28
202 CS_ARCH_WASM,
203 (cs_mode)0,
204 "WASM",
205 "wasm"
206 },
207 {
208 //item 29
209 CS_ARCH_BPF,
210 CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC,
211 "cBPF",
212 "bpf"
213 },
214 {
215 //item 30
216 CS_ARCH_BPF,
217 CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
218 "eBPF",
219 "ebpf"
220 },
221 {
222 //item 31
223 CS_ARCH_BPF,
224 CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC,
225 "cBPF",
226 "bpfbe"
227 },
228 {
229 //item 32
230 CS_ARCH_BPF,
231 CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED,
232 "eBPF",
233 "ebpfbe"
234 },
235 {
236 // item 33
237 CS_ARCH_X86,
238 CS_MODE_16,
239 "X86 16 (Intel syntax)",
240 "x16"
241 },
242 {
243 // item 34
244 CS_ARCH_M68K,
245 CS_MODE_M68K_040,
246 "M68K mode 40",
247 "m68k40"
248 },
249 {
250 //item 35
251 CS_ARCH_M680X,
252 (cs_mode)CS_MODE_M680X_6800,
253 "M680X_M6800",
254 "m6800"
255 },
256 {
257 //item 36
258 CS_ARCH_M680X,
259 (cs_mode)CS_MODE_M680X_6801,
260 "M680X_M6801",
261 "m6801"
262 },
263 {
264 //item 37
265 CS_ARCH_M680X,
266 (cs_mode)CS_MODE_M680X_6805,
267 "M680X_M6805",
268 "m6805"
269 },
270 {
271 //item 38
272 CS_ARCH_M680X,
273 (cs_mode)CS_MODE_M680X_6808,
274 "M680X_M6808",
275 "m6808"
276 },
277 {
278 //item 39
279 CS_ARCH_M680X,
280 (cs_mode)CS_MODE_M680X_6811,
281 "M680X_M6811",
282 "m6811"
283 },
284 {
285 //item 40
286 CS_ARCH_M680X,
287 (cs_mode)CS_MODE_M680X_CPU12,
288 "M680X_cpu12",
289 "cpu12"
290 },
291 {
292 //item 41
293 CS_ARCH_M680X,
294 (cs_mode)CS_MODE_M680X_6301,
295 "M680X_M6808",
296 "hd6301"
297 },
298 {
299 //item 42
300 CS_ARCH_M680X,
301 (cs_mode)CS_MODE_M680X_6309,
302 "M680X_M6808",
303 "hd6309"
304 },
305 {
306 //item 43
307 CS_ARCH_M680X,
308 (cs_mode)CS_MODE_M680X_HCS08,
309 "M680X_M6808",
310 "hcs08"
311 },
312 {
313 //item 44
314 CS_ARCH_RISCV,
315 CS_MODE_RISCV32,
316 "RISCV",
317 "riscv32"
318 },
319 {
320 //item 45
321 CS_ARCH_RISCV,
322 CS_MODE_RISCV64,
323 "RISCV",
324 "riscv64"
325 },
326 {
327 //item 46
328 CS_ARCH_PPC,
329 CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX,
330 "ppc+qpx",
331 "ppc64beqpx"
332 },
333
334 // dummy entry to mark the end of this array.
335 // DO NOT DELETE THIS
336 {
337 0,
338 0,
339 NULL,
340 NULL,
341 },
342 };
343
344 // get length of platforms[]
platform_len(void)345 unsigned int platform_len(void)
346 {
347 unsigned int c;
348
349 for(c = 0; platforms[c].cstoolname; c++);
350
351 return c;
352 }
353
354 // get platform entry encoded n (first byte for input data of OSS fuzz)
get_platform_entry(uint8_t n)355 unsigned int get_platform_entry(uint8_t n)
356 {
357 return n % platform_len();
358 }
359
360 // get cstoolname from encoded n (first byte for input data of OSS fuzz)
get_platform_cstoolname(uint8_t n)361 const char *get_platform_cstoolname(uint8_t n)
362 {
363 return platforms[get_platform_entry(n)].cstoolname;
364 }
365
366