1//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the instructions that make up the Intel TSX instruction
11// set.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// TSX instructions
17
18def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
19                     [SDNPHasChain, SDNPSideEffect]>;
20
21let SchedRW = [WriteSystem] in {
22
23//let usesCustomInserter = 1 in
24//def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
25//               "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
26//             Requires<[HasRTM]>;
27
28let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
29def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst),
30                         "xbegin\t$dst", []>, OpSize16;
31def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst),
32                         "xbegin\t$dst", []>, OpSize32;
33}
34
35// Psuedo instruction to fake the definition of EAX on the fallback code path.
36//let isPseudo = 1, Defs = [EAX] in {
37//def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>;
38//}
39
40def XEND : I<0x01, MRM_D5, (outs), (ins),
41             "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
42
43let Defs = [EFLAGS] in
44def XTEST : I<0x01, MRM_D6, (outs), (ins),
45              "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasRTM]>;
46
47def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
48                 "xabort\t$imm",
49                 [(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;
50} // SchedRW
51
52// HLE prefixes
53let SchedRW = [WriteSystem] in {
54
55let isAsmParserOnly = 1 in {
56def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>;
57def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>;
58}
59
60} // SchedRW
61