1 #ifndef _INTELXVF_H 2 #define _INTELXVF_H 3 4 /** @file 5 * 6 * Intel 10 Gigabit Ethernet virtual function network card driver 7 * 8 */ 9 10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); 11 12 #include "intelvf.h" 13 14 /** Control Register */ 15 #define INTELXVF_CTRL 0x0000UL 16 #define INTELXVF_CTRL_RST 0x04000000UL /**< Function-level reset */ 17 18 /** Link Status Register */ 19 #define INTELXVF_LINKS 0x0010UL 20 #define INTELXVF_LINKS_UP 0x40000000UL /**< Link up */ 21 22 /** Extended Interrupt Cause Read Register */ 23 #define INTELXVF_EICR 0x0100UL 24 #define INTELXVF_EIRQ_RX0 0x00000001UL /**< RX queue 0 (via IVAR) */ 25 #define INTELXVF_EIRQ_TX0 0x00000002UL /**< TX queue 0 (via IVAR) */ 26 #define INTELXVF_EIRQ_MBOX 0x00000004UL /**< Mailbox (via IVARM) */ 27 28 /** Extended Interrupt Mask Set/Read Register */ 29 #define INTELXVF_EIMS 0x0108UL 30 31 /** Extended Interrupt Mask Clear Register */ 32 #define INTELXVF_EIMC 0x010cUL 33 34 /** Interrupt Vector Allocation Register */ 35 #define INTELXVF_IVAR 0x0120UL 36 #define INTELXVF_IVAR_RX0(bit) ( (bit) << 0 ) /**< RX queue 0 allocation */ 37 #define INTELXVF_IVAR_RX0_DEFAULT INTELXVF_IVAR_RX0 ( 0x00 ) 38 #define INTELXVF_IVAR_RX0_MASK INTELXVF_IVAR_RX0 ( 0x01 ) 39 #define INTELXVF_IVAR_RX0_VALID 0x00000080UL /**< RX queue 0 valid */ 40 #define INTELXVF_IVAR_TX0(bit) ( (bit) << 8 ) /**< TX queue 0 allocation */ 41 #define INTELXVF_IVAR_TX0_DEFAULT INTELXVF_IVAR_TX0 ( 0x01 ) 42 #define INTELXVF_IVAR_TX0_MASK INTELXVF_IVAR_TX0 ( 0x01 ) 43 #define INTELXVF_IVAR_TX0_VALID 0x00008000UL /**< TX queue 0 valid */ 44 45 /** Interrupt Vector Allocation Miscellaneous Register */ 46 #define INTELXVF_IVARM 0x0140UL 47 #define INTELXVF_IVARM_MBOX(bit) ( (bit) << 0 ) /**< Mailbox allocation */ 48 #define INTELXVF_IVARM_MBOX_DEFAULT INTELXVF_IVARM_MBOX ( 0x02 ) 49 #define INTELXVF_IVARM_MBOX_MASK INTELXVF_IVARM_MBOX ( 0x03 ) 50 #define INTELXVF_IVARM_MBOX_VALID 0x00000080UL /**< Mailbox valid */ 51 52 /** Mailbox Memory Register Base */ 53 #define INTELXVF_MBMEM 0x0200UL 54 55 /** Mailbox Control Register */ 56 #define INTELXVF_MBCTRL 0x02fcUL 57 58 /** Packet Split Receive Type */ 59 #define INTELXVF_PSRTYPE 0x0300UL 60 61 /** Receive Descriptor register block */ 62 #define INTELXVF_RD(n) ( 0x1000UL + ( 0x40 * (n) ) ) 63 64 /** RX DCA Control Register */ 65 #define INTELXVF_DCA_RXCTRL 0x100cUL 66 #define INTELXVF_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL /**< Must be zero */ 67 68 /** Split Receive Control Register */ 69 #define INTELXVF_SRRCTL 0x1014UL 70 #define INTELXVF_SRRCTL_BSIZE(kb) ( (kb) << 0 ) /**< Receive buffer size */ 71 #define INTELXVF_SRRCTL_BSIZE_DEFAULT INTELXVF_SRRCTL_BSIZE ( 0x02 ) 72 #define INTELXVF_SRRCTL_BSIZE_MASK INTELXVF_SRRCTL_BSIZE ( 0x1f ) 73 #define INTELXVF_SRRCTL_BHDRSIZE(kb) ( (kb) << 8 ) /**< Header size */ 74 #define INTELXVF_SRRCTL_BHDRSIZE_DEFAULT INTELXVF_SRRCTL_BHDRSIZE ( 0x04 ) 75 #define INTELXVF_SRRCTL_BHDRSIZE_MASK INTELXVF_SRRCTL_BHDRSIZE ( 0x0f ) 76 #define INTELXVF_SRRCTL_DESCTYPE(typ) ( (typ) << 25 ) /**< Descriptor type */ 77 #define INTELXVF_SRRCTL_DESCTYPE_DEFAULT INTELXVF_SRRCTL_DESCTYPE ( 0x00 ) 78 #define INTELXVF_SRRCTL_DESCTYPE_MASK INTELXVF_SRRCTL_DESCTYPE ( 0x07 ) 79 #define INTELXVF_SRRCTL_DROP_EN 0x10000000UL 80 81 /** Good Packets Received Count */ 82 #define INTELXVF_GPRC 0x101c 83 84 /** Good Packets Received Count Low */ 85 #define INTELXVF_GORCL 0x1020 86 87 /** Good Packets Received Count High */ 88 #define INTELXVF_GORCH 0x1024 89 90 /* Multicast Packets Received Count */ 91 #define INTELXVF_MPRC 0x1034 92 93 /** Transmit Descriptor register block */ 94 #define INTELXVF_TD(n) ( 0x2000UL + ( 0x40 * (n) ) ) 95 96 /** Good Packets Transmitted Count */ 97 #define INTELXVF_GPTC 0x201c 98 99 /** Good Packets Transmitted Count Low */ 100 #define INTELXVF_GOTCL 0x2020 101 102 /** Good Packets Transmitted Count High */ 103 #define INTELXVF_GOTCH 0x2024 104 105 /** Negotiate API version mailbox message */ 106 #define INTELXVF_MSG_TYPE_VERSION 0x00000008UL 107 108 /** API version 1.1 */ 109 #define INTELXVF_MSG_VERSION_1_1 0x00000002UL 110 111 /** Number of queues */ 112 #define INTELXVF_NUM_RINGS 8 113 114 #endif /* _INTELXVF_H */ 115