1 /**************************************************************************
2 *
3 * tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
4 * Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301, USA.
20 *
21 * Portions of this code based on:
22 * lan.c: Linux ThunderLan Driver:
23 *
24 * by James Banks
25 *
26 * (C) 1997-1998 Caldera, Inc.
27 * (C) 1998 James Banks
28 * (C) 1999-2001 Torben Mathiasen
29 * (C) 2002 Samuel Chessman
30 *
31 * REVISION HISTORY:
32 * ================
33 * v1.0 07-08-2003 timlegge Initial not quite working version
34 * v1.1 07-27-2003 timlegge Sync 5.0 and 5.1 versions
35 * v1.2 08-19-2003 timlegge Implement Multicast Support
36 * v1.3 08-23-2003 timlegge Fix the transmit Function
37 * v1.4 01-17-2004 timlegge Initial driver output cleanup
38 *
39 * Indent Options: indent -kr -i8
40 ***************************************************************************/
41
42 FILE_LICENCE ( GPL2_OR_LATER );
43
44 #include "etherboot.h"
45 #include "nic.h"
46 #include <ipxe/pci.h>
47 #include <ipxe/ethernet.h>
48 #include <mii.h>
49 #include "tlan.h"
50
51 #define drv_version "v1.4"
52 #define drv_date "01-17-2004"
53
54 /* NIC specific static variables go here */
55 #define HZ 100
56 #define TX_TIME_OUT (6*HZ)
57
58 /* Condensed operations for readability. */
59 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
60 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
61
62 static void TLan_ResetLists(struct nic *nic __unused);
63 static void TLan_ResetAdapter(struct nic *nic __unused);
64 static void TLan_FinishReset(struct nic *nic __unused);
65
66 static void TLan_EeSendStart(u16);
67 static int TLan_EeSendByte(u16, u8, int);
68 static void TLan_EeReceiveByte(u16, u8 *, int);
69 static int TLan_EeReadByte(u16 io_base, u8, u8 *);
70
71 static void TLan_PhyDetect(struct nic *nic);
72 static void TLan_PhyPowerDown(struct nic *nic);
73 static void TLan_PhyPowerUp(struct nic *nic);
74
75
76 static void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac);
77
78 static void TLan_PhyReset(struct nic *nic);
79 static void TLan_PhyStartLink(struct nic *nic);
80 static void TLan_PhyFinishAutoNeg(struct nic *nic);
81
82 #ifdef MONITOR
83 static void TLan_PhyMonitor(struct nic *nic);
84 #endif
85
86
87 static void refill_rx(struct nic *nic __unused);
88
89 static int TLan_MiiReadReg(struct nic *nic __unused, u16, u16, u16 *);
90 static void TLan_MiiSendData(u16, u32, unsigned);
91 static void TLan_MiiSync(u16);
92 static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16);
93
94
95 static const char *media[] = {
96 "10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
97 "100baseTx-FD", "100baseT4", NULL
98 };
99
100 /* This much match tlan_pci_tbl[]! */
101 enum tlan_nics {
102 NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
103 4, NETEL100PI = 5,
104 NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
105 10, NETELLIGENT_10_100_WS_5100 = 11,
106 NETELLIGENT_10_T2 = 12
107 };
108
109 struct pci_id_info {
110 const char *name;
111 int nic_id;
112 struct match_info {
113 u32 pci, pci_mask, subsystem, subsystem_mask;
114 u32 revision, revision_mask; /* Only 8 bits. */
115 } id;
116 u32 flags;
117 u16 addrOfs; /* Address Offset */
118 };
119
120 static const struct pci_id_info tlan_pci_tbl[] = {
121 {"Compaq Netelligent 10 T PCI UTP", NETEL10,
122 {0xae340e11, 0xffffffff, 0, 0, 0, 0},
123 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
124 {"Compaq Netelligent 10/100 TX PCI UTP", NETEL100,
125 {0xae320e11, 0xffffffff, 0, 0, 0, 0},
126 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
127 {"Compaq Integrated NetFlex-3/P", NETFLEX3I,
128 {0xae350e11, 0xffffffff, 0, 0, 0, 0},
129 TLAN_ADAPTER_NONE, 0x83},
130 {"Compaq NetFlex-3/P", THUNDER,
131 {0xf1300e11, 0xffffffff, 0, 0, 0, 0},
132 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
133 {"Compaq NetFlex-3/P", NETFLEX3B,
134 {0xf1500e11, 0xffffffff, 0, 0, 0, 0},
135 TLAN_ADAPTER_NONE, 0x83},
136 {"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI,
137 {0xae430e11, 0xffffffff, 0, 0, 0, 0},
138 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
139 {"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D,
140 {0xae400e11, 0xffffffff, 0, 0, 0, 0},
141 TLAN_ADAPTER_NONE, 0x83},
142 {"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I,
143 {0xb0110e11, 0xffffffff, 0, 0, 0, 0},
144 TLAN_ADAPTER_NONE, 0x83},
145 {"Olicom OC-2183/2185", OC2183,
146 {0x0013108d, 0xffffffff, 0, 0, 0, 0},
147 TLAN_ADAPTER_USE_INTERN_10, 0x83},
148 {"Olicom OC-2325", OC2325,
149 {0x0012108d, 0xffffffff, 0, 0, 0, 0},
150 TLAN_ADAPTER_UNMANAGED_PHY, 0xF8},
151 {"Olicom OC-2326", OC2326,
152 {0x0014108d, 0xffffffff, 0, 0, 0, 0},
153 TLAN_ADAPTER_USE_INTERN_10, 0xF8},
154 {"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100,
155 {0xb0300e11, 0xffffffff, 0, 0, 0, 0},
156 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
157 {"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2,
158 {0xb0120e11, 0xffffffff, 0, 0, 0, 0},
159 TLAN_ADAPTER_NONE, 0x83},
160 {"Compaq NetFlex-3/E", 0, /* EISA card */
161 {0, 0, 0, 0, 0, 0},
162 TLAN_ADAPTER_ACTIVITY_LED | TLAN_ADAPTER_UNMANAGED_PHY |
163 TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
164 {"Compaq NetFlex-3/E", 0, /* EISA card */
165 {0, 0, 0, 0, 0, 0},
166 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
167 {NULL, 0,
168 {0, 0, 0, 0, 0, 0},
169 0, 0},
170 };
171
172 struct TLanList {
173 u32 forward;
174 u16 cStat;
175 u16 frameSize;
176 struct {
177 u32 count;
178 u32 address;
179 } buffer[TLAN_BUFFERS_PER_LIST];
180 };
181
182 struct {
183 struct TLanList tx_ring[TLAN_NUM_TX_LISTS];
184 unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS];
185 struct TLanList rx_ring[TLAN_NUM_RX_LISTS];
186 unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS];
187 } tlan_buffers __shared;
188 #define tx_ring tlan_buffers.tx_ring
189 #define txb tlan_buffers.txb
190 #define rx_ring tlan_buffers.rx_ring
191 #define rxb tlan_buffers.rxb
192
193 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
194
195 static int chip_idx;
196
197 /*****************************************************************
198 * TLAN Private Information Structure
199 *
200 ****************************************************************/
201 static struct tlan_private {
202 unsigned short vendor_id; /* PCI Vendor code */
203 unsigned short dev_id; /* PCI Device code */
204 const char *nic_name;
205 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
206 unsigned rx_buf_sz; /* Based on mtu + Slack */
207 struct TLanList *txList;
208 u32 txHead;
209 u32 txInProgress;
210 u32 txTail;
211 int eoc;
212 u32 phyOnline;
213 u32 aui;
214 u32 duplex;
215 u32 phy[2];
216 u32 phyNum;
217 u32 speed;
218 u8 tlanRev;
219 u8 tlanFullDuplex;
220 u8 link;
221 u8 neg_be_verbose;
222 } TLanPrivateInfo;
223
224 static struct tlan_private *priv;
225
226 static u32 BASE;
227
228 /***************************************************************
229 * TLan_ResetLists
230 *
231 * Returns:
232 * Nothing
233 * Parms:
234 * dev The device structure with the list
235 * stuctures to be reset.
236 *
237 * This routine sets the variables associated with managing
238 * the TLAN lists to their initial values.
239 *
240 **************************************************************/
241
TLan_ResetLists(struct nic * nic __unused)242 static void TLan_ResetLists(struct nic *nic __unused)
243 {
244
245 int i;
246 struct TLanList *list;
247 priv->txHead = 0;
248 priv->txTail = 0;
249
250 for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
251 list = &tx_ring[i];
252 list->cStat = TLAN_CSTAT_UNUSED;
253 list->buffer[0].address = virt_to_bus(txb +
254 (i * TLAN_MAX_FRAME_SIZE));
255 list->buffer[2].count = 0;
256 list->buffer[2].address = 0;
257 list->buffer[9].address = 0;
258 }
259
260 priv->cur_rx = 0;
261 priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
262 // priv->rx_head_desc = &rx_ring[0];
263
264 /* Initialize all the Rx descriptors */
265 for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
266 rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
267 rx_ring[i].cStat = TLAN_CSTAT_READY;
268 rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
269 rx_ring[i].buffer[0].count =
270 TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
271 rx_ring[i].buffer[0].address =
272 virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
273 rx_ring[i].buffer[1].count = 0;
274 rx_ring[i].buffer[1].address = 0;
275 }
276
277 /* Mark the last entry as wrapping the ring */
278 rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
279 priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
280
281 } /* TLan_ResetLists */
282
283 /***************************************************************
284 * TLan_Reset
285 *
286 * Returns:
287 * 0
288 * Parms:
289 * dev Pointer to device structure of adapter
290 * to be reset.
291 *
292 * This function resets the adapter and it's physical
293 * device. See Chap. 3, pp. 9-10 of the "ThunderLAN
294 * Programmer's Guide" for details. The routine tries to
295 * implement what is detailed there, though adjustments
296 * have been made.
297 *
298 **************************************************************/
299
TLan_ResetAdapter(struct nic * nic __unused)300 void TLan_ResetAdapter(struct nic *nic __unused)
301 {
302 int i;
303 u32 addr;
304 u32 data;
305 u8 data8;
306
307 priv->tlanFullDuplex = FALSE;
308 priv->phyOnline = 0;
309 /* 1. Assert reset bit. */
310
311 data = inl(BASE + TLAN_HOST_CMD);
312 data |= TLAN_HC_AD_RST;
313 outl(data, BASE + TLAN_HOST_CMD);
314
315 udelay(1000);
316
317 /* 2. Turn off interrupts. ( Probably isn't necessary ) */
318
319 data = inl(BASE + TLAN_HOST_CMD);
320 data |= TLAN_HC_INT_OFF;
321 outl(data, BASE + TLAN_HOST_CMD);
322 /* 3. Clear AREGs and HASHs. */
323
324 for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
325 TLan_DioWrite32(BASE, (u16) i, 0);
326 }
327
328 /* 4. Setup NetConfig register. */
329
330 data =
331 TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
332 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
333
334 /* 5. Load Ld_Tmr and Ld_Thr in HOST_CMD. */
335
336 outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
337 outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
338
339 /* 6. Unreset the MII by setting NMRST (in NetSio) to 1. */
340
341 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
342 addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
343 TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
344
345 /* 7. Setup the remaining registers. */
346
347 if (priv->tlanRev >= 0x30) {
348 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
349 TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
350 }
351 TLan_PhyDetect(nic);
352 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
353
354 if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
355 data |= TLAN_NET_CFG_BIT;
356 if (priv->aui == 1) {
357 TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
358 } else if (priv->duplex == TLAN_DUPLEX_FULL) {
359 TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
360 priv->tlanFullDuplex = TRUE;
361 } else {
362 TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
363 }
364 }
365
366 if (priv->phyNum == 0) {
367 data |= TLAN_NET_CFG_PHY_EN;
368 }
369 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
370
371 if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
372 TLan_FinishReset(nic);
373 } else {
374 TLan_PhyPowerDown(nic);
375 }
376
377 } /* TLan_ResetAdapter */
378
TLan_FinishReset(struct nic * nic)379 void TLan_FinishReset(struct nic *nic)
380 {
381
382 u8 data;
383 u32 phy;
384 u8 sio;
385 u16 status;
386 u16 partner;
387 u16 tlphy_ctl;
388 u16 tlphy_par;
389 u16 tlphy_id1, tlphy_id2;
390 int i;
391
392 phy = priv->phy[priv->phyNum];
393
394 data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
395 if (priv->tlanFullDuplex) {
396 data |= TLAN_NET_CMD_DUPLEX;
397 }
398 TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
399 data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
400 if (priv->phyNum == 0) {
401 data |= TLAN_NET_MASK_MASK7;
402 }
403 TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
404 TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
405 TLan_MiiReadReg(nic, phy, MII_PHYSID1, &tlphy_id1);
406 TLan_MiiReadReg(nic, phy, MII_PHYSID2, &tlphy_id2);
407
408 if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
409 || (priv->aui)) {
410 status = BMSR_LSTATUS;
411 DBG ( "TLAN: %s: Link forced.\n", priv->nic_name );
412 } else {
413 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
414 udelay(1000);
415 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
416 if ((status & BMSR_LSTATUS) && /* We only support link info on Nat.Sem. PHY's */
417 (tlphy_id1 == NAT_SEM_ID1)
418 && (tlphy_id2 == NAT_SEM_ID2)) {
419 TLan_MiiReadReg(nic, phy, MII_LPA, &partner);
420 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
421 &tlphy_par);
422
423 DBG ( "TLAN: %s: Link active with ",
424 priv->nic_name );
425 if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
426 DBG ( "forced 10%sMbps %s-Duplex\n",
427 tlphy_par & TLAN_PHY_SPEED_100 ? ""
428 : "0",
429 tlphy_par & TLAN_PHY_DUPLEX_FULL ?
430 "Full" : "Half" );
431 } else {
432 DBG
433 ( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
434 tlphy_par & TLAN_PHY_SPEED_100 ? "" :
435 "0",
436 tlphy_par & TLAN_PHY_DUPLEX_FULL ?
437 "Full" : "Half" );
438 DBG ( "TLAN: Partner capability: " );
439 for (i = 5; i <= 10; i++)
440 if (partner & (1 << i)) {
441 DBG ( "%s", media[i - 5] );
442 }
443 DBG ( "\n" );
444 }
445
446 TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
447 #ifdef MONITOR
448 /* We have link beat..for now anyway */
449 priv->link = 1;
450 /*Enabling link beat monitoring */
451 /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */
452 mdelay(10000);
453 TLan_PhyMonitor(nic);
454 #endif
455 } else if (status & BMSR_LSTATUS) {
456 DBG ( "TLAN: %s: Link active\n", priv->nic_name );
457 TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
458 }
459 }
460
461 if (priv->phyNum == 0) {
462 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
463 tlphy_ctl |= TLAN_TC_INTEN;
464 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
465 sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
466 sio |= TLAN_NET_SIO_MINTEN;
467 TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
468 }
469
470 if (status & BMSR_LSTATUS) {
471 TLan_SetMac(nic, 0, nic->node_addr);
472 priv->phyOnline = 1;
473 outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
474 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
475 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
476 } else {
477 DBG
478 ( "TLAN: %s: Link inactive, will retry in 10 secs...\n",
479 priv->nic_name );
480 /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */
481 mdelay(10000);
482 TLan_FinishReset(nic);
483 return;
484
485 }
486
487 } /* TLan_FinishReset */
488
489 /**************************************************************************
490 POLL - Wait for a frame
491 ***************************************************************************/
tlan_poll(struct nic * nic,int retrieve)492 static int tlan_poll(struct nic *nic, int retrieve)
493 {
494 /* return true if there's an ethernet packet ready to read */
495 /* nic->packet should contain data on return */
496 /* nic->packetlen should contain length of data */
497 u32 framesize;
498 u32 host_cmd = 0;
499 u32 ack = 1;
500 int eoc = 0;
501 int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
502 u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
503 u16 host_int = inw(BASE + TLAN_HOST_INT);
504
505 if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
506 return 1;
507
508 outw(host_int, BASE + TLAN_HOST_INT);
509
510 if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
511 return 0;
512
513 /* printf("PI-1: 0x%hX\n", host_int); */
514 if (tmpCStat & TLAN_CSTAT_EOC)
515 eoc = 1;
516
517 framesize = rx_ring[entry].frameSize;
518
519 nic->packetlen = framesize;
520
521 DBG ( ".%d.", (unsigned int) framesize );
522
523 memcpy(nic->packet, rxb +
524 (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
525
526 rx_ring[entry].cStat = 0;
527
528 DBG ( "%d", entry );
529
530 entry = (entry + 1) % TLAN_NUM_RX_LISTS;
531 priv->cur_rx = entry;
532 if (eoc) {
533 if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
534 TLAN_CSTAT_READY) {
535 ack |= TLAN_HC_GO | TLAN_HC_RT;
536 host_cmd = TLAN_HC_ACK | ack | 0x001C0000;
537 outl(host_cmd, BASE + TLAN_HOST_CMD);
538 }
539 } else {
540 host_cmd = TLAN_HC_ACK | ack | (0x000C0000);
541 outl(host_cmd, BASE + TLAN_HOST_CMD);
542
543 DBG ( "AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM) );
544 DBG ( "PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT) );
545 }
546 refill_rx(nic);
547 return (1); /* initially as this is called to flush the input */
548 }
549
refill_rx(struct nic * nic __unused)550 static void refill_rx(struct nic *nic __unused)
551 {
552 int entry = 0;
553
554 for (;
555 (priv->cur_rx - priv->dirty_rx +
556 TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
557 priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
558 entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
559 rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
560 rx_ring[entry].cStat = TLAN_CSTAT_READY;
561 }
562
563 }
564
565 /**************************************************************************
566 TRANSMIT - Transmit a frame
567 ***************************************************************************/
tlan_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)568 static void tlan_transmit(struct nic *nic, const char *d, /* Destination */
569 unsigned int t, /* Type */
570 unsigned int s, /* size */
571 const char *p)
572 { /* Packet */
573 u16 nstype;
574 u32 to;
575 struct TLanList *tail_list;
576 struct TLanList *head_list;
577 u8 *tail_buffer;
578 u32 ack = 0;
579 u32 host_cmd;
580 int eoc = 0;
581 u16 tmpCStat;
582 u16 host_int = inw(BASE + TLAN_HOST_INT);
583
584 int entry = 0;
585
586 DBG ( "INT0-0x%hX\n", host_int );
587
588 if (!priv->phyOnline) {
589 printf("TRANSMIT: %s PHY is not ready\n", priv->nic_name);
590 return;
591 }
592
593 tail_list = priv->txList + priv->txTail;
594
595 if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
596 printf("TRANSMIT: %s is busy (Head=%p Tail=%x)\n",
597 priv->nic_name, priv->txList, (unsigned int) priv->txTail);
598 tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
599 // priv->txBusyCount++;
600 return;
601 }
602
603 tail_list->forward = 0;
604
605 tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
606
607 /* send the packet to destination */
608 memcpy(tail_buffer, d, ETH_ALEN);
609 memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
610 nstype = htons((u16) t);
611 memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
612 memcpy(tail_buffer + ETH_HLEN, p, s);
613
614 s += ETH_HLEN;
615 s &= 0x0FFF;
616 while (s < ETH_ZLEN)
617 tail_buffer[s++] = '\0';
618
619 /*=====================================================*/
620 /* Receive
621 * 0000 0000 0001 1100
622 * 0000 0000 0000 1100
623 * 0000 0000 0000 0011 = 0x0003
624 *
625 * 0000 0000 0000 0000 0000 0000 0000 0011
626 * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
627 *
628 * Transmit
629 * 0000 0000 0001 1100
630 * 0000 0000 0000 0100
631 * 0000 0000 0000 0001 = 0x0001
632 *
633 * 0000 0000 0000 0000 0000 0000 0000 0001
634 * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
635 * */
636
637 /* Setup the transmit descriptor */
638 tail_list->frameSize = (u16) s;
639 tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s;
640 tail_list->buffer[1].count = 0;
641 tail_list->buffer[1].address = 0;
642
643 tail_list->cStat = TLAN_CSTAT_READY;
644
645 DBG ( "INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
646
647 if (!priv->txInProgress) {
648 priv->txInProgress = 1;
649 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
650 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
651 } else {
652 if (priv->txTail == 0) {
653 DBG ( "Out buffer\n" );
654 (priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
655 virt_to_le32desc(tail_list);
656 } else {
657 DBG ( "Fix this \n" );
658 (priv->txList + (priv->txTail - 1))->forward =
659 virt_to_le32desc(tail_list);
660 }
661 }
662
663 CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
664
665 DBG ( "INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
666
667 to = currticks() + TX_TIME_OUT;
668 while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
669
670 head_list = priv->txList + priv->txHead;
671 while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP)
672 && (ack < 255)) {
673 ack++;
674 if(tmpCStat & TLAN_CSTAT_EOC)
675 eoc =1;
676 head_list->cStat = TLAN_CSTAT_UNUSED;
677 CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
678 head_list = priv->txList + priv->txHead;
679
680 }
681 if(!ack)
682 printf("Incomplete TX Frame\n");
683
684 if(eoc) {
685 head_list = priv->txList + priv->txHead;
686 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
687 outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
688 ack |= TLAN_HC_GO;
689 } else {
690 priv->txInProgress = 0;
691 }
692 }
693 if(ack) {
694 host_cmd = TLAN_HC_ACK | ack;
695 outl(host_cmd, BASE + TLAN_HOST_CMD);
696 }
697
698 if(priv->tlanRev < 0x30 ) {
699 ack = 1;
700 head_list = priv->txList + priv->txHead;
701 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
702 outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
703 ack |= TLAN_HC_GO;
704 } else {
705 priv->txInProgress = 0;
706 }
707 host_cmd = TLAN_HC_ACK | ack | 0x00140000;
708 outl(host_cmd, BASE + TLAN_HOST_CMD);
709
710 }
711
712 if (currticks() >= to) {
713 printf("TX Time Out");
714 }
715 }
716
717 /**************************************************************************
718 DISABLE - Turn off ethernet interface
719 ***************************************************************************/
tlan_disable(struct nic * nic __unused)720 static void tlan_disable ( struct nic *nic __unused ) {
721 /* put the card in its initial state */
722 /* This function serves 3 purposes.
723 * This disables DMA and interrupts so we don't receive
724 * unexpected packets or interrupts from the card after
725 * etherboot has finished.
726 * This frees resources so etherboot may use
727 * this driver on another interface
728 * This allows etherboot to reinitialize the interface
729 * if something is something goes wrong.
730 *
731 */
732 outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
733 }
734
735 /**************************************************************************
736 IRQ - Enable, Disable, or Force interrupts
737 ***************************************************************************/
tlan_irq(struct nic * nic __unused,irq_action_t action __unused)738 static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused)
739 {
740 switch ( action ) {
741 case DISABLE :
742 break;
743 case ENABLE :
744 break;
745 case FORCE :
746 break;
747 }
748 }
749
750 static struct nic_operations tlan_operations = {
751 .connect = dummy_connect,
752 .poll = tlan_poll,
753 .transmit = tlan_transmit,
754 .irq = tlan_irq,
755
756 };
757
TLan_SetMulticastList(struct nic * nic)758 static void TLan_SetMulticastList(struct nic *nic) {
759 int i;
760 u8 tmp;
761
762 /* !IFF_PROMISC */
763 tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
764 TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
765
766 /* IFF_ALLMULTI */
767 for(i = 0; i< 3; i++)
768 TLan_SetMac(nic, i + 1, NULL);
769 TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
770 TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
771
772
773 }
774 /**************************************************************************
775 PROBE - Look for an adapter, this routine's visible to the outside
776 ***************************************************************************/
777
778 #define board_found 1
779 #define valid_link 0
tlan_probe(struct nic * nic,struct pci_device * pci)780 static int tlan_probe ( struct nic *nic, struct pci_device *pci ) {
781
782 u16 data = 0;
783 int err;
784 int i;
785
786 if (pci->ioaddr == 0)
787 return 0;
788
789 nic->irqno = 0;
790 nic->ioaddr = pci->ioaddr;
791
792 BASE = pci->ioaddr;
793
794 /* Set nic as PCI bus master */
795 adjust_pci_device(pci);
796
797 /* Point to private storage */
798 priv = &TLanPrivateInfo;
799
800 /* Figure out which chip we're dealing with */
801 i = 0;
802 chip_idx = -1;
803 while (tlan_pci_tbl[i].name) {
804 if ((((u32) pci->device << 16) | pci->vendor) ==
805 (tlan_pci_tbl[i].id.pci & 0xffffffff)) {
806 chip_idx = i;
807 break;
808 }
809 i++;
810 }
811 if (chip_idx == -1)
812 return 0;
813
814 priv->vendor_id = pci->vendor;
815 priv->dev_id = pci->device;
816 priv->nic_name = pci->id->name;
817 priv->eoc = 0;
818
819 err = 0;
820 for (i = 0; i < 6; i++)
821 err |= TLan_EeReadByte(BASE,
822 (u8) tlan_pci_tbl[chip_idx].
823 addrOfs + i,
824 (u8 *) & nic->node_addr[i]);
825 if (err) {
826 printf ( "TLAN: %s: Error reading MAC from eeprom: %d\n",
827 pci->id->name, err);
828 } else {
829 DBG ( "%s: %s at ioaddr %#lX, ",
830 pci->id->name, eth_ntoa ( nic->node_addr ), pci->ioaddr );
831 }
832
833 priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
834 printf("revision: 0x%hX\n", priv->tlanRev);
835
836 TLan_ResetLists(nic);
837 TLan_ResetAdapter(nic);
838
839 data = inl(BASE + TLAN_HOST_CMD);
840 data |= TLAN_HC_INT_OFF;
841 outw(data, BASE + TLAN_HOST_CMD);
842
843 TLan_SetMulticastList(nic);
844 udelay(100);
845 priv->txList = tx_ring;
846
847 /* if (board_found && valid_link)
848 {*/
849 /* point to NIC specific routines */
850 nic->nic_op = &tlan_operations;
851 return 1;
852 }
853
854
855 /*****************************************************************************
856 ******************************************************************************
857
858 ThunderLAN Driver Eeprom routines
859
860 The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A
861 EEPROM. These functions are based on information in Microchip's
862 data sheet. I don't know how well this functions will work with
863 other EEPROMs.
864
865 ******************************************************************************
866 *****************************************************************************/
867
868
869 /***************************************************************
870 * TLan_EeSendStart
871 *
872 * Returns:
873 * Nothing
874 * Parms:
875 * io_base The IO port base address for the
876 * TLAN device with the EEPROM to
877 * use.
878 *
879 * This function sends a start cycle to an EEPROM attached
880 * to a TLAN chip.
881 *
882 **************************************************************/
883
TLan_EeSendStart(u16 io_base)884 void TLan_EeSendStart(u16 io_base)
885 {
886 u16 sio;
887
888 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
889 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
890
891 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
892 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
893 TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
894 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
895 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
896
897 } /* TLan_EeSendStart */
898
899 /***************************************************************
900 * TLan_EeSendByte
901 *
902 * Returns:
903 * If the correct ack was received, 0, otherwise 1
904 * Parms: io_base The IO port base address for the
905 * TLAN device with the EEPROM to
906 * use.
907 * data The 8 bits of information to
908 * send to the EEPROM.
909 * stop If TLAN_EEPROM_STOP is passed, a
910 * stop cycle is sent after the
911 * byte is sent after the ack is
912 * read.
913 *
914 * This function sends a byte on the serial EEPROM line,
915 * driving the clock to send each bit. The function then
916 * reverses transmission direction and reads an acknowledge
917 * bit.
918 *
919 **************************************************************/
920
TLan_EeSendByte(u16 io_base,u8 data,int stop)921 int TLan_EeSendByte(u16 io_base, u8 data, int stop)
922 {
923 int err;
924 u8 place;
925 u16 sio;
926
927 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
928 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
929
930 /* Assume clock is low, tx is enabled; */
931 for (place = 0x80; place != 0; place >>= 1) {
932 if (place & data)
933 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
934 else
935 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
936 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
937 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
938 }
939 TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
940 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
941 err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
942 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
943 TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
944
945 if ((!err) && stop) {
946 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
947 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
948 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
949 }
950
951 return (err);
952
953 } /* TLan_EeSendByte */
954
955 /***************************************************************
956 * TLan_EeReceiveByte
957 *
958 * Returns:
959 * Nothing
960 * Parms:
961 * io_base The IO port base address for the
962 * TLAN device with the EEPROM to
963 * use.
964 * data An address to a char to hold the
965 * data sent from the EEPROM.
966 * stop If TLAN_EEPROM_STOP is passed, a
967 * stop cycle is sent after the
968 * byte is received, and no ack is
969 * sent.
970 *
971 * This function receives 8 bits of data from the EEPROM
972 * over the serial link. It then sends and ack bit, or no
973 * ack and a stop bit. This function is used to retrieve
974 * data after the address of a byte in the EEPROM has been
975 * sent.
976 *
977 **************************************************************/
978
TLan_EeReceiveByte(u16 io_base,u8 * data,int stop)979 void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop)
980 {
981 u8 place;
982 u16 sio;
983
984 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
985 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
986 *data = 0;
987
988 /* Assume clock is low, tx is enabled; */
989 TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
990 for (place = 0x80; place; place >>= 1) {
991 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
992 if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
993 *data |= place;
994 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
995 }
996
997 TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
998 if (!stop) {
999 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */
1000 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1001 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1002 } else {
1003 TLan_SetBit(TLAN_NET_SIO_EDATA, sio); /* No ack = 1 (?) */
1004 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1005 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1006 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
1007 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1008 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1009 }
1010
1011 } /* TLan_EeReceiveByte */
1012
1013 /***************************************************************
1014 * TLan_EeReadByte
1015 *
1016 * Returns:
1017 * No error = 0, else, the stage at which the error
1018 * occurred.
1019 * Parms:
1020 * io_base The IO port base address for the
1021 * TLAN device with the EEPROM to
1022 * use.
1023 * ee_addr The address of the byte in the
1024 * EEPROM whose contents are to be
1025 * retrieved.
1026 * data An address to a char to hold the
1027 * data obtained from the EEPROM.
1028 *
1029 * This function reads a byte of information from an byte
1030 * cell in the EEPROM.
1031 *
1032 **************************************************************/
1033
TLan_EeReadByte(u16 io_base,u8 ee_addr,u8 * data)1034 int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data)
1035 {
1036 int err;
1037 int ret = 0;
1038
1039
1040 TLan_EeSendStart(io_base);
1041 err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
1042 if (err) {
1043 ret = 1;
1044 goto fail;
1045 }
1046 err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
1047 if (err) {
1048 ret = 2;
1049 goto fail;
1050 }
1051 TLan_EeSendStart(io_base);
1052 err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
1053 if (err) {
1054 ret = 3;
1055 goto fail;
1056 }
1057 TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
1058 fail:
1059
1060 return ret;
1061
1062 } /* TLan_EeReadByte */
1063
1064
1065 /*****************************************************************************
1066 ******************************************************************************
1067
1068 ThunderLAN Driver MII Routines
1069
1070 These routines are based on the information in Chap. 2 of the
1071 "ThunderLAN Programmer's Guide", pp. 15-24.
1072
1073 ******************************************************************************
1074 *****************************************************************************/
1075
1076
1077 /***************************************************************
1078 * TLan_MiiReadReg
1079 *
1080 * Returns:
1081 * 0 if ack received ok
1082 * 1 otherwise.
1083 *
1084 * Parms:
1085 * dev The device structure containing
1086 * The io address and interrupt count
1087 * for this device.
1088 * phy The address of the PHY to be queried.
1089 * reg The register whose contents are to be
1090 * retrieved.
1091 * val A pointer to a variable to store the
1092 * retrieved value.
1093 *
1094 * This function uses the TLAN's MII bus to retrieve the contents
1095 * of a given register on a PHY. It sends the appropriate info
1096 * and then reads the 16-bit register value from the MII bus via
1097 * the TLAN SIO register.
1098 *
1099 **************************************************************/
1100
TLan_MiiReadReg(struct nic * nic __unused,u16 phy,u16 reg,u16 * val)1101 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val)
1102 {
1103 u8 nack;
1104 u16 sio, tmp;
1105 u32 i;
1106 int err;
1107 int minten;
1108
1109 err = FALSE;
1110 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1111 sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1112
1113 TLan_MiiSync(BASE);
1114
1115 minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1116 if (minten)
1117 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1118
1119 TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1120 TLan_MiiSendData(BASE, 0x2, 2); /* Read ( 10b ) */
1121 TLan_MiiSendData(BASE, phy, 5); /* Device # */
1122 TLan_MiiSendData(BASE, reg, 5); /* Register # */
1123
1124
1125 TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */
1126
1127 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Clock Idle bit */
1128 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1129 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Wait 300ns */
1130
1131 nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio); /* Check for ACK */
1132 TLan_SetBit(TLAN_NET_SIO_MCLK, sio); /* Finish ACK */
1133 if (nack) { /* No ACK, so fake it */
1134 for (i = 0; i < 16; i++) {
1135 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1136 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1137 }
1138 tmp = 0xffff;
1139 err = TRUE;
1140 } else { /* ACK, so read data */
1141 for (tmp = 0, i = 0x8000; i; i >>= 1) {
1142 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1143 if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
1144 tmp |= i;
1145 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1146 }
1147 }
1148
1149
1150 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Idle cycle */
1151 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1152
1153 if (minten)
1154 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1155
1156 *val = tmp;
1157
1158 return err;
1159
1160 } /* TLan_MiiReadReg */
1161
1162 /***************************************************************
1163 * TLan_MiiSendData
1164 *
1165 * Returns:
1166 * Nothing
1167 * Parms:
1168 * base_port The base IO port of the adapter in
1169 * question.
1170 * dev The address of the PHY to be queried.
1171 * data The value to be placed on the MII bus.
1172 * num_bits The number of bits in data that are to
1173 * be placed on the MII bus.
1174 *
1175 * This function sends on sequence of bits on the MII
1176 * configuration bus.
1177 *
1178 **************************************************************/
1179
TLan_MiiSendData(u16 base_port,u32 data,unsigned num_bits)1180 void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits)
1181 {
1182 u16 sio;
1183 u32 i;
1184
1185 if (num_bits == 0)
1186 return;
1187
1188 outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1189 sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1190 TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
1191
1192 for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
1193 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1194 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1195 if (data & i)
1196 TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
1197 else
1198 TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
1199 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1200 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1201 }
1202
1203 } /* TLan_MiiSendData */
1204
1205 /***************************************************************
1206 * TLan_MiiSync
1207 *
1208 * Returns:
1209 * Nothing
1210 * Parms:
1211 * base_port The base IO port of the adapter in
1212 * question.
1213 *
1214 * This functions syncs all PHYs in terms of the MII configuration
1215 * bus.
1216 *
1217 **************************************************************/
1218
TLan_MiiSync(u16 base_port)1219 void TLan_MiiSync(u16 base_port)
1220 {
1221 int i;
1222 u16 sio;
1223
1224 outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1225 sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1226
1227 TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
1228 for (i = 0; i < 32; i++) {
1229 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1230 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1231 }
1232
1233 } /* TLan_MiiSync */
1234
1235 /***************************************************************
1236 * TLan_MiiWriteReg
1237 *
1238 * Returns:
1239 * Nothing
1240 * Parms:
1241 * dev The device structure for the device
1242 * to write to.
1243 * phy The address of the PHY to be written to.
1244 * reg The register whose contents are to be
1245 * written.
1246 * val The value to be written to the register.
1247 *
1248 * This function uses the TLAN's MII bus to write the contents of a
1249 * given register on a PHY. It sends the appropriate info and then
1250 * writes the 16-bit register value from the MII configuration bus
1251 * via the TLAN SIO register.
1252 *
1253 **************************************************************/
1254
TLan_MiiWriteReg(struct nic * nic __unused,u16 phy,u16 reg,u16 val)1255 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
1256 {
1257 u16 sio;
1258 int minten;
1259
1260 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1261 sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1262
1263 TLan_MiiSync(BASE);
1264
1265 minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1266 if (minten)
1267 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1268
1269 TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1270 TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
1271 TLan_MiiSendData(BASE, phy, 5); /* Device # */
1272 TLan_MiiSendData(BASE, reg, 5); /* Register # */
1273
1274 TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
1275 TLan_MiiSendData(BASE, val, 16); /* Send Data */
1276
1277 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Idle cycle */
1278 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1279
1280 if (minten)
1281 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1282
1283
1284 } /* TLan_MiiWriteReg */
1285
1286 /***************************************************************
1287 * TLan_SetMac
1288 *
1289 * Returns:
1290 * Nothing
1291 * Parms:
1292 * dev Pointer to device structure of adapter
1293 * on which to change the AREG.
1294 * areg The AREG to set the address in (0 - 3).
1295 * mac A pointer to an array of chars. Each
1296 * element stores one byte of the address.
1297 * IE, it isn't in ascii.
1298 *
1299 * This function transfers a MAC address to one of the
1300 * TLAN AREGs (address registers). The TLAN chip locks
1301 * the register on writing to offset 0 and unlocks the
1302 * register after writing to offset 5. If NULL is passed
1303 * in mac, then the AREG is filled with 0's.
1304 *
1305 **************************************************************/
1306
TLan_SetMac(struct nic * nic __unused,int areg,unsigned char * mac)1307 void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac)
1308 {
1309 int i;
1310
1311 areg *= 6;
1312
1313 if (mac != NULL) {
1314 for (i = 0; i < 6; i++)
1315 TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1316 mac[i]);
1317 } else {
1318 for (i = 0; i < 6; i++)
1319 TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1320 }
1321
1322 } /* TLan_SetMac */
1323
1324 /*********************************************************************
1325 * TLan_PhyDetect
1326 *
1327 * Returns:
1328 * Nothing
1329 * Parms:
1330 * dev A pointer to the device structure of the adapter
1331 * for which the PHY needs determined.
1332 *
1333 * So far I've found that adapters which have external PHYs
1334 * may also use the internal PHY for part of the functionality.
1335 * (eg, AUI/Thinnet). This function finds out if this TLAN
1336 * chip has an internal PHY, and then finds the first external
1337 * PHY (starting from address 0) if it exists).
1338 *
1339 ********************************************************************/
1340
TLan_PhyDetect(struct nic * nic)1341 void TLan_PhyDetect(struct nic *nic)
1342 {
1343 u16 control;
1344 u16 hi;
1345 u16 lo;
1346 u32 phy;
1347
1348 if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
1349 priv->phyNum = 0xFFFF;
1350 return;
1351 }
1352
1353 TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_PHYSID1, &hi);
1354
1355 if (hi != 0xFFFF) {
1356 priv->phy[0] = TLAN_PHY_MAX_ADDR;
1357 } else {
1358 priv->phy[0] = TLAN_PHY_NONE;
1359 }
1360
1361 priv->phy[1] = TLAN_PHY_NONE;
1362 for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
1363 TLan_MiiReadReg(nic, phy, MII_BMCR, &control);
1364 TLan_MiiReadReg(nic, phy, MII_PHYSID1, &hi);
1365 TLan_MiiReadReg(nic, phy, MII_PHYSID2, &lo);
1366 if ((control != 0xFFFF) || (hi != 0xFFFF)
1367 || (lo != 0xFFFF)) {
1368 printf("PHY found at %hX %hX %hX %hX\n",
1369 (unsigned int) phy, control, hi, lo);
1370 if ((priv->phy[1] == TLAN_PHY_NONE)
1371 && (phy != TLAN_PHY_MAX_ADDR)) {
1372 priv->phy[1] = phy;
1373 }
1374 }
1375 }
1376
1377 if (priv->phy[1] != TLAN_PHY_NONE) {
1378 priv->phyNum = 1;
1379 } else if (priv->phy[0] != TLAN_PHY_NONE) {
1380 priv->phyNum = 0;
1381 } else {
1382 printf
1383 ("TLAN: Cannot initialize device, no PHY was found!\n");
1384 }
1385
1386 } /* TLan_PhyDetect */
1387
TLan_PhyPowerDown(struct nic * nic)1388 void TLan_PhyPowerDown(struct nic *nic)
1389 {
1390
1391 u16 value;
1392 DBG ( "%s: Powering down PHY(s).\n", priv->nic_name );
1393 value = BMCR_PDOWN | BMCR_LOOPBACK | BMCR_ISOLATE;
1394 TLan_MiiSync(BASE);
1395 TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value);
1396 if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
1397 &&
1398 (!(tlan_pci_tbl[chip_idx].
1399 flags & TLAN_ADAPTER_USE_INTERN_10))) {
1400 TLan_MiiSync(BASE);
1401 TLan_MiiWriteReg(nic, priv->phy[1], MII_BMCR, value);
1402 }
1403
1404 /* Wait for 50 ms and powerup
1405 * This is abitrary. It is intended to make sure the
1406 * tranceiver settles.
1407 */
1408 /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
1409 mdelay(50);
1410 TLan_PhyPowerUp(nic);
1411
1412 } /* TLan_PhyPowerDown */
1413
1414
TLan_PhyPowerUp(struct nic * nic)1415 void TLan_PhyPowerUp(struct nic *nic)
1416 {
1417 u16 value;
1418
1419 DBG ( "%s: Powering up PHY.\n", priv->nic_name );
1420 TLan_MiiSync(BASE);
1421 value = BMCR_LOOPBACK;
1422 TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value);
1423 TLan_MiiSync(BASE);
1424 /* Wait for 500 ms and reset the
1425 * tranceiver. The TLAN docs say both 50 ms and
1426 * 500 ms, so do the longer, just in case.
1427 */
1428 mdelay(500);
1429 TLan_PhyReset(nic);
1430 /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
1431
1432 } /* TLan_PhyPowerUp */
1433
TLan_PhyReset(struct nic * nic)1434 void TLan_PhyReset(struct nic *nic)
1435 {
1436 u16 phy;
1437 u16 value;
1438
1439 phy = priv->phy[priv->phyNum];
1440
1441 DBG ( "%s: Reseting PHY.\n", priv->nic_name );
1442 TLan_MiiSync(BASE);
1443 value = BMCR_LOOPBACK | BMCR_RESET;
1444 TLan_MiiWriteReg(nic, phy, MII_BMCR, value);
1445 TLan_MiiReadReg(nic, phy, MII_BMCR, &value);
1446 while (value & BMCR_RESET) {
1447 TLan_MiiReadReg(nic, phy, MII_BMCR, &value);
1448 }
1449
1450 /* Wait for 500 ms and initialize.
1451 * I don't remember why I wait this long.
1452 * I've changed this to 50ms, as it seems long enough.
1453 */
1454 /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
1455 mdelay(50);
1456 TLan_PhyStartLink(nic);
1457
1458 } /* TLan_PhyReset */
1459
1460
TLan_PhyStartLink(struct nic * nic)1461 void TLan_PhyStartLink(struct nic *nic)
1462 {
1463
1464 u16 ability;
1465 u16 control;
1466 u16 data;
1467 u16 phy;
1468 u16 status;
1469 u16 tctl;
1470
1471 phy = priv->phy[priv->phyNum];
1472 DBG ( "%s: Trying to activate link.\n", priv->nic_name );
1473 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
1474 TLan_MiiReadReg(nic, phy, MII_BMSR, &ability);
1475
1476 if ((status & BMSR_ANEGCAPABLE) && (!priv->aui)) {
1477 ability = status >> 11;
1478 if (priv->speed == TLAN_SPEED_10 &&
1479 priv->duplex == TLAN_DUPLEX_HALF) {
1480 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0000);
1481 } else if (priv->speed == TLAN_SPEED_10 &&
1482 priv->duplex == TLAN_DUPLEX_FULL) {
1483 priv->tlanFullDuplex = TRUE;
1484 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0100);
1485 } else if (priv->speed == TLAN_SPEED_100 &&
1486 priv->duplex == TLAN_DUPLEX_HALF) {
1487 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2000);
1488 } else if (priv->speed == TLAN_SPEED_100 &&
1489 priv->duplex == TLAN_DUPLEX_FULL) {
1490 priv->tlanFullDuplex = TRUE;
1491 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2100);
1492 } else {
1493
1494 /* Set Auto-Neg advertisement */
1495 TLan_MiiWriteReg(nic, phy, MII_ADVERTISE,
1496 (ability << 5) | 1);
1497 /* Enablee Auto-Neg */
1498 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1000);
1499 /* Restart Auto-Neg */
1500 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1200);
1501 /* Wait for 4 sec for autonegotiation
1502 * to complete. The max spec time is less than this
1503 * but the card need additional time to start AN.
1504 * .5 sec should be plenty extra.
1505 */
1506 DBG ( "TLAN: %s: Starting autonegotiation.\n",
1507 priv->nic_name );
1508 mdelay(4000);
1509 TLan_PhyFinishAutoNeg(nic);
1510 /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1511 return;
1512 }
1513
1514 }
1515
1516 if ((priv->aui) && (priv->phyNum != 0)) {
1517 priv->phyNum = 0;
1518 data =
1519 TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1520 TLAN_NET_CFG_PHY_EN;
1521 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1522 mdelay(50);
1523 /* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1524 TLan_PhyPowerDown(nic);
1525 return;
1526 } else if (priv->phyNum == 0) {
1527 control = 0;
1528 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
1529 if (priv->aui) {
1530 tctl |= TLAN_TC_AUISEL;
1531 } else {
1532 tctl &= ~TLAN_TC_AUISEL;
1533 if (priv->duplex == TLAN_DUPLEX_FULL) {
1534 control |= BMCR_FULLDPLX;
1535 priv->tlanFullDuplex = TRUE;
1536 }
1537 if (priv->speed == TLAN_SPEED_100) {
1538 control |= BMCR_SPEED100;
1539 }
1540 }
1541 TLan_MiiWriteReg(nic, phy, MII_BMCR, control);
1542 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
1543 }
1544
1545 /* Wait for 2 sec to give the tranceiver time
1546 * to establish link.
1547 */
1548 /* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */
1549 mdelay(2000);
1550 TLan_FinishReset(nic);
1551
1552 } /* TLan_PhyStartLink */
1553
TLan_PhyFinishAutoNeg(struct nic * nic)1554 void TLan_PhyFinishAutoNeg(struct nic *nic)
1555 {
1556
1557 u16 an_adv;
1558 u16 an_lpa;
1559 u16 data;
1560 u16 mode;
1561 u16 phy;
1562 u16 status;
1563
1564 phy = priv->phy[priv->phyNum];
1565
1566 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
1567 udelay(1000);
1568 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
1569
1570 if (!(status & BMSR_ANEGCOMPLETE)) {
1571 /* Wait for 8 sec to give the process
1572 * more time. Perhaps we should fail after a while.
1573 */
1574 if (!priv->neg_be_verbose++) {
1575 printf
1576 ("TLAN: Giving autonegotiation more time.\n");
1577 printf
1578 ("TLAN: Please check that your adapter has\n");
1579 printf
1580 ("TLAN: been properly connected to a HUB or Switch.\n");
1581 printf
1582 ("TLAN: Trying to establish link in the background...\n");
1583 }
1584 mdelay(8000);
1585 TLan_PhyFinishAutoNeg(nic);
1586 /* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1587 return;
1588 }
1589
1590 DBG ( "TLAN: %s: Autonegotiation complete.\n", priv->nic_name );
1591 TLan_MiiReadReg(nic, phy, MII_ADVERTISE, &an_adv);
1592 TLan_MiiReadReg(nic, phy, MII_LPA, &an_lpa);
1593 mode = an_adv & an_lpa & 0x03E0;
1594 if (mode & 0x0100) {
1595 printf("Full Duplex\n");
1596 priv->tlanFullDuplex = TRUE;
1597 } else if (!(mode & 0x0080) && (mode & 0x0040)) {
1598 priv->tlanFullDuplex = TRUE;
1599 printf("Full Duplex\n");
1600 }
1601
1602 if ((!(mode & 0x0180))
1603 && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
1604 && (priv->phyNum != 0)) {
1605 priv->phyNum = 0;
1606 data =
1607 TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1608 TLAN_NET_CFG_PHY_EN;
1609 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1610 /* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1611 mdelay(400);
1612 TLan_PhyPowerDown(nic);
1613 return;
1614 }
1615
1616 if (priv->phyNum == 0) {
1617 if ((priv->duplex == TLAN_DUPLEX_FULL)
1618 || (an_adv & an_lpa & 0x0040)) {
1619 TLan_MiiWriteReg(nic, phy, MII_BMCR,
1620 BMCR_ANENABLE | BMCR_FULLDPLX);
1621 DBG
1622 ( "TLAN: Starting internal PHY with FULL-DUPLEX\n" );
1623 } else {
1624 TLan_MiiWriteReg(nic, phy, MII_BMCR,
1625 BMCR_ANENABLE);
1626 DBG
1627 ( "TLAN: Starting internal PHY with HALF-DUPLEX\n" );
1628 }
1629 }
1630
1631 /* Wait for 100 ms. No reason in partiticular.
1632 */
1633 /* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
1634 mdelay(100);
1635 TLan_FinishReset(nic);
1636
1637 } /* TLan_PhyFinishAutoNeg */
1638
1639 #ifdef MONITOR
1640
1641 /*********************************************************************
1642 *
1643 * TLan_phyMonitor
1644 *
1645 * Returns:
1646 * None
1647 *
1648 * Params:
1649 * dev The device structure of this device.
1650 *
1651 *
1652 * This function monitors PHY condition by reading the status
1653 * register via the MII bus. This can be used to give info
1654 * about link changes (up/down), and possible switch to alternate
1655 * media.
1656 *
1657 ********************************************************************/
1658
TLan_PhyMonitor(struct net_device * dev)1659 void TLan_PhyMonitor(struct net_device *dev)
1660 {
1661 TLanPrivateInfo *priv = dev->priv;
1662 u16 phy;
1663 u16 phy_status;
1664
1665 phy = priv->phy[priv->phyNum];
1666
1667 /* Get PHY status register */
1668 TLan_MiiReadReg(nic, phy, MII_BMSR, &phy_status);
1669
1670 /* Check if link has been lost */
1671 if (!(phy_status & BMSR_LSTATUS)) {
1672 if (priv->link) {
1673 priv->link = 0;
1674 printf("TLAN: %s has lost link\n", priv->nic_name);
1675 priv->flags &= ~IFF_RUNNING;
1676 mdelay(2000);
1677 TLan_PhyMonitor(nic);
1678 /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1679 return;
1680 }
1681 }
1682
1683 /* Link restablished? */
1684 if ((phy_status & BMSR_LSTATUS) && !priv->link) {
1685 priv->link = 1;
1686 printf("TLAN: %s has reestablished link\n",
1687 priv->nic_name);
1688 priv->flags |= IFF_RUNNING;
1689 }
1690
1691 /* Setup a new monitor */
1692 /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1693 mdelay(2000);
1694 TLan_PhyMonitor(nic);
1695 }
1696
1697 #endif /* MONITOR */
1698
1699 static struct pci_device_id tlan_nics[] = {
1700 PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP", 0),
1701 PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP", 0),
1702 PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P", 0),
1703 PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P", 0),
1704 PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P", 0),
1705 PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP", 0),
1706 PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP", 0),
1707 PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP", 0),
1708 PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185", 0),
1709 PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325", 0),
1710 PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326", 0),
1711 PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP", 0),
1712 PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax", 0),
1713 };
1714
1715 PCI_DRIVER ( tlan_driver, tlan_nics, PCI_NO_CLASS );
1716
1717 DRIVER ( "TLAN/PCI", nic_driver, pci_driver, tlan_driver,
1718 tlan_probe, tlan_disable );
1719
1720 /*
1721 * Local variables:
1722 * c-basic-offset: 8
1723 * c-indent-level: 8
1724 * tab-width: 8
1725 * End:
1726 */
1727