1/* PALcode and C runtime functions for the CLIPPER system emulation.
2
3   Copyright (C) 2011 Richard Henderson
4
5   This file is part of QEMU PALcode.
6
7   This program is free software; you can redistribute it and/or modify
8   it under the terms of the GNU General Public License as published by
9   the Free Software Foundation; either version 2 of the License or
10   (at your option) any later version.
11
12   This program is distributed in the hope that it will be useful,
13   but WITHOUT ANY WARRANTY; without even the implied warranty of
14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
15   of the GNU General Public License for more details.
16
17   You should have received a copy of the GNU General Public License
18   along with this program; see the file COPYING.  If not see
19   <http://www.gnu.org/licenses/>.  */
20
21#include "pal.h"
22#include SYSTEM_H
23
24/*
25 * Sys_Setup
26 *
27 * Do any system specific setup necessary.
28 *
29 * INPUT PARAMETERS
30 *
31 *	a0 = whami
32 *	p7 = return address
33 */
34	.globl	Sys_Setup
35	.ent	Sys_Setup
36Sys_Setup:
37	.frame	$sp, 0, p7, 0
38	LOAD_PHYS_CCHIP	t0
39	lda		t0, TYPHOON_CCHIP_DIR0(t0)
40	// DIR[23] differ from DIR[01] by 0x400
41	// DIR[13] differ from DIR[02] by 0x40
42	and		a0, 2, t4
43	and		a0, 1, t3
44	sll		t4, 9, t4
45	sll		t3, 6, t3
46	addq		t0, t4, t0
47	addq		t0, t3, t0
48	// IIC[0-4] differ from DIR[0-4] by 0x100
49	lda		t2, 0x100(t0)
50	mtpr		t0, ptCpuDIR
51	mtpr		t2, ptCpuIIC
52	ret
53	.end	Sys_Setup
54
55/*
56 * Sys_Dev_Vector
57 *
58 * Load the SRM interrupt vector for the system.
59 *
60 * INPUT PARAMETERS
61 *
62 *	p7 = return address
63 *
64 * OUTPUT PARAMETERS
65 *
66 *	a1 = interrupt vector
67 */
68
69	.globl	Sys_Dev_Vector
70	.ent	Sys_Dev_Vector
71Sys_Dev_Vector:
72	.frame	$sp, 0, p7, 0
73	mfpr	a1, ptCpuDIR		// Load int mask for this CPU
74	ldq_p	a1, 0(a1)
75	beq	a1, CallPal_Rti		// No interrupts asserted?
76
77	cttz	a1, a1			// Find the first asserted interrupt.
78
79	cmpeq	a1, 55, a0		// Is this an ISA interrupt?
80	addq	a1, 16, a1		// PCI interrupt numbers start at 16
81	beq	a0, 1f
82
83	LOAD_PHYS_PCHIP0_IACK a1	// IACK results in the ISA irq
84	ldl_p	a1, 0(a1)
85
861:	sll	a1, 4, a1
87	lda	a1, 0x800(a1)
88	ret	$31, (p7), 0
89	.end Sys_Dev_Vector
90
91/*
92 * Cserve_Ena
93 *
94 * Unmask a PCI interrupt
95 */
96	.globl	Cserve_Ena
97Cserve_Ena:
98	// FIXME
99	hw_rei
100ENDFN	Cserve_Ena
101
102/*
103 * Cserve_Dis
104 *
105 * Mask a PCI interrupt
106 */
107	.globl	Cserve_Dis
108Cserve_Dis:
109	// FIXME
110	hw_rei
111ENDFN	Cserve_Dis
112
113/*
114 * PCI parameters
115 */
116
117	.section .sdata
118
119	.align	3
120	.globl	pci_io_base
121	.type	pci_io_base, @object
122	.size	pci_io_base, 8
123pci_io_base:
124	.quad	PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_IO
125
126	.globl	pci_conf_base
127	.type	pci_conf_base, @object
128	.size	pci_conf_base, 8
129pci_conf_base:
130	.quad	PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_CONF
131
132	.align	3
133	.globl	pci_mem_base
134	.type	pci_mem_base, @object
135	.size	pci_mem_base, 8
136pci_mem_base:
137	.quad	PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_MEM
138
139