1/*
2 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
3 *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
4 *
5 * Modified for the at91rm9200dk board by
6 * (C) Copyright 2004
7 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29
30#ifndef CONFIG_SKIP_LOWLEVEL_INIT
31
32#include <asm/arch/hardware.h>
33#include <asm/arch/at91_mc.h>
34#include <asm/arch/at91_pmc.h>
35#include <asm/arch/at91_pio.h>
36
37#define ARM920T_CONTROL	0xC0000000	/* @ set bit 31 (iA) and 30 (nF) */
38
39_MTEXT_BASE:
40#undef START_FROM_MEM
41#ifdef START_FROM_MEM
42	.word	TEXT_BASE-PHYS_FLASH_1
43#else
44	.word	TEXT_BASE
45#endif
46
47.globl lowlevel_init
48lowlevel_init:
49	ldr     r1, =AT91_ASM_PMC_MOR
50	/* Main oscillator Enable register */
51#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
52	ldr     r0, =0x0000FF01		/* Enable main oscillator */
53#else
54	ldr     r0, =0x0000FF00		/* Disable main oscillator */
55#endif
56	str     r0, [r1] /*AT91C_CKGR_MOR] */
57	/* Add loop to compensate Main Oscillator startup time */
58	ldr     r0, =0x00000010
59LoopOsc:
60	subs    r0, r0, #1
61	bhi     LoopOsc
62
63	/* memory control configuration */
64	/* this isn't very elegant, but	 what the heck */
65	ldr	r0, =SMRDATA
66	ldr	r1, _MTEXT_BASE
67	sub	r0, r0, r1
68	add	r2, r0, #80
69pllloop:
70	/* the address */
71	ldr	r1, [r0], #4
72	/* the value */
73	ldr	r3, [r0], #4
74	str	r3, [r1]
75	cmp	r2, r0
76	bne	pllloop
77	/* delay - this is all done by guess */
78	ldr	r0, =0x00010000
79	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
80lock:
81	subs	r0, r0, #1
82	bhi	lock
83	ldr	r0, =SMRDATA1
84	ldr	r1, _MTEXT_BASE
85	sub	r0, r0, r1
86	add	r2, r0, #176
87sdinit:
88	/* the address */
89	ldr	r1, [r0], #4
90	/* the value */
91	ldr	r3, [r0], #4
92	str	r3, [r1]
93	cmp	r2, r0
94	bne	sdinit
95
96	/* switch from FastBus to Asynchronous clock mode */
97	mrc	p15, 0, r0, c1, c0, 0
98	orr	r0, r0, #ARM920T_CONTROL
99	mcr	p15, 0, r0, c1, c0, 0
100
101	/* everything is fine now */
102	mov	pc, lr
103
104	.ltorg
105
106SMRDATA:
107	.word AT91_ASM_MC_EBI_CFG
108	.word CONFIG_SYS_EBI_CFGR_VAL
109	.word AT91_ASM_MC_SMC_CSR0
110	.word CONFIG_SYS_SMC_CSR0_VAL
111	.word AT91_ASM_PMC_PLLAR
112	.word CONFIG_SYS_PLLAR_VAL
113	.word AT91_ASM_PMC_PLLBR
114	.word CONFIG_SYS_PLLBR_VAL
115	.word AT91_ASM_PMC_MCKR
116	.word CONFIG_SYS_MCKR_VAL
117	/* here there's a delay */
118SMRDATA1:
119	.word AT91_ASM_PIOC_ASR
120	.word CONFIG_SYS_PIOC_ASR_VAL
121	.word AT91_ASM_PIOC_BSR
122	.word CONFIG_SYS_PIOC_BSR_VAL
123	.word AT91_ASM_PIOC_PDR
124	.word CONFIG_SYS_PIOC_PDR_VAL
125	.word AT91_ASM_MC_EBI_CSA
126	.word CONFIG_SYS_EBI_CSA_VAL
127	.word AT91_ASM_MC_SDRAMC_CR
128	.word CONFIG_SYS_SDRC_CR_VAL
129	.word AT91_ASM_MC_SDRAMC_MR
130	.word CONFIG_SYS_SDRC_MR_VAL
131	.word CONFIG_SYS_SDRAM
132	.word CONFIG_SYS_SDRAM_VAL
133	.word AT91_ASM_MC_SDRAMC_MR
134	.word CONFIG_SYS_SDRC_MR_VAL1
135	.word CONFIG_SYS_SDRAM
136	.word CONFIG_SYS_SDRAM_VAL
137	.word CONFIG_SYS_SDRAM
138	.word CONFIG_SYS_SDRAM_VAL
139	.word CONFIG_SYS_SDRAM
140	.word CONFIG_SYS_SDRAM_VAL
141	.word CONFIG_SYS_SDRAM
142	.word CONFIG_SYS_SDRAM_VAL
143	.word CONFIG_SYS_SDRAM
144	.word CONFIG_SYS_SDRAM_VAL
145	.word CONFIG_SYS_SDRAM
146	.word CONFIG_SYS_SDRAM_VAL
147	.word CONFIG_SYS_SDRAM
148	.word CONFIG_SYS_SDRAM_VAL
149	.word CONFIG_SYS_SDRAM
150	.word CONFIG_SYS_SDRAM_VAL
151	.word AT91_ASM_MC_SDRAMC_MR
152	.word CONFIG_SYS_SDRC_MR_VAL2
153	.word CONFIG_SYS_SDRAM1
154	.word CONFIG_SYS_SDRAM_VAL
155	.word AT91_ASM_MC_SDRAMC_TR
156	.word CONFIG_SYS_SDRC_TR_VAL
157	.word CONFIG_SYS_SDRAM
158	.word CONFIG_SYS_SDRAM_VAL
159	.word AT91_ASM_MC_SDRAMC_MR
160	.word CONFIG_SYS_SDRC_MR_VAL3
161	.word CONFIG_SYS_SDRAM
162	.word CONFIG_SYS_SDRAM_VAL
163	/* SMRDATA1 is 176 bytes long */
164#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
165