1 /*
2 * (C) Copyright 2007-2009 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24 #include <common.h>
25 #include <asm/io.h>
26 #include <asm/mpc512x.h>
27
28 /*
29 * MDDRC Config Runtime Settings
30 */
31 ddr512x_config_t default_mddrc_config = {
32 .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG,
33 .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
34 .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1,
35 .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2,
36 };
37
38 u32 default_init_seq[] = {
39 CONFIG_SYS_DDRCMD_NOP,
40 CONFIG_SYS_DDRCMD_NOP,
41 CONFIG_SYS_DDRCMD_NOP,
42 CONFIG_SYS_DDRCMD_NOP,
43 CONFIG_SYS_DDRCMD_NOP,
44 CONFIG_SYS_DDRCMD_NOP,
45 CONFIG_SYS_DDRCMD_NOP,
46 CONFIG_SYS_DDRCMD_NOP,
47 CONFIG_SYS_DDRCMD_NOP,
48 CONFIG_SYS_DDRCMD_NOP,
49 CONFIG_SYS_DDRCMD_PCHG_ALL,
50 CONFIG_SYS_DDRCMD_NOP,
51 CONFIG_SYS_DDRCMD_RFSH,
52 CONFIG_SYS_DDRCMD_NOP,
53 CONFIG_SYS_DDRCMD_RFSH,
54 CONFIG_SYS_DDRCMD_NOP,
55 CONFIG_SYS_MICRON_INIT_DEV_OP,
56 CONFIG_SYS_DDRCMD_NOP,
57 CONFIG_SYS_DDRCMD_EM2,
58 CONFIG_SYS_DDRCMD_NOP,
59 CONFIG_SYS_DDRCMD_PCHG_ALL,
60 CONFIG_SYS_DDRCMD_EM2,
61 CONFIG_SYS_DDRCMD_EM3,
62 CONFIG_SYS_DDRCMD_EN_DLL,
63 CONFIG_SYS_MICRON_INIT_DEV_OP,
64 CONFIG_SYS_DDRCMD_PCHG_ALL,
65 CONFIG_SYS_DDRCMD_RFSH,
66 CONFIG_SYS_MICRON_INIT_DEV_OP,
67 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
68 CONFIG_SYS_DDRCMD_PCHG_ALL,
69 CONFIG_SYS_DDRCMD_NOP
70 };
71
72 /*
73 * fixed sdram init:
74 * The board doesn't use memory modules that have serial presence
75 * detect or similar mechanism for discovery of the DRAM settings
76 */
fixed_sdram(ddr512x_config_t * mddrc_config,u32 * dram_init_seq,int seq_sz)77 long int fixed_sdram(ddr512x_config_t *mddrc_config,
78 u32 *dram_init_seq, int seq_sz)
79 {
80 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
81 u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
82 u32 msize_log2 = __ilog2(msize);
83 u32 i;
84
85 /* take default settings and init sequence if necessary */
86 if (mddrc_config == NULL)
87 mddrc_config = &default_mddrc_config;
88 if (dram_init_seq == NULL) {
89 dram_init_seq = default_init_seq;
90 seq_sz = sizeof(default_init_seq)/sizeof(u32);
91 }
92
93 /* Initialize IO Control */
94 out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
95
96 /* Initialize DDR Local Window */
97 out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
98 out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
99 sync_law(&im->sysconf.ddrlaw.ar);
100
101 /* DDR Enable */
102 out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN);
103
104 /* Initialize DDR Priority Manager */
105 out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
106 out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
107 out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
108 out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
109 out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
110 out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
111 out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
112 out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
113 out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
114 out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
115 out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
116 out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
117 out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
118 out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
119 out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
120 out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
121 out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
122 out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
123 out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
124 out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
125 out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
126 out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
127 out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
128
129 /*
130 * Initialize MDDRC
131 * put MDDRC in CMD mode and
132 * set the max time between refreshes to 0 during init process
133 */
134 out_be32(&im->mddrc.ddr_sys_config,
135 mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK);
136 out_be32(&im->mddrc.ddr_time_config0,
137 mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK);
138 out_be32(&im->mddrc.ddr_time_config1,
139 mddrc_config->ddr_time_config1);
140 out_be32(&im->mddrc.ddr_time_config2,
141 mddrc_config->ddr_time_config2);
142
143 /* Initialize DDR with either default or supplied init sequence */
144 for (i = 0; i < seq_sz; i++)
145 out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
146
147 /* Start MDDRC */
148 out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
149 out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
150
151 msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
152 /* Fix DDR Local Window for new size */
153 out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
154 sync_law(&im->sysconf.ddrlaw.ar);
155
156 return msize;
157 }
158