1 /* 2 * (C) Copyright 2003 3 * MuLogic B.V. 4 * 5 * (C) Copyright 2002 6 * Simple Network Magic Corporation 7 * 8 * (C) Copyright 2000 9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 /* 31 * board/config.h - configuration options, board specific 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* various debug settings */ 38 #undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ 39 #undef CONFIG_SILENT_CONSOLE /* silent console */ 40 #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ 41 #undef DEBUG_FLASH /* debug flash code */ 42 #undef FLASH_DEBUG /* debug fash code */ 43 #undef DEBUG_ENV /* debug environment code */ 44 45 #define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ 46 #define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ 47 48 /* 49 * High Level Configuration Options 50 * (easy to change) 51 */ 52 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 53 #define CONFIG_QS850 1 /* ...on a QS850 module */ 54 #define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ 55 56 /* Select the target clock speed */ 57 #undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ 58 #undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ 59 #undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ 60 #define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ 61 #undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ 62 63 #ifdef CONFIG_CLOCK_16MHZ 64 #define CONFIG_CLOCK_MULT 512 65 #endif 66 67 #ifdef CONFIG_CLOCK_33MHZ 68 #define CONFIG_CLOCK_MULT 1024 69 #endif 70 71 #ifdef CONFIG_CLOCK_50MHZ 72 #define CONFIG_CLOCK_MULT 1525 73 #endif 74 75 #ifdef CONFIG_CLOCK_66MHZ 76 #define CONFIG_CLOCK_MULT 2048 77 #endif 78 79 #ifdef CONFIG_CLOCK_80MHZ 80 #define CONFIG_CLOCK_MULT 2441 81 #endif 82 83 /* choose flash size, 4Mb or 8Mb */ 84 #define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ 85 #undef CONFIG_FLASH_8MB /* board has 8Mb flash */ 86 87 #define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ 88 89 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 90 #undef CONFIG_8xx_CONS_SMC2 91 #undef CONFIG_8xx_CONS_NONE 92 93 #define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ 94 95 #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ 96 97 /* Define default IP addresses */ 98 #define CONFIG_IPADDR 192.168.1.99 /* own ip address */ 99 #define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ 100 101 /* message to say directly after booting */ 102 #define CONFIG_PREBOOT "echo '';" \ 103 "echo 'type:';" \ 104 "echo 'run boot_nfs to boot to NFS';" \ 105 "echo 'run boot_flash to boot to flash';" \ 106 "echo '';" \ 107 "echo 'run flash_rootfs to install a new rootfs';" \ 108 "echo 'run flash_env to clear the env sector';" \ 109 "echo 'run flash_rw to clear the rw fs';" \ 110 "echo 'run flash_uboot to install a new u-boot';" \ 111 "echo 'run flash_kernel to install a new kernel';" 112 113 /* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ 114 #define CONFIG_BOOTDELAY 5 115 #define CONFIG_BOOTCOMMAND "run boot_nfs" 116 117 #undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ 118 119 /* Our flash filesystem looks like this 120 * 121 * 4Mb board: 122 * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) 123 * ffec 0000 - ffed ffff read-write filesystem (ext2) 124 * ffee 0000 - ffef ffff environment 125 * fff0 0000 - fff1 ffff u-boot 126 * fff2 0000 - ffff ffff linux kernel 127 * 128 * 8Mb board: 129 * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) 130 * ffec 0000 - ffed ffff read-write filesystem (ext2) 131 * ffee 0000 - ffef ffff environment 132 * fff0 0000 - fff1 ffff u-boot 133 * fff2 0000 - ffff ffff linux kernel 134 * 135 */ 136 137 /* environment for 4Mb board */ 138 #ifdef CONFIG_FLASH_4MB 139 #define CONFIG_EXTRA_ENV_SETTINGS \ 140 "serial#=QS850\0" \ 141 "hostname=qs850\0" \ 142 "netdev=eth0\0" \ 143 "ethaddr=00:01:02:B4:36:56\0" \ 144 "rootpath=/exports/rootfs\0" \ 145 "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ 146 /* fill in variables */ \ 147 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ 148 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ 149 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ 150 /* commands */ \ 151 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ 152 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ 153 /* reinstall flash parts */ \ 154 "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ 155 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ 156 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ 157 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ 158 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" 159 #endif /* CONFIG_FLASH_4MB */ 160 161 /* environment for 8Mb board */ 162 #ifdef CONFIG_FLASH_8MB 163 #define CONFIG_EXTRA_ENV_SETTINGS \ 164 "serial#=QS850\0" \ 165 "hostname=qs850\0" \ 166 "netdev=eth0\0" \ 167 "ethaddr=00:01:02:B4:36:56\0" \ 168 "rootpath=/exports/rootfs\0" \ 169 "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ 170 /* fill in variables */ \ 171 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ 172 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ 173 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ 174 /* commands */ \ 175 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ 176 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ 177 /* reinstall flash parts */ \ 178 "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ 179 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ 180 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ 181 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ 182 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" 183 #endif /* CONFIG_FLASH_8MB */ 184 185 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 186 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 187 #undef CONFIG_WATCHDOG /* watchdog disabled */ 188 #undef CONFIG_STATUS_LED /* Status LED disabled */ 189 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 190 191 /* 192 * BOOTP options 193 */ 194 #define CONFIG_BOOTP_SUBNETMASK 195 #define CONFIG_BOOTP_GATEWAY 196 #define CONFIG_BOOTP_HOSTNAME 197 #define CONFIG_BOOTP_BOOTPATH 198 #define CONFIG_BOOTP_BOOTFILESIZE 199 200 #undef CONFIG_MAC_PARTITION 201 #undef CONFIG_DOS_PARTITION 202 203 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 204 205 206 /* 207 * Command line configuration. 208 */ 209 210 #define CONFIG_CMD_BDI 211 #define CONFIG_CMD_BOOTD 212 #define CONFIG_CMD_CONSOLE 213 #define CONFIG_CMD_DATE 214 #define CONFIG_CMD_SAVEENV 215 #define CONFIG_CMD_FLASH 216 #define CONFIG_CMD_IMI 217 #define CONFIG_CMD_IMMAP 218 #define CONFIG_CMD_MEMORY 219 #define CONFIG_CMD_NET 220 #define CONFIG_CMD_RUN 221 222 223 /*----------------------------------------------------------------------- 224 * Environment variable storage is in FLASH, one sector before U-boot 225 */ 226 #define CONFIG_ENV_IS_IN_FLASH 1 227 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ 228 #define CONFIG_ENV_SIZE 0x2000 /* 8kb */ 229 #define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */ 230 231 /*----------------------------------------------------------------------- 232 * Miscellaneous configurable options 233 */ 234 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 235 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 236 237 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 238 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 239 240 #if defined(CONFIG_CMD_KGDB) 241 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 242 #else 243 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 244 #endif 245 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 246 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 247 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 248 249 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ 250 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 251 252 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ 253 254 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 255 256 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 257 258 /*----------------------------------------------------------------------- 259 * Low Level Configuration Settings 260 * (address mappings, register initial values, etc.) 261 * You should know what you are doing if you make changes here. 262 */ 263 264 /*----------------------------------------------------------------------- 265 * Internal Memory Mapped Register 266 */ 267 #define CONFIG_SYS_IMMR 0xFF000000 268 269 /*----------------------------------------------------------------------- 270 * Definitions for initial stack pointer and data area (in DPRAM) 271 */ 272 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 273 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 274 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 275 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 276 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 277 278 /*----------------------------------------------------------------------- 279 * Start addresses for the final memory configuration 280 * (Set up by the startup code) 281 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 282 */ 283 #define CONFIG_SYS_SDRAM_BASE 0x00000000 284 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ 285 286 #define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ 287 #define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ 288 289 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 290 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */ 291 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 292 293 /* 294 * For booting Linux, the board info and command line data 295 * have to be in the first 8 MB of memory, since this is 296 * the maximum mapped by the Linux kernel during initialization. 297 */ 298 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 299 300 /*----------------------------------------------------------------------- 301 * TODO flash parameters 302 * FLASH organization for Intel Strataflash 303 */ 304 #undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */ 305 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 306 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 307 308 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 309 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 310 311 /*----------------------------------------------------------------------- 312 * Cache Configuration 313 */ 314 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 315 #if defined(CONFIG_CMD_KGDB) 316 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 317 #endif 318 319 /*----------------------------------------------------------------------- 320 * SYPCR - System Protection Control 11-9 321 * SYPCR can only be written once after reset! 322 *----------------------------------------------------------------------- 323 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 324 */ 325 326 #ifdef CONFIG_WATCHDOG 327 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) 328 #else 329 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) 330 #endif 331 332 /*----------------------------------------------------------------------- 333 * SIUMCR - SIU Module Configuration 11-6 334 *----------------------------------------------------------------------- 335 */ 336 #define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) 337 338 /*----------------------------------------------------------------------- 339 * TBSCR - Time Base Status and Control 11-26 340 *----------------------------------------------------------------------- 341 */ 342 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 343 344 /*----------------------------------------------------------------------- 345 * RTCSC - Real-Time Clock Status and Control Register 11-27 346 *----------------------------------------------------------------------- 347 */ 348 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 349 350 /*----------------------------------------------------------------------- 351 * PISCR - Periodic Interrupt Status and Control 11-31 352 *----------------------------------------------------------------------- 353 */ 354 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 355 356 /*----------------------------------------------------------------------- 357 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 358 *----------------------------------------------------------------------- 359 */ 360 361 /* MF (Multiplication Factor of SPLL) */ 362 /* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */ 363 #define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) 364 #define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) 365 366 /*----------------------------------------------------------------------- 367 * SCCR - System Clock and reset Control Register 15-27 368 *----------------------------------------------------------------------- 369 */ 370 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) 371 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) 372 #define CONFIG_SYS_BRGCLK_PRESCALE 1 373 #endif 374 375 #if defined(CONFIG_CLOCK_66MHZ) 376 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) 377 #define CONFIG_SYS_BRGCLK_PRESCALE 4 378 #endif 379 380 #if defined(CONFIG_CLOCK_80MHZ) 381 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) 382 #define CONFIG_SYS_BRGCLK_PRESCALE 4 383 #endif 384 385 #define SCCR_MASK CONFIG_SYS_SCCR 386 387 /*----------------------------------------------------------------------- 388 * Debug Enable Register 389 * 0x73E67C0F - All interrupts handled by BDM 390 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM 391 *----------------------------------------------------------------------- 392 #define CONFIG_SYS_DER 0x73E67C0F 393 #define CONFIG_SYS_DER 0x0082400F 394 395 #------------------------------------------------------------------------- 396 # Program the Debug Enable Register (DER). This register provides the user 397 # with the reason for entering into the debug mode. We want all conditions 398 # to end up as an exception. We don't want to enter into debug mode for 399 # any condition. See the back of of the Development Support section of the 400 # MPC860 User Manual for a description of this register. 401 #------------------------------------------------------------------------- 402 */ 403 #define CONFIG_SYS_DER 0 404 405 /*----------------------------------------------------------------------- 406 * Memory Controller Initialization Constants 407 *----------------------------------------------------------------------- 408 */ 409 410 /* 411 * BR0 and OR0 (AMD dual FLASH devices) 412 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) 413 */ 414 #define CONFIG_SYS_PRELIM_OR_AM 415 #define CONFIG_SYS_OR_TIMING_FLASH 416 417 /* 418 *----------------------------------------------------------------------- 419 * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) 420 * flash that resides on the QS850. 421 *----------------------------------------------------------------------- 422 */ 423 424 /* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ 425 /* represents a minumum 32K block size. */ 426 #define vBR0_BA ((0xFF80 << 16) + (0 << 15)) 427 #define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V) 428 429 /* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ 430 /* which defines a 8 Mbyte memory block. */ 431 #define vOR0_AM ((0xFF80 << 16) + (0 << 15)) 432 433 #if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) 434 /* 0101 = Add a 5 clock cycle wait state */ 435 #define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) 436 #endif 437 438 #if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) 439 /* 0011 = Add a 3 clock cycle wait state */ 440 /* 29.8ns clock * (3 + 2) = 149ns cycle time */ 441 #define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) 442 #endif 443 444 #if defined(CONFIG_CLOCK_16MHZ) 445 /* 0010 = Add a 2 clock cycle wait state */ 446 #define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) 447 #endif 448 449 /* 450 * BR1 and OR1 (SDRAM) 451 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) 452 * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) 453 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) 454 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) 455 */ 456 457 #define SDRAM_BASE 0x00000000 /* SDRAM bank */ 458 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ 459 460 /* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which 461 * represents a 128 Mbyte block the DRAM in 462 * this address base. 463 */ 464 #define vOR1_AM ((0xF800 << 16) + (0 << 15)) 465 #define vBR1_BA ((0x0000 << 16) + (0 << 15)) 466 #define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) 467 #define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) 468 469 /* Machine A Mode Register */ 470 471 /* PTA Periodic Timer A */ 472 473 #if defined(CONFIG_CLOCK_80MHZ) 474 #define vMAMR_PTA (19 << 24) 475 #endif 476 477 #if defined(CONFIG_CLOCK_66MHZ) 478 #define vMAMR_PTA (16 << 24) 479 #endif 480 481 #if defined(CONFIG_CLOCK_50MHZ) 482 #define vMAMR_PTA (195 << 24) 483 #endif 484 485 #if defined(CONFIG_CLOCK_33MHZ) 486 #define vMAMR_PTA (131 << 24) 487 #endif 488 489 #if defined(CONFIG_CLOCK_16MHZ) 490 #define vMAMR_PTA (65 << 24) 491 #endif 492 493 /* For boards with 16M of SDRAM */ 494 #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ 495 #define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ 496 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 497 498 /* For boards with 32M of SDRAM */ 499 #define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ 500 #define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ 501 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 502 503 504 /* Memory Periodic Timer Prescaler Register */ 505 506 #if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) 507 /* Divide by 32 */ 508 #define CONFIG_SYS_MPTPR 0x02 509 #endif 510 511 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) 512 /* Divide by 16 */ 513 #define CONFIG_SYS_MPTPR 0x04 514 #endif 515 516 /* 517 * BR2 and OR2 (Unused) 518 * Base address = 0xF020_0000 - 0xF020_0FFF 519 * 520 */ 521 #define CONFIG_SYS_OR2_PRELIM 0xFFF00000 522 #define CONFIG_SYS_BR2_PRELIM 0xF0200000 523 524 /* 525 * BR3 and OR3 (External Bus CS3) 526 * Base address = 0xF030_0000 - 0xF030_0FFF 527 * 528 */ 529 #define CONFIG_SYS_OR3_PRELIM 0xFFF00000 530 #define CONFIG_SYS_BR3_PRELIM 0xF0300000 531 532 /* 533 * BR4 and OR4 (External Bus CS3) 534 * Base address = 0xF040_0000 - 0xF040_0FFF 535 * 536 */ 537 #define CONFIG_SYS_OR4_PRELIM 0xFFF00000 538 #define CONFIG_SYS_BR4_PRELIM 0xF0400000 539 540 541 /* 542 * BR4 and OR4 (External Bus CS3) 543 * Base address = 0xF050_0000 - 0xF050_0FFF 544 * 545 */ 546 #define CONFIG_SYS_OR5_PRELIM 0xFFF00000 547 #define CONFIG_SYS_BR5_PRELIM 0xF0500000 548 549 /* 550 * BR6 and OR6 (Unused) 551 * Base address = 0xF060_0000 - 0xF060_0FFF 552 * 553 */ 554 #define CONFIG_SYS_OR6_PRELIM 0xFFF00000 555 #define CONFIG_SYS_BR6_PRELIM 0xF0600000 556 557 /* 558 * BR7 and OR7 (Unused) 559 * Base address = 0xF070_0000 - 0xF070_0FFF 560 * 561 */ 562 #define CONFIG_SYS_OR7_PRELIM 0xFFF00000 563 #define CONFIG_SYS_BR7_PRELIM 0xF0700000 564 565 /* 566 * Internal Definitions 567 * 568 * Boot Flags 569 */ 570 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 571 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 572 573 /* 574 * Sanity checks 575 */ 576 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) 577 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured 578 #endif 579 580 #endif /* __CONFIG_H */ 581