1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6/dts-v1/;
7
8/* First 128KB is for PSCI ATF. */
9/memreserve/ 0x40000000 0x00020000;
10
11#include "fsl-imx8mq.dtsi"
12
13/ {
14	model = "Freescale i.MX8MQ EVK";
15	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
16
17	chosen {
18		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
19	};
20
21	regulators {
22		compatible = "simple-bus";
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		reg_usdhc2_vmmc: usdhc2_vmmc {
27			compatible = "regulator-fixed";
28			regulator-name = "VSD_3V3";
29			regulator-min-microvolt = <3300000>;
30			regulator-max-microvolt = <3300000>;
31			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
32			enable-active-high;
33		};
34	};
35
36	pwmleds {
37		compatible = "pwm-leds";
38
39		ledpwm2 {
40			label = "PWM2";
41			pwms = <&pwm2 0 50000>;
42			max-brightness = <255>;
43		};
44	};
45};
46
47&iomuxc {
48	pinctrl-names = "default";
49
50	imx8mq-evk {
51		pinctrl_fec1: fec1grp {
52			fsl,pins = <
53				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
54				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
55				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
56				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
57				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
58				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
59				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
60				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
61				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
62				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
63				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
64				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
65				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
66				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
67				MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
68			>;
69		};
70
71		pinctrl_i2c1: i2c1grp {
72			fsl,pins = <
73				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL	0x4000007f
74				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA	0x4000007f
75			>;
76		};
77
78		pinctrl_i2c2: i2c2grp {
79			fsl,pins = <
80				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL	0x4000007f
81				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA	0x4000007f
82			>;
83		};
84
85		pinctrl_pwm2: pwm2grp {
86			fsl,pins = <
87				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16
88			>;
89		};
90
91		pinctrl_qspi: qspigrp {
92			fsl,pins = <
93				MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
94				MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
95				MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
96				MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
97				MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
98				MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
99
100			>;
101		};
102
103		pinctrl_usdhc1: usdhc1grp {
104			fsl,pins = <
105				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83
106				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3
107				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc3
108				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc3
109				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc3
110				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc3
111				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc3
112				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc3
113				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc3
114				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc3
115				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83
116				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
117			>;
118		};
119
120		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
121			fsl,pins = <
122				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85
123				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5
124				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc5
125				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc5
126				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc5
127				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc5
128				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc5
129				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc5
130				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc5
131				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc5
132				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85
133				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
134			>;
135		};
136
137		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
138			fsl,pins = <
139				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87
140				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7
141				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc7
142				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc7
143				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc7
144				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc7
145				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc7
146				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc7
147				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc7
148				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc7
149				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87
150				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
151			>;
152		};
153
154		pinctrl_usdhc2_gpio: usdhc2grpgpio {
155			fsl,pins = <
156				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
157				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
158			>;
159		};
160
161		pinctrl_usdhc2: usdhc2grp {
162			fsl,pins = <
163				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
164				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
165				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
166				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
167				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
168				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
169				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
170			>;
171		};
172
173		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
174			fsl,pins = <
175				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85
176				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5
177				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc5
178				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc5
179				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc5
180				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc5
181				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
182			>;
183		};
184
185		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
186			fsl,pins = <
187				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x87
188				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7
189				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc7
190				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc7
191				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc7
192				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc7
193				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
194			>;
195		};
196
197		pinctrl_sai2: sai2grp {
198			fsl,pins = <
199				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
200				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
201				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
202				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
203				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
204			>;
205		};
206
207		pinctrl_wdog: wdoggrp {
208			fsl,pins = <
209				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
210			>;
211		};
212	};
213};
214
215&fec1 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_fec1>;
218	phy-mode = "rgmii-id";
219	phy-handle = <&ethphy0>;
220	fsl,magic-packet;
221	status = "okay";
222
223	mdio {
224		#address-cells = <1>;
225		#size-cells = <0>;
226
227		ethphy0: ethernet-phy@0 {
228			compatible = "ethernet-phy-ieee802.3-c22";
229			reg = <0>;
230			at803x,led-act-blind-workaround;
231			at803x,eee-disabled;
232		};
233	};
234};
235
236&i2c1 {
237	clock-frequency = <100000>;
238	pinctrl-names = "default";
239	pinctrl-0 = <&pinctrl_i2c1>;
240	status = "okay";
241
242	pmic: pfuze100@08 {
243		compatible = "fsl,pfuze100";
244		reg = <0x08>;
245
246		regulators {
247			sw1a_reg: sw1ab {
248				regulator-min-microvolt = <300000>;
249				regulator-max-microvolt = <1875000>;
250				regulator-always-on;
251			};
252
253			sw1c_reg: sw1c {
254				regulator-min-microvolt = <300000>;
255				regulator-max-microvolt = <1875000>;
256				regulator-always-on;
257			};
258
259			sw2_reg: sw2 {
260				regulator-min-microvolt = <800000>;
261				regulator-max-microvolt = <3300000>;
262				regulator-always-on;
263			};
264
265			sw3a_reg: sw3ab {
266				regulator-min-microvolt = <400000>;
267				regulator-max-microvolt = <1975000>;
268				regulator-always-on;
269			};
270
271			sw4_reg: sw4 {
272				regulator-min-microvolt = <800000>;
273				regulator-max-microvolt = <3300000>;
274				regulator-always-on;
275			};
276
277			swbst_reg: swbst {
278				regulator-min-microvolt = <5000000>;
279				regulator-max-microvolt = <5150000>;
280			};
281
282			snvs_reg: vsnvs {
283				regulator-min-microvolt = <1000000>;
284				regulator-max-microvolt = <3000000>;
285				regulator-always-on;
286			};
287
288			vref_reg: vrefddr {
289				regulator-always-on;
290			};
291
292			vgen1_reg: vgen1 {
293				regulator-min-microvolt = <800000>;
294				regulator-max-microvolt = <1550000>;
295			};
296
297			vgen2_reg: vgen2 {
298				regulator-min-microvolt = <800000>;
299				regulator-max-microvolt = <1550000>;
300				regulator-always-on;
301			};
302
303			vgen3_reg: vgen3 {
304				regulator-min-microvolt = <1800000>;
305				regulator-max-microvolt = <3300000>;
306				regulator-always-on;
307			};
308
309			vgen4_reg: vgen4 {
310				regulator-min-microvolt = <1800000>;
311				regulator-max-microvolt = <3300000>;
312				regulator-always-on;
313			};
314
315			vgen5_reg: vgen5 {
316				regulator-min-microvolt = <1800000>;
317				regulator-max-microvolt = <3300000>;
318				regulator-always-on;
319			};
320
321			vgen6_reg: vgen6 {
322				regulator-min-microvolt = <1800000>;
323				regulator-max-microvolt = <3300000>;
324			};
325		};
326	};
327};
328
329&i2c2 {
330	clock-frequency = <100000>;
331	pinctrl-names = "default";
332	pinctrl-0 = <&pinctrl_i2c2>;
333	status = "disabled";
334};
335
336&pwm2 {
337	pinctrl-names = "default";
338	pinctrl-0 = <&pinctrl_pwm2>;
339	status = "okay";
340};
341
342&lcdif {
343	status = "okay";
344	disp-dev = "mipi_dsi_northwest";
345	display = <&display0>;
346
347	display0: display@0 {
348		bits-per-pixel = <24>;
349		bus-width = <24>;
350
351		display-timings {
352			native-mode = <&timing0>;
353			timing0: timing0 {
354			clock-frequency = <9200000>;
355			hactive = <480>;
356			vactive = <272>;
357			hfront-porch = <8>;
358			hback-porch = <4>;
359			hsync-len = <41>;
360			vback-porch = <2>;
361			vfront-porch = <4>;
362			vsync-len = <10>;
363
364			hsync-active = <0>;
365			vsync-active = <0>;
366			de-active = <1>;
367			pixelclk-active = <0>;
368			};
369		};
370	};
371};
372
373&qspi {
374	pinctrl-names = "default";
375	pinctrl-0 = <&pinctrl_qspi>;
376	status = "okay";
377
378	flash0: n25q256a@0 {
379		reg = <0>;
380		#address-cells = <1>;
381		#size-cells = <1>;
382		compatible = "micron,n25q256a";
383		spi-max-frequency = <29000000>;
384		spi-nor,ddr-quad-read-dummy = <6>;
385	};
386};
387
388&usdhc1 {
389	pinctrl-names = "default", "state_100mhz", "state_200mhz";
390	pinctrl-0 = <&pinctrl_usdhc1>;
391	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
392	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
393	bus-width = <8>;
394	non-removable;
395	status = "okay";
396};
397
398&usdhc2 {
399	pinctrl-names = "default", "state_100mhz", "state_200mhz";
400	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
401	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
402	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
403	bus-width = <4>;
404	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
405	vmmc-supply = <&reg_usdhc2_vmmc>;
406	status = "okay";
407};
408
409&wdog1 {
410	pinctrl-names = "default";
411	pinctrl-0 = <&pinctrl_wdog>;
412	fsl,ext-reset-output;
413	status = "okay";
414};
415