1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih410-clock.dtsi"
10#include "stih407-family.dtsi"
11#include "stih410-pinctrl.dtsi"
12/ {
13	aliases {
14		bdisp0 = &bdisp0;
15	};
16
17	cpus {
18		cpu@0 {
19			st,syscfg = <&syscfg_core 0x8e0>;
20			st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
21			clocks = <&clk_m_a9>;
22			operating-points-v2 = <&cpu0_opp_table>;
23		};
24		cpu@1 {
25			clocks = <&clk_m_a9>;
26			operating-points-v2 = <&cpu0_opp_table>;
27		};
28	};
29
30	cpu0_opp_table: opp_table0 {
31		compatible = "operating-points-v2";
32		opp-shared;
33
34		opp@1500000000 {
35			opp-supported-hw = <0xffffffff  0xffffffff  0xffffffff>;
36			opp-hz = /bits/ 64 <1500000000>;
37			clock-latency-ns = <10000000>;
38			opp-suspend;
39		};
40		opp@1200000000 {
41			opp-supported-hw = <0xffffffff  0xffffffff  0xffffffff>;
42			opp-hz = /bits/ 64 <1200000000>;
43			clock-latency-ns = <10000000>;
44		};
45		opp@800000000 {
46			opp-supported-hw = <0xffffffff  0xffffffff  0xffffffff>;
47			opp-hz = /bits/ 64 <800000000>;
48			clock-latency-ns = <10000000>;
49		};
50		opp@400000000 {
51			opp-supported-hw = <0xffffffff  0xffffffff  0xffffffff>;
52			opp-hz = /bits/ 64 <400000000>;
53			clock-latency-ns = <10000000>;
54		};
55	};
56
57	soc {
58		syscfg_opp: @08a6583c {
59			compatible = "syscon";
60			reg = <0x08a6583c 0x8>;
61		};
62
63		usb2_picophy1: phy2 {
64			compatible = "st,stih407-usb2-phy";
65			#phy-cells = <0>;
66			st,syscfg = <&syscfg_core 0xf8 0xf4>;
67			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
68				 <&picophyreset STIH407_PICOPHY0_RESET>;
69			reset-names = "global", "port";
70
71			status = "disabled";
72		};
73
74		usb2_picophy2: phy3 {
75			compatible = "st,stih407-usb2-phy";
76			#phy-cells = <0>;
77			st,syscfg = <&syscfg_core 0xfc 0xf4>;
78			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
79				 <&picophyreset STIH407_PICOPHY1_RESET>;
80			reset-names = "global", "port";
81
82			status = "disabled";
83		};
84
85		ohci0: usb@9a03c00 {
86			compatible = "generic-ohci";
87			reg = <0x9a03c00 0x100>;
88			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
89			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
90				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
91			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
92				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
93			reset-names = "power", "softreset";
94
95			phys = <&usb2_picophy1>;
96			phy-names = "usb";
97
98			status = "disabled";
99		};
100
101		ehci0: usb@9a03e00 {
102			compatible = "generic-ehci";
103			reg = <0x9a03e00 0x100>;
104			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
105			pinctrl-names = "default";
106			pinctrl-0 = <&pinctrl_usb0>;
107			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
108				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
109			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
110				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
111			reset-names = "power", "softreset";
112			phys = <&usb2_picophy1>;
113			phy-names = "usb";
114
115			status = "disabled";
116		};
117
118		ohci1: usb@9a83c00 {
119			compatible = "generic-ohci";
120			reg = <0x9a83c00 0x100>;
121			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
122			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
123				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
124			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
125				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
126			reset-names = "power", "softreset";
127
128			phys = <&usb2_picophy2>;
129			phy-names = "usb";
130
131			status = "disabled";
132		};
133
134		ehci1: usb@9a83e00 {
135			compatible = "generic-ehci";
136			reg = <0x9a83e00 0x100>;
137			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
138			pinctrl-names = "default";
139			pinctrl-0 = <&pinctrl_usb1>;
140			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
141				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
142			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
143				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
144			reset-names = "power", "softreset";
145
146			phys = <&usb2_picophy2>;
147			phy-names = "usb";
148
149			status = "disabled";
150		};
151
152		sti-display-subsystem {
153			compatible = "st,sti-display-subsystem";
154			#address-cells = <1>;
155			#size-cells = <1>;
156
157			assigned-clocks	= <&clk_s_d2_quadfs 0>,
158					  <&clk_s_d2_quadfs 1>,
159					  <&clk_s_c0_pll1 0>,
160					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
161					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
162					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
163					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
164					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
165					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
166					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
167					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;
168
169			assigned-clock-parents = <0>,
170						 <0>,
171						 <0>,
172						 <&clk_s_c0_pll1 0>,
173						 <&clk_s_c0_pll1 0>,
174						 <&clk_s_d2_quadfs 0>,
175						 <&clk_s_d2_quadfs 1>,
176						 <&clk_s_d2_quadfs 0>,
177						 <&clk_s_d2_quadfs 0>,
178						 <&clk_s_d2_quadfs 0>,
179						 <&clk_s_d2_quadfs 0>;
180
181			assigned-clock-rates = <297000000>,
182					       <297000000>,
183					       <0>,
184					       <400000000>,
185					       <400000000>;
186
187			ranges;
188
189			sti-compositor@9d11000 {
190				compatible = "st,stih407-compositor";
191				reg = <0x9d11000 0x1000>;
192
193				clock-names = "compo_main",
194					      "compo_aux",
195					      "pix_main",
196					      "pix_aux",
197					      "pix_gdp1",
198					      "pix_gdp2",
199					      "pix_gdp3",
200					      "pix_gdp4",
201					      "main_parent",
202					      "aux_parent";
203
204				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
205					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
206					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
207					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
208					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
209					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
210					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
211					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
212					 <&clk_s_d2_quadfs 0>,
213					 <&clk_s_d2_quadfs 1>;
214
215				reset-names = "compo-main", "compo-aux";
216				resets = <&softreset STIH407_COMPO_SOFTRESET>,
217					 <&softreset STIH407_COMPO_SOFTRESET>;
218				st,vtg = <&vtg_main>, <&vtg_aux>;
219			};
220
221			sti-tvout@8d08000 {
222				compatible = "st,stih407-tvout";
223				reg = <0x8d08000 0x1000>;
224				reg-names = "tvout-reg";
225				reset-names = "tvout";
226				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
227				#address-cells = <1>;
228				#size-cells = <1>;
229				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
230						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
231						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
232						  <&clk_s_d0_flexgen CLK_PCM_0>,
233						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
234						  <&clk_s_d2_flexgen CLK_HDDAC>;
235
236				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
237							 <&clk_tmdsout_hdmi>,
238							 <&clk_s_d2_quadfs 0>,
239							 <&clk_s_d0_quadfs 0>,
240							 <&clk_s_d2_quadfs 0>,
241							 <&clk_s_d2_quadfs 0>;
242			};
243
244			sti_hdmi: sti-hdmi@8d04000 {
245				compatible = "st,stih407-hdmi";
246				#sound-dai-cells = <0>;
247				reg = <0x8d04000 0x1000>;
248				reg-names = "hdmi-reg";
249				interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
250				interrupt-names	= "irq";
251				clock-names = "pix",
252					      "tmds",
253					      "phy",
254					      "audio",
255					      "main_parent",
256					      "aux_parent";
257
258				clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
259					 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
260					 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
261					 <&clk_s_d0_flexgen CLK_PCM_0>,
262					 <&clk_s_d2_quadfs 0>,
263					 <&clk_s_d2_quadfs 1>;
264
265				hdmi,hpd-gpio = <&pio5 3>;
266				reset-names = "hdmi";
267				resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
268				ddc = <&hdmiddc>;
269			};
270
271			sti-hda@8d02000 {
272				compatible = "st,stih407-hda";
273				status = "disabled";
274				reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
275				reg-names = "hda-reg", "video-dacs-ctrl";
276				clock-names = "pix",
277					      "hddac",
278					      "main_parent",
279					      "aux_parent";
280				clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
281					 <&clk_s_d2_flexgen CLK_HDDAC>,
282					 <&clk_s_d2_quadfs 0>,
283					 <&clk_s_d2_quadfs 1>;
284			};
285
286			sti-dvo@8d00400 {
287				compatible = "st,stih407-dvo";
288				status = "disabled";
289				reg = <0x8d00400 0x200>;
290				reg-names = "dvo-reg";
291				clock-names = "dvo_pix",
292					      "dvo",
293					      "main_parent",
294					      "aux_parent";
295				clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>,
296					 <&clk_s_d2_flexgen CLK_DVO>,
297					 <&clk_s_d2_quadfs 0>,
298					 <&clk_s_d2_quadfs 1>;
299				pinctrl-names = "default";
300				pinctrl-0 = <&pinctrl_dvo>;
301			};
302
303			sti-hqvdp@9c000000 {
304				compatible = "st,stih407-hqvdp";
305				reg = <0x9C00000 0x100000>;
306				clock-names = "hqvdp", "pix_main";
307				clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
308					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
309				reset-names = "hqvdp";
310				resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
311				st,vtg = <&vtg_main>;
312			};
313		};
314
315		bdisp0:bdisp@9f10000 {
316			compatible = "st,stih407-bdisp";
317			reg = <0x9f10000 0x1000>;
318			interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
319			clock-names = "bdisp";
320			clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
321		};
322
323		hva@8c85000 {
324			compatible = "st,st-hva";
325			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
326			reg-names = "hva_registers", "hva_esram";
327			interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
328				     <GIC_SPI 59 IRQ_TYPE_NONE>;
329			clock-names = "clk_hva";
330			clocks = <&clk_s_c0_flexgen CLK_HVA>;
331		};
332
333		thermal@91a0000 {
334			compatible = "st,stih407-thermal";
335			reg = <0x91a0000 0x28>;
336			clock-names = "thermal";
337			clocks = <&clk_sysin>;
338			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
339		};
340
341		g1@8c80000 {
342			compatible = "st,g1";
343			reg = <0x8c80000 0x194>;
344			interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
345		};
346
347		temp0{
348			compatible = "st,stih407-thermal";
349			reg = <0x91a0000 0x28>;
350			clock-names = "thermal";
351			clocks = <&clk_sysin>;
352			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
353		};
354
355		delta0 {
356			compatible = "st,delta";
357			clock-names = "delta", "delta-st231", "delta-flash-promip";
358			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
359			    <&clk_s_c0_flexgen CLK_ST231_DMU>,
360			    <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
361		};
362
363		h264pp0: h264pp@8c00000 {
364			compatible = "st,h264pp";
365			reg = <0x8c00000 0x20000>;
366			interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
367			clock-names = "clk_h264pp_0";
368			clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
369		};
370
371		mali: mali@09f00000 {
372			compatible	= "arm,mali-400";
373			reg		= <0x09f00000 0x10000>;
374			interrupts	= <GIC_SPI 49 IRQ_TYPE_NONE>,
375					  <GIC_SPI 50 IRQ_TYPE_NONE>,
376					  <GIC_SPI 41 IRQ_TYPE_NONE>,
377					  <GIC_SPI 45 IRQ_TYPE_NONE>,
378					  <GIC_SPI 42 IRQ_TYPE_NONE>,
379					  <GIC_SPI 46 IRQ_TYPE_NONE>,
380					  <GIC_SPI 43 IRQ_TYPE_NONE>,
381					  <GIC_SPI 47 IRQ_TYPE_NONE>,
382					  <GIC_SPI 44 IRQ_TYPE_NONE>,
383					  <GIC_SPI 48 IRQ_TYPE_NONE>;
384			interrupt-names = "IRQGP",
385					  "IRQGPMMU",
386					  "IRQPP0",
387					  "IRQPPMMU0",
388					  "IRQPP1",
389					  "IRQPPMMU1",
390					  "IRQPP2",
391					  "IRQPPMMU2",
392					  "IRQPP3",
393					  "IRQPPMMU3";
394			clock-names	= "gpu-clk";
395			clocks		= <&clk_s_c0_flexgen CLK_ICN_GPU>;
396			reset-names	= "gpu";
397			resets		= <&softreset STIH407_GPU_SOFTRESET>;
398		};
399
400		delta0 {
401			compatible = "st,st-delta";
402			clock-names = "delta",
403				      "delta-st231",
404				      "delta-flash-promip";
405			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
406				 <&clk_s_c0_flexgen CLK_ST231_DMU>,
407				 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
408		};
409
410		h264pp0: h264pp@8c00000 {
411			compatible = "st,h264pp";
412			reg = <0x8c00000 0x20000>;
413			interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
414			clock-names = "clk_h264pp_0";
415			clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
416		};
417
418		mali: mali@09f00000 {
419			compatible	= "arm,mali-400";
420			reg		= <0x09f00000 0x10000>;
421			interrupts	= <GIC_SPI 49 IRQ_TYPE_NONE>,
422					  <GIC_SPI 50 IRQ_TYPE_NONE>,
423					  <GIC_SPI 41 IRQ_TYPE_NONE>,
424					  <GIC_SPI 45 IRQ_TYPE_NONE>,
425					  <GIC_SPI 42 IRQ_TYPE_NONE>,
426					  <GIC_SPI 46 IRQ_TYPE_NONE>,
427					  <GIC_SPI 43 IRQ_TYPE_NONE>,
428					  <GIC_SPI 47 IRQ_TYPE_NONE>,
429					  <GIC_SPI 44 IRQ_TYPE_NONE>,
430					  <GIC_SPI 48 IRQ_TYPE_NONE>;
431			interrupt-names = "IRQGP",
432					  "IRQGPMMU",
433					  "IRQPP0",
434					  "IRQPPMMU0",
435					  "IRQPP1",
436					  "IRQPPMMU1",
437					  "IRQPP2",
438					  "IRQPPMMU2",
439					  "IRQPP3",
440					  "IRQPPMMU3";
441			clock-names	= "gpu-clk";
442			clocks		= <&clk_s_c0_flexgen CLK_ICN_GPU>;
443			reset-names	= "gpu";
444			resets		= <&softreset STIH407_GPU_SOFTRESET>;
445		};
446
447		hva@8c85000{
448			compatible = "st,st-hva";
449			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
450			reg-names = "hva_registers", "hva_esram";
451			interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
452				     <GIC_SPI 59 IRQ_TYPE_NONE>;
453			clock-names = "clk_hva";
454			clocks = <&clk_s_c0_flexgen CLK_HVA>;
455		};
456	};
457};
458