1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Xilinx CSE NAND board DTS
4 *
5 * Copyright (C) 2018 Xilinx, Inc.
6 */
7/dts-v1/;
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	model = "Zynq CSE NAND Board";
13	compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
14
15	aliases {
16		serial0 = &dcc;
17	};
18
19	memory@0 {
20		device_type = "memory";
21		reg = <0x0 0x400000>;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	dcc: dcc {
29		compatible = "arm,dcc";
30		status = "disabled";
31		u-boot,dm-pre-reloc;
32	};
33
34	amba: amba {
35		u-boot,dm-pre-reloc;
36		compatible = "simple-bus";
37		#address-cells = <1>;
38		#size-cells = <1>;
39		ranges;
40
41		slcr: slcr@f8000000 {
42			u-boot,dm-pre-reloc;
43			#address-cells = <1>;
44			#size-cells = <1>;
45			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
46			reg = <0xF8000000 0x1000>;
47			ranges;
48			clkc: clkc@100 {
49				u-boot,dm-pre-reloc;
50				#clock-cells = <1>;
51				compatible = "xlnx,ps7-clkc";
52				clock-output-names = "armpll", "ddrpll",
53						"iopll", "cpu_6or4x",
54						"cpu_3or2x", "cpu_2x", "cpu_1x",
55						"ddr2x", "ddr3x", "dci",
56						"lqspi", "smc", "pcap", "gem0",
57						"gem1", "fclk0", "fclk1",
58						"fclk2", "fclk3", "can0",
59						"can1", "sdio0", "sdio1",
60						"uart0", "uart1", "spi0",
61						"spi1", "dma", "usb0_aper",
62						"usb1_aper", "gem0_aper",
63						"gem1_aper", "sdio0_aper",
64						"sdio1_aper", "spi0_aper",
65						"spi1_aper", "can0_aper",
66						"can1_aper", "i2c0_aper",
67						"i2c1_aper", "uart0_aper",
68						"uart1_aper", "gpio_aper",
69						"lqspi_aper", "smc_aper",
70						"swdt", "dbg_trc", "dbg_apb";
71				reg = <0x100 0x100>;
72			};
73		};
74	};
75};
76
77&dcc {
78	status = "okay";
79};
80