1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/arch/tegra.h> 9 #include <asm/arch-tegra/pmc.h> 10 #include "../cpu.h" 11 enable_cpu_power_rail(void)12static void enable_cpu_power_rail(void) 13 { 14 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 15 u32 reg; 16 17 reg = readl(&pmc->pmc_cntrl); 18 reg |= CPUPWRREQ_OE; 19 writel(reg, &pmc->pmc_cntrl); 20 21 /* 22 * The TI PMU65861C needs a 3.75ms delay between enabling 23 * the power rail and enabling the CPU clock. This delay 24 * between SM1EN and SM1 is for switching time + the ramp 25 * up of the voltage to the CPU (VDD_CPU from PMU). 26 */ 27 udelay(3750); 28 } 29 start_cpu(u32 reset_vector)30void start_cpu(u32 reset_vector) 31 { 32 /* Enable VDD_CPU */ 33 enable_cpu_power_rail(); 34 35 /* Hold the CPUs in reset */ 36 reset_A9_cpu(1); 37 38 /* Disable the CPU clock */ 39 enable_cpu_clock(0); 40 41 /* Enable CoreSight */ 42 clock_enable_coresight(1); 43 44 /* 45 * Set the entry point for CPU execution from reset, 46 * if it's a non-zero value. 47 */ 48 if (reset_vector) 49 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 50 51 /* Enable the CPU clock */ 52 enable_cpu_clock(1); 53 54 /* If the CPU doesn't already have power, power it up */ 55 powerup_cpu(); 56 57 /* Take the CPU out of reset */ 58 reset_A9_cpu(0); 59 } 60