1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 */
5
6 /*
7 * PCI Configuration space access support for MPC83xx PCI Bridge
8 */
9 #include <asm/mmu.h>
10 #include <asm/io.h>
11 #include <common.h>
12 #include <mpc83xx.h>
13 #include <pci.h>
14 #include <i2c.h>
15 #include <asm/fsl_i2c.h>
16 #include "../common/pq-mds-pib.h"
17
18 static struct pci_region pci1_regions[] = {
19 {
20 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
21 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
22 size: CONFIG_SYS_PCI1_MEM_SIZE,
23 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
24 },
25 {
26 bus_start: CONFIG_SYS_PCI1_IO_BASE,
27 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
28 size: CONFIG_SYS_PCI1_IO_SIZE,
29 flags: PCI_REGION_IO
30 },
31 {
32 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
33 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
34 size: CONFIG_SYS_PCI1_MMIO_SIZE,
35 flags: PCI_REGION_MEM
36 },
37 };
38
39 #ifdef CONFIG_MPC83XX_PCI2
40 static struct pci_region pci2_regions[] = {
41 {
42 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
43 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
44 size: CONFIG_SYS_PCI2_MEM_SIZE,
45 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
46 },
47 {
48 bus_start: CONFIG_SYS_PCI2_IO_BASE,
49 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
50 size: CONFIG_SYS_PCI2_IO_SIZE,
51 flags: PCI_REGION_IO
52 },
53 {
54 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
55 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
56 size: CONFIG_SYS_PCI2_MMIO_SIZE,
57 flags: PCI_REGION_MEM
58 },
59 };
60 #endif
61
pci_init_board(void)62 void pci_init_board(void)
63 #ifdef CONFIG_PCISLAVE
64 {
65 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
66 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
67 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
68 struct pci_region *reg[] = { pci1_regions };
69
70 /* Configure PCI Local Access Windows */
71 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
72 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
73
74 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
75 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
76
77 mpc83xx_pci_init(1, reg);
78
79 /*
80 * Configure PCI Inbound Translation Windows
81 */
82 pci_ctrl[0].pitar0 = 0x0;
83 pci_ctrl[0].pibar0 = 0x0;
84 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
85 PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
86
87 pci_ctrl[0].pitar1 = 0x0;
88 pci_ctrl[0].pibar1 = 0x0;
89 pci_ctrl[0].piebar1 = 0x0;
90 pci_ctrl[0].piwar1 &= ~PIWAR_EN;
91
92 pci_ctrl[0].pitar2 = 0x0;
93 pci_ctrl[0].pibar2 = 0x0;
94 pci_ctrl[0].piebar2 = 0x0;
95 pci_ctrl[0].piwar2 &= ~PIWAR_EN;
96
97 /* Unlock the configuration bit */
98 mpc83xx_pcislave_unlock(0);
99 printf("PCI: Agent mode enabled\n");
100 }
101 #else
102 {
103 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
104 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
105 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
106 #ifndef CONFIG_MPC83XX_PCI2
107 struct pci_region *reg[] = { pci1_regions };
108 #else
109 struct pci_region *reg[] = { pci1_regions, pci2_regions };
110 #endif
111
112 /* initialize the PCA9555PW IO expander on the PIB board */
113 pib_init();
114
115 #if defined(CONFIG_PCI_66M)
116 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
117 printf("PCI clock is 66MHz\n");
118 #elif defined(CONFIG_PCI_33M)
119 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
120 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
121 printf("PCI clock is 33MHz\n");
122 #else
123 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
124 printf("PCI clock is 66MHz\n");
125 #endif
126 udelay(2000);
127
128 /* Configure PCI Local Access Windows */
129 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
130 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
131
132 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
133 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
134
135 udelay(2000);
136
137 #ifndef CONFIG_MPC83XX_PCI2
138 mpc83xx_pci_init(1, reg);
139 #else
140 mpc83xx_pci_init(2, reg);
141 #endif
142 }
143 #endif /* CONFIG_PCISLAVE */
144