1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
9 *
10 * Permission to use, copy, modify, and distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
12 * copyright notice and this permission notice appear in all copies.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 *
22 */
23
24 FILE_LICENCE ( MIT );
25
26 #define _ATH5K_RESET
27
28 /*****************************\
29 Reset functions and helpers
30 \*****************************/
31
32 #include <ipxe/pci.h> /* To determine if a card is pci-e */
33 #include <unistd.h>
34
35 #include "ath5k.h"
36 #include "reg.h"
37 #include "base.h"
38
39 /* Find last set bit; fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32 */
fls(int x)40 static int fls(int x)
41 {
42 int r = 32;
43
44 if (!x)
45 return 0;
46 if (!(x & 0xffff0000u)) {
47 x <<= 16;
48 r -= 16;
49 }
50 if (!(x & 0xff000000u)) {
51 x <<= 8;
52 r -= 8;
53 }
54 if (!(x & 0xf0000000u)) {
55 x <<= 4;
56 r -= 4;
57 }
58 if (!(x & 0xc0000000u)) {
59 x <<= 2;
60 r -= 2;
61 }
62 if (!(x & 0x80000000u)) {
63 x <<= 1;
64 r -= 1;
65 }
66 return r;
67 }
68
69
70 /**
71 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
72 *
73 * @ah: the &struct ath5k_hw
74 * @channel: the currently set channel upon reset
75 *
76 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
77 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
78 *
79 * Since delta slope is floating point we split it on its exponent and
80 * mantissa and provide these values on hw.
81 *
82 * For more infos i think this patent is related
83 * http://www.freepatentsonline.com/7184495.html
84 */
ath5k_hw_write_ofdm_timings(struct ath5k_hw * ah,struct net80211_channel * channel)85 static int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
86 struct net80211_channel *channel)
87 {
88 /* Get exponent and mantissa and set it */
89 u32 coef_scaled, coef_exp, coef_man,
90 ds_coef_exp, ds_coef_man, clock;
91
92 if (!(ah->ah_version == AR5K_AR5212) ||
93 !(channel->hw_value & CHANNEL_OFDM)) {
94 DBG("ath5k: attempt to set OFDM timings on non-OFDM channel\n");
95 return -EFAULT;
96 }
97
98 /* Get coefficient
99 * ALGO: coef = (5 * clock * carrier_freq) / 2)
100 * we scale coef by shifting clock value by 24 for
101 * better precision since we use integers */
102 /* TODO: Half/quarter rate */
103 clock = ath5k_hw_htoclock(1, channel->hw_value & CHANNEL_TURBO);
104
105 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
106
107 /* Get exponent
108 * ALGO: coef_exp = 14 - highest set bit position */
109 coef_exp = fls(coef_scaled) - 1;
110
111 /* Doesn't make sense if it's zero*/
112 if (!coef_scaled || !coef_exp)
113 return -EINVAL;
114
115 /* Note: we've shifted coef_scaled by 24 */
116 coef_exp = 14 - (coef_exp - 24);
117
118
119 /* Get mantissa (significant digits)
120 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
121 coef_man = coef_scaled +
122 (1 << (24 - coef_exp - 1));
123
124 /* Calculate delta slope coefficient exponent
125 * and mantissa (remove scaling) and set them on hw */
126 ds_coef_man = coef_man >> (24 - coef_exp);
127 ds_coef_exp = coef_exp - 16;
128
129 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
130 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
131 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
132 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
133
134 return 0;
135 }
136
137 /**
138 * ath5k_hw_write_rate_duration - fill rate code to duration table
139 *
140 * @ah: the &struct ath5k_hw
141 * @mode: one of enum ath5k_driver_mode
142 *
143 * Write the rate code to duration table upon hw reset. This is a helper for
144 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on
145 * the hardware, based on current mode, for each rate. The rates which are
146 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
147 * different rate code so we write their value twice (one for long preample
148 * and one for short).
149 *
150 * Note: Band doesn't matter here, if we set the values for OFDM it works
151 * on both a and g modes. So all we have to do is set values for all g rates
152 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
153 * quarter rate mode, we need to use another set of bitrates (that's why we
154 * need the mode parameter) but we don't handle these proprietary modes yet.
155 */
ath5k_hw_write_rate_duration(struct ath5k_hw * ah,unsigned int mode __unused)156 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
157 unsigned int mode __unused)
158 {
159 struct ath5k_softc *sc = ah->ah_sc;
160 u16 rate;
161 int i;
162
163 /* Write rate duration table */
164 for (i = 0; i < sc->hwinfo->nr_rates[NET80211_BAND_2GHZ]; i++) {
165 u32 reg;
166 u16 tx_time;
167
168 rate = sc->hwinfo->rates[NET80211_BAND_2GHZ][i];
169
170 /* Set ACK timeout */
171 reg = AR5K_RATE_DUR(ath5k_bitrate_to_hw_rix(rate));
172
173 /* An ACK frame consists of 10 bytes. If you add the FCS,
174 * it's 14 bytes. Note we use the control rate and not the
175 * actual rate for this rate. See mac80211 tx.c
176 * ieee80211_duration() for a brief description of
177 * what rate we should choose to TX ACKs. */
178 tx_time = net80211_duration(sc->dev, 14, rate);
179
180 ath5k_hw_reg_write(ah, tx_time, reg);
181
182 if (rate != 20 && rate != 55 && rate != 110)
183 continue;
184
185 /*
186 * We're not distinguishing short preamble here,
187 * This is true, all we'll get is a longer value here
188 * which is not necessarilly bad.
189 */
190 ath5k_hw_reg_write(ah, tx_time,
191 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
192 }
193 }
194
195 /*
196 * Reset chipset
197 */
ath5k_hw_nic_reset(struct ath5k_hw * ah,u32 val)198 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
199 {
200 int ret;
201 u32 mask = val ? val : ~0U;
202
203 /* Read-and-clear RX Descriptor Pointer*/
204 ath5k_hw_reg_read(ah, AR5K_RXDP);
205
206 /*
207 * Reset the device and wait until success
208 */
209 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
210
211 /* Wait at least 128 PCI clocks */
212 udelay(15);
213
214 if (ah->ah_version == AR5K_AR5210) {
215 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
216 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
217 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
218 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
219 } else {
220 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
221 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
222 }
223
224 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, 0);
225
226 /*
227 * Reset configuration register (for hw byte-swap). Note that this
228 * is only set for big endian. We do the necessary magic in
229 * AR5K_INIT_CFG.
230 */
231 if ((val & AR5K_RESET_CTL_PCU) == 0)
232 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
233
234 return ret;
235 }
236
237 /*
238 * Sleep control
239 */
ath5k_hw_wake(struct ath5k_hw * ah)240 int ath5k_hw_wake(struct ath5k_hw *ah)
241 {
242 unsigned int i;
243 u32 staid, data;
244
245 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
246 staid &= ~AR5K_STA_ID1_PWR_SV;
247
248 /* Preserve sleep duration */
249 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
250 if (data & 0xffc00000)
251 data = 0;
252 else
253 data = data & 0xfffcffff;
254
255 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
256 udelay(15);
257
258 for (i = 50; i > 0; i--) {
259 /* Check if the chip did wake up */
260 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
261 AR5K_PCICFG_SPWR_DN) == 0)
262 break;
263
264 /* Wait a bit and retry */
265 udelay(200);
266 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
267 }
268
269 /* Fail if the chip didn't wake up */
270 if (i <= 0)
271 return -EIO;
272
273 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
274
275 return 0;
276 }
277
278 /*
279 * Bring up MAC + PHY Chips and program PLL
280 * TODO: Half/Quarter rate support
281 */
ath5k_hw_nic_wakeup(struct ath5k_hw * ah,int flags,int initial __unused)282 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial __unused)
283 {
284 struct pci_device *pdev = ah->ah_sc->pdev;
285 u32 turbo, mode, clock, bus_flags;
286 int ret;
287
288 turbo = 0;
289 mode = 0;
290 clock = 0;
291
292 /* Wakeup the device */
293 ret = ath5k_hw_wake(ah);
294 if (ret) {
295 DBG("ath5k: failed to wake up the MAC chip\n");
296 return ret;
297 }
298
299 if (ah->ah_version != AR5K_AR5210) {
300 /*
301 * Get channel mode flags
302 */
303
304 if (ah->ah_radio >= AR5K_RF5112) {
305 mode = AR5K_PHY_MODE_RAD_RF5112;
306 clock = AR5K_PHY_PLL_RF5112;
307 } else {
308 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
309 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
310 }
311
312 if (flags & CHANNEL_2GHZ) {
313 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
314 clock |= AR5K_PHY_PLL_44MHZ;
315
316 if (flags & CHANNEL_CCK) {
317 mode |= AR5K_PHY_MODE_MOD_CCK;
318 } else if (flags & CHANNEL_OFDM) {
319 /* XXX Dynamic OFDM/CCK is not supported by the
320 * AR5211 so we set MOD_OFDM for plain g (no
321 * CCK headers) operation. We need to test
322 * this, 5211 might support ofdm-only g after
323 * all, there are also initial register values
324 * in the code for g mode (see initvals.c). */
325 if (ah->ah_version == AR5K_AR5211)
326 mode |= AR5K_PHY_MODE_MOD_OFDM;
327 else
328 mode |= AR5K_PHY_MODE_MOD_DYN;
329 } else {
330 DBG("ath5k: invalid radio modulation mode\n");
331 return -EINVAL;
332 }
333 } else if (flags & CHANNEL_5GHZ) {
334 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
335
336 if (ah->ah_radio == AR5K_RF5413)
337 clock = AR5K_PHY_PLL_40MHZ_5413;
338 else
339 clock |= AR5K_PHY_PLL_40MHZ;
340
341 if (flags & CHANNEL_OFDM)
342 mode |= AR5K_PHY_MODE_MOD_OFDM;
343 else {
344 DBG("ath5k: invalid radio modulation mode\n");
345 return -EINVAL;
346 }
347 } else {
348 DBG("ath5k: invalid radio frequency mode\n");
349 return -EINVAL;
350 }
351
352 if (flags & CHANNEL_TURBO)
353 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
354 } else { /* Reset the device */
355
356 /* ...enable Atheros turbo mode if requested */
357 if (flags & CHANNEL_TURBO)
358 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
359 AR5K_PHY_TURBO);
360 }
361
362 /* reseting PCI on PCI-E cards results card to hang
363 * and always return 0xffff... so we ingore that flag
364 * for PCI-E cards */
365 if (pci_find_capability(pdev, PCI_CAP_ID_EXP))
366 bus_flags = 0;
367 else
368 bus_flags = AR5K_RESET_CTL_PCI;
369
370 /* Reset chipset */
371 if (ah->ah_version == AR5K_AR5210) {
372 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
373 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
374 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
375 mdelay(2);
376 } else {
377 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
378 AR5K_RESET_CTL_BASEBAND | bus_flags);
379 }
380 if (ret) {
381 DBG("ath5k: failed to reset the MAC chip\n");
382 return -EIO;
383 }
384
385 /* ...wakeup again!*/
386 ret = ath5k_hw_wake(ah);
387 if (ret) {
388 DBG("ath5k: failed to resume the MAC chip\n");
389 return ret;
390 }
391
392 /* ...final warm reset */
393 if (ath5k_hw_nic_reset(ah, 0)) {
394 DBG("ath5k: failed to warm reset the MAC chip\n");
395 return -EIO;
396 }
397
398 if (ah->ah_version != AR5K_AR5210) {
399
400 /* ...update PLL if needed */
401 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
402 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
403 udelay(300);
404 }
405
406 /* ...set the PHY operating mode */
407 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
408 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
409 }
410
411 return 0;
412 }
413
ath5k_hw_chan_has_spur_noise(struct ath5k_hw * ah,struct net80211_channel * channel)414 static int ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
415 struct net80211_channel *channel)
416 {
417 u8 refclk_freq;
418
419 if ((ah->ah_radio == AR5K_RF5112) ||
420 (ah->ah_radio == AR5K_RF5413) ||
421 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
422 refclk_freq = 40;
423 else
424 refclk_freq = 32;
425
426 if ((channel->center_freq % refclk_freq != 0) &&
427 ((channel->center_freq % refclk_freq < 10) ||
428 (channel->center_freq % refclk_freq > 22)))
429 return 1;
430 else
431 return 0;
432 }
433
434 /* TODO: Half/Quarter rate */
ath5k_hw_tweak_initval_settings(struct ath5k_hw * ah,struct net80211_channel * channel)435 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
436 struct net80211_channel *channel)
437 {
438 if (ah->ah_version == AR5K_AR5212 &&
439 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
440
441 /* Setup ADC control */
442 ath5k_hw_reg_write(ah,
443 (AR5K_REG_SM(2,
444 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
445 AR5K_REG_SM(2,
446 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
447 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
448 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
449 AR5K_PHY_ADC_CTL);
450
451
452
453 /* Disable barker RSSI threshold */
454 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
455 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
456
457 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
458 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
459
460 /* Set the mute mask */
461 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
462 }
463
464 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
465 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
466 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
467
468 /* Enable DCU double buffering */
469 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
470 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
471 AR5K_TXCFG_DCU_DBL_BUF_DIS);
472
473 /* Set DAC/ADC delays */
474 if (ah->ah_version == AR5K_AR5212) {
475 u32 scal;
476 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
477 scal = AR5K_PHY_SCAL_32MHZ_2417;
478 else if (ath5k_eeprom_is_hb63(ah))
479 scal = AR5K_PHY_SCAL_32MHZ_HB63;
480 else
481 scal = AR5K_PHY_SCAL_32MHZ;
482 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
483 }
484
485 /* Set fast ADC */
486 if ((ah->ah_radio == AR5K_RF5413) ||
487 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
488 u32 fast_adc = 1;
489
490 if (channel->center_freq == 2462 ||
491 channel->center_freq == 2467)
492 fast_adc = 0;
493
494 /* Only update if needed */
495 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
496 ath5k_hw_reg_write(ah, fast_adc,
497 AR5K_PHY_FAST_ADC);
498 }
499
500 /* Fix for first revision of the RF5112 RF chipset */
501 if (ah->ah_radio == AR5K_RF5112 &&
502 ah->ah_radio_5ghz_revision <
503 AR5K_SREV_RAD_5112A) {
504 u32 data;
505 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
506 AR5K_PHY_CCKTXCTL);
507 if (channel->hw_value & CHANNEL_5GHZ)
508 data = 0xffb81020;
509 else
510 data = 0xffb80d20;
511 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
512 }
513
514 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
515 u32 usec_reg;
516 /* 5311 has different tx/rx latency masks
517 * from 5211, since we deal 5311 the same
518 * as 5211 when setting initvals, shift
519 * values here to their proper locations */
520 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
521 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
522 AR5K_USEC_32 |
523 AR5K_USEC_TX_LATENCY_5211 |
524 AR5K_REG_SM(29,
525 AR5K_USEC_RX_LATENCY_5210)),
526 AR5K_USEC_5211);
527 /* Clear QCU/DCU clock gating register */
528 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
529 /* Set DAC/ADC delays */
530 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
531 /* Enable PCU FIFO corruption ECO */
532 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
533 AR5K_DIAG_SW_ECO_ENABLE);
534 }
535 }
536
ath5k_hw_commit_eeprom_settings(struct ath5k_hw * ah,struct net80211_channel * channel,u8 * ant,u8 ee_mode)537 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
538 struct net80211_channel *channel, u8 *ant, u8 ee_mode)
539 {
540 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
541 s16 cck_ofdm_pwr_delta;
542
543 /* Adjust power delta for channel 14 */
544 if (channel->center_freq == 2484)
545 cck_ofdm_pwr_delta =
546 ((ee->ee_cck_ofdm_power_delta -
547 ee->ee_scaled_cck_delta) * 2) / 10;
548 else
549 cck_ofdm_pwr_delta =
550 (ee->ee_cck_ofdm_power_delta * 2) / 10;
551
552 /* Set CCK to OFDM power delta on tx power
553 * adjustment register */
554 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
555 if (channel->hw_value == CHANNEL_G)
556 ath5k_hw_reg_write(ah,
557 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
558 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
559 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
560 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
561 AR5K_PHY_TX_PWR_ADJ);
562 else
563 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
564 } else {
565 /* For older revs we scale power on sw during tx power
566 * setup */
567 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
568 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
569 ee->ee_cck_ofdm_gain_delta;
570 }
571
572 /* Set antenna idle switch table */
573 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
574 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
575 (ah->ah_antenna[ee_mode][0] |
576 AR5K_PHY_ANT_CTL_TXRX_EN));
577
578 /* Set antenna switch table */
579 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
580 AR5K_PHY_ANT_SWITCH_TABLE_0);
581 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
582 AR5K_PHY_ANT_SWITCH_TABLE_1);
583
584 /* Noise floor threshold */
585 ath5k_hw_reg_write(ah,
586 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
587 AR5K_PHY_NFTHRES);
588
589 if ((channel->hw_value & CHANNEL_TURBO) &&
590 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
591 /* Switch settling time (Turbo) */
592 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
593 AR5K_PHY_SETTLING_SWITCH,
594 ee->ee_switch_settling_turbo[ee_mode]);
595
596 /* Tx/Rx attenuation (Turbo) */
597 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
598 AR5K_PHY_GAIN_TXRX_ATTEN,
599 ee->ee_atn_tx_rx_turbo[ee_mode]);
600
601 /* ADC/PGA desired size (Turbo) */
602 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
603 AR5K_PHY_DESIRED_SIZE_ADC,
604 ee->ee_adc_desired_size_turbo[ee_mode]);
605
606 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
607 AR5K_PHY_DESIRED_SIZE_PGA,
608 ee->ee_pga_desired_size_turbo[ee_mode]);
609
610 /* Tx/Rx margin (Turbo) */
611 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
612 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
613 ee->ee_margin_tx_rx_turbo[ee_mode]);
614
615 } else {
616 /* Switch settling time */
617 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
618 AR5K_PHY_SETTLING_SWITCH,
619 ee->ee_switch_settling[ee_mode]);
620
621 /* Tx/Rx attenuation */
622 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
623 AR5K_PHY_GAIN_TXRX_ATTEN,
624 ee->ee_atn_tx_rx[ee_mode]);
625
626 /* ADC/PGA desired size */
627 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
628 AR5K_PHY_DESIRED_SIZE_ADC,
629 ee->ee_adc_desired_size[ee_mode]);
630
631 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
632 AR5K_PHY_DESIRED_SIZE_PGA,
633 ee->ee_pga_desired_size[ee_mode]);
634
635 /* Tx/Rx margin */
636 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
637 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
638 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
639 ee->ee_margin_tx_rx[ee_mode]);
640 }
641
642 /* XPA delays */
643 ath5k_hw_reg_write(ah,
644 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
645 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
646 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
647 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
648
649 /* XLNA delay */
650 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
651 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
652 ee->ee_tx_end2xlna_enable[ee_mode]);
653
654 /* Thresh64 (ANI) */
655 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
656 AR5K_PHY_NF_THRESH62,
657 ee->ee_thr_62[ee_mode]);
658
659
660 /* False detect backoff for channels
661 * that have spur noise. Write the new
662 * cyclic power RSSI threshold. */
663 if (ath5k_hw_chan_has_spur_noise(ah, channel))
664 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
665 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
666 AR5K_INIT_CYCRSSI_THR1 +
667 ee->ee_false_detect[ee_mode]);
668 else
669 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
670 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
671 AR5K_INIT_CYCRSSI_THR1);
672
673 /* I/Q correction
674 * TODO: Per channel i/q infos ? */
675 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
676 AR5K_PHY_IQ_CORR_ENABLE |
677 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
678 ee->ee_q_cal[ee_mode]);
679
680 /* Heavy clipping -disable for now */
681 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
682 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
683
684 return;
685 }
686
687 /*
688 * Main reset function
689 */
ath5k_hw_reset(struct ath5k_hw * ah,struct net80211_channel * channel,int change_channel)690 int ath5k_hw_reset(struct ath5k_hw *ah,
691 struct net80211_channel *channel, int change_channel)
692 {
693 u32 s_seq[10], s_ant, s_led[3], staid1_flags;
694 u32 phy_tst1;
695 u8 mode, freq, ee_mode, ant[2];
696 int i, ret;
697
698 s_ant = 0;
699 ee_mode = 0;
700 staid1_flags = 0;
701 freq = 0;
702 mode = 0;
703
704 /*
705 * Save some registers before a reset
706 */
707 /*DCU/Antenna selection not available on 5210*/
708 if (ah->ah_version != AR5K_AR5210) {
709
710 switch (channel->hw_value & CHANNEL_MODES) {
711 case CHANNEL_A:
712 mode = AR5K_MODE_11A;
713 freq = AR5K_INI_RFGAIN_5GHZ;
714 ee_mode = AR5K_EEPROM_MODE_11A;
715 break;
716 case CHANNEL_G:
717 mode = AR5K_MODE_11G;
718 freq = AR5K_INI_RFGAIN_2GHZ;
719 ee_mode = AR5K_EEPROM_MODE_11G;
720 break;
721 case CHANNEL_B:
722 mode = AR5K_MODE_11B;
723 freq = AR5K_INI_RFGAIN_2GHZ;
724 ee_mode = AR5K_EEPROM_MODE_11B;
725 break;
726 case CHANNEL_T:
727 mode = AR5K_MODE_11A_TURBO;
728 freq = AR5K_INI_RFGAIN_5GHZ;
729 ee_mode = AR5K_EEPROM_MODE_11A;
730 break;
731 case CHANNEL_TG:
732 if (ah->ah_version == AR5K_AR5211) {
733 DBG("ath5k: TurboG not available on 5211\n");
734 return -EINVAL;
735 }
736 mode = AR5K_MODE_11G_TURBO;
737 freq = AR5K_INI_RFGAIN_2GHZ;
738 ee_mode = AR5K_EEPROM_MODE_11G;
739 break;
740 case CHANNEL_XR:
741 if (ah->ah_version == AR5K_AR5211) {
742 DBG("ath5k: XR mode not available on 5211\n");
743 return -EINVAL;
744 }
745 mode = AR5K_MODE_XR;
746 freq = AR5K_INI_RFGAIN_5GHZ;
747 ee_mode = AR5K_EEPROM_MODE_11A;
748 break;
749 default:
750 DBG("ath5k: invalid channel (%d MHz)\n",
751 channel->center_freq);
752 return -EINVAL;
753 }
754
755 if (change_channel) {
756 /*
757 * Save frame sequence count
758 * For revs. after Oahu, only save
759 * seq num for DCU 0 (Global seq num)
760 */
761 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
762
763 for (i = 0; i < 10; i++)
764 s_seq[i] = ath5k_hw_reg_read(ah,
765 AR5K_QUEUE_DCU_SEQNUM(i));
766
767 } else {
768 s_seq[0] = ath5k_hw_reg_read(ah,
769 AR5K_QUEUE_DCU_SEQNUM(0));
770 }
771 }
772
773 /* Save default antenna */
774 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
775
776 if (ah->ah_version == AR5K_AR5212) {
777 /* Since we are going to write rf buffer
778 * check if we have any pending gain_F
779 * optimization settings */
780 if (change_channel && ah->ah_rf_banks != NULL)
781 ath5k_hw_gainf_calibrate(ah);
782 }
783 }
784
785 /*GPIOs*/
786 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
787 AR5K_PCICFG_LEDSTATE;
788 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
789 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
790
791 /* AR5K_STA_ID1 flags, only preserve antenna
792 * settings and ack/cts rate mode */
793 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
794 (AR5K_STA_ID1_DEFAULT_ANTENNA |
795 AR5K_STA_ID1_DESC_ANTENNA |
796 AR5K_STA_ID1_RTS_DEF_ANTENNA |
797 AR5K_STA_ID1_ACKCTS_6MB |
798 AR5K_STA_ID1_BASE_RATE_11B |
799 AR5K_STA_ID1_SELFGEN_DEF_ANT);
800
801 /* Wakeup the device */
802 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, 0);
803 if (ret)
804 return ret;
805
806 /* PHY access enable */
807 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
808 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
809 else
810 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
811 AR5K_PHY(0));
812
813 /* Write initial settings */
814 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
815 if (ret)
816 return ret;
817
818 /*
819 * 5211/5212 Specific
820 */
821 if (ah->ah_version != AR5K_AR5210) {
822
823 /*
824 * Write initial RF gain settings
825 * This should work for both 5111/5112
826 */
827 ret = ath5k_hw_rfgain_init(ah, freq);
828 if (ret)
829 return ret;
830
831 mdelay(1);
832
833 /*
834 * Tweak initval settings for revised
835 * chipsets and add some more config
836 * bits
837 */
838 ath5k_hw_tweak_initval_settings(ah, channel);
839
840 /*
841 * Set TX power (FIXME)
842 */
843 ret = ath5k_hw_txpower(ah, channel, ee_mode,
844 AR5K_TUNE_DEFAULT_TXPOWER);
845 if (ret)
846 return ret;
847
848 /* Write rate duration table only on AR5212 */
849 if (ah->ah_version == AR5K_AR5212)
850 ath5k_hw_write_rate_duration(ah, mode);
851
852 /*
853 * Write RF buffer
854 */
855 ret = ath5k_hw_rfregs_init(ah, channel, mode);
856 if (ret)
857 return ret;
858
859
860 /* Write OFDM timings on 5212*/
861 if (ah->ah_version == AR5K_AR5212 &&
862 channel->hw_value & CHANNEL_OFDM) {
863 ret = ath5k_hw_write_ofdm_timings(ah, channel);
864 if (ret)
865 return ret;
866 }
867
868 /*Enable/disable 802.11b mode on 5111
869 (enable 2111 frequency converter + CCK)*/
870 if (ah->ah_radio == AR5K_RF5111) {
871 if (mode == AR5K_MODE_11B)
872 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
873 AR5K_TXCFG_B_MODE);
874 else
875 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
876 AR5K_TXCFG_B_MODE);
877 }
878
879 /*
880 * In case a fixed antenna was set as default
881 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
882 * registers.
883 */
884 if (s_ant != 0) {
885 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
886 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
887 else /* 2 - Aux */
888 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
889 } else {
890 ant[0] = AR5K_ANT_FIXED_A;
891 ant[1] = AR5K_ANT_FIXED_B;
892 }
893
894 /* Commit values from EEPROM */
895 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode);
896
897 } else {
898 /*
899 * For 5210 we do all initialization using
900 * initvals, so we don't have to modify
901 * any settings (5210 also only supports
902 * a/aturbo modes)
903 */
904 mdelay(1);
905 /* Disable phy and wait */
906 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
907 mdelay(1);
908 }
909
910 /*
911 * Restore saved values
912 */
913
914 /*DCU/Antenna selection not available on 5210*/
915 if (ah->ah_version != AR5K_AR5210) {
916
917 if (change_channel) {
918 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
919 for (i = 0; i < 10; i++)
920 ath5k_hw_reg_write(ah, s_seq[i],
921 AR5K_QUEUE_DCU_SEQNUM(i));
922 } else {
923 ath5k_hw_reg_write(ah, s_seq[0],
924 AR5K_QUEUE_DCU_SEQNUM(0));
925 }
926 }
927
928 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
929 }
930
931 /* Ledstate */
932 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
933
934 /* Gpio settings */
935 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
936 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
937
938 /* Restore sta_id flags and preserve our mac address*/
939 ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id),
940 AR5K_STA_ID0);
941 ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id),
942 AR5K_STA_ID1);
943
944
945 /*
946 * Configure PCU
947 */
948
949 /* Restore bssid and bssid mask */
950 /* XXX: add ah->aid once mac80211 gives this to us */
951 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
952
953 /* Set PCU config */
954 ath5k_hw_set_opmode(ah);
955
956 /* Clear any pending interrupts
957 * PISR/SISR Not available on 5210 */
958 if (ah->ah_version != AR5K_AR5210)
959 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
960
961 /* Set RSSI/BRSSI thresholds
962 *
963 * Note: If we decide to set this value
964 * dynamicaly, have in mind that when AR5K_RSSI_THR
965 * register is read it might return 0x40 if we haven't
966 * wrote anything to it plus BMISS RSSI threshold is zeroed.
967 * So doing a save/restore procedure here isn't the right
968 * choice. Instead store it on ath5k_hw */
969 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
970 AR5K_TUNE_BMISS_THRES <<
971 AR5K_RSSI_THR_BMISS_S),
972 AR5K_RSSI_THR);
973
974 /* MIC QoS support */
975 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
976 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
977 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
978 }
979
980 /* QoS NOACK Policy */
981 if (ah->ah_version == AR5K_AR5212) {
982 ath5k_hw_reg_write(ah,
983 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
984 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
985 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
986 AR5K_QOS_NOACK);
987 }
988
989
990 /*
991 * Configure PHY
992 */
993
994 /* Set channel on PHY */
995 ret = ath5k_hw_channel(ah, channel);
996 if (ret)
997 return ret;
998
999 /*
1000 * Enable the PHY and wait until completion
1001 * This includes BaseBand and Synthesizer
1002 * activation.
1003 */
1004 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1005
1006 /*
1007 * On 5211+ read activation -> rx delay
1008 * and use it.
1009 *
1010 * TODO: Half/quarter rate support
1011 */
1012 if (ah->ah_version != AR5K_AR5210) {
1013 u32 delay;
1014 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1015 AR5K_PHY_RX_DELAY_M;
1016 delay = (channel->hw_value & CHANNEL_CCK) ?
1017 ((delay << 2) / 22) : (delay / 10);
1018
1019 udelay(100 + (2 * delay));
1020 } else {
1021 mdelay(1);
1022 }
1023
1024 /*
1025 * Perform ADC test to see if baseband is ready
1026 * Set tx hold and check adc test register
1027 */
1028 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1029 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1030 for (i = 0; i <= 20; i++) {
1031 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1032 break;
1033 udelay(200);
1034 }
1035 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
1036
1037 /*
1038 * Start automatic gain control calibration
1039 *
1040 * During AGC calibration RX path is re-routed to
1041 * a power detector so we don't receive anything.
1042 *
1043 * This method is used to calibrate some static offsets
1044 * used together with on-the fly I/Q calibration (the
1045 * one performed via ath5k_hw_phy_calibrate), that doesn't
1046 * interrupt rx path.
1047 *
1048 * While rx path is re-routed to the power detector we also
1049 * start a noise floor calibration, to measure the
1050 * card's noise floor (the noise we measure when we are not
1051 * transmiting or receiving anything).
1052 *
1053 * If we are in a noisy environment AGC calibration may time
1054 * out and/or noise floor calibration might timeout.
1055 */
1056 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1057 AR5K_PHY_AGCCTL_CAL);
1058
1059 /* At the same time start I/Q calibration for QAM constellation
1060 * -no need for CCK- */
1061 ah->ah_calibration = 0;
1062 if (!(mode == AR5K_MODE_11B)) {
1063 ah->ah_calibration = 1;
1064 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1065 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1066 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1067 AR5K_PHY_IQ_RUN);
1068 }
1069
1070 /* Wait for gain calibration to finish (we check for I/Q calibration
1071 * during ath5k_phy_calibrate) */
1072 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1073 AR5K_PHY_AGCCTL_CAL, 0, 0)) {
1074 DBG("ath5k: gain calibration timeout (%d MHz)\n",
1075 channel->center_freq);
1076 }
1077
1078 /*
1079 * If we run NF calibration before AGC, it always times out.
1080 * Binary HAL starts NF and AGC calibration at the same time
1081 * and only waits for AGC to finish. Also if AGC or NF cal.
1082 * times out, reset doesn't fail on binary HAL. I believe
1083 * that's wrong because since rx path is routed to a detector,
1084 * if cal. doesn't finish we won't have RX. Sam's HAL for AR5210/5211
1085 * enables noise floor calibration after offset calibration and if noise
1086 * floor calibration fails, reset fails. I believe that's
1087 * a better approach, we just need to find a polling interval
1088 * that suits best, even if reset continues we need to make
1089 * sure that rx path is ready.
1090 */
1091 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
1092
1093
1094 /*
1095 * Configure QCUs/DCUs
1096 */
1097
1098 /* TODO: HW Compression support for data queues */
1099 /* TODO: Burst prefetch for data queues */
1100
1101 /*
1102 * Reset queues and start beacon timers at the end of the reset routine
1103 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
1104 * Note: If we want we can assign multiple qcus on one dcu.
1105 */
1106 ret = ath5k_hw_reset_tx_queue(ah);
1107 if (ret) {
1108 DBG("ath5k: failed to reset TX queue\n");
1109 return ret;
1110 }
1111
1112 /*
1113 * Configure DMA/Interrupts
1114 */
1115
1116 /*
1117 * Set Rx/Tx DMA Configuration
1118 *
1119 * Set standard DMA size (128). Note that
1120 * a DMA size of 512 causes rx overruns and tx errors
1121 * on pci-e cards (tested on 5424 but since rx overruns
1122 * also occur on 5416/5418 with madwifi we set 128
1123 * for all PCI-E cards to be safe).
1124 *
1125 * XXX: need to check 5210 for this
1126 * TODO: Check out tx triger level, it's always 64 on dumps but I
1127 * guess we can tweak it and see how it goes ;-)
1128 */
1129 if (ah->ah_version != AR5K_AR5210) {
1130 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1131 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
1132 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1133 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
1134 }
1135
1136 /* Pre-enable interrupts on 5211/5212*/
1137 if (ah->ah_version != AR5K_AR5210)
1138 ath5k_hw_set_imr(ah, ah->ah_imr);
1139
1140 /*
1141 * Setup RFKill interrupt if rfkill flag is set on eeprom.
1142 * TODO: Use gpio pin and polarity infos from eeprom
1143 * TODO: Handle this in ath5k_intr because it'll result
1144 * a nasty interrupt storm.
1145 */
1146 #if 0
1147 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
1148 ath5k_hw_set_gpio_input(ah, 0);
1149 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
1150 if (ah->ah_gpio[0] == 0)
1151 ath5k_hw_set_gpio_intr(ah, 0, 1);
1152 else
1153 ath5k_hw_set_gpio_intr(ah, 0, 0);
1154 }
1155 #endif
1156
1157 /*
1158 * Disable beacons and reset the register
1159 */
1160 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1161 AR5K_BEACON_RESET_TSF);
1162
1163 return 0;
1164 }
1165
1166 #undef _ATH5K_RESET
1167