1 #ifndef _AXGE_H 2 #define _AXGE_H 3 4 /** @file 5 * 6 * Asix 10/100/1000 USB Ethernet driver 7 * 8 */ 9 10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); 11 12 #include <ipxe/usb.h> 13 #include <ipxe/usbnet.h> 14 15 /** Read MAC register */ 16 #define AXGE_READ_MAC_REGISTER \ 17 ( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \ 18 USB_REQUEST_TYPE ( 0x01 ) ) 19 20 /** Write MAC register */ 21 #define AXGE_WRITE_MAC_REGISTER \ 22 ( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \ 23 USB_REQUEST_TYPE ( 0x01 ) ) 24 25 /** Physical Link Status Register */ 26 #define AXGE_PLSR 0x02 27 #define AXGE_PLSR_EPHY_10 0x10 /**< Ethernet at 10Mbps */ 28 #define AXGE_PLSR_EPHY_100 0x20 /**< Ethernet at 100Mbps */ 29 #define AXGE_PLSR_EPHY_1000 0x40 /**< Ethernet at 1000Mbps */ 30 #define AXGE_PLSR_EPHY_ANY \ 31 ( AXGE_PLSR_EPHY_10 | \ 32 AXGE_PLSR_EPHY_100 | \ 33 AXGE_PLSR_EPHY_1000 ) 34 35 /** RX Control Register */ 36 #define AXGE_RCR 0x0b 37 #define AXGE_RCR_PRO 0x0001 /**< Promiscuous mode */ 38 #define AXGE_RCR_AMALL 0x0002 /**< Accept all multicasts */ 39 #define AXGE_RCR_AB 0x0008 /**< Accept broadcasts */ 40 #define AXGE_RCR_SO 0x0080 /**< Start operation */ 41 42 /** Node ID Register */ 43 #define AXGE_NIDR 0x10 44 45 /** Medium Status Register */ 46 #define AXGE_MSR 0x22 47 #define AXGE_MSR_GM 0x0001 /**< Gigabit mode */ 48 #define AXGE_MSR_FD 0x0002 /**< Full duplex */ 49 #define AXGE_MSR_RFC 0x0010 /**< RX flow control enable */ 50 #define AXGE_MSR_TFC 0x0020 /**< TX flow control enable */ 51 #define AXGE_MSR_RE 0x0100 /**< Receive enable */ 52 #define AXGE_MSR_PS 0x0200 /**< 100Mbps port speed */ 53 54 /** Ethernet PHY Power and Reset Control Register */ 55 #define AXGE_EPPRCR 0x26 56 #define AXGE_EPPRCR_IPRL 0x0020 /**< Undocumented */ 57 58 /** Delay after initialising EPPRCR */ 59 #define AXGE_EPPRCR_DELAY_MS 200 60 61 /** Bulk IN Control Register (undocumented) */ 62 #define AXGE_BICR 0x2e 63 64 /** Bulk IN Control (undocumented) */ 65 struct axge_bulk_in_control { 66 /** Control */ 67 uint8_t ctrl; 68 /** Timer */ 69 uint16_t timer; 70 /** Size */ 71 uint8_t size; 72 /** Inter-frame gap */ 73 uint8_t ifg; 74 } __attribute__ (( packed )); 75 76 /** Clock Select Register (undocumented) */ 77 #define AXGE_CSR 0x33 78 #define AXGE_CSR_BCS 0x01 /**< Undocumented */ 79 #define AXGE_CSR_ACS 0x02 /**< Undocumented */ 80 81 /** Delay after initialising CSR */ 82 #define AXGE_CSR_DELAY_MS 100 83 84 /** Transmit packet header */ 85 struct axge_tx_header { 86 /** Packet length */ 87 uint32_t len; 88 /** Answers on a postcard, please */ 89 uint32_t wtf; 90 } __attribute__ (( packed )); 91 92 /** Receive packet footer */ 93 struct axge_rx_footer { 94 /** Packet count */ 95 uint16_t count; 96 /** Header offset */ 97 uint16_t offset; 98 } __attribute__ (( packed )); 99 100 /** Receive packet descriptor */ 101 struct axge_rx_descriptor { 102 /** Checksum information */ 103 uint16_t check; 104 /** Length and error flags */ 105 uint16_t len_flags; 106 } __attribute__ (( packed )); 107 108 /** Receive packet length mask */ 109 #define AXGE_RX_LEN_MASK 0x1fff 110 111 /** Receive packet length alignment */ 112 #define AXGE_RX_LEN_PAD_ALIGN 8 113 114 /** Receive packet CRC error */ 115 #define AXGE_RX_CRC_ERROR 0x2000 116 117 /** Receive packet dropped error */ 118 #define AXGE_RX_DROP_ERROR 0x8000 119 120 /** Interrupt data */ 121 struct axge_interrupt { 122 /** Magic signature */ 123 uint16_t magic; 124 /** Link state */ 125 uint16_t link; 126 /** PHY register MR01 */ 127 uint16_t mr01; 128 /** PHY register MR05 */ 129 uint16_t mr05; 130 } __attribute__ (( packed )); 131 132 /** Interrupt magic signature */ 133 #define AXGE_INTR_MAGIC 0x00a1 134 135 /** Link is up */ 136 #define AXGE_INTR_LINK_PPLS 0x0001 137 138 /** An AXGE network device */ 139 struct axge_device { 140 /** USB device */ 141 struct usb_device *usb; 142 /** USB bus */ 143 struct usb_bus *bus; 144 /** Network device */ 145 struct net_device *netdev; 146 /** USB network device */ 147 struct usbnet_device usbnet; 148 /** Device configuration */ 149 unsigned int config; 150 /** Link state has changed */ 151 int check_link; 152 }; 153 154 /** Interrupt maximum fill level 155 * 156 * This is a policy decision. 157 */ 158 #define AXGE_INTR_MAX_FILL 2 159 160 /** Bulk IN maximum fill level 161 * 162 * This is a policy decision. 163 */ 164 #define AXGE_IN_MAX_FILL 8 165 166 /** Bulk IN buffer size 167 * 168 * This is a policy decision. 169 */ 170 #define AXGE_IN_MTU 2048 171 172 /** Amount of space to reserve at start of bulk IN buffers 173 * 174 * This is required to allow for protocols such as ARP which may reuse 175 * a received I/O buffer for transmission. 176 */ 177 #define AXGE_IN_RESERVE sizeof ( struct axge_tx_header ) 178 179 #endif /* _AXGE_H */ 180