1 /* 2 * (C) Copyright 2000, 2001, 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr 29 * U-Boot port on RPXlite board 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 #define RPXClassic_50MHz 36 37 /* 38 * High Level Configuration Options 39 * (easy to change) 40 */ 41 42 #define CONFIG_MPC860 1 43 #define CONFIG_RPXCLASSIC 1 44 45 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 46 #undef CONFIG_8xx_CONS_SMC2 47 #undef CONFIG_8xx_CONS_NONE 48 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ 49 50 /* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */ 51 #define CONFIG_FEC_ENET 52 #ifdef CONFIG_FEC_ENET 53 #define CONFIG_SYS_DISCOVER_PHY 1 54 #define CONFIG_MII 1 55 #endif /* CONFIG_FEC_ENET */ 56 #define CONFIG_MISC_INIT_R 57 58 /* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */ 59 #if 1 60 #define CONFIG_VIDEO_SED13806 61 #define CONFIG_NEC_NL6448BC20 62 #define CONFIG_VIDEO_SED13806_16BPP 63 64 #define CONFIG_CFB_CONSOLE 65 #define CONFIG_VIDEO_LOGO 66 #define CONFIG_VIDEO_BMP_LOGO 67 #define CONFIG_CONSOLE_EXTRA_INFO 68 #define CONFIG_VGA_AS_SINGLE_DEVICE 69 #define CONFIG_VIDEO_SW_CURSOR 70 #endif 71 72 #if 0 73 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 74 #else 75 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 76 #endif 77 78 #define CONFIG_ZERO_BOOTDELAY_CHECK 1 79 80 #undef CONFIG_BOOTARGS 81 #define CONFIG_BOOTCOMMAND \ 82 "tftpboot; " \ 83 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 84 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 85 "bootm" 86 87 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 88 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 89 90 #undef CONFIG_WATCHDOG /* watchdog disabled */ 91 92 /* 93 * BOOTP options 94 */ 95 #define CONFIG_BOOTP_SUBNETMASK 96 #define CONFIG_BOOTP_GATEWAY 97 #define CONFIG_BOOTP_HOSTNAME 98 #define CONFIG_BOOTP_BOOTPATH 99 #define CONFIG_BOOTP_BOOTFILESIZE 100 101 102 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 103 104 105 /* 106 * Command line configuration. 107 */ 108 #include <config_cmd_default.h> 109 110 #define CONFIG_CMD_ELF 111 112 113 /* 114 * Miscellaneous configurable options 115 */ 116 #define CONFIG_SYS_RESET_ADDRESS 0x80000000 117 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 118 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 119 #if defined(CONFIG_CMD_KGDB) 120 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 121 #else 122 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 123 #endif 124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 125 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 126 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 127 128 #define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ 129 #define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ 130 131 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 132 133 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 134 135 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 136 137 /* 138 * Low Level Configuration Settings 139 * (address mappings, register initial values, etc.) 140 * You should know what you are doing if you make changes here. 141 */ 142 /*----------------------------------------------------------------------- 143 * Internal Memory Mapped Register 144 */ 145 #define CONFIG_SYS_IMMR 0xFA200000 146 147 /*----------------------------------------------------------------------------- 148 * I2C Configuration 149 *----------------------------------------------------------------------------- 150 */ 151 #define CONFIG_I2C 1 152 #define CONFIG_SYS_I2C_SPEED 50000 153 #define CONFIG_SYS_I2C_SLAVE 0x34 154 155 156 /* enable I2C and select the hardware/software driver */ 157 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 158 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 159 /* 160 * Software (bit-bang) I2C driver configuration 161 */ 162 #define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ 163 #define I2C_ACTIVE (iop->pdir |= 0x00000010) 164 #define I2C_TRISTATE (iop->pdir &= ~0x00000010) 165 #define I2C_READ ((iop->pdat & 0x00000010) != 0) 166 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ 167 else iop->pdat &= ~0x00000010 168 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ 169 else iop->pdat &= ~0x00000020 170 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 171 172 173 # define CONFIG_SYS_I2C_SPEED 50000 174 # define CONFIG_SYS_I2C_SLAVE 0x34 175 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ 176 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 177 /* mask of address bits that overflow into the "EEPROM chip address" */ 178 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 179 180 /*----------------------------------------------------------------------- 181 * Definitions for initial stack pointer and data area (in DPRAM) 182 */ 183 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 184 #define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ 185 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 186 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 187 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 188 189 /*----------------------------------------------------------------------- 190 * Start addresses for the final memory configuration 191 * (Set up by the startup code) 192 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 193 */ 194 #define CONFIG_SYS_SDRAM_BASE 0x00000000 195 #define CONFIG_SYS_FLASH_BASE 0xFF000000 196 197 #if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE) 198 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 199 #else 200 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ 201 #endif 202 #define CONFIG_SYS_MONITOR_BASE 0xFF000000 203 /*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ 204 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 205 206 /* 207 * For booting Linux, the board info and command line data 208 * have to be in the first 8 MB of memory, since this is 209 * the maximum mapped by the Linux kernel during initialization. 210 */ 211 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 212 213 /*----------------------------------------------------------------------- 214 * FLASH organization 215 */ 216 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 217 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 218 219 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 220 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 221 222 #if 0 223 #define CONFIG_ENV_IS_IN_FLASH 1 224 #define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ 225 #define CONFIG_ENV_SECT_SIZE 0x8000 226 #define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ 227 #else 228 #define CONFIG_ENV_IS_IN_NVRAM 1 229 #define CONFIG_ENV_ADDR 0xfa000100 230 #define CONFIG_ENV_SIZE 0x1000 231 #endif 232 233 /*----------------------------------------------------------------------- 234 * Cache Configuration 235 */ 236 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 237 #if defined(CONFIG_CMD_KGDB) 238 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 239 #endif 240 241 /*----------------------------------------------------------------------- 242 * SYPCR - System Protection Control 11-9 243 * SYPCR can only be written once after reset! 244 *----------------------------------------------------------------------- 245 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 246 */ 247 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 248 SYPCR_SWP) 249 250 /*----------------------------------------------------------------------- 251 * SIUMCR - SIU Module Configuration 11-6 252 *----------------------------------------------------------------------- 253 * PCMCIA config., multi-function pin tri-state 254 */ 255 #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) 256 257 /*----------------------------------------------------------------------- 258 * TBSCR - Time Base Status and Control 11-26 259 *----------------------------------------------------------------------- 260 * Clear Reference Interrupt Status, Timebase freezing enabled 261 */ 262 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) 263 264 /*----------------------------------------------------------------------- 265 * RTCSC - Real-Time Clock Status and Control Register 11-27 266 *----------------------------------------------------------------------- 267 */ 268 /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ 269 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) 270 271 /*----------------------------------------------------------------------- 272 * PISCR - Periodic Interrupt Status and Control 11-31 273 *----------------------------------------------------------------------- 274 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 275 */ 276 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) 277 278 /*----------------------------------------------------------------------- 279 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 280 *----------------------------------------------------------------------- 281 * Reset PLL lock status sticky bit, timer expired status bit and timer 282 * interrupt status bit 283 * 284 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! 285 */ 286 /* up to 50 MHz we use a 1:1 clock */ 287 #define CONFIG_SYS_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST) 288 289 /*----------------------------------------------------------------------- 290 * SCCR - System Clock and reset Control Register 15-27 291 *----------------------------------------------------------------------- 292 * Set clock output, timebase and RTC source and divider, 293 * power management and some other internal clocks 294 */ 295 #define SCCR_MASK SCCR_EBDF00 296 /* up to 50 MHz we use a 1:1 clock */ 297 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) 298 299 /*----------------------------------------------------------------------- 300 * PCMCIA stuff 301 *----------------------------------------------------------------------- 302 * 303 */ 304 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 305 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 306 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 307 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 308 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 309 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 310 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 311 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 312 313 /*----------------------------------------------------------------------- 314 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 315 *----------------------------------------------------------------------- 316 */ 317 318 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 319 320 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 321 #undef CONFIG_IDE_LED /* LED for ide not supported */ 322 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 323 324 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 325 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 326 327 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 328 329 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 330 331 /* Offset for data I/O */ 332 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 333 334 /* Offset for normal register accesses */ 335 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 336 337 /* Offset for alternate registers */ 338 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 339 340 /*----------------------------------------------------------------------- 341 * 342 *----------------------------------------------------------------------- 343 * 344 */ 345 /* #define CONFIG_SYS_DER 0x2002000F */ 346 #define CONFIG_SYS_DER 0 347 348 /* 349 * Init Memory Controller: 350 * 351 * BR0 and OR0 (FLASH) 352 */ 353 354 #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ 355 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ 356 357 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ 358 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) 359 360 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 361 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) 362 363 /* 364 * BR1 and OR1 (SDRAM) 365 * 366 */ 367 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ 368 #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ 369 370 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 371 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 372 373 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 374 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 375 376 /* RPXLITE mem setting */ 377 #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ 378 #define CONFIG_SYS_OR3_PRELIM 0xff7f8970 379 #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ 380 #define CONFIG_SYS_OR4_PRELIM 0xFFF80970 381 382 /* ECCX CS settings */ 383 #define SED13806_OR 0xFFC00108 /* - 4 Mo 384 - Burst inhibit 385 - external TA */ 386 #define SED13806_REG_ADDR 0xa0000000 387 #define SED13806_ACCES 0x801 /* 16 bit access */ 388 389 390 /* Global definitions for the ECCX board */ 391 #define ECCX_CSR_ADDR (0xfac00000) 392 #define ECCX_CSR8_OFFSET (0x8) 393 #define ECCX_CSR11_OFFSET (0xB) 394 #define ECCX_CSR12_OFFSET (0xC) 395 396 #define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET) 397 #define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET) 398 #define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET) 399 400 401 #define REG_GPIO_CTRL 0x008 402 403 /* Definitions for CSR8 */ 404 #define ECCX_ENEPSON 0x80 /* Bit 0: 405 0= disable and reset SED1386 406 1= enable SED1386 */ 407 /* Bit 1: 0= SED1386 in Big Endian mode */ 408 /* 1= SED1386 in little endian mode */ 409 #define ECCX_LE 0x40 410 #define ECCX_BE 0x00 411 412 /* Bit 2,3: Selection */ 413 /* 00 = Disabled */ 414 /* 01 = CS2 is used for the SED1386 */ 415 /* 10 = CS5 is used for the SED1386 */ 416 /* 11 = reserved */ 417 #define ECCX_CS2 0x10 418 #define ECCX_CS5 0x20 419 420 /* Definitions for CSR12 */ 421 #define ECCX_ID 0x02 422 #define ECCX_860 0x01 423 424 /* 425 * Memory Periodic Timer Prescaler 426 */ 427 428 /* periodic timer for refresh */ 429 #define CONFIG_SYS_MAMR_PTA 58 430 431 /* 432 * Refresh clock Prescalar 433 */ 434 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 435 436 /* 437 * MAMR settings for SDRAM 438 */ 439 440 /* 10 column SDRAM */ 441 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 442 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ 443 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) 444 445 /* 446 * Internal Definitions 447 * 448 * Boot Flags 449 */ 450 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 451 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 452 453 454 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ 455 /* Configuration variable added by yooth. */ 456 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ 457 458 /* 459 * BCSRx 460 * 461 * Board Status and Control Registers 462 * 463 */ 464 465 #define BCSR0 0xFA400000 466 #define BCSR1 0xFA400001 467 #define BCSR2 0xFA400002 468 #define BCSR3 0xFA400003 469 470 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ 471 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ 472 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ 473 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ 474 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ 475 #define BCSR0_COLTEST 0x20 476 #define BCSR0_ETHLPBK 0x40 477 #define BCSR0_ETHEN 0x80 478 479 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ 480 #define BCSR1_PCVCTL6 0x02 481 #define BCSR1_PCVCTL5 0x04 482 #define BCSR1_PCVCTL4 0x08 483 #define BCSR1_IPB5SEL 0x10 484 485 #define BCSR2_MIIRST 0x80 486 #define BCSR2_MIIPWRDWN 0x40 487 #define BCSR2_MIICTL 0x08 488 489 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ 490 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */ 491 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ 492 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ 493 #define BCSR3_D27 0x10 /* Dip Switch settings */ 494 #define BCSR3_D26 0x20 495 #define BCSR3_D25 0x40 496 #define BCSR3_D24 0x80 497 498 499 /* 500 * Environment setting 501 */ 502 503 /* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */ 504 /* #define CONFIG_IPADDR 10.10.106.1 */ 505 /* #define CONFIG_SERVERIP 10.10.104.11 */ 506 507 #endif /* __CONFIG_H */ 508