1 /* 2 * (C) Copyright 2009 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * Based on include/configs/canyonlands.h 6 * (C) Copyright 2008 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center 27 */ 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 */ 34 /* 35 * This config file is used for CompactCenter(codename intip) and DevCon-Center 36 */ 37 #define CONFIG_460EX 1 /* Specific PPC460EX */ 38 #ifdef CONFIG_DEVCONCENTER 39 #define CONFIG_HOSTNAME devconcenter 40 #define CONFIG_IDENT_STRING " devconcenter 0.02" 41 #else 42 #define CONFIG_HOSTNAME intip 43 #define CONFIG_IDENT_STRING " intip 0.02" 44 #endif 45 #define CONFIG_440 1 46 #define CONFIG_4xx 1 /* ... PPC4xx family */ 47 48 /* 49 * Include common defines/options for all AMCC eval boards 50 */ 51 #include "amcc-common.h" 52 53 #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ 54 55 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 56 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ 57 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 58 #define CONFIG_BOARD_TYPES 1 /* support board types */ 59 #define CONFIG_FIT 60 #define CFG_ALT_MEMTEST 61 62 /* 63 * Base addresses -- Note these are effective addresses where the 64 * actual resources get mapped (not physical addresses) 65 */ 66 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ 67 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ 68 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE 69 70 /* EBC stuff */ 71 #ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ 72 #define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */ 73 #define CONFIG_SYS_FLASH_SIZE (128 << 20) 74 #else 75 #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */ 76 #define CONFIG_SYS_FLASH_SIZE (64 << 20) 77 #endif 78 79 #define CONFIG_SYS_NVRAM_BASE 0xE0000000 80 #define CONFIG_SYS_UART_BASE 0xE0100000 81 #define CONFIG_SYS_IO_BASE 0xE0200000 82 83 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ 84 #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 85 #ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ 86 #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000 87 #else 88 #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000 89 #endif 90 #define CONFIG_SYS_FLASH_BASE_PHYS \ 91 (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ 92 | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) 93 94 #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ 95 #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ 96 #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 97 98 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ 99 100 #define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ 101 102 /* 103 * Initial RAM & stack pointer (placed in OCM) 104 */ 105 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ 106 #define CONFIG_SYS_INIT_RAM_END (4 << 10) 107 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ 108 #define CONFIG_SYS_GBL_DATA_OFFSET \ 109 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 110 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 112 /* 113 * Serial Port 114 */ 115 #undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ 116 117 /* 118 * Environment 119 */ 120 /* 121 * Define here the location of the environment variables (FLASH). 122 */ 123 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 124 #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ 125 126 /* 127 * FLASH related 128 */ 129 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 130 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 131 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ 132 133 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 134 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 135 #ifdef CONFIG_DEVCONCENTER 136 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/ 137 #else 138 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ 139 #endif 140 141 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ 142 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ 143 144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */ 145 #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ 146 147 #ifdef CONFIG_ENV_IS_IN_FLASH 148 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ 149 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 150 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 151 152 /* Address and size of Redundant Environment Sector */ 153 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) 154 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 155 #endif /* CONFIG_ENV_IS_IN_FLASH */ 156 157 /* 158 * DDR SDRAM 159 */ 160 161 #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ 162 163 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ 164 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ 165 #undef CONFIG_PPC4xx_DDR_METHOD_A 166 167 /* DDR1/2 SDRAM Device Control Register Data Values */ 168 /* Memory Queue */ 169 #define CONFIG_SYS_SDRAM_R0BAS 0x0000f800 170 #define CONFIG_SYS_SDRAM_R1BAS 0x00000000 171 #define CONFIG_SYS_SDRAM_R2BAS 0x00000000 172 #define CONFIG_SYS_SDRAM_R3BAS 0x00000000 173 #define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 174 #define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 175 #define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00 176 #define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 177 #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 178 179 /* SDRAM Controller */ 180 #define CONFIG_SYS_SDRAM0_MB0CF 0x00000201 181 #define CONFIG_SYS_SDRAM0_MB1CF 0x00000000 182 #define CONFIG_SYS_SDRAM0_MB2CF 0x00000000 183 #define CONFIG_SYS_SDRAM0_MB3CF 0x00000000 184 #define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000 185 #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 186 #define CONFIG_SYS_SDRAM0_MODT0 0x00000000 187 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 188 #define CONFIG_SYS_SDRAM0_MODT2 0x00000000 189 #define CONFIG_SYS_SDRAM0_MODT3 0x00000000 190 #define CONFIG_SYS_SDRAM0_CODT 0x00000020 191 #define CONFIG_SYS_SDRAM0_RTR 0x06180000 192 #define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000 193 #define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400 194 #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 195 #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 196 #define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002 197 #define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 198 #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 199 #define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 200 #define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000 201 #define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 202 #define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 203 #define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 204 #define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382 205 #define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002 206 #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 207 #define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000 208 #define CONFIG_SYS_SDRAM0_RQDC 0x80000038 209 #define CONFIG_SYS_SDRAM0_RFDC 0x00000257 210 #define CONFIG_SYS_SDRAM0_RDCC 0x40000000 211 #define CONFIG_SYS_SDRAM0_DLCR 0x00000000 212 #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 213 #define CONFIG_SYS_SDRAM0_WRDTR 0x84000823 214 #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 215 #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 216 #define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15 217 #define CONFIG_SYS_SDRAM0_MMODE 0x00000442 218 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000002 219 220 #define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ 221 222 /* 223 * I2C 224 */ 225 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ 226 227 #define CONFIG_SYS_I2C_MULTI_EEPROMS 228 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) 229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 232 233 /* I2C bootstrap EEPROM */ 234 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 235 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 236 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 237 238 /* I2C SYSMON */ 239 #define CONFIG_DTT_LM63 1 /* National LM63 */ 240 #define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ 241 #define CONFIG_DTT_PWM_LOOKUPTABLE \ 242 { { 40, 10 }, { 50, 20 }, { 60, 40 } } 243 #define CONFIG_DTT_TACH_LIMIT 0xa10 244 245 /* RTC configuration */ 246 #define CONFIG_RTC_DS1337 1 247 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 248 249 /* 250 * Ethernet 251 */ 252 #define CONFIG_IBM_EMAC4_V4 1 253 254 #define CONFIG_HAS_ETH0 255 #define CONFIG_HAS_ETH1 256 257 #define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ 258 #define CONFIG_PHY1_ADDR 3 259 260 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ 261 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 262 #define CONFIG_PHY_DYNAMIC_ANEG 1 263 264 /* 265 * USB-OHCI 266 */ 267 #define CONFIG_USB_OHCI_NEW 268 #define CONFIG_USB_STORAGE 269 #undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/ 270 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */ 271 #define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */ 272 #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) 273 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" 274 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 275 276 /* 277 * Default environment variables 278 */ 279 #define CONFIG_EXTRA_ENV_SETTINGS \ 280 CONFIG_AMCC_DEF_ENV \ 281 CONFIG_AMCC_DEF_ENV_POWERPC \ 282 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 283 "kernel_addr=fc000000\0" \ 284 "fdt_addr=fc1e0000\0" \ 285 "ramdisk_addr=fc200000\0" \ 286 "pciconfighost=1\0" \ 287 "pcie_mode=RP:RP\0" \ 288 "" 289 290 /* 291 * Commands additional to the ones defined in amcc-common.h 292 */ 293 #define CONFIG_CMD_CHIP_CONFIG 294 #define CONFIG_CMD_DATE 295 #define CONFIG_CMD_DTT 296 #define CONFIG_CMD_EXT2 297 #define CONFIG_CMD_FAT 298 #define CONFIG_CMD_PCI 299 #define CONFIG_CMD_SDRAM 300 #define CONFIG_CMD_SNTP 301 #define CONFIG_CMD_USB 302 303 /* Partitions */ 304 #define CONFIG_MAC_PARTITION 305 #define CONFIG_DOS_PARTITION 306 #define CONFIG_ISO_PARTITION 307 308 /* 309 * PCI stuff 310 */ 311 /* General PCI */ 312 #define CONFIG_PCI /* include pci support */ 313 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 314 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 315 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 316 #define CONFIG_PCI_DISABLE_PCIE 317 318 /* Board-specific PCI */ 319 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ 320 #undef CONFIG_SYS_PCI_MASTER_INIT 321 322 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ 323 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ 324 325 326 /* 327 * External Bus Controller (EBC) Setup 328 */ 329 330 /* 331 * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the 332 * boot EBC mapping only supports a maximum of 16MBytes 333 * (4.ff00.0000 - 4.ffff.ffff). 334 * To solve this problem, the FLASH has to get remapped to another 335 * EBC address which accepts bigger regions: 336 * 337 * 0xfc00.0000 -> 4.cc00.0000 338 */ 339 340 341 /* Memory Bank 0 (NOR-FLASH) initialization */ 342 #define CONFIG_SYS_EBC_PB0AP 0x10055e00 343 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) 344 345 /* Memory Bank 1 (NVRAM) initialization */ 346 #define CONFIG_SYS_EBC_PB1AP 0x02815480 347 /* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/ 348 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000) 349 350 /* Memory Bank 2 (UART) initialization */ 351 #define CONFIG_SYS_EBC_PB2AP 0x02815480 352 /* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/ 353 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000) 354 355 /* Memory Bank 3 (IO) initialization */ 356 #define CONFIG_SYS_EBC_PB3AP 0x02815480 357 /* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/ 358 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000) 359 360 /* 361 * PPC4xx GPIO Configuration 362 */ 363 /* 460EX: Use USB configuration */ 364 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ 365 { \ 366 /* GPIO Core 0 */ \ 367 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ 368 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ 369 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ 370 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ 371 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ 372 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ 373 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ 374 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ 375 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ 376 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ 377 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ 378 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ 379 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ 380 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ 381 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ 382 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ 383 {GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ 384 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ 385 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ 386 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ 387 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ 388 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ 389 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ 390 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ 391 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ 392 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ 393 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ 394 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ 395 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ 396 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ 397 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ 398 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ 399 }, \ 400 { \ 401 /* GPIO Core 1 */ \ 402 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ 403 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ 404 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ 405 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ 406 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ 407 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ 408 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ 409 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ 410 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ 411 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ 412 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ 413 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ 414 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ 415 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ 416 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ 417 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ 418 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ 419 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ 420 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \ 421 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \ 422 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \ 423 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \ 424 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \ 425 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \ 426 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \ 427 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ 428 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ 429 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ 430 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ 431 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \ 432 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \ 433 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \ 434 } \ 435 } 436 437 #endif /* __CONFIG_H */ 438