1 /* 2 * include/mpc8220.h 3 * 4 * Prototypes, etc. for the Motorola MPC8220 5 * embedded cpu chips 6 * 7 * 2004 (c) Freescale, Inc. 8 * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 #ifndef __MPC8220_H__ 29 #define __MPC8220_H__ 30 31 /* Processor name */ 32 #if defined(CONFIG_MPC8220) 33 #define CPU_ID_STR "MPC8220" 34 #endif 35 36 /* Exception offsets (PowerPC standard) */ 37 #define EXC_OFF_SYS_RESET 0x0100 38 #define _START_OFFSET EXC_OFF_SYS_RESET 39 40 /* Internal memory map */ 41 /* MPC8220 Internal Register MMAP */ 42 #define MMAP_MBAR (CONFIG_SYS_MBAR + 0x00000000) /* chip selects */ 43 #define MMAP_MEMCTL (CONFIG_SYS_MBAR + 0x00000100) /* sdram controller */ 44 #define MMAP_XLBARB (CONFIG_SYS_MBAR + 0x00000200) /* xlb arbitration control */ 45 #define MMAP_CDM (CONFIG_SYS_MBAR + 0x00000300) /* clock distribution module */ 46 #define MMAP_VDOPLL (CONFIG_SYS_MBAR + 0x00000400) /* video PLL */ 47 #define MMAP_FB (CONFIG_SYS_MBAR + 0x00000500) /* flex bus controller */ 48 #define MMAP_PCFG (CONFIG_SYS_MBAR + 0x00000600) /* port config */ 49 #define MMAP_ICTL (CONFIG_SYS_MBAR + 0x00000700) /* interrupt controller */ 50 #define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) /* general purpose timers */ 51 #define MMAP_SLTMR (CONFIG_SYS_MBAR + 0x00000900) /* slice timers */ 52 #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) /* gpio module */ 53 #define MMAP_XCPCI (CONFIG_SYS_MBAR + 0x00000B00) /* pci controller */ 54 #define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) /* pci arbiter */ 55 #define MMAP_EXTDMA1 (CONFIG_SYS_MBAR + 0x00000D00) /* external dma1 */ 56 #define MMAP_EXTDMA2 (CONFIG_SYS_MBAR + 0x00000E00) /* external dma1 */ 57 #define MMAP_USBH (CONFIG_SYS_MBAR + 0x00001000) /* usb host */ 58 #define MMAP_CMTMR (CONFIG_SYS_MBAR + 0x00007f00) /* comm timers */ 59 #define MMAP_DMA (CONFIG_SYS_MBAR + 0x00008000) /* dma */ 60 #define MMAP_USBD (CONFIG_SYS_MBAR + 0x00008200) /* usb device */ 61 #define MMAP_COMMPCI (CONFIG_SYS_MBAR + 0x00008400) /* pci comm Bus regs */ 62 #define MMAP_1284 (CONFIG_SYS_MBAR + 0x00008500) /* 1284 */ 63 #define MMAP_PEV (CONFIG_SYS_MBAR + 0x00008600) /* print engine video */ 64 #define MMAP_PSC1 (CONFIG_SYS_MBAR + 0x00008800) /* psc1 block */ 65 #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008f00) /* i2c controller */ 66 #define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009000) /* fast ethernet 1 */ 67 #define MMAP_FEC2 (CONFIG_SYS_MBAR + 0x00009800) /* fast ethernet 2 */ 68 #define MMAP_JBIGRAM (CONFIG_SYS_MBAR + 0x0000a000) /* jbig RAM */ 69 #define MMAP_JBIG (CONFIG_SYS_MBAR + 0x0000c000) /* jbig */ 70 #define MMAP_PDLA (CONFIG_SYS_MBAR + 0x00010000) /* */ 71 #define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001ff00) /* SRAM config */ 72 #define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00020000) /* SRAM */ 73 74 #define SRAM_SIZE 0x8000 /* 32 KB */ 75 76 /* ------------------------------------------------------------------------ */ 77 /* 78 * Macro for Programmable Serial Channel 79 */ 80 /* equates for mode reg. 1 for channel A or B */ 81 #define PSC_MR1_RX_RTS 0x80000000 /* receiver RTS enabled */ 82 #define PSC_MR1_RX_INT 0x40000000 /* receiver intrupt enabled */ 83 #define PSC_MR1_ERR_MODE 0x20000000 /* block error mode */ 84 #define PSC_MR1_PAR_MODE_MULTI 0x18000000 /* multi_drop mode */ 85 #define PSC_MR1_NO_PARITY 0x10000000 /* no parity mode */ 86 #define PSC_MR1_ALWAYS_0 0x08000000 /* force parity mode */ 87 #define PSC_MR1_ALWAYS_1 0x0c000000 /* force parity mode */ 88 #define PSC_MR1_EVEN_PARITY 0x00000000 /* parity mode */ 89 #define PSC_MR1_ODD_PARITY 0x04000000 /* 0 = even, 1 = odd */ 90 #define PSC_MR1_BITS_CHAR_8 0x03000000 /* 8 bits */ 91 #define PSC_MR1_BITS_CHAR_7 0x02000000 /* 7 bits */ 92 #define PSC_MR1_BITS_CHAR_6 0x01000000 /* 6 bits */ 93 #define PSC_MR1_BITS_CHAR_5 0x00000000 /* 5 bits */ 94 95 /* equates for mode reg. 2 for channel A or B */ 96 #define PSC_MR2_NORMAL_MODE 0x00000000 /* normal channel mode */ 97 #define PSC_MR2_AUTO_MODE 0x40000000 /* automatic channel mode */ 98 #define PSC_MR2_LOOPBACK_LOCL 0x80000000 /* local loopback channel mode */ 99 #define PSC_MR2_LOOPBACK_REMT 0xc0000000 /* remote loopback channel mode */ 100 #define PSC_MR2_TX_RTS 0x20000000 /* transmitter RTS enabled */ 101 #define PSC_MR2_TX_CTS 0x10000000 /* transmitter CTS enabled */ 102 #define PSC_MR2_STOP_BITS_2 0x0f000000 /* 2 stop bits */ 103 #define PSC_MR2_STOP_BITS_1 0x07000000 /* 1 stop bit */ 104 105 /* equates for status reg. A or B */ 106 #define PSC_SR_BREAK 0x80000000 /* received break */ 107 #define PSC_SR_NEOF PSC_SR_BREAK /* Next byte is EOF - MIR/FIR */ 108 #define PSC_SR_FRAMING 0x40000000 /* framing error */ 109 #define PSC_SR_PHYERR PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */ 110 #define PSC_SR_PARITY 0x20000000 /* parity error */ 111 #define PSC_SR_CRCERR PSC_SR_PARITY /* CRC error */ 112 #define PSC_SR_OVERRUN 0x10000000 /* overrun error */ 113 #define PSC_SR_TXEMT 0x08000000 /* transmitter empty */ 114 #define PSC_SR_TXRDY 0x04000000 /* transmitter ready*/ 115 #define PSC_SR_FFULL 0x02000000 /* fifo full */ 116 #define PSC_SR_RXRDY 0x01000000 /* receiver ready */ 117 #define PSC_SR_DEOF 0x00800000 /* Detect EOF or RX-FIFO contain EOF */ 118 #define PSC_SR_ERR 0x00400000 /* Error Status including FIFO */ 119 120 /* equates for clock select reg. */ 121 #define PSC_CSRX16EXT_CLK 0x1110 /* x 16 ext_clock */ 122 #define PSC_CSRX1EXT_CLK 0x1111 /* x 1 ext_clock */ 123 124 /* equates for command reg. A or B */ 125 #define PSC_CR_NO_COMMAND 0x00000000 /* no command */ 126 #define PSC_CR_RST_MR_PTR_CMD 0x10000000 /* reset mr pointer command */ 127 #define PSC_CR_RST_RX_CMD 0x20000000 /* reset receiver command */ 128 #define PSC_CR_RST_TX_CMD 0x30000000 /* reset transmitter command */ 129 #define PSC_CR_RST_ERR_STS_CMD 0x40000000 /* reset error status cmnd */ 130 #define PSC_CR_RST_BRK_INT_CMD 0x50000000 /* reset break int. command */ 131 #define PSC_CR_STR_BREAK_CMD 0x60000000 /* start break command */ 132 #define PSC_CR_STP_BREAK_CMD 0x70000000 /* stop break command */ 133 #define PSC_CR_RX_ENABLE 0x01000000 /* receiver enabled */ 134 #define PSC_CR_RX_DISABLE 0x02000000 /* receiver disabled */ 135 #define PSC_CR_TX_ENABLE 0x04000000 /* transmitter enabled */ 136 #define PSC_CR_TX_DISABLE 0x08000000 /* transmitter disabled */ 137 138 /* equates for input port change reg. */ 139 #define PSC_IPCR_SYNC 0x80000000 /* Sync Detect */ 140 #define PSC_IPCR_D_CTS 0x10000000 /* Delta CTS */ 141 #define PSC_IPCR_CTS 0x01000000 /* CTS - current state of PSC_CTS */ 142 143 /* equates for auxiliary control reg. (timer and counter clock selects) */ 144 #define PSC_ACR_BRG 0x80000000 /* for 68681 compatibility 145 baud rate gen select 146 0 = set 1; 1 = set 2 147 equates are set 2 ONLY */ 148 #define PSC_ACR_TMR_EXT_CLK_16 0x70000000 /* xtnl clock divided by 16 */ 149 #define PSC_ACR_TMR_EXT_CLK 0x60000000 /* external clock */ 150 #define PSC_ACR_TMR_IP2_16 0x50000000 /* ip2 divided by 16 */ 151 #define PSC_ACR_TMR_IP2 0x40000000 /* ip2 */ 152 #define PSC_ACR_CTR_EXT_CLK_16 0x30000000 /* xtnl clock divided by 16 */ 153 #define PSC_ACR_CTR_TXCB 0x20000000 /* channel B xmitr clock */ 154 #define PSC_ACR_CTR_TXCA 0x10000000 /* channel A xmitr clock */ 155 #define PSC_ACR_CTR_IP2 0x00000000 /* ip2 */ 156 #define PSC_ACR_IEC0 0x01000000 /* interrupt enable ctrl for D_CTS */ 157 158 /* equates for int. status reg. */ 159 #define PSC_ISR_IPC 0x80000000 /* input port change*/ 160 #define PSC_ISR_BREAK 0x04000000 /* delta break */ 161 #define PSC_ISR_RX_RDY 0x02000000 /* receiver rdy /fifo full */ 162 #define PSC_ISR_TX_RDY 0x01000000 /* transmitter ready */ 163 #define PSC_ISR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */ 164 #define PSC_ISR_ERR 0x00400000 /* Error Status including FIFO */ 165 166 /* equates for int. mask reg. */ 167 #define PSC_IMR_CLEAR 0xff000000 /* Clear the imr */ 168 #define PSC_IMR_IPC 0x80000000 /* input port change*/ 169 #define PSC_IMR_BREAK 0x04000000 /* delta break */ 170 #define PSC_IMR_RX_RDY 0x02000000 /* rcvr ready / fifo full */ 171 #define PSC_IMR_TX_RDY 0x01000000 /* transmitter ready */ 172 #define PSC_IMR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */ 173 #define PSC_IMR_ERR 0x00400000 /* Error Status including FIFO */ 174 175 /* equates for input port reg. */ 176 #define PSC_IP_LPWRB 0x80000000 /* Low power mode in Ac97 */ 177 #define PSC_IP_TGL 0x40000000 /* test usage */ 178 #define PSC_IP_CTS 0x01000000 /* CTS */ 179 180 /* equates for output port bit set reg. */ 181 #define PSC_OPSET_RTS 0x01000000 /* Assert PSC_RTS output */ 182 183 /* equates for output port bit reset reg. */ 184 #define PSC_OPRESET_RTS 0x01000000 /* Assert PSC_RTS output */ 185 186 /* equates for rx FIFO number of data reg. */ 187 #define PSC_RFNUM(x) ((x&0xff)<<24)/* receive count */ 188 189 /* equates for tx FIFO number of data reg. */ 190 #define PSC_TFNUM(x) ((x&0xff)<<24)/* receive count */ 191 192 /* equates for rx FIFO status reg */ 193 #define PSC_RFSTAT_TAG(x) ((x&3)<<28) /* tag */ 194 #define PSC_RFSTAT_FRAME0 0x08 /* Frame Indicator 0 */ 195 #define PSC_RFSTAT_FRAME1 0x04 /* Frame Indicator 1 */ 196 #define PSC_RFSTAT_FRAME2 0x02 /* Frame Indicator 2 */ 197 #define PSC_RFSTAT_FRAME3 0x01 /* Frame Indicator 3 */ 198 #define PSC_RFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */ 199 #define PSC_RFSTAT_ERR 0x00400000 /* Fifo err */ 200 #define PSC_RFSTAT_UF 0x00200000 /* Underflow */ 201 #define PSC_RFSTAT_OF 0x00100000 /* overflow */ 202 #define PSC_RFSTAT_FR 0x00080000 /* frame ready */ 203 #define PSC_RFSTAT_FULL 0x00040000 /* full */ 204 #define PSC_RFSTAT_ALARM 0x00020000 /* alarm */ 205 #define PSC_RFSTAT_EMPTY 0x00010000 /* empty */ 206 207 /* equates for tx FIFO status reg */ 208 #define PSC_TFSTAT_TAG(x) ((x&3)<<28) /* tag */ 209 #define PSC_TFSTAT_FRAME0 0x08 /* Frame Indicator 0 */ 210 #define PSC_TFSTAT_FRAME1 0x04 /* Frame Indicator 1 */ 211 #define PSC_TFSTAT_FRAME2 0x02 /* Frame Indicator 2 */ 212 #define PSC_TFSTAT_FRAME3 0x01 /* Frame Indicator 3 */ 213 #define PSC_TFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */ 214 #define PSC_TFSTAT_ERR 0x00400000 /* Fifo err */ 215 #define PSC_TFSTAT_UF 0x00200000 /* Underflow */ 216 #define PSC_TFSTAT_OF 0x00100000 /* overflow */ 217 #define PSC_TFSTAT_FR 0x00080000 /* frame ready */ 218 #define PSC_TFSTAT_FULL 0x00040000 /* full */ 219 #define PSC_TFSTAT_ALARM 0x00020000 /* alarm */ 220 #define PSC_TFSTAT_EMPTY 0x00010000 /* empty */ 221 222 /* equates for rx FIFO control reg. */ 223 #define PSC_RFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */ 224 #define PSC_RFCNTL_FRAME 0x08000000 /* Frame mode enable */ 225 #define PSC_RFCNTL_GR(x) ((x&7)<<24) /* Granularity */ 226 227 /* equates for tx FIFO control reg. */ 228 #define PSC_TFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */ 229 #define PSC_TFCNTL_FRAME 0x08000000 /* Frame mode enable */ 230 #define PSC_TFCNTL_GR(x) ((x&7)<<24) /* Granularity */ 231 232 /* equates for rx FIFO alarm reg */ 233 #define PSC_RFALARM(x) (x&0x1ff) /* Alarm */ 234 235 /* equates for tx FIFO alarm reg */ 236 #define PSC_TFALARM(x) (x&0x1ff) /* Alarm */ 237 238 /* equates for rx FIFO read pointer */ 239 #define PSC_RFRPTR(x) (x&0x1ff) /* read pointer */ 240 241 /* equates for tx FIFO read pointer */ 242 #define PSC_TFRPTR(x) (x&0x1ff) /* read pointer */ 243 244 /* equates for rx FIFO write pointer */ 245 #define PSC_RFWPTR(x) (x&0x1ff) /* write pointer */ 246 247 /* equates for rx FIFO write pointer */ 248 #define PSC_TFWPTR(x) (x&0x1ff) /* write pointer */ 249 250 /* equates for rx FIFO last read frame pointer reg */ 251 #define PSC_RFLRFPTR(x) (x&0x1ff) /* last read frame pointer */ 252 253 /* equates for tx FIFO last read frame pointer reg */ 254 #define PSC_TFLRFPTR(x) (x&0x1ff) /* last read frame pointer */ 255 256 /* equates for rx FIFO last write frame pointer reg */ 257 #define PSC_RFLWFPTR(x) (x&0x1ff) /* last write frame pointer */ 258 259 /* equates for tx FIFO last write frame pointer reg */ 260 #define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */ 261 262 /* PCI configuration (only for PLL determination)*/ 263 #define PCI_REG_PCIGSCR (MMAP_XCPCI + 0x60) /* Global status/control register */ 264 #define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK 0x07000000 265 #define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT 24 266 267 #define PCI_REG_PCICAR (MMAP_XCPCI + 0xF8) /* Configuration Address Register */ 268 269 /* ------------------------------------------------------------------------ */ 270 /* 271 * Macro for General Purpose Timer 272 */ 273 /* Enable and Mode Select */ 274 #define GPT_OCT(x) (x & 0x3)<<4/* Output Compare Type */ 275 #define GPT_ICT(x) (x & 0x3) /* Input Capture Type */ 276 #define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */ 277 #define GPT_CTRL_CE 0x10 /* Counter Enable */ 278 #define GPT_CTRL_STPCNT 0x04 /* Stop continous */ 279 #define GPT_CTRL_ODRAIN 0x02 /* Open Drain */ 280 #define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */ 281 #define GPT_MODE_GPIO(x) (x & 0x3)<<4/* Gpio Mode Type */ 282 #define GPT_TMS_ICT 0x01 /* Input Capture Enable */ 283 #define GPT_TMS_OCT 0x02 /* Output Capture Enable */ 284 #define GPT_TMS_PWM 0x03 /* PWM Capture Enable */ 285 #define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */ 286 287 #define GPT_PWM_WIDTH(x) (x & 0xffff) 288 289 /* Status */ 290 #define GPT_STA_CAPTURE(x) (x & 0xffff)/* Read of internal counter */ 291 292 #define GPT_OVFPIN_OVF(x) (x & 0x70) /* Internal counter roll over */ 293 #define GPT_OVFPIN_PIN 0x01 /* Input pin - Timer 0 and 1 */ 294 295 #define GPT_INT_TEXP 0x08 /* Timer Expired in Internal Timer mode */ 296 #define GPT_INT_PWMP 0x04 /* PWM end of period occurred */ 297 #define GPT_INT_COMP 0x02 /* OC reference event occurred */ 298 #define GPT_INT_CAPT 0x01 /* IC reference event occurred */ 299 300 /* ------------------------------------------------------------------------ */ 301 /* 302 * Port configuration 303 */ 304 #define CONFIG_SYS_FEC1_PORT0_CONFIG 0x00000000 305 #define CONFIG_SYS_FEC1_PORT1_CONFIG 0x00000000 306 #define CONFIG_SYS_1284_PORT0_CONFIG 0x00000000 307 #define CONFIG_SYS_1284_PORT1_CONFIG 0x00000000 308 #define CONFIG_SYS_FEC2_PORT2_CONFIG 0x00000000 309 #define CONFIG_SYS_PEV_PORT2_CONFIG 0x00000000 310 #define CONFIG_SYS_GP0_PORT0_CONFIG 0x00000000 311 #define CONFIG_SYS_GP1_PORT2_CONFIG 0xaaaaaac0 312 #define CONFIG_SYS_PSC_PORT3_CONFIG 0x00020000 313 #define CONFIG_SYS_CS1_PORT3_CONFIG 0x00000000 314 #define CONFIG_SYS_CS2_PORT3_CONFIG 0x10000000 315 #define CONFIG_SYS_CS3_PORT3_CONFIG 0x40000000 316 #define CONFIG_SYS_CS4_PORT3_CONFIG 0x00000400 317 #define CONFIG_SYS_CS5_PORT3_CONFIG 0x00000200 318 #define CONFIG_SYS_PCI_PORT3_CONFIG 0x01400180 319 #define CONFIG_SYS_I2C_PORT3_CONFIG 0x00000000 320 #define CONFIG_SYS_GP2_PORT3_CONFIG 0x000200a0 321 322 /* ------------------------------------------------------------------------ */ 323 /* 324 * DRAM configuration 325 */ 326 327 /* Field definitions for the control register */ 328 #define CTL_MODE_ENABLE_SHIFT 31 329 #define CTL_CKE_SHIFT 30 330 #define CTL_DDR_SHIFT 29 331 #define CTL_REFRESH_SHIFT 28 332 #define CTL_ADDRMUX_SHIFT 24 333 #define CTL_PRECHARGE_SHIFT 23 334 #define CTL_DRIVE_RULE_SHIFT 22 335 #define CTL_REFRESH_INTERVAL_SHIFT 16 336 #define CTL_DQSOEN_SHIFT 8 337 #define CTL_BUFFERED_SHIFT 4 338 #define CTL_REFRESH_CMD_SHIFT 2 339 #define CTL_PRECHARGE_CMD_SHIFT 1 340 341 #define CTL_MODE_ENABLE (1<<CTL_MODE_ENABLE_SHIFT) 342 #define CTL_CKE_HIGH (1<<CTL_CKE_SHIFT) 343 #define CTL_DDR_MODE (1<<CTL_DDR_SHIFT) 344 #define CTL_REFRESH_ENABLE (1<<CTL_REFRESH_SHIFT) 345 #define CTL_ADDRMUX(value) ((value)<<CTL_ADDRMUX_SHIFT) 346 #define CTL_A8PRECHARGE (1<<CTL_PRECHARGE_SHIFT) 347 #define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT) 348 #define CTL_DQSOEN(value) ((value)<<CTL_DQSOEN_SHIFT) 349 #define CTL_BUFFERED (1<<CTL_BUFFERED_SHIFT) 350 #define CTL_REFRESH_CMD (1<<CTL_REFRESH_CMD_SHIFT) 351 #define CTL_PRECHARGE_CMD (1<<CTL_PRECHARGE_CMD_SHIFT) 352 353 /* Field definitions for config register 1 */ 354 355 #define CFG1_SRD2RWP_SHIFT 28 356 #define CFG1_SWT2RWP_SHIFT 24 357 #define CFG1_RLATENCY_SHIFT 20 358 #define CFG1_ACT2WR_SHIFT 16 359 #define CFG1_PRE2ACT_SHIFT 12 360 #define CFG1_REF2ACT_SHIFT 8 361 #define CFG1_WLATENCY_SHIFT 4 362 363 #define CFG1_SRD2RWP(value) ((value)<<CFG1_SRD2RWP_SHIFT) 364 #define CFG1_SWT2RWP(value) ((value)<<CFG1_SWT2RWP_SHIFT) 365 #define CFG1_RLATENCY(value) ((value)<<CFG1_RLATENCY_SHIFT) 366 #define CFG1_ACT2WR(value) ((value)<<CFG1_ACT2WR_SHIFT) 367 #define CFG1_PRE2ACT(value) ((value)<<CFG1_PRE2ACT_SHIFT) 368 #define CFG1_REF2ACT(value) ((value)<<CFG1_REF2ACT_SHIFT) 369 #define CFG1_WLATENCY(value) ((value)<<CFG1_WLATENCY_SHIFT) 370 371 /* Field definitions for config register 2 */ 372 #define CFG2_BRD2RP_SHIFT 28 373 #define CFG2_BWT2RWP_SHIFT 24 374 #define CFG2_BRD2WT_SHIFT 20 375 #define CFG2_BURSTLEN_SHIFT 16 376 377 #define CFG2_BRD2RP(value) ((value)<<CFG2_BRD2RP_SHIFT) 378 #define CFG2_BWT2RWP(value) ((value)<<CFG2_BWT2RWP_SHIFT) 379 #define CFG2_BRD2WT(value) ((value)<<CFG2_BRD2WT_SHIFT) 380 #define CFG2_BURSTLEN(value) ((value)<<CFG2_BURSTLEN_SHIFT) 381 382 /* Field definitions for the mode/extended mode register - mode 383 * register access 384 */ 385 #define MODE_REG_SHIFT 30 386 #define MODE_OPMODE_SHIFT 25 387 #define MODE_CL_SHIFT 22 388 #define MODE_BT_SHIFT 21 389 #define MODE_BURSTLEN_SHIFT 18 390 #define MODE_CMD_SHIFT 16 391 392 #define MODE_MODE 0 393 #define MODE_OPMODE(value) ((value)<<MODE_OPMODE_SHIFT) 394 #define MODE_CL(value) ((value)<<MODE_CL_SHIFT) 395 #define MODE_BT_INTERLEAVED (1<<MODE_BT_SHIFT) 396 #define MODE_BT_SEQUENTIAL (0<<MODE_BT_SHIFT) 397 #define MODE_BURSTLEN(value) ((value)<<MODE_BURSTLEN_SHIFT) 398 #define MODE_CMD (1<<MODE_CMD_SHIFT) 399 400 #define MODE_BURSTLEN_8 3 401 #define MODE_BURSTLEN_4 2 402 #define MODE_BURSTLEN_2 1 403 404 #define MODE_CL_2 2 405 #define MODE_CL_2p5 6 406 #define MODE_OPMODE_NORMAL 0 407 #define MODE_OPMODE_RESETDLL 2 408 409 410 /* Field definitions for the mode/extended mode register - extended 411 * mode register access 412 */ 413 #define MODE_X_DLL_SHIFT 18 /* DLL enable/disable */ 414 #define MODE_X_DS_SHIFT 19 /* Drive strength normal/reduced */ 415 #define MODE_X_QFC_SHIFT 20 /* QFC function (whatever that is) */ 416 #define MODE_X_OPMODE_SHIFT 21 417 418 #define MODE_EXTENDED (1<<MODE_REG_SHIFT) 419 #define MODE_X_DLL_ENABLE 0 420 #define MODE_X_DLL_DISABLE (1<<MODE_X_DLL_SHIFT) 421 #define MODE_X_DS_NORMAL 0 422 #define MODE_X_DS_REDUCED (1<<MODE_X_DS_SHIFT) 423 #define MODE_X_QFC_DISABLED 0 424 #define MODE_X_OPMODE(value) ((value)<<MODE_X_OPMODE_SHIFT) 425 426 #ifndef __ASSEMBLY__ 427 /* 428 * DMA control/status registers. 429 */ 430 struct mpc8220_dma { 431 u32 taskBar; /* DMA + 0x00 */ 432 u32 currentPointer; /* DMA + 0x04 */ 433 u32 endPointer; /* DMA + 0x08 */ 434 u32 variablePointer;/* DMA + 0x0c */ 435 436 u8 IntVect1; /* DMA + 0x10 */ 437 u8 IntVect2; /* DMA + 0x11 */ 438 u16 PtdCntrl; /* DMA + 0x12 */ 439 440 u32 IntPend; /* DMA + 0x14 */ 441 u32 IntMask; /* DMA + 0x18 */ 442 443 u16 tcr_0; /* DMA + 0x1c */ 444 u16 tcr_1; /* DMA + 0x1e */ 445 u16 tcr_2; /* DMA + 0x20 */ 446 u16 tcr_3; /* DMA + 0x22 */ 447 u16 tcr_4; /* DMA + 0x24 */ 448 u16 tcr_5; /* DMA + 0x26 */ 449 u16 tcr_6; /* DMA + 0x28 */ 450 u16 tcr_7; /* DMA + 0x2a */ 451 u16 tcr_8; /* DMA + 0x2c */ 452 u16 tcr_9; /* DMA + 0x2e */ 453 u16 tcr_a; /* DMA + 0x30 */ 454 u16 tcr_b; /* DMA + 0x32 */ 455 u16 tcr_c; /* DMA + 0x34 */ 456 u16 tcr_d; /* DMA + 0x36 */ 457 u16 tcr_e; /* DMA + 0x38 */ 458 u16 tcr_f; /* DMA + 0x3a */ 459 460 u8 IPR0; /* DMA + 0x3c */ 461 u8 IPR1; /* DMA + 0x3d */ 462 u8 IPR2; /* DMA + 0x3e */ 463 u8 IPR3; /* DMA + 0x3f */ 464 u8 IPR4; /* DMA + 0x40 */ 465 u8 IPR5; /* DMA + 0x41 */ 466 u8 IPR6; /* DMA + 0x42 */ 467 u8 IPR7; /* DMA + 0x43 */ 468 u8 IPR8; /* DMA + 0x44 */ 469 u8 IPR9; /* DMA + 0x45 */ 470 u8 IPR10; /* DMA + 0x46 */ 471 u8 IPR11; /* DMA + 0x47 */ 472 u8 IPR12; /* DMA + 0x48 */ 473 u8 IPR13; /* DMA + 0x49 */ 474 u8 IPR14; /* DMA + 0x4a */ 475 u8 IPR15; /* DMA + 0x4b */ 476 u8 IPR16; /* DMA + 0x4c */ 477 u8 IPR17; /* DMA + 0x4d */ 478 u8 IPR18; /* DMA + 0x4e */ 479 u8 IPR19; /* DMA + 0x4f */ 480 u8 IPR20; /* DMA + 0x50 */ 481 u8 IPR21; /* DMA + 0x51 */ 482 u8 IPR22; /* DMA + 0x52 */ 483 u8 IPR23; /* DMA + 0x53 */ 484 u8 IPR24; /* DMA + 0x54 */ 485 u8 IPR25; /* DMA + 0x55 */ 486 u8 IPR26; /* DMA + 0x56 */ 487 u8 IPR27; /* DMA + 0x57 */ 488 u8 IPR28; /* DMA + 0x58 */ 489 u8 IPR29; /* DMA + 0x59 */ 490 u8 IPR30; /* DMA + 0x5a */ 491 u8 IPR31; /* DMA + 0x5b */ 492 493 u32 res1; /* DMA + 0x5c */ 494 u32 res2; /* DMA + 0x60 */ 495 u32 res3; /* DMA + 0x64 */ 496 u32 MDEDebug; /* DMA + 0x68 */ 497 u32 ADSDebug; /* DMA + 0x6c */ 498 u32 Value1; /* DMA + 0x70 */ 499 u32 Value2; /* DMA + 0x74 */ 500 u32 Control; /* DMA + 0x78 */ 501 u32 Status; /* DMA + 0x7c */ 502 u32 EU00; /* DMA + 0x80 */ 503 u32 EU01; /* DMA + 0x84 */ 504 u32 EU02; /* DMA + 0x88 */ 505 u32 EU03; /* DMA + 0x8c */ 506 u32 EU04; /* DMA + 0x90 */ 507 u32 EU05; /* DMA + 0x94 */ 508 u32 EU06; /* DMA + 0x98 */ 509 u32 EU07; /* DMA + 0x9c */ 510 u32 EU10; /* DMA + 0xa0 */ 511 u32 EU11; /* DMA + 0xa4 */ 512 u32 EU12; /* DMA + 0xa8 */ 513 u32 EU13; /* DMA + 0xac */ 514 u32 EU14; /* DMA + 0xb0 */ 515 u32 EU15; /* DMA + 0xb4 */ 516 u32 EU16; /* DMA + 0xb8 */ 517 u32 EU17; /* DMA + 0xbc */ 518 u32 EU20; /* DMA + 0xc0 */ 519 u32 EU21; /* DMA + 0xc4 */ 520 u32 EU22; /* DMA + 0xc8 */ 521 u32 EU23; /* DMA + 0xcc */ 522 u32 EU24; /* DMA + 0xd0 */ 523 u32 EU25; /* DMA + 0xd4 */ 524 u32 EU26; /* DMA + 0xd8 */ 525 u32 EU27; /* DMA + 0xdc */ 526 u32 EU30; /* DMA + 0xe0 */ 527 u32 EU31; /* DMA + 0xe4 */ 528 u32 EU32; /* DMA + 0xe8 */ 529 u32 EU33; /* DMA + 0xec */ 530 u32 EU34; /* DMA + 0xf0 */ 531 u32 EU35; /* DMA + 0xf4 */ 532 u32 EU36; /* DMA + 0xf8 */ 533 u32 EU37; /* DMA + 0xfc */ 534 }; 535 536 /* 537 * PCI Header Registers 538 */ 539 typedef struct mpc8220_xcpci { 540 u32 dev_ven_id; /* 0xb00 - device/vendor ID */ 541 u32 stat_cmd_reg; /* 0xb04 - status command register */ 542 u32 class_code_rev_id; /* 0xb08 - class code / revision ID */ 543 u32 bist_htyp_lat_cshl; /* 0xb0c - BIST/HeaderType/Latency/cache line */ 544 u32 base0; /* 0xb10 - base address 0 */ 545 u32 base1; /* 0xb14 - base address 1 */ 546 u32 reserved1[4]; /* 0xb18->0xd27 - base address 2 - 5 */ 547 u32 cis; /* 0xb28 - cardBus CIS pointer */ 548 u32 sub_sys_ven_id; /* 0xb2c - sub system ID/ subsystem vendor ID */ 549 u32 reserved2; /* 0xb30 - expansion ROM base address */ 550 u32 reserved3; /* 0xb00 - reserved */ 551 u32 reserved4; /* 0xb00 - reserved */ 552 u32 mlat_mgnt_ipl; /* 0xb3c - MaxLat/MinGnt/ int pin/int line */ 553 u32 reserved5[8]; 554 /* MPC8220 specific - not accessible in PCI header space externally */ 555 u32 glb_stat_ctl; /* 0xb60 - Global Status Control */ 556 u32 target_bar0; /* 0xb64 - Target Base Address 0 */ 557 u32 target_bar1; /* 0xb68 - Target Base Address 1 */ 558 u32 target_ctrl; /* 0xb6c - Target Control */ 559 u32 init_win0; /* 0xb70 - Initiator Window 0 Base/Translation */ 560 u32 init_win1; /* 0xb74 - Initiator Window 1 Base/Translation */ 561 u32 init_win2; /* 0xb78 - Initiator Window 2 Base/Translation */ 562 u32 reserved6; /* 0xb7c - reserved */ 563 u32 init_win_cfg; /* 0xb80 */ 564 u32 init_ctrl; /* 0xb84 */ 565 u32 init_stat; /* 0xb88 */ 566 u32 reserved7[27]; 567 u32 cfg_adr; /* 0xbf8 */ 568 u32 reserved8; 569 } mpc8220_xcpci_t; 570 571 /* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB, 572 reg1 - 1GB */ 573 #define PCI_BASE_ADDR_REG0 0x40000000 574 #define PCI_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE) 575 #define PCI_TARGET_BASE_ADDR_REG0 (CONFIG_SYS_MBAR) 576 #define PCI_TARGET_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE) 577 #define PCI_TARGET_BASE_ADDR_EN 1<<0 578 579 580 /* PCI Global Status/Control Register (PCIGSCR) */ 581 #define PCI_GLB_STAT_CTRL_PE_SHIFT 29 582 #define PCI_GLB_STAT_CTRL_SE_SHIFT 28 583 #define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT 24 584 #define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK 0x7 585 #define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT 16 586 #define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK 0x7 587 #define PCI_GLB_STAT_CTRL_PEE_SHIFT 13 588 #define PCI_GLB_STAT_CTRL_SEE_SHIFT 12 589 #define PCI_GLB_STAT_CTRL_PR_SHIFT 0 590 591 #define PCI_GLB_STAT_CTRL_PE (1<<PCI_GLB_STAT_CTRL_PE_SHIFT) 592 #define PCI_GLB_STAT_CTRL_SE (1<<PCI_GLB_STAT_CTRL_SE_SHIFT) 593 #define PCI_GLB_STAT_CTRL_PEE (1<<PCI_GLB_STAT_CTRL_PEE_SHIFT) 594 #define PCI_GLB_STAT_CTRL_SEE (1<<PCI_GLB_STAT_CTRL_SEE_SHIFT) 595 #define PCI_GLB_STAT_CTRL_PR (1<<PCI_GLB_STAT_CTRL_PR_SHIFT) 596 597 /* PCI Target Control Register (PCITCR) */ 598 #define PCI_TARGET_CTRL_LD_SHIFT 24 599 #define PCI_TARGET_CTRL_P_SHIFT 16 600 601 #define PCI_TARGET_CTRL_LD (1<<PCI_TARGET_CTRL_LD_SHIFT) 602 #define PCI_TARGET_CTRL_P (1<<PCI_TARGET_CTRL_P_SHIFT) 603 604 /* PCI Initiator Window Configuration Register (PCIIWCR) */ 605 #define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT 27 606 #define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT 25 607 #define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK 0x3 608 #define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT 24 609 #define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT 19 610 #define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT 17 611 #define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK 0x3 612 #define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT 16 613 #define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT 11 614 #define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT 9 615 #define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK 0x3 616 #define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT 8 617 618 #define PCI_INIT_WIN_CFG_WIN_MEM_READ 0x0 619 #define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE 0x1 620 #define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE 0x2 621 622 #define PCI_INIT_WIN_CFG_WIN0_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT) 623 #define PCI_INIT_WIN_CFG_WIN0_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT) 624 #define PCI_INIT_WIN_CFG_WIN1_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT) 625 #define PCI_INIT_WIN_CFG_WIN1_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT) 626 #define PCI_INIT_WIN_CFG_WIN2_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT) 627 #define PCI_INIT_WIN_CFG_WIN2_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT) 628 629 /* PCI Initiator Control Register (PCIICR) */ 630 #define PCI_INIT_CTRL_REE_SHIFT 26 631 #define PCI_INIT_CTRL_IAE_SHIFT 25 632 #define PCI_INIT_CTRL_TAE_SHIFT 24 633 #define PCI_INIT_CTRL_MAX_RETRIES_SHIFT 0 634 #define PCI_INIT_CTRL_MAX_RETRIES_MASK 0xff 635 636 #define PCI_INIT_CTRL_REE (1<<PCI_INIT_CTRL_REE_SHIFT) 637 #define PCI_INIT_CTRL_IAE (1<<PCI_INIT_CTRL_IAE_SHIFT) 638 #define PCI_INIT_CTRL_TAE (1<<PCI_INIT_CTRL_TAE_SHIFT) 639 640 /* PCI Status/Command Register (PCISCR) - PCI Dword 1 */ 641 #define PCI_STAT_CMD_PE_SHIFT 31 642 #define PCI_STAT_CMD_SE_SHIFT 30 643 #define PCI_STAT_CMD_MA_SHIFT 29 644 #define PCI_STAT_CMD_TR_SHIFT 28 645 #define PCI_STAT_CMD_TS_SHIFT 27 646 #define PCI_STAT_CMD_DT_SHIFT 25 647 #define PCI_STAT_CMD_DT_MASK 0x3 648 #define PCI_STAT_CMD_DP_SHIFT 24 649 #define PCI_STAT_CMD_FC_SHIFT 23 650 #define PCI_STAT_CMD_R_SHIFT 22 651 #define PCI_STAT_CMD_66M_SHIFT 21 652 #define PCI_STAT_CMD_C_SHIFT 20 653 #define PCI_STAT_CMD_F_SHIFT 9 654 #define PCI_STAT_CMD_S_SHIFT 8 655 #define PCI_STAT_CMD_ST_SHIFT 7 656 #define PCI_STAT_CMD_PER_SHIFT 6 657 #define PCI_STAT_CMD_V_SHIFT 5 658 #define PCI_STAT_CMD_MW_SHIFT 4 659 #define PCI_STAT_CMD_SP_SHIFT 3 660 #define PCI_STAT_CMD_B_SHIFT 2 661 #define PCI_STAT_CMD_M_SHIFT 1 662 #define PCI_STAT_CMD_IO_SHIFT 0 663 664 #define PCI_STAT_CMD_PE (1<<PCI_STAT_CMD_PE_SHIFT) 665 #define PCI_STAT_CMD_SE (1<<PCI_STAT_CMD_SE_SHIFT) 666 #define PCI_STAT_CMD_MA (1<<PCI_STAT_CMD_MA_SHIFT) 667 #define PCI_STAT_CMD_TR (1<<PCI_STAT_CMD_TR_SHIFT) 668 #define PCI_STAT_CMD_TS (1<<PCI_STAT_CMD_TS_SHIFT) 669 #define PCI_STAT_CMD_DP (1<<PCI_STAT_CMD_DP_SHIFT) 670 #define PCI_STAT_CMD_FC (1<<PCI_STAT_CMD_FC_SHIFT) 671 #define PCI_STAT_CMD_R (1<<PCI_STAT_CMD_R_SHIFT) 672 #define PCI_STAT_CMD_66M (1<<PCI_STAT_CMD_66M_SHIFT) 673 #define PCI_STAT_CMD_C (1<<PCI_STAT_CMD_C_SHIFT) 674 #define PCI_STAT_CMD_F (1<<PCI_STAT_CMD_F_SHIFT) 675 #define PCI_STAT_CMD_S (1<<PCI_STAT_CMD_S_SHIFT) 676 #define PCI_STAT_CMD_ST (1<<PCI_STAT_CMD_ST_SHIFT) 677 #define PCI_STAT_CMD_PER (1<<PCI_STAT_CMD_PER_SHIFT) 678 #define PCI_STAT_CMD_V (1<<PCI_STAT_CMD_V_SHIFT) 679 #define PCI_STAT_CMD_MW (1<<PCI_STAT_CMD_MW_SHIFT) 680 #define PCI_STAT_CMD_SP (1<<PCI_STAT_CMD_SP_SHIFT) 681 #define PCI_STAT_CMD_B (1<<PCI_STAT_CMD_B_SHIFT) 682 #define PCI_STAT_CMD_M (1<<PCI_STAT_CMD_M_SHIFT) 683 #define PCI_STAT_CMD_IO (1<<PCI_STAT_CMD_IO_SHIFT) 684 685 /* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */ 686 #define PCI_CFG1_HT_SHIFT 16 687 #define PCI_CFG1_HT_MASK 0xff 688 #define PCI_CFG1_LT_SHIFT 8 689 #define PCI_CFG1_LT_MASK 0xff 690 #define PCI_CFG1_CLS_SHIFT 0 691 #define PCI_CFG1_CLS_MASK 0xf 692 693 /* function prototypes */ 694 void loadtask(int basetask, int tasks); 695 u32 dramSetup(void); 696 697 #if defined(CONFIG_PSC_CONSOLE) 698 int psc_serial_init (void); 699 void psc_serial_putc(const char c); 700 void psc_serial_puts (const char *s); 701 int psc_serial_getc(void); 702 int psc_serial_tstc(void); 703 void psc_serial_setbrg(void); 704 #endif 705 706 #if defined (CONFIG_EXTUART_CONSOLE) 707 int ext_serial_init (void); 708 void ext_serial_putc(const char c); 709 void ext_serial_puts (const char *s); 710 int ext_serial_getc(void); 711 int ext_serial_tstc(void); 712 void ext_serial_setbrg(void); 713 #endif 714 715 #endif /* __ASSEMBLY__ */ 716 717 #endif /* __MPC8220_H__ */ 718