1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * K2G EVM: Pinmux configuration
4 *
5 * (C) Copyright 2015
6 * Texas Instruments Incorporated, <www.ti.com>
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/mux-k2g.h>
12 #include <asm/arch/hardware.h>
13 #include "board.h"
14
15 struct pin_cfg k2g_generic_pin_cfg[] = {
16 /* UART0 */
17 { 115, MODE(0) }, /* SOC_UART0_RXD */
18 { 116, MODE(0) }, /* SOC_UART0_TXD */
19
20 /* I2C 0 */
21 { 223, MODE(0) }, /* SOC_I2C0_SCL */
22 { 224, MODE(0) }, /* SOC_I2C0_SDA */
23
24 /* I2C 1 */
25 { 225, MODE(0) }, /* SOC_I2C1_SCL */
26 { 226, MODE(0) }, /* SOC_I2C1_SDA */
27 { MAX_PIN_N, }
28 };
29
30 struct pin_cfg k2g_evm_pin_cfg[] = {
31 /* GPMC */
32 { 0, MODE(0) }, /* GPMCAD0 */
33 { 1, MODE(0) }, /* GPMCAD1 */
34 { 2, MODE(0) }, /* GPMCAD2 */
35 { 3, MODE(0) }, /* GPMCAD3 */
36 { 4, MODE(0) }, /* GPMCAD4 */
37 { 5, MODE(0) }, /* GPMCAD5 */
38 { 6, MODE(0) }, /* GPMCAD6 */
39 { 7, MODE(0) }, /* GPMCAD7 */
40 { 8, MODE(0) }, /* GPMCAD8 */
41 { 9, MODE(0) }, /* GPMCAD9 */
42 { 10, MODE(0) }, /* GPMCAD10 */
43 { 11, MODE(0) }, /* GPMCAD11 */
44 { 12, MODE(0) }, /* GPMCAD12 */
45 { 13, MODE(0) }, /* GPMCAD13 */
46 { 14, MODE(0) }, /* GPMCAD14 */
47 { 15, MODE(0) }, /* GPMCAD15 */
48 { 17, MODE(0) }, /* GPMCADVNALE */
49 { 18, MODE(0) }, /* GPMCOENREN */
50 { 19, MODE(0) }, /* GPMCWEN */
51 { 20, MODE(0) }, /* GPMCBE0NCLE */
52 { 22, MODE(0) }, /* GPMCWAIT0 */
53 { 24, MODE(0) }, /* GPMCWPN */
54 { 26, MODE(0) }, /* GPMCCSN0 */
55
56 /* GPIOs */
57 { 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */
58 { 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */
59 { 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */
60 { 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */
61 { 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */
62 { 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */
63 { 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */
64 { 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */
65 { 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */
66 { 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */
67 { 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */
68 { 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */
69 { 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/
70 { 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */
71 { 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */
72 { 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */
73 { 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */
74 { 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */
75
76 /* MLB */
77 { 23, MODE(2) }, /* SOC_MLBCLK */
78 { 25, MODE(2) }, /* SOC_MLBSIG */
79 { 27, MODE(2) }, /* SOC_MLBDAT */
80
81 /* DSS */
82 { 30, MODE(0) }, /* SOC_DSSDATA23 */
83 { 31, MODE(0) }, /* SOC_DSSDATA22 */
84 { 32, MODE(0) }, /* SOC_DSSDATA21 */
85 { 33, MODE(0) }, /* SOC_DSSDATA20 */
86 { 34, MODE(0) }, /* SOC_DSSDATA19 */
87 { 35, MODE(0) }, /* SOC_DSSDATA18 */
88 { 36, MODE(0) }, /* SOC_DSSDATA17 */
89 { 37, MODE(0) }, /* SOC_DSSDATA16 */
90 { 38, MODE(0) }, /* SOC_DSSDATA15 */
91 { 39, MODE(0) }, /* SOC_DSSDATA14 */
92 { 40, MODE(0) }, /* SOC_DSSDATA13 */
93 { 41, MODE(0) }, /* SOC_DSSDATA12 */
94 { 42, MODE(0) }, /* SOC_DSSDATA11 */
95 { 43, MODE(0) }, /* SOC_DSSDATA10 */
96 { 44, MODE(0) }, /* SOC_DSSDATA9 */
97 { 45, MODE(0) }, /* SOC_DSSDATA8 */
98 { 46, MODE(0) }, /* SOC_DSSDATA7 */
99 { 47, MODE(0) }, /* SOC_DSSDATA6 */
100 { 48, MODE(0) }, /* SOC_DSSDATA5 */
101 { 49, MODE(0) }, /* SOC_DSSDATA4 */
102 { 50, MODE(0) }, /* SOC_DSSDATA3 */
103 { 51, MODE(0) }, /* SOC_DSSDATA2 */
104 { 52, MODE(0) }, /* SOC_DSSDATA1 */
105 { 53, MODE(0) }, /* SOC_DSSDATA0 */
106 { 54, MODE(0) }, /* SOC_DSSVSYNC */
107 { 55, MODE(0) }, /* SOC_DSSHSYNC */
108 { 56, MODE(0) }, /* SOC_DSSPCLK */
109 { 57, MODE(0) }, /* SOC_DSS_DE */
110 { 58, MODE(0) }, /* SOC_DSS_FID */
111 { 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */
112
113 /* MMC1 */
114 { 59, MODE(0) }, /* SOC_MMC1_DAT7 */
115 { 60, MODE(0) }, /* SOC_MMC1_DAT6 */
116 { 61, MODE(0) }, /* SOC_MMC1_DAT5 */
117 { 62, MODE(0) }, /* SOC_MMC1_DAT4 */
118 { 63, MODE(0) }, /* SOC_MMC1_DAT3 */
119 { 64, MODE(0) }, /* SOC_MMC1_DAT2 */
120 { 65, MODE(0) }, /* SOC_MMC1_DAT1 */
121 { 66, MODE(0) }, /* SOC_MMC1_DAT0 */
122 { 67, MODE(0) }, /* SOC_MMC1_CLK */
123 { 68, MODE(0) }, /* SOC_MMC1_CMD */
124 { 69, MODE(0) }, /* MMC1SDCD TP125 */
125 { 70, MODE(0) }, /* SOC_MMC1_SDWP */
126 { 71, MODE(0) }, /* MMC1POW TP124 */
127
128 /* RGMII */
129 { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */
130 { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */
131 { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */
132 { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */
133 { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */
134 { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */
135 { 85, MODE(1) }, /* SOC_RGMII_TXCLK */
136 { 91, MODE(1) }, /* SOC_RGMII_TXD3 */
137 { 92, MODE(1) }, /* SOC_RGMII_TXD2 */
138 { 93, MODE(1) }, /* SOC_RGMII_TXD1 */
139 { 94, MODE(1) }, /* SOC_RGMII_TXD0 */
140 { 95, MODE(1) }, /* SOC_RGMII_TXCTL */
141 { 98, MODE(0) }, /* SOC_MDIO_DATA */
142 { 99, MODE(0) }, /* SOC_MDIO_CLK */
143
144 /* PWM */
145 { 73, MODE(4) }, /* SOC_EHRPWM3A */
146 { 74, MODE(4) }, /* SOC_EHRPWM3B */
147 { 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */
148 { 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */
149 { 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */
150 { 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */
151 { 199, MODE(4) }, /* SOC_EHRPWM4A */
152 { 200, MODE(4) }, /* SOC_EHRPWM4B */
153 { 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */
154 { 219, MODE(4) }, /* SOC_EHRPWM5A */
155 { 220, MODE(4) }, /* SOC_EHRPWM5B */
156 { 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */
157
158 /* SPI3 */
159 { 86, MODE(1) }, /* SOC_SPI3_SCS0 */
160 { 88, MODE(1) }, /* SOC_SPI3_CLK */
161 { 89, MODE(1) }, /* SOC_SPI3_MISO */
162 { 90, MODE(1) }, /* SOC_SPI3_MOSI */
163
164 /* CLK */
165 { 97, MODE(0) }, /* SMD - TP132 */
166
167 /* SPI0 */
168 { 100, MODE(0) }, /* SOC_SPI0_SCS0 */
169 { 101, MODE(0) }, /* SOC_SPI0_SCS1 */
170 { 102, MODE(0) }, /* SOC_SPI0_CLK */
171 { 103, MODE(0) }, /* SOC_SPI0_MISO */
172 { 104, MODE(0) }, /* SOC_SPI0_MOSI */
173
174 /* SPI1 NORFLASH */
175 { 105, MODE(0) }, /* SOC_SPI1_SCS0 */
176 { 107, MODE(0) }, /* SOC_SPI1_CLK */
177 { 108, MODE(0) }, /* SOC_SPI1_MISO */
178 { 109, MODE(0) }, /* SOC_SPI1_MOSI */
179
180 /* SPI2 */
181 { 110, MODE(0) }, /* SOC_SPI2_SCS0 */
182 { 111, MODE(1) }, /* SOC_HOUT */
183 { 112, MODE(0) }, /* SOC_SPI2_CLK */
184 { 113, MODE(0) }, /* SOC_SPI2_MISO */
185 { 114, MODE(0) }, /* SOC_SPI2_MOSI */
186
187 /* UART0 */
188 { 115, MODE(0) }, /* SOC_UART0_RXD */
189 { 116, MODE(0) }, /* SOC_UART0_TXD */
190 { 117, MODE(0) }, /* SOC_UART0_CTSn */
191 { 118, MODE(0) }, /* SOC_UART0_RTSn */
192
193 /* UART1 */
194 { 119, MODE(0) }, /* SOC_UART1_RXD */
195 { 120, MODE(0) }, /* SOC_UART1_TXD */
196 { 121, MODE(0) }, /* SOC_UART1_CTSn */
197 { 122, MODE(0) }, /* SOC_UART1_RTSn */
198
199 /* UART2 */
200 { 123, MODE(0) }, /* SOC_UART2_RXD */
201 { 124, MODE(0) }, /* SOC_UART2_TXD */
202 { 125, MODE(0) }, /* UART0_TXVR_EN */
203 { 126, MODE(4) }, /* SOC_CPTS_TS_COMP */
204
205 /* DCAN */
206 { 127, MODE(0) }, /* SOC_DCAN0_TX */
207 { 128, MODE(0) }, /* SOC_DCAN0_RX */
208 { 137, MODE(1) }, /* SOC_DCAN1_TX */
209 { 138, MODE(1) }, /* SOC_DCAN1_RX */
210
211 /* QSPI */
212 { 129, MODE(0) }, /* SOC_QSPI_CLK */
213 { 130, MODE(0) }, /* SOC_QSPI_RTCLK */
214 { 131, MODE(0) }, /* SOC_QSPI_D0 */
215 { 132, MODE(0) }, /* SOC_QSPI_D1 */
216 { 133, MODE(0) }, /* SOC_QSPI_D2 */
217 { 134, MODE(0) }, /* SOC_QSPI_D3 */
218 { 135, MODE(0) }, /* SOC_QSPI_CSN0 */
219 { 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */
220
221 /* MCASP2 */
222 { 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */
223 { 140, MODE(4) }, /* SOC_MCASP2AXR1 */
224 { 141, MODE(4) }, /* SOC_MCASP2AXR2 */
225 { 142, MODE(4) }, /* SOC_MCASP2AXR3 */
226 { 143, MODE(4) }, /* SOC_MCASP2AXR4 */
227 { 144, MODE(4) }, /* SOC_MCASP2AXR5 */
228 { 145, MODE(4) }, /* SOC_McASP2ACLKR */
229 { 146, MODE(4) }, /* SOC_McASP2FSR */
230 { 147, MODE(4) }, /* SOC_McASP2AHCLKR */
231 { 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */
232 { 149, MODE(4) }, /* SOC_McASP2FSX */
233 { 150, MODE(4) }, /* SOC_McASP2AHCLKX */
234 { 151, MODE(4) }, /* SOC_McASP2ACLKX */
235
236 /* MCASP1 */
237 { 152, MODE(4) }, /* SOC_MCASP1ACLKR */
238 { 153, MODE(4) }, /* SOC_MCASP1FSR */
239 { 154, MODE(4) }, /* SOC_MCASP1AHCLKR */
240 { 155, MODE(4) }, /* SOC_MCASP1ACLKX */
241 { 156, MODE(4) }, /* SOC_MCASP1FSX */
242 { 157, MODE(4) }, /* SOC_MCASP1AHCLKX */
243 { 158, MODE(4) }, /* SOC_MCASP1AMUTE */
244 { 159, MODE(4) }, /* SOC_MCASP1AXR0 */
245 { 160, MODE(4) }, /* SOC_MCASP1AXR1 */
246 { 161, MODE(4) }, /* SOC_MCASP1AXR2 */
247 { 162, MODE(4) }, /* SOC_MCASP1AXR3 */
248 { 163, MODE(4) }, /* SOC_MCASP1AXR4 */
249 { 164, MODE(4) }, /* SOC_MCASP1AXR5 */
250 { 165, MODE(4) }, /* SOC_MCASP1AXR6 */
251 { 166, MODE(4) }, /* SOC_MCASP1AXR7 */
252 { 167, MODE(4) }, /* SOC_MCASP1AXR8 */
253 { 168, MODE(4) }, /* SOC_MCASP1AXR9 */
254
255 /* MCASP0 */
256 { 169, MODE(4) }, /* SOC_MCASP0AMUTE */
257 { 170, MODE(4) }, /* SOC_MCASP0ACLKR */
258 { 171, MODE(4) }, /* SOC_MCASP0FSR */
259 { 172, MODE(4) }, /* SOC_MCASP0AHCLKR */
260 { 173, MODE(4) }, /* SOC_MCASP0ACLKX */
261 { 174, MODE(4) }, /* SOC_MCASP0FSX */
262 { 175, MODE(4) }, /* SOC_MCASP0AHCLKX */
263 { 176, MODE(4) }, /* SOC_MCASP0AXR0 */
264 { 177, MODE(4) }, /* SOC_MCASP0AXR1 */
265 { 178, MODE(4) }, /* SOC_MCASP0AXR2 */
266 { 179, MODE(4) }, /* SOC_MCASP0AXR3 */
267 { 180, MODE(4) }, /* SOC_MCASP0AXR4 */
268 { 181, MODE(4) }, /* SOC_MCASP0AXR5 */
269 { 182, MODE(4) }, /* SOC_MCASP0AXR6 */
270 { 183, MODE(4) }, /* SOC_MCASP0AXR7 */
271 { 184, MODE(4) }, /* SOC_MCASP0AXR8 */
272 { 185, MODE(4) }, /* SOC_MCASP0AXR9 */
273 { 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */
274 { 188, MODE(4) }, /* SOC_MCASP0AXR12 */
275 { 189, MODE(4) }, /* SOC_MCASP0AXR13 */
276 { 190, MODE(4) }, /* SOC_MCASP0AXR14 */
277 { 191, MODE(4) }, /* SOC_MCASP0AXR15 */
278
279 /* MMC0 */
280 { 192, MODE(2) }, /* SOC_MMC0_DAT3 */
281 { 193, MODE(2) }, /* SOC_MMC0_DAT2 */
282 { 194, MODE(2) }, /* SOC_MMC0_DAT1 */
283 { 195, MODE(2) }, /* SOC_MMC0_DAT0 */
284 { 196, MODE(2) }, /* SOC_MMC0_CLK */
285 { 197, MODE(2) }, /* SOC_MMC0_CMD */
286 { 187, MODE(2) }, /* SOC_MMC0_SDCD */
287
288 /* McBSP */
289 { 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */
290 { 29, MODE(2) }, /* SOC_TIMO1 */
291 { 210, MODE(2) }, /* SOC_MCBSPDR */
292 { 211, MODE(2) }, /* SOC_MCBSPDX */
293 { 212, MODE(2) }, /* SOC_MCBSPFSX */
294 { 213, MODE(2) }, /* SOC_MCBSPCLKX */
295 { 214, MODE(2) }, /* SOC_MCBSPFSR */
296 { 215, MODE(2) }, /* SOC_MCBSPCLKR */
297
298 /* I2C */
299 { 223, MODE(0) }, /* SOC_I2C0_SCL */
300 { 224, MODE(0) }, /* SOC_I2C0_SDA */
301 { 225, MODE(0) }, /* SOC_I2C1_SCL */
302 { 226, MODE(0) }, /* SOC_I2C1_SDA */
303 { 227, MODE(0) }, /* SOC_I2C2_SCL */
304 { 228, MODE(0) }, /* SOC_I2C2_SDA */
305 { 229, MODE(0) }, /* NMIz */
306 { 230, MODE(0) }, /* LRESETz */
307 { 231, MODE(0) }, /* LRESETNMIENz */
308
309 { 235, MODE(0) },
310 { 236, MODE(0) },
311 { 237, MODE(0) },
312 { 238, MODE(0) },
313 { 239, MODE(0) },
314 { 240, MODE(0) },
315 { 241, MODE(0) },
316 { 242, MODE(0) },
317 { 243, MODE(0) },
318 { 244, MODE(0) },
319
320 { 258, MODE(0) }, /* USB0DRVVBUS */
321 { 259, MODE(0) }, /* USB1DRVVBUS */
322 { MAX_PIN_N, }
323 };
324
325 struct pin_cfg k2g_ice_evm_pin_cfg[] = {
326 /* MMC 1 */
327 { 63, MODE(0) | PIN_PTD }, /* MMC1_DAT3.MMC1_DAT3 */
328 { 64, MODE(0) | PIN_PTU }, /* MMC1_DAT2.MMC1_DAT2 */
329 { 65, MODE(0) | PIN_PTU }, /* MMC1_DAT1.MMC1_DAT1 */
330 { 66, MODE(0) | PIN_PTD }, /* MMC1_DAT0.MMC1_DAT0 */
331 { 67, MODE(0) | PIN_PTD }, /* MMC1_CLK.MMC1_CLK */
332 { 68, MODE(0) | PIN_PTD }, /* MMC1_CMD.MMC1_CMD */
333 { 69, MODE(3) | PIN_PTU }, /* MMC1_SDCD.GPIO0_69 */
334 { 70, MODE(0) | PIN_PTU }, /* MMC1_SDWP.MMC1_SDWP */
335 { 71, MODE(0) | PIN_PTD }, /* MMC1_POW.MMC1_POW */
336
337 /* I2C 0 */
338 { 223, MODE(0) }, /* SOC_I2C0_SCL */
339 { 224, MODE(0) }, /* SOC_I2C0_SDA */
340
341 /* QSPI */
342 { 129, MODE(0) }, /* SOC_QSPI_CLK */
343 { 130, MODE(0) }, /* SOC_QSPI_RTCLK */
344 { 131, MODE(0) }, /* SOC_QSPI_D0 */
345 { 132, MODE(0) }, /* SOC_QSPI_D1 */
346 { 133, MODE(0) }, /* SOC_QSPI_D2 */
347 { 134, MODE(0) }, /* SOC_QSPI_D3 */
348 { 135, MODE(0) }, /* SOC_QSPI_CSN0 */
349 { MAX_PIN_N, }
350 };
351
k2g_mux_config(void)352 void k2g_mux_config(void)
353 {
354 if (!board_ti_was_eeprom_read()) {
355 configure_pin_mux(k2g_generic_pin_cfg);
356 } else if (board_is_k2g_gp() || board_is_k2g_g1()) {
357 configure_pin_mux(k2g_evm_pin_cfg);
358 } else if (board_is_k2g_ice()) {
359 configure_pin_mux(k2g_ice_evm_pin_cfg);
360 } else {
361 puts("Unknown board, cannot configure pinmux.");
362 hang();
363 }
364 }
365