1 /*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_I386_H
20 #define CPU_I386_H
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 #ifdef TARGET_X86_64
26 #define TARGET_LONG_BITS 64
27 #else
28 #define TARGET_LONG_BITS 32
29 #endif
30
31 /* target supports implicit self modifying code */
32 #define TARGET_HAS_SMC
33 /* support for self modifying code even if the modified instruction is
34 close to the modifying instruction */
35 #define TARGET_HAS_PRECISE_SMC
36
37 #define TARGET_HAS_ICE 1
38
39 #ifdef TARGET_X86_64
40 #define ELF_MACHINE EM_X86_64
41 #define ELF_MACHINE_UNAME "x86_64"
42 #else
43 #define ELF_MACHINE EM_386
44 #define ELF_MACHINE_UNAME "i686"
45 #endif
46
47 #define CPUArchState struct CPUX86State
48
49 #include "exec/cpu-defs.h"
50
51 #include "fpu/softfloat.h"
52
53 #define R_EAX 0
54 #define R_ECX 1
55 #define R_EDX 2
56 #define R_EBX 3
57 #define R_ESP 4
58 #define R_EBP 5
59 #define R_ESI 6
60 #define R_EDI 7
61
62 #define R_AL 0
63 #define R_CL 1
64 #define R_DL 2
65 #define R_BL 3
66 #define R_AH 4
67 #define R_CH 5
68 #define R_DH 6
69 #define R_BH 7
70
71 #define R_ES 0
72 #define R_CS 1
73 #define R_SS 2
74 #define R_DS 3
75 #define R_FS 4
76 #define R_GS 5
77
78 /* segment descriptor fields */
79 #define DESC_G_MASK (1 << 23)
80 #define DESC_B_SHIFT 22
81 #define DESC_B_MASK (1 << DESC_B_SHIFT)
82 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
83 #define DESC_L_MASK (1 << DESC_L_SHIFT)
84 #define DESC_AVL_MASK (1 << 20)
85 #define DESC_P_MASK (1 << 15)
86 #define DESC_DPL_SHIFT 13
87 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
88 #define DESC_S_MASK (1 << 12)
89 #define DESC_TYPE_SHIFT 8
90 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
91 #define DESC_A_MASK (1 << 8)
92
93 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
94 #define DESC_C_MASK (1 << 10) /* code: conforming */
95 #define DESC_R_MASK (1 << 9) /* code: readable */
96
97 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
98 #define DESC_W_MASK (1 << 9) /* data: writable */
99
100 #define DESC_TSS_BUSY_MASK (1 << 9)
101
102 /* eflags masks */
103 #define CC_C 0x0001
104 #define CC_P 0x0004
105 #define CC_A 0x0010
106 #define CC_Z 0x0040
107 #define CC_S 0x0080
108 #define CC_O 0x0800
109
110 #define TF_SHIFT 8
111 #define IOPL_SHIFT 12
112 #define VM_SHIFT 17
113
114 #define TF_MASK 0x00000100
115 #define IF_MASK 0x00000200
116 #define DF_MASK 0x00000400
117 #define IOPL_MASK 0x00003000
118 #define NT_MASK 0x00004000
119 #define RF_MASK 0x00010000
120 #define VM_MASK 0x00020000
121 #define AC_MASK 0x00040000
122 #define VIF_MASK 0x00080000
123 #define VIP_MASK 0x00100000
124 #define ID_MASK 0x00200000
125
126 /* hidden flags - used internally by qemu to represent additional cpu
127 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
128 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
129 positions to ease oring with eflags. */
130 /* current cpl */
131 #define HF_CPL_SHIFT 0
132 /* true if soft mmu is being used */
133 #define HF_SOFTMMU_SHIFT 2
134 /* true if hardware interrupts must be disabled for next instruction */
135 #define HF_INHIBIT_IRQ_SHIFT 3
136 /* 16 or 32 segments */
137 #define HF_CS32_SHIFT 4
138 #define HF_SS32_SHIFT 5
139 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
140 #define HF_ADDSEG_SHIFT 6
141 /* copy of CR0.PE (protected mode) */
142 #define HF_PE_SHIFT 7
143 #define HF_TF_SHIFT 8 /* must be same as eflags */
144 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
145 #define HF_EM_SHIFT 10
146 #define HF_TS_SHIFT 11
147 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
148 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
149 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
150 #define HF_RF_SHIFT 16 /* must be same as eflags */
151 #define HF_VM_SHIFT 17 /* must be same as eflags */
152 #define HF_AC_SHIFT 18 /* must be same as eflags */
153 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
154 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
155 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
156 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
157 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
158
159 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
160 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
161 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
162 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
163 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
164 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
165 #define HF_PE_MASK (1 << HF_PE_SHIFT)
166 #define HF_TF_MASK (1 << HF_TF_SHIFT)
167 #define HF_MP_MASK (1 << HF_MP_SHIFT)
168 #define HF_EM_MASK (1 << HF_EM_SHIFT)
169 #define HF_TS_MASK (1 << HF_TS_SHIFT)
170 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
171 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
172 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
173 #define HF_RF_MASK (1 << HF_RF_SHIFT)
174 #define HF_VM_MASK (1 << HF_VM_SHIFT)
175 #define HF_AC_MASK (1 << HF_AC_SHIFT)
176 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
177 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
178 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
179 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
180 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
181
182 /* hflags2 */
183
184 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
185 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
186 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
187 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
188
189 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
190 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
191 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
192 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
193
194 #define CR0_PE_SHIFT 0
195 #define CR0_MP_SHIFT 1
196
197 #define CR0_PE_MASK (1U << 0)
198 #define CR0_MP_MASK (1U << 1)
199 #define CR0_EM_MASK (1U << 2)
200 #define CR0_TS_MASK (1U << 3)
201 #define CR0_ET_MASK (1U << 4)
202 #define CR0_NE_MASK (1U << 5)
203 #define CR0_WP_MASK (1U << 16)
204 #define CR0_AM_MASK (1U << 18)
205 #define CR0_PG_MASK (1U << 31)
206
207 #define CR4_VME_MASK (1U << 0)
208 #define CR4_PVI_MASK (1U << 1)
209 #define CR4_TSD_MASK (1U << 2)
210 #define CR4_DE_MASK (1U << 3)
211 #define CR4_PSE_MASK (1U << 4)
212 #define CR4_PAE_MASK (1U << 5)
213 #define CR4_MCE_MASK (1U << 6)
214 #define CR4_PGE_MASK (1U << 7)
215 #define CR4_PCE_MASK (1U << 8)
216 #define CR4_OSFXSR_SHIFT 9
217 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
218 #define CR4_OSXMMEXCPT_MASK (1U << 10)
219 #define CR4_VMXE_MASK (1U << 13)
220 #define CR4_SMXE_MASK (1U << 14)
221 #define CR4_FSGSBASE_MASK (1U << 16)
222 #define CR4_PCIDE_MASK (1U << 17)
223 #define CR4_OSXSAVE_MASK (1U << 18)
224 #define CR4_SMEP_MASK (1U << 20)
225 #define CR4_SMAP_MASK (1U << 21)
226
227 #define DR6_BD (1 << 13)
228 #define DR6_BS (1 << 14)
229 #define DR6_BT (1 << 15)
230 #define DR6_FIXED_1 0xffff0ff0
231
232 #define DR7_GD (1 << 13)
233 #define DR7_TYPE_SHIFT 16
234 #define DR7_LEN_SHIFT 18
235 #define DR7_FIXED_1 0x00000400
236 #define DR7_LOCAL_BP_MASK 0x55
237 #define DR7_MAX_BP 4
238 #define DR7_TYPE_BP_INST 0x0
239 #define DR7_TYPE_DATA_WR 0x1
240 #define DR7_TYPE_IO_RW 0x2
241 #define DR7_TYPE_DATA_RW 0x3
242
243 #define PG_PRESENT_BIT 0
244 #define PG_RW_BIT 1
245 #define PG_USER_BIT 2
246 #define PG_PWT_BIT 3
247 #define PG_PCD_BIT 4
248 #define PG_ACCESSED_BIT 5
249 #define PG_DIRTY_BIT 6
250 #define PG_PSE_BIT 7
251 #define PG_GLOBAL_BIT 8
252 #define PG_PSE_PAT_BIT 12
253 #define PG_NX_BIT 63
254
255 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
256 #define PG_RW_MASK (1 << PG_RW_BIT)
257 #define PG_USER_MASK (1 << PG_USER_BIT)
258 #define PG_PWT_MASK (1 << PG_PWT_BIT)
259 #define PG_PCD_MASK (1 << PG_PCD_BIT)
260 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
261 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
262 #define PG_PSE_MASK (1 << PG_PSE_BIT)
263 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
264 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
265 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
266 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
267 #define PG_HI_USER_MASK 0x7ff0000000000000LL
268 #define PG_NX_MASK (1ULL << PG_NX_BIT)
269
270 #define PG_ERROR_W_BIT 1
271
272 #define PG_ERROR_P_MASK 0x01
273 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
274 #define PG_ERROR_U_MASK 0x04
275 #define PG_ERROR_RSVD_MASK 0x08
276 #define PG_ERROR_I_D_MASK 0x10
277
278 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
279 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
280
281 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
282 #define MCE_BANKS_DEF 10
283
284 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
285 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
286 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
287
288 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
289 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
290 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
291 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
292 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
293 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
294 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
295 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
296 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
297
298 /* MISC register defines */
299 #define MCM_ADDR_SEGOFF 0 /* segment offset */
300 #define MCM_ADDR_LINEAR 1 /* linear address */
301 #define MCM_ADDR_PHYS 2 /* physical address */
302 #define MCM_ADDR_MEM 3 /* memory address */
303 #define MCM_ADDR_GENERIC 7 /* generic */
304
305 #define MSR_IA32_TSC 0x10
306 #define MSR_IA32_APICBASE 0x1b
307 #define MSR_IA32_APICBASE_BSP (1<<8)
308 #define MSR_IA32_APICBASE_ENABLE (1<<11)
309 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
310 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
311 #define MSR_TSC_ADJUST 0x0000003b
312 #define MSR_IA32_TSCDEADLINE 0x6e0
313
314 #define MSR_P6_PERFCTR0 0xc1
315
316 #define MSR_MTRRcap 0xfe
317 #define MSR_MTRRcap_VCNT 8
318 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
319 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
320
321 #define MSR_IA32_SYSENTER_CS 0x174
322 #define MSR_IA32_SYSENTER_ESP 0x175
323 #define MSR_IA32_SYSENTER_EIP 0x176
324
325 #define MSR_MCG_CAP 0x179
326 #define MSR_MCG_STATUS 0x17a
327 #define MSR_MCG_CTL 0x17b
328
329 #define MSR_P6_EVNTSEL0 0x186
330
331 #define MSR_IA32_PERF_STATUS 0x198
332
333 #define MSR_IA32_MISC_ENABLE 0x1a0
334 /* Indicates good rep/movs microcode on some processors: */
335 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
336
337 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
338 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
339
340 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
341
342 #define MSR_MTRRfix64K_00000 0x250
343 #define MSR_MTRRfix16K_80000 0x258
344 #define MSR_MTRRfix16K_A0000 0x259
345 #define MSR_MTRRfix4K_C0000 0x268
346 #define MSR_MTRRfix4K_C8000 0x269
347 #define MSR_MTRRfix4K_D0000 0x26a
348 #define MSR_MTRRfix4K_D8000 0x26b
349 #define MSR_MTRRfix4K_E0000 0x26c
350 #define MSR_MTRRfix4K_E8000 0x26d
351 #define MSR_MTRRfix4K_F0000 0x26e
352 #define MSR_MTRRfix4K_F8000 0x26f
353
354 #define MSR_PAT 0x277
355
356 #define MSR_MTRRdefType 0x2ff
357
358 #define MSR_CORE_PERF_FIXED_CTR0 0x309
359 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
360 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
361 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
362 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
363 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
364 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
365
366 #define MSR_MC0_CTL 0x400
367 #define MSR_MC0_STATUS 0x401
368 #define MSR_MC0_ADDR 0x402
369 #define MSR_MC0_MISC 0x403
370
371 #define MSR_EFER 0xc0000080
372
373 #define MSR_EFER_SCE (1 << 0)
374 #define MSR_EFER_LME (1 << 8)
375 #define MSR_EFER_LMA (1 << 10)
376 #define MSR_EFER_NXE (1 << 11)
377 #define MSR_EFER_SVME (1 << 12)
378 #define MSR_EFER_FFXSR (1 << 14)
379
380 #define MSR_STAR 0xc0000081
381 #define MSR_LSTAR 0xc0000082
382 #define MSR_CSTAR 0xc0000083
383 #define MSR_FMASK 0xc0000084
384 #define MSR_FSBASE 0xc0000100
385 #define MSR_GSBASE 0xc0000101
386 #define MSR_KERNELGSBASE 0xc0000102
387 #define MSR_TSC_AUX 0xc0000103
388
389 #define MSR_VM_HSAVE_PA 0xc0010117
390
391 #define MSR_IA32_BNDCFGS 0x00000d90
392
393 #define XSTATE_FP (1ULL << 0)
394 #define XSTATE_SSE (1ULL << 1)
395 #define XSTATE_YMM (1ULL << 2)
396 #define XSTATE_BNDREGS (1ULL << 3)
397 #define XSTATE_BNDCSR (1ULL << 4)
398 #define XSTATE_OPMASK (1ULL << 5)
399 #define XSTATE_ZMM_Hi256 (1ULL << 6)
400 #define XSTATE_Hi16_ZMM (1ULL << 7)
401
402
403 /* CPUID feature words */
404 typedef enum FeatureWord {
405 FEAT_1_EDX, /* CPUID[1].EDX */
406 FEAT_1_ECX, /* CPUID[1].ECX */
407 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
408 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
409 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
410 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
411 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
412 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
413 FEAT_SVM, /* CPUID[8000_000A].EDX */
414 FEATURE_WORDS,
415 } FeatureWord;
416
417 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
418
419 /* cpuid_features bits */
420 #define CPUID_FP87 (1U << 0)
421 #define CPUID_VME (1U << 1)
422 #define CPUID_DE (1U << 2)
423 #define CPUID_PSE (1U << 3)
424 #define CPUID_TSC (1U << 4)
425 #define CPUID_MSR (1U << 5)
426 #define CPUID_PAE (1U << 6)
427 #define CPUID_MCE (1U << 7)
428 #define CPUID_CX8 (1U << 8)
429 #define CPUID_APIC (1U << 9)
430 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
431 #define CPUID_MTRR (1U << 12)
432 #define CPUID_PGE (1U << 13)
433 #define CPUID_MCA (1U << 14)
434 #define CPUID_CMOV (1U << 15)
435 #define CPUID_PAT (1U << 16)
436 #define CPUID_PSE36 (1U << 17)
437 #define CPUID_PN (1U << 18)
438 #define CPUID_CLFLUSH (1U << 19)
439 #define CPUID_DTS (1U << 21)
440 #define CPUID_ACPI (1U << 22)
441 #define CPUID_MMX (1U << 23)
442 #define CPUID_FXSR (1U << 24)
443 #define CPUID_SSE (1U << 25)
444 #define CPUID_SSE2 (1U << 26)
445 #define CPUID_SS (1U << 27)
446 #define CPUID_HT (1U << 28)
447 #define CPUID_TM (1U << 29)
448 #define CPUID_IA64 (1U << 30)
449 #define CPUID_PBE (1U << 31)
450
451 #define CPUID_EXT_SSE3 (1U << 0)
452 #define CPUID_EXT_PCLMULQDQ (1U << 1)
453 #define CPUID_EXT_DTES64 (1U << 2)
454 #define CPUID_EXT_MONITOR (1U << 3)
455 #define CPUID_EXT_DSCPL (1U << 4)
456 #define CPUID_EXT_VMX (1U << 5)
457 #define CPUID_EXT_SMX (1U << 6)
458 #define CPUID_EXT_EST (1U << 7)
459 #define CPUID_EXT_TM2 (1U << 8)
460 #define CPUID_EXT_SSSE3 (1U << 9)
461 #define CPUID_EXT_CID (1U << 10)
462 #define CPUID_EXT_FMA (1U << 12)
463 #define CPUID_EXT_CX16 (1U << 13)
464 #define CPUID_EXT_XTPR (1U << 14)
465 #define CPUID_EXT_PDCM (1U << 15)
466 #define CPUID_EXT_PCID (1U << 17)
467 #define CPUID_EXT_DCA (1U << 18)
468 #define CPUID_EXT_SSE41 (1U << 19)
469 #define CPUID_EXT_SSE42 (1U << 20)
470 #define CPUID_EXT_X2APIC (1U << 21)
471 #define CPUID_EXT_MOVBE (1U << 22)
472 #define CPUID_EXT_POPCNT (1U << 23)
473 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
474 #define CPUID_EXT_AES (1U << 25)
475 #define CPUID_EXT_XSAVE (1U << 26)
476 #define CPUID_EXT_OSXSAVE (1U << 27)
477 #define CPUID_EXT_AVX (1U << 28)
478 #define CPUID_EXT_F16C (1U << 29)
479 #define CPUID_EXT_RDRAND (1U << 30)
480 #define CPUID_EXT_HYPERVISOR (1U << 31)
481
482 #define CPUID_EXT2_FPU (1U << 0)
483 #define CPUID_EXT2_VME (1U << 1)
484 #define CPUID_EXT2_DE (1U << 2)
485 #define CPUID_EXT2_PSE (1U << 3)
486 #define CPUID_EXT2_TSC (1U << 4)
487 #define CPUID_EXT2_MSR (1U << 5)
488 #define CPUID_EXT2_PAE (1U << 6)
489 #define CPUID_EXT2_MCE (1U << 7)
490 #define CPUID_EXT2_CX8 (1U << 8)
491 #define CPUID_EXT2_APIC (1U << 9)
492 #define CPUID_EXT2_SYSCALL (1U << 11)
493 #define CPUID_EXT2_MTRR (1U << 12)
494 #define CPUID_EXT2_PGE (1U << 13)
495 #define CPUID_EXT2_MCA (1U << 14)
496 #define CPUID_EXT2_CMOV (1U << 15)
497 #define CPUID_EXT2_PAT (1U << 16)
498 #define CPUID_EXT2_PSE36 (1U << 17)
499 #define CPUID_EXT2_MP (1U << 19)
500 #define CPUID_EXT2_NX (1U << 20)
501 #define CPUID_EXT2_MMXEXT (1U << 22)
502 #define CPUID_EXT2_MMX (1U << 23)
503 #define CPUID_EXT2_FXSR (1U << 24)
504 #define CPUID_EXT2_FFXSR (1U << 25)
505 #define CPUID_EXT2_PDPE1GB (1U << 26)
506 #define CPUID_EXT2_RDTSCP (1U << 27)
507 #define CPUID_EXT2_LM (1U << 29)
508 #define CPUID_EXT2_3DNOWEXT (1U << 30)
509 #define CPUID_EXT2_3DNOW (1U << 31)
510
511 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
512 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
513 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
514 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
515 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
516 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
517 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
518 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
519 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
520 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
521
522 #define CPUID_EXT3_LAHF_LM (1U << 0)
523 #define CPUID_EXT3_CMP_LEG (1U << 1)
524 #define CPUID_EXT3_SVM (1U << 2)
525 #define CPUID_EXT3_EXTAPIC (1U << 3)
526 #define CPUID_EXT3_CR8LEG (1U << 4)
527 #define CPUID_EXT3_ABM (1U << 5)
528 #define CPUID_EXT3_SSE4A (1U << 6)
529 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
530 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
531 #define CPUID_EXT3_OSVW (1U << 9)
532 #define CPUID_EXT3_IBS (1U << 10)
533 #define CPUID_EXT3_XOP (1U << 11)
534 #define CPUID_EXT3_SKINIT (1U << 12)
535 #define CPUID_EXT3_WDT (1U << 13)
536 #define CPUID_EXT3_LWP (1U << 15)
537 #define CPUID_EXT3_FMA4 (1U << 16)
538 #define CPUID_EXT3_TCE (1U << 17)
539 #define CPUID_EXT3_NODEID (1U << 19)
540 #define CPUID_EXT3_TBM (1U << 21)
541 #define CPUID_EXT3_TOPOEXT (1U << 22)
542 #define CPUID_EXT3_PERFCORE (1U << 23)
543 #define CPUID_EXT3_PERFNB (1U << 24)
544
545 #define CPUID_SVM_NPT (1U << 0)
546 #define CPUID_SVM_LBRV (1U << 1)
547 #define CPUID_SVM_SVMLOCK (1U << 2)
548 #define CPUID_SVM_NRIPSAVE (1U << 3)
549 #define CPUID_SVM_TSCSCALE (1U << 4)
550 #define CPUID_SVM_VMCBCLEAN (1U << 5)
551 #define CPUID_SVM_FLUSHASID (1U << 6)
552 #define CPUID_SVM_DECODEASSIST (1U << 7)
553 #define CPUID_SVM_PAUSEFILTER (1U << 10)
554 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
555
556 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
557 #define CPUID_7_0_EBX_BMI1 (1U << 3)
558 #define CPUID_7_0_EBX_HLE (1U << 4)
559 #define CPUID_7_0_EBX_AVX2 (1U << 5)
560 #define CPUID_7_0_EBX_SMEP (1U << 7)
561 #define CPUID_7_0_EBX_BMI2 (1U << 8)
562 #define CPUID_7_0_EBX_ERMS (1U << 9)
563 #define CPUID_7_0_EBX_INVPCID (1U << 10)
564 #define CPUID_7_0_EBX_RTM (1U << 11)
565 #define CPUID_7_0_EBX_MPX (1U << 14)
566 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
567 #define CPUID_7_0_EBX_RDSEED (1U << 18)
568 #define CPUID_7_0_EBX_ADX (1U << 19)
569 #define CPUID_7_0_EBX_SMAP (1U << 20)
570 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
571 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
572 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
573
574 /* CPUID[0x80000007].EDX flags: */
575 #define CPUID_APM_INVTSC (1U << 8)
576
577 #define CPUID_VENDOR_SZ 12
578
579 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
580 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
581 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
582 #define CPUID_VENDOR_INTEL "GenuineIntel"
583
584 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
585 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
586 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
587 #define CPUID_VENDOR_AMD "AuthenticAMD"
588
589 #define CPUID_VENDOR_VIA "CentaurHauls"
590
591 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
592 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
593
594 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
595 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
596 #endif
597
598 #define EXCP00_DIVZ 0
599 #define EXCP01_DB 1
600 #define EXCP02_NMI 2
601 #define EXCP03_INT3 3
602 #define EXCP04_INTO 4
603 #define EXCP05_BOUND 5
604 #define EXCP06_ILLOP 6
605 #define EXCP07_PREX 7
606 #define EXCP08_DBLE 8
607 #define EXCP09_XERR 9
608 #define EXCP0A_TSS 10
609 #define EXCP0B_NOSEG 11
610 #define EXCP0C_STACK 12
611 #define EXCP0D_GPF 13
612 #define EXCP0E_PAGE 14
613 #define EXCP10_COPR 16
614 #define EXCP11_ALGN 17
615 #define EXCP12_MCHK 18
616
617 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
618 for syscall instruction */
619
620 /* i386-specific interrupt pending bits. */
621 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
622 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
623 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
624 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
625 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
626 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
627 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
628
629 /* Use a clearer name for this. */
630 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
631
632 typedef enum {
633 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
634 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
635
636 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
637 CC_OP_MULW,
638 CC_OP_MULL,
639 CC_OP_MULQ,
640
641 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
642 CC_OP_ADDW,
643 CC_OP_ADDL,
644 CC_OP_ADDQ,
645
646 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
647 CC_OP_ADCW,
648 CC_OP_ADCL,
649 CC_OP_ADCQ,
650
651 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
652 CC_OP_SUBW,
653 CC_OP_SUBL,
654 CC_OP_SUBQ,
655
656 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
657 CC_OP_SBBW,
658 CC_OP_SBBL,
659 CC_OP_SBBQ,
660
661 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
662 CC_OP_LOGICW,
663 CC_OP_LOGICL,
664 CC_OP_LOGICQ,
665
666 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
667 CC_OP_INCW,
668 CC_OP_INCL,
669 CC_OP_INCQ,
670
671 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
672 CC_OP_DECW,
673 CC_OP_DECL,
674 CC_OP_DECQ,
675
676 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
677 CC_OP_SHLW,
678 CC_OP_SHLL,
679 CC_OP_SHLQ,
680
681 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
682 CC_OP_SARW,
683 CC_OP_SARL,
684 CC_OP_SARQ,
685
686 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
687 CC_OP_BMILGW,
688 CC_OP_BMILGL,
689 CC_OP_BMILGQ,
690
691 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
692 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
693 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
694
695 CC_OP_CLR, /* Z set, all other flags clear. */
696
697 CC_OP_NB,
698 } CCOp;
699
700 typedef struct SegmentCache {
701 uint32_t selector;
702 target_ulong base;
703 uint32_t limit;
704 uint32_t flags;
705 } SegmentCache;
706
707 typedef union {
708 uint8_t _b[16];
709 uint16_t _w[8];
710 uint32_t _l[4];
711 uint64_t _q[2];
712 float32 _s[4];
713 float64 _d[2];
714 } XMMReg;
715
716 typedef union {
717 uint8_t _b[32];
718 uint16_t _w[16];
719 uint32_t _l[8];
720 uint64_t _q[4];
721 float32 _s[8];
722 float64 _d[4];
723 } YMMReg;
724
725 typedef union {
726 uint8_t _b[64];
727 uint16_t _w[32];
728 uint32_t _l[16];
729 uint64_t _q[8];
730 float32 _s[16];
731 float64 _d[8];
732 } ZMMReg;
733
734 typedef union {
735 uint8_t _b[8];
736 uint16_t _w[4];
737 uint32_t _l[2];
738 float32 _s[2];
739 uint64_t q;
740 } MMXReg;
741
742 typedef struct BNDReg {
743 uint64_t lb;
744 uint64_t ub;
745 } BNDReg;
746
747 typedef struct BNDCSReg {
748 uint64_t cfgu;
749 uint64_t sts;
750 } BNDCSReg;
751
752 #ifdef HOST_WORDS_BIGENDIAN
753 #define ZMM_B(n) _b[63 - (n)]
754 #define ZMM_W(n) _w[31 - (n)]
755 #define ZMM_L(n) _l[15 - (n)]
756 #define ZMM_S(n) _s[15 - (n)]
757 #define ZMM_Q(n) _q[7 - (n)]
758 #define ZMM_D(n) _d[7 - (n)]
759
760 #define YMM_B(n) _b[31 - (n)]
761 #define YMM_W(n) _w[15 - (n)]
762 #define YMM_L(n) _l[7 - (n)]
763 #define YMM_S(n) _s[7 - (n)]
764 #define YMM_Q(n) _q[3 - (n)]
765 #define YMM_D(n) _d[3 - (n)]
766
767 #define XMM_B(n) _b[15 - (n)]
768 #define XMM_W(n) _w[7 - (n)]
769 #define XMM_L(n) _l[3 - (n)]
770 #define XMM_S(n) _s[3 - (n)]
771 #define XMM_Q(n) _q[1 - (n)]
772 #define XMM_D(n) _d[1 - (n)]
773
774 #define MMX_B(n) _b[7 - (n)]
775 #define MMX_W(n) _w[3 - (n)]
776 #define MMX_L(n) _l[1 - (n)]
777 #define MMX_S(n) _s[1 - (n)]
778 #else
779 #define ZMM_B(n) _b[n]
780 #define ZMM_W(n) _w[n]
781 #define ZMM_L(n) _l[n]
782 #define ZMM_S(n) _s[n]
783 #define ZMM_Q(n) _q[n]
784 #define ZMM_D(n) _d[n]
785
786 #define YMM_B(n) _b[n]
787 #define YMM_W(n) _w[n]
788 #define YMM_L(n) _l[n]
789 #define YMM_S(n) _s[n]
790 #define YMM_Q(n) _q[n]
791 #define YMM_D(n) _d[n]
792
793 #define XMM_B(n) _b[n]
794 #define XMM_W(n) _w[n]
795 #define XMM_L(n) _l[n]
796 #define XMM_S(n) _s[n]
797 #define XMM_Q(n) _q[n]
798 #define XMM_D(n) _d[n]
799
800 #define MMX_B(n) _b[n]
801 #define MMX_W(n) _w[n]
802 #define MMX_L(n) _l[n]
803 #define MMX_S(n) _s[n]
804 #endif
805 #define MMX_Q(n) q
806
807 typedef union {
808 floatx80 QEMU_ALIGN(16, d);
809 MMXReg mmx;
810 } FPReg;
811
812 typedef struct {
813 uint64_t base;
814 uint64_t mask;
815 } MTRRVar;
816
817 #define CPU_NB_REGS64 16
818 #define CPU_NB_REGS32 8
819
820 #ifdef TARGET_X86_64
821 #define CPU_NB_REGS CPU_NB_REGS64
822 #else
823 #define CPU_NB_REGS CPU_NB_REGS32
824 #endif
825
826 #define MAX_FIXED_COUNTERS 3
827 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
828
829 #define NB_MMU_MODES 3
830
831 #define NB_OPMASK_REGS 8
832
833 typedef enum TPRAccess {
834 TPR_ACCESS_READ,
835 TPR_ACCESS_WRITE,
836 } TPRAccess;
837
838 typedef struct CPUX86State {
839 /* standard registers */
840 target_ulong regs[CPU_NB_REGS];
841 target_ulong eip;
842 target_ulong eflags0; // copy of eflags that does not change thru the BB
843 target_ulong eflags; /* eflags register. During CPU emulation, CC
844 flags and DF are set to zero because they are
845 stored elsewhere */
846
847 /* emulator internal eflags handling */
848 target_ulong cc_dst;
849 target_ulong cc_src;
850 target_ulong cc_src2;
851 uint32_t cc_op;
852 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
853 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
854 are known at translation time. */
855 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
856
857 /* segments */
858 SegmentCache segs[6]; /* selector values */
859 SegmentCache ldt;
860 SegmentCache tr;
861 SegmentCache gdt; /* only base and limit are used */
862 SegmentCache idt; /* only base and limit are used */
863
864 target_ulong cr[5]; /* NOTE: cr1 is unused */
865 int32_t a20_mask;
866
867 BNDReg bnd_regs[4];
868 BNDCSReg bndcs_regs;
869 uint64_t msr_bndcfgs;
870
871 /* Beginning of state preserved by INIT (dummy marker). */
872 //struct {} start_init_save;
873 int start_init_save;
874
875 /* FPU state */
876 unsigned int fpstt; /* top of stack index */
877 uint16_t fpus;
878 uint16_t fpuc;
879 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
880 FPReg fpregs[8];
881 /* KVM-only so far */
882 uint16_t fpop;
883 uint64_t fpip;
884 uint64_t fpdp;
885
886 /* emulator internal variables */
887 float_status fp_status;
888 floatx80 ft0;
889
890 float_status mmx_status; /* for 3DNow! float ops */
891 float_status sse_status;
892 uint32_t mxcsr;
893 XMMReg xmm_regs[CPU_NB_REGS];
894 XMMReg xmm_t0;
895 MMXReg mmx_t0;
896
897 XMMReg ymmh_regs[CPU_NB_REGS];
898
899 uint64_t opmask_regs[NB_OPMASK_REGS];
900 YMMReg zmmh_regs[CPU_NB_REGS];
901 #ifdef TARGET_X86_64
902 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
903 #endif
904
905 /* sysenter registers */
906 uint32_t sysenter_cs;
907 target_ulong sysenter_esp;
908 target_ulong sysenter_eip;
909 uint64_t efer;
910 uint64_t star;
911
912 uint64_t vm_hsave;
913
914 #ifdef TARGET_X86_64
915 target_ulong lstar;
916 target_ulong cstar;
917 target_ulong fmask;
918 target_ulong kernelgsbase;
919 #endif
920
921 uint64_t tsc;
922 uint64_t tsc_adjust;
923 uint64_t tsc_deadline;
924
925 uint64_t mcg_status;
926 uint64_t msr_ia32_misc_enable;
927 uint64_t msr_ia32_feature_control;
928
929 uint64_t msr_fixed_ctr_ctrl;
930 uint64_t msr_global_ctrl;
931 uint64_t msr_global_status;
932 uint64_t msr_global_ovf_ctrl;
933 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
934 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
935 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
936
937 uint64_t pat;
938 uint32_t smbase;
939
940 /* End of state preserved by INIT (dummy marker). */
941 //struct {} end_init_save;
942 int end_init_save;
943
944 uint64_t system_time_msr;
945 uint64_t wall_clock_msr;
946 uint64_t steal_time_msr;
947 uint64_t async_pf_en_msr;
948 uint64_t pv_eoi_en_msr;
949
950 uint64_t msr_hv_hypercall;
951 uint64_t msr_hv_guest_os_id;
952 uint64_t msr_hv_vapic;
953 uint64_t msr_hv_tsc;
954
955 /* exception/interrupt handling */
956 int error_code;
957 int exception_is_int;
958 target_ulong exception_next_eip;
959 target_ulong dr[8]; /* debug registers */
960 union {
961 struct CPUBreakpoint *cpu_breakpoint[4];
962 struct CPUWatchpoint *cpu_watchpoint[4];
963 }; /* break/watchpoints for dr[0..3] */
964 int old_exception; /* exception in flight */
965
966 uint64_t vm_vmcb;
967 uint64_t tsc_offset;
968 uint64_t intercept;
969 uint16_t intercept_cr_read;
970 uint16_t intercept_cr_write;
971 uint16_t intercept_dr_read;
972 uint16_t intercept_dr_write;
973 uint32_t intercept_exceptions;
974 uint8_t v_tpr;
975
976 /* KVM states, automatically cleared on reset */
977 uint8_t nmi_injected;
978 uint8_t nmi_pending;
979
980 CPU_COMMON
981
982 /* Fields from here on are preserved across CPU reset. */
983
984 /* processor features (e.g. for CPUID insn) */
985 uint32_t cpuid_level;
986 uint32_t cpuid_xlevel;
987 uint32_t cpuid_xlevel2;
988 uint32_t cpuid_vendor1;
989 uint32_t cpuid_vendor2;
990 uint32_t cpuid_vendor3;
991 uint32_t cpuid_version;
992 FeatureWordArray features;
993 uint32_t cpuid_model[12];
994 uint32_t cpuid_apic_id;
995
996 /* MTRRs */
997 uint64_t mtrr_fixed[11];
998 uint64_t mtrr_deftype;
999 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1000
1001 /* For KVM */
1002 uint32_t mp_state;
1003 int32_t exception_injected;
1004 int32_t interrupt_injected;
1005 uint8_t soft_interrupt;
1006 uint8_t has_error_code;
1007 uint32_t sipi_vector;
1008 bool tsc_valid;
1009 int tsc_khz;
1010 void *kvm_xsave_buf;
1011
1012 uint64_t mcg_cap;
1013 uint64_t mcg_ctl;
1014 uint64_t mce_banks[MCE_BANKS_DEF*4];
1015
1016 uint64_t tsc_aux;
1017
1018 /* vmstate */
1019 uint16_t fpus_vmstate;
1020 uint16_t fptag_vmstate;
1021 uint16_t fpregs_format_vmstate;
1022 uint64_t xstate_bv;
1023
1024 uint64_t xcr0;
1025
1026 TPRAccess tpr_access_type;
1027
1028 // Unicorn engine
1029 struct uc_struct *uc;
1030 } CPUX86State;
1031
1032 #include "cpu-qom.h"
1033
1034 X86CPU *cpu_x86_init(struct uc_struct *uc, const char *cpu_model);
1035 X86CPU *cpu_x86_create(struct uc_struct *uc, const char *cpu_model, Error **errp);
1036 int cpu_x86_exec(struct uc_struct *uc, CPUX86State *s);
1037 void x86_cpudef_setup(void);
1038 int cpu_x86_support_mca_broadcast(CPUX86State *env);
1039
1040 int cpu_get_pic_interrupt(CPUX86State *s);
1041 /* MSDOS compatibility mode FPU exception support */
1042 void cpu_set_ferr(CPUX86State *s);
1043
1044 /* this function must always be used to load data in the segment
1045 cache: it synchronizes the hflags with the segment cache values */
cpu_x86_load_seg_cache(CPUX86State * env,int seg_reg,unsigned int selector,target_ulong base,unsigned int limit,unsigned int flags)1046 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1047 int seg_reg, unsigned int selector,
1048 target_ulong base,
1049 unsigned int limit,
1050 unsigned int flags)
1051 {
1052 SegmentCache *sc;
1053 unsigned int new_hflags;
1054
1055 sc = &env->segs[seg_reg];
1056 sc->selector = selector;
1057 sc->base = base;
1058 sc->limit = limit;
1059 sc->flags = flags;
1060
1061 /* update the hidden flags */
1062 {
1063 if (seg_reg == R_CS) {
1064 #ifdef TARGET_X86_64
1065 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1066 /* long mode */
1067 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1068 env->hflags &= ~(HF_ADDSEG_MASK);
1069 } else
1070 #endif
1071 {
1072 /* legacy / compatibility case */
1073 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1074 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1075 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1076 new_hflags;
1077 }
1078 }
1079 if (seg_reg == R_SS) {
1080 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1081 #if HF_CPL_MASK != 3
1082 #error HF_CPL_MASK is hardcoded
1083 #endif
1084 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1085 }
1086 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1087 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1088 if (env->hflags & HF_CS64_MASK) {
1089 /* zero base assumed for DS, ES and SS in long mode */
1090 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1091 (env->eflags & VM_MASK) ||
1092 !(env->hflags & HF_CS32_MASK)) {
1093 /* XXX: try to avoid this test. The problem comes from the
1094 fact that is real mode or vm86 mode we only modify the
1095 'base' and 'selector' fields of the segment cache to go
1096 faster. A solution may be to force addseg to one in
1097 translate-i386.c. */
1098 new_hflags |= HF_ADDSEG_MASK;
1099 } else {
1100 new_hflags |= ((env->segs[R_DS].base |
1101 env->segs[R_ES].base |
1102 env->segs[R_SS].base) != 0) <<
1103 HF_ADDSEG_SHIFT;
1104 }
1105 env->hflags = (env->hflags &
1106 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1107 }
1108 }
1109
cpu_x86_load_seg_cache_sipi(X86CPU * cpu,uint8_t sipi_vector)1110 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1111 uint8_t sipi_vector)
1112 {
1113 CPUState *cs = CPU(cpu);
1114 CPUX86State *env = &cpu->env;
1115
1116 env->eip = 0;
1117 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1118 sipi_vector << 12,
1119 env->segs[R_CS].limit,
1120 env->segs[R_CS].flags);
1121 cs->halted = 0;
1122 }
1123
1124 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1125 target_ulong *base, unsigned int *limit,
1126 unsigned int *flags);
1127
1128 /* op_helper.c */
1129 /* used for debug or cpu save/restore */
1130 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
1131 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
1132
1133 /* cpu-exec.c */
1134 /* the following helpers are only usable in user mode simulation as
1135 they can trigger unexpected exceptions */
1136 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1137 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1138 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1139
1140 /* the binding language can not catch the exceptions.
1141 check the arguments, return error instead of raise exceptions. */
1142 int uc_check_cpu_x86_load_seg(CPUX86State *env, int seg_reg, int sel);
1143
1144 /* you can call this signal handler from your SIGBUS and SIGSEGV
1145 signal handlers to inform the virtual CPU of exceptions. non zero
1146 is returned if the signal was handled by the virtual CPU. */
1147 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1148 void *puc);
1149
1150 /* cpuid.c */
1151 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1152 uint32_t *eax, uint32_t *ebx,
1153 uint32_t *ecx, uint32_t *edx);
1154 void cpu_clear_apic_feature(CPUX86State *env);
1155 void host_cpuid(uint32_t function, uint32_t count,
1156 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1157
1158 /* helper.c */
1159 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
1160 int is_write, int mmu_idx);
1161 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1162
hw_local_breakpoint_enabled(unsigned long dr7,int index)1163 static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
1164 {
1165 return (dr7 >> (index * 2)) & 1;
1166 }
1167
hw_global_breakpoint_enabled(unsigned long dr7,int index)1168 static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
1169 {
1170 return (dr7 >> (index * 2)) & 2;
1171
1172 }
hw_breakpoint_enabled(unsigned long dr7,int index)1173 static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
1174 {
1175 return hw_global_breakpoint_enabled(dr7, index) ||
1176 hw_local_breakpoint_enabled(dr7, index);
1177 }
1178
hw_breakpoint_type(unsigned long dr7,int index)1179 static inline int hw_breakpoint_type(unsigned long dr7, int index)
1180 {
1181 return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
1182 }
1183
hw_breakpoint_len(unsigned long dr7,int index)1184 static inline int hw_breakpoint_len(unsigned long dr7, int index)
1185 {
1186 int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
1187 return (len == 2) ? 8 : len + 1;
1188 }
1189
1190 void hw_breakpoint_insert(CPUX86State *env, int index);
1191 void hw_breakpoint_remove(CPUX86State *env, int index);
1192 bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
1193 void breakpoint_handler(CPUState *cs);
1194
1195 /* will be suppressed */
1196 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1197 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1198 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1199
1200 /* hw/pc.c */
1201 void cpu_smm_update(CPUX86State *env);
1202 uint64_t cpu_get_tsc(CPUX86State *env);
1203
1204 #define TARGET_PAGE_BITS 12
1205
1206 #ifdef TARGET_X86_64
1207 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1208 /* ??? This is really 48 bits, sign-extended, but the only thing
1209 accessible to userland with bit 48 set is the VSYSCALL, and that
1210 is handled via other mechanisms. */
1211 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1212 #else
1213 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1214 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1215 #endif
1216
1217 /* XXX: This value should match the one returned by CPUID
1218 * and in exec.c */
1219 # if defined(TARGET_X86_64)
1220 # define PHYS_ADDR_MASK 0xffffffffffLL
1221 # else
1222 # define PHYS_ADDR_MASK 0xfffffffffLL
1223 # endif
1224
cpu_init(struct uc_struct * uc,const char * cpu_model)1225 static inline CPUX86State *cpu_init(struct uc_struct *uc, const char *cpu_model)
1226 {
1227 X86CPU *cpu = cpu_x86_init(uc, cpu_model);
1228 if (cpu == NULL) {
1229 return NULL;
1230 }
1231 return &cpu->env;
1232 }
1233
1234 #ifdef TARGET_I386
1235 #define cpu_exec cpu_x86_exec
1236 #define cpu_gen_code cpu_x86_gen_code
1237 #define cpu_signal_handler cpu_x86_signal_handler
1238 #define cpudef_setup x86_cpudef_setup
1239 #endif
1240
1241 /* MMU modes definitions */
1242 #define MMU_MODE0_SUFFIX _ksmap
1243 #define MMU_MODE1_SUFFIX _user
1244 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
1245 #define MMU_KSMAP_IDX 0
1246 #define MMU_USER_IDX 1
1247 #define MMU_KNOSMAP_IDX 2
cpu_mmu_index(CPUX86State * env)1248 static inline int cpu_mmu_index(CPUX86State *env)
1249 {
1250 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1251 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1252 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1253 }
1254
cpu_mmu_index_kernel(CPUX86State * env)1255 static inline int cpu_mmu_index_kernel(CPUX86State *env)
1256 {
1257 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1258 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1259 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1260 }
1261
1262 #define CC_DST (env->cc_dst)
1263 #define CC_SRC (env->cc_src)
1264 #define CC_SRC2 (env->cc_src2)
1265 #define CC_OP (env->cc_op)
1266
1267 /* n must be a constant to be efficient */
lshift(target_long x,int n)1268 static inline target_long lshift(target_long x, int n)
1269 {
1270 if (n >= 0) {
1271 return x << n;
1272 } else {
1273 return x >> (-n);
1274 }
1275 }
1276
1277 /* float macros */
1278 #define FT0 (env->ft0)
1279 #define ST0 (env->fpregs[env->fpstt].d)
1280 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1281 #define ST1 ST(1)
1282
1283 /* translate.c */
1284 void optimize_flags_init(struct uc_struct *);
1285
1286 #include "exec/cpu-all.h"
1287 #include "svm.h"
1288
1289 #if !defined(CONFIG_USER_ONLY)
1290 #include "hw/i386/apic.h"
1291 #endif
1292
1293 #include "exec/exec-all.h"
1294
cpu_get_tb_cpu_state(CPUX86State * env,target_ulong * pc,target_ulong * cs_base,int * flags)1295 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1296 target_ulong *cs_base, int *flags)
1297 {
1298 *cs_base = env->segs[R_CS].base;
1299 *pc = *cs_base + env->eip;
1300 *flags = env->hflags |
1301 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1302 }
1303
1304 void do_cpu_init(X86CPU *cpu);
1305 void do_cpu_sipi(X86CPU *cpu);
1306
1307 #define MCE_INJECT_BROADCAST 1
1308 #define MCE_INJECT_UNCOND_AO 2
1309
1310 /* excp_helper.c */
1311 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1312 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1313 int error_code);
1314 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1315 int error_code, int next_eip_addend);
1316
1317 /* cc_helper.c */
1318 extern const uint8_t parity_table[256];
1319 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1320 void update_fp_status(CPUX86State *env);
1321
cpu_compute_eflags(CPUX86State * env)1322 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1323 {
1324 return (env->eflags & ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)) | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1325 }
1326
1327 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
1328 * after generating a call to a helper that uses this.
1329 */
cpu_load_eflags(CPUX86State * env,int eflags,int update_mask)1330 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1331 int update_mask)
1332 {
1333 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1334 CC_OP = CC_OP_EFLAGS;
1335 env->df = 1 - (2 * ((eflags >> 10) & 1));
1336 env->eflags = (env->eflags & ~update_mask) |
1337 (eflags & update_mask) | 0x2;
1338 }
1339
1340 /* load efer and update the corresponding hflags. XXX: do consistency
1341 checks with cpuid bits? */
cpu_load_efer(CPUX86State * env,uint64_t val)1342 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1343 {
1344 env->efer = val;
1345 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1346 if (env->efer & MSR_EFER_LMA) {
1347 env->hflags |= HF_LMA_MASK;
1348 }
1349 if (env->efer & MSR_EFER_SVME) {
1350 env->hflags |= HF_SVME_MASK;
1351 }
1352 }
1353
1354 /* fpu_helper.c */
1355 void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
1356 void cpu_set_fpuc(CPUX86State *env, uint16_t val);
1357
1358 /* svm_helper.c */
1359 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1360 uint64_t param);
1361 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1362
1363 /* seg_helper.c */
1364 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1365
1366 void do_smm_enter(X86CPU *cpu);
1367
1368 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1369
1370 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1371 uint32_t feat_add, uint32_t feat_remove);
1372
1373 void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features);
1374 void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features);
1375
1376
1377 /* Return name of 32-bit register, from a R_* constant */
1378 const char *get_register_name_32(unsigned int reg);
1379
1380 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index);
1381 void enable_compat_apic_id_mode(void);
1382
1383 #define APIC_DEFAULT_ADDRESS 0xfee00000
1384 #define APIC_SPACE_SIZE 0x100000
1385
1386 #endif /* CPU_I386_H */
1387