1 /*
2 ===========================================================================
3 Copyright (C) 2008 Przemyslaw Iskra <sparky@pld-linux.org>
4
5 This file is part of Quake III Arena source code.
6
7 Quake III Arena source code is free software; you can redistribute it
8 and/or modify it under the terms of the GNU General Public License as
9 published by the Free Software Foundation; either version 2 of the License,
10 or (at your option) any later version.
11
12 Quake III Arena source code is distributed in the hope that it will be
13 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with Quake III Arena source code; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 ===========================================================================
21
22 * File includes code from GNU binutils, exactly:
23 * - include/opcode/ppc.h - licensed under GPL v1 or later
24 * - opcodes/ppc-opc.c - licensed under GPL v2 or later
25 *
26 * ppc.h -- Header file for PowerPC opcode table
27 * Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
28 * 2007 Free Software Foundation, Inc.
29 * Written by Ian Lance Taylor, Cygnus Suppor
30 *
31 * This file is part of GDB, GAS, and the GNU binutils.
32 *
33 * ppc-opc.c -- PowerPC opcode list
34 * Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
35 * 2005, 2006, 2007 Free Software Foundation, Inc.
36 * Written by Ian Lance Taylor, Cygnus Support
37 *
38 * This file is part of GDB, GAS, and the GNU binutils.
39 *
40 */
41
42 #include "vm_powerpc_asm.h"
43
44 #include <string.h>
45 #include <stdio.h>
46 #include <inttypes.h>
47
48 /* return nop on error */
49 #define ASM_ERROR_OPC (0x60000000)
50
51 /*
52 * BEGIN OF ppc.h
53 */
54
55 #define ppc_cpu_t int
56
57 struct powerpc_opcode
58 {
59 const char *name;
60 unsigned long opcode;
61 unsigned long mask;
62 ppc_cpu_t flags;
63 unsigned char operands[8];
64 };
65
66 static const struct powerpc_opcode powerpc_opcodes[];
67 static const int powerpc_num_opcodes;
68
69 #define PPC_OPCODE_PPC 1
70 #define PPC_OPCODE_POWER 2
71 #define PPC_OPCODE_POWER2 4
72 #define PPC_OPCODE_32 8
73 #define PPC_OPCODE_64 0x10
74 #define PPC_OPCODE_601 0x20
75 #define PPC_OPCODE_COMMON 0x40
76 #define PPC_OPCODE_ANY 0x80
77 #define PPC_OPCODE_64_BRIDGE 0x100
78 #define PPC_OPCODE_ALTIVEC 0x200
79 #define PPC_OPCODE_403 0x400
80 #define PPC_OPCODE_BOOKE 0x800
81 #define PPC_OPCODE_BOOKE64 0x1000
82 #define PPC_OPCODE_440 0x2000
83 #define PPC_OPCODE_POWER4 0x4000
84 #define PPC_OPCODE_NOPOWER4 0x8000
85 #define PPC_OPCODE_CLASSIC 0x10000
86 #define PPC_OPCODE_SPE 0x20000
87 #define PPC_OPCODE_ISEL 0x40000
88 #define PPC_OPCODE_EFS 0x80000
89 #define PPC_OPCODE_BRLOCK 0x100000
90 #define PPC_OPCODE_PMR 0x200000
91 #define PPC_OPCODE_CACHELCK 0x400000
92 #define PPC_OPCODE_RFMCI 0x800000
93 #define PPC_OPCODE_POWER5 0x1000000
94 #define PPC_OPCODE_E300 0x2000000
95 #define PPC_OPCODE_POWER6 0x4000000
96 #define PPC_OPCODE_CELL 0x8000000
97 #define PPC_OPCODE_PPCPS 0x10000000
98 #define PPC_OPCODE_E500MC 0x20000000
99 #define PPC_OPCODE_405 0x40000000
100 #define PPC_OPCODE_VSX 0x80000000
101
102 #define PPC_OP(i) (((i) >> 26) & 0x3f)
103
104 struct powerpc_operand
105 {
106 unsigned int bitm;
107 int shift;
108 unsigned long (*insert)
109 (unsigned long, long, int, const char **);
110 unsigned long flags;
111 };
112
113 static const struct powerpc_operand powerpc_operands[];
114 static const unsigned int num_powerpc_operands;
115
116 #define PPC_OPERAND_SIGNED (0x1)
117 #define PPC_OPERAND_SIGNOPT (0x2)
118 #define PPC_OPERAND_FAKE (0x4)
119 #define PPC_OPERAND_PARENS (0x8)
120 #define PPC_OPERAND_CR (0x10)
121 #define PPC_OPERAND_GPR (0x20)
122 #define PPC_OPERAND_GPR_0 (0x40)
123 #define PPC_OPERAND_FPR (0x80)
124 #define PPC_OPERAND_RELATIVE (0x100)
125 #define PPC_OPERAND_ABSOLUTE (0x200)
126 #define PPC_OPERAND_OPTIONAL (0x400)
127 #define PPC_OPERAND_NEXT (0x800)
128 #define PPC_OPERAND_NEGATIVE (0x1000)
129 #define PPC_OPERAND_VR (0x2000)
130 #define PPC_OPERAND_DS (0x4000)
131 #define PPC_OPERAND_DQ (0x8000)
132 #define PPC_OPERAND_PLUS1 (0x10000)
133 #define PPC_OPERAND_FSL (0x20000)
134 #define PPC_OPERAND_FCR (0x40000)
135 #define PPC_OPERAND_UDI (0x80000)
136 #define PPC_OPERAND_VSR (0x100000)
137
138 /*
139 * END OF ppc.h
140 */
141
142 #define PPC_DEST_ARCH PPC_OPCODE_PPC
143
144 ppc_instruction_t
asm_instruction(powerpc_iname_t sname,const int argc,const long int * argv)145 asm_instruction( powerpc_iname_t sname, const int argc, const long int *argv )
146 {
147 const char *errmsg = NULL;
148 const char *name;
149 unsigned long int ret;
150 const struct powerpc_opcode *opcode = NULL;
151 int argi, argj;
152
153 opcode = &powerpc_opcodes[ sname ];
154 name = opcode->name;
155
156 if ( ! opcode ) {
157 printf( "Can't find opcode %d\n", sname );
158 return ASM_ERROR_OPC;
159 }
160 if ( ( opcode->flags & PPC_DEST_ARCH ) != PPC_DEST_ARCH ) {
161 printf( "opcode %s not defined for this arch\n", name );
162 return ASM_ERROR_OPC;
163 }
164
165 ret = opcode->opcode;
166
167 argi = argj = 0;
168 while ( opcode->operands[ argi ] != 0 ) {
169 long int op = 0;
170 const struct powerpc_operand *operand = &powerpc_operands[ opcode->operands[ argi ] ];
171
172 if ( ! (operand->flags & PPC_OPERAND_FAKE) ) {
173 if ( argj >= argc ) {
174 printf( "Not enough arguments for %s, got %d\n", name, argc );
175 return ASM_ERROR_OPC;
176 }
177
178 op = argv[ argj++ ];
179 }
180
181 if ( operand->insert ) {
182 errmsg = NULL;
183 ret = operand->insert( ret, op, PPC_DEST_ARCH, &errmsg );
184 if ( errmsg ) {
185 printf( "%s: error while inserting operand %d (0x%.2lx): %s\n",
186 name, argi, op, errmsg );
187 }
188 } else {
189 unsigned long int opu = *(unsigned long int *)&op;
190 unsigned long int bitm = operand->bitm;
191 unsigned long int bitm_full = bitm | ( bitm & 1 ? 0 : 0xf );
192
193 if ( operand->flags & PPC_OPERAND_SIGNED ) {
194 bitm_full >>= 1;
195
196 if ( ( opu & ~bitm_full ) != 0 && ( opu | bitm_full ) != -1 )
197 printf( "%s: signed operand nr.%d to wide. op: %.8lx, mask: %.8lx\n",
198 name, argi, opu, bitm );
199 } else {
200 if ( ( opu & ~bitm_full ) != 0 )
201 printf( "%s: unsigned operand nr.%d to wide. op: %.8lx, mask: %.8lx\n",
202 name, argi, opu, bitm );
203 }
204 if ( (bitm & 1) == 0 ) {
205 if ( opu & 0xf & ~bitm )
206 printf( "%s: operand nr.%d not aligned correctly. op: %.8lx, mask: %.8lx\n",
207 name, argi, opu, bitm );
208 }
209
210 ret |= ( op & operand->bitm ) << operand->shift;
211 }
212 argi++;
213 }
214 if ( argc > argj ) {
215 printf( "Too many arguments for %s, got %d\n", name, argc );
216 return ASM_ERROR_OPC;
217 }
218
219 return ret;
220 }
221
222
223 /*
224 * BEGIN OF ppc-opc.c
225 */
226
227 #define ATTRIBUTE_UNUSED
228 #define _(x) (x)
229
230 /* Local insertion and extraction functions. */
231
232 static unsigned long insert_bdm (unsigned long, long, int, const char **);
233 static unsigned long insert_bo (unsigned long, long, int, const char **);
234 static unsigned long insert_ras (unsigned long, long, int, const char **);
235 static unsigned long insert_rbs (unsigned long, long, int, const char **);
236
237 /* The operands table.
238
239 The fields are bitm, shift, insert, extract, flags.
240 */
241
242 static const struct powerpc_operand powerpc_operands[] =
243 {
244 /* The zero index is used to indicate the end of the list of
245 operands. */
246 #define UNUSED 0
247 { 0, 0, NULL, 0 },
248
249 /* The BA field in an XL form instruction. */
250 #define BA UNUSED + 1
251 /* The BI field in a B form or XL form instruction. */
252 #define BI BA
253 #define BI_MASK (0x1f << 16)
254 { 0x1f, 16, NULL, PPC_OPERAND_CR },
255
256 /* The BD field in a B form instruction. The lower two bits are
257 forced to zero. */
258 #define BD BA + 1
259 { 0xfffc, 0, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
260
261 /* The BD field in a B form instruction when the - modifier is used.
262 This sets the y bit of the BO field appropriately. */
263 #define BDM BD + 1
264 { 0xfffc, 0, insert_bdm,
265 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
266
267 /* The BF field in an X or XL form instruction. */
268 #define BF BDM + 1
269 /* The CRFD field in an X form instruction. */
270 #define CRFD BF
271 { 0x7, 23, NULL, PPC_OPERAND_CR },
272
273 /* An optional BF field. This is used for comparison instructions,
274 in which an omitted BF field is taken as zero. */
275 #define OBF BF + 1
276 { 0x7, 23, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
277
278 /* The BO field in a B form instruction. Certain values are
279 illegal. */
280 #define BO OBF + 1
281 #define BO_MASK (0x1f << 21)
282 { 0x1f, 21, insert_bo, 0 },
283
284 /* The condition register number portion of the BI field in a B form
285 or XL form instruction. This is used for the extended
286 conditional branch mnemonics, which set the lower two bits of the
287 BI field. This field is optional. */
288 #define CR BO + 1
289 { 0x7, 18, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
290
291 /* The D field in a D form instruction. This is a displacement off
292 a register, and implies that the next operand is a register in
293 parentheses. */
294 #define D CR + 1
295 { 0xffff, 0, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
296
297 /* The DS field in a DS form instruction. This is like D, but the
298 lower two bits are forced to zero. */
299 #define DS D + 1
300 { 0xfffc, 0, NULL,
301 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
302
303 /* The FRA field in an X or A form instruction. */
304 #define FRA DS + 1
305 #define FRA_MASK (0x1f << 16)
306 { 0x1f, 16, NULL, PPC_OPERAND_FPR },
307
308 /* The FRB field in an X or A form instruction. */
309 #define FRB FRA + 1
310 #define FRB_MASK (0x1f << 11)
311 { 0x1f, 11, NULL, PPC_OPERAND_FPR },
312
313 /* The FRC field in an A form instruction. */
314 #define FRC FRB + 1
315 #define FRC_MASK (0x1f << 6)
316 { 0x1f, 6, NULL, PPC_OPERAND_FPR },
317
318 /* The FRS field in an X form instruction or the FRT field in a D, X
319 or A form instruction. */
320 #define FRS FRC + 1
321 #define FRT FRS
322 { 0x1f, 21, NULL, PPC_OPERAND_FPR },
323
324 /* The LI field in an I form instruction. The lower two bits are
325 forced to zero. */
326 #define LI FRS + 1
327 { 0x3fffffc, 0, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
328
329 /* The ME field in an M form instruction. */
330 #define ME LI + 1
331 #define ME_MASK (0x1f << 1)
332 { 0x1f, 1, NULL, 0 },
333
334 /* The MB and ME fields in an M form instruction expressed a single
335 operand which is a bitmask indicating which bits to select. This
336 is a two operand form using PPC_OPERAND_NEXT. See the
337 description in opcode/ppc.h for what this means. */
338 #define MBE ME + 1
339 { 0x1f, 6, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
340
341 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
342 #define RA MBE + 1
343 #define RA_MASK (0x1f << 16)
344 { 0x1f, 16, NULL, PPC_OPERAND_GPR },
345
346 /* As above, but 0 in the RA field means zero, not r0. */
347 #define RA0 RA + 1
348 { 0x1f, 16, NULL, PPC_OPERAND_GPR_0 },
349
350 /* The RA field in a D or X form instruction which is an updating
351 store or an updating floating point load, which means that the RA
352 field may not be zero. */
353 #define RAS RA0 + 1
354 { 0x1f, 16, insert_ras, PPC_OPERAND_GPR_0 },
355
356 /* The RB field in an X, XO, M, or MDS form instruction. */
357 #define RB RAS + 1
358 #define RB_MASK (0x1f << 11)
359 { 0x1f, 11, NULL, PPC_OPERAND_GPR },
360
361 /* The RB field in an X form instruction when it must be the same as
362 the RS field in the instruction. This is used for extended
363 mnemonics like mr. */
364 #define RBS RB + 1
365 { 0x1f, 11, insert_rbs, PPC_OPERAND_FAKE },
366
367 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
368 instruction or the RT field in a D, DS, X, XFX or XO form
369 instruction. */
370 #define RS RBS + 1
371 #define RT RS
372 #define RT_MASK (0x1f << 21)
373 { 0x1f, 21, NULL, PPC_OPERAND_GPR },
374
375 /* The SH field in an X or M form instruction. */
376 #define SH RS + 1
377 #define SH_MASK (0x1f << 11)
378 /* The other UIMM field in a EVX form instruction. */
379 #define EVUIMM SH
380 { 0x1f, 11, NULL, 0 },
381
382 /* The SI field in a D form instruction. */
383 #define SI SH + 1
384 { 0xffff, 0, NULL, PPC_OPERAND_SIGNED },
385
386 /* The UI field in a D form instruction. */
387 #define UI SI + 1
388 { 0xffff, 0, NULL, 0 },
389
390 };
391
392 static const unsigned int num_powerpc_operands =
393 (sizeof (powerpc_operands) / sizeof (powerpc_operands[0]));
394
395 /* The functions used to insert and extract complicated operands. */
396
397 /* The BD field in a B form instruction when the - modifier is used.
398 This modifier means that the branch is not expected to be taken.
399 For chips built to versions of the architecture prior to version 2
400 (ie. not Power4 compatible), we set the y bit of the BO field to 1
401 if the offset is negative. When extracting, we require that the y
402 bit be 1 and that the offset be positive, since if the y bit is 0
403 we just want to print the normal form of the instruction.
404 Power4 compatible targets use two bits, "a", and "t", instead of
405 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
406 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
407 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
408 for branch on CTR. We only handle the taken/not-taken hint here.
409 Note that we don't relax the conditions tested here when
410 disassembling with -Many because insns using extract_bdm and
411 extract_bdp always occur in pairs. One or the other will always
412 be valid. */
413
414 static unsigned long
insert_bdm(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)415 insert_bdm (unsigned long insn,
416 long value,
417 int dialect,
418 const char **errmsg ATTRIBUTE_UNUSED)
419 {
420 if ((dialect & PPC_OPCODE_POWER4) == 0)
421 {
422 if ((value & 0x8000) != 0)
423 insn |= 1 << 21;
424 }
425 else
426 {
427 if ((insn & (0x14 << 21)) == (0x04 << 21))
428 insn |= 0x02 << 21;
429 else if ((insn & (0x14 << 21)) == (0x10 << 21))
430 insn |= 0x08 << 21;
431 }
432 return insn | (value & 0xfffc);
433 }
434
435
436 /* Check for legal values of a BO field. */
437
438 static int
valid_bo(long value,int dialect,int extract)439 valid_bo (long value, int dialect, int extract)
440 {
441 if ((dialect & PPC_OPCODE_POWER4) == 0)
442 {
443 int valid;
444 /* Certain encodings have bits that are required to be zero.
445 These are (z must be zero, y may be anything):
446 001zy
447 011zy
448 1z00y
449 1z01y
450 1z1zz
451 */
452 switch (value & 0x14)
453 {
454 default:
455 case 0:
456 valid = 1;
457 break;
458 case 0x4:
459 valid = (value & 0x2) == 0;
460 break;
461 case 0x10:
462 valid = (value & 0x8) == 0;
463 break;
464 case 0x14:
465 valid = value == 0x14;
466 break;
467 }
468 /* When disassembling with -Many, accept power4 encodings too. */
469 if (valid
470 || (dialect & PPC_OPCODE_ANY) == 0
471 || !extract)
472 return valid;
473 }
474
475 /* Certain encodings have bits that are required to be zero.
476 These are (z must be zero, a & t may be anything):
477 0000z
478 0001z
479 0100z
480 0101z
481 001at
482 011at
483 1a00t
484 1a01t
485 1z1zz
486 */
487 if ((value & 0x14) == 0)
488 return (value & 0x1) == 0;
489 else if ((value & 0x14) == 0x14)
490 return value == 0x14;
491 else
492 return 1;
493 }
494
495 /* The BO field in a B form instruction. Warn about attempts to set
496 the field to an illegal value. */
497
498 static unsigned long
insert_bo(unsigned long insn,long value,int dialect,const char ** errmsg)499 insert_bo (unsigned long insn,
500 long value,
501 int dialect,
502 const char **errmsg)
503 {
504 if (!valid_bo (value, dialect, 0))
505 *errmsg = _("invalid conditional option");
506 return insn | ((value & 0x1f) << 21);
507 }
508
509 /* The RA field in a D or X form instruction which is an updating
510 store or an updating floating point load, which means that the RA
511 field may not be zero. */
512
513 static unsigned long
insert_ras(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)514 insert_ras (unsigned long insn,
515 long value,
516 int dialect ATTRIBUTE_UNUSED,
517 const char **errmsg)
518 {
519 if (value == 0)
520 *errmsg = _("invalid register operand when updating");
521 return insn | ((value & 0x1f) << 16);
522 }
523
524 /* The RB field in an X form instruction when it must be the same as
525 the RS field in the instruction. This is used for extended
526 mnemonics like mr. This operand is marked FAKE. The insertion
527 function just copies the BT field into the BA field, and the
528 extraction function just checks that the fields are the same. */
529
530 static unsigned long
insert_rbs(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)531 insert_rbs (unsigned long insn,
532 long value ATTRIBUTE_UNUSED,
533 int dialect ATTRIBUTE_UNUSED,
534 const char **errmsg ATTRIBUTE_UNUSED)
535 {
536 return insn | (((insn >> 21) & 0x1f) << 11);
537 }
538
539
540 /* Macros used to form opcodes. */
541
542 /* The main opcode. */
543 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
544 #define OP_MASK OP (0x3f)
545
546 /* The main opcode combined with a trap code in the TO field of a D
547 form instruction. Used for extended mnemonics for the trap
548 instructions. */
549 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
550 #define OPTO_MASK (OP_MASK | TO_MASK)
551
552 /* The main opcode combined with a comparison size bit in the L field
553 of a D form or X form instruction. Used for extended mnemonics for
554 the comparison instructions. */
555 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
556 #define OPL_MASK OPL (0x3f,1)
557
558 /* An A form instruction. */
559 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
560 #define A_MASK A (0x3f, 0x1f, 1)
561
562 /* An A_MASK with the FRB field fixed. */
563 #define AFRB_MASK (A_MASK | FRB_MASK)
564
565 /* An A_MASK with the FRC field fixed. */
566 #define AFRC_MASK (A_MASK | FRC_MASK)
567
568 /* An A_MASK with the FRA and FRC fields fixed. */
569 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
570
571 /* An AFRAFRC_MASK, but with L bit clear. */
572 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
573
574 /* A B form instruction. */
575 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
576 #define B_MASK B (0x3f, 1, 1)
577
578 /* A B form instruction setting the BO field. */
579 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
580 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
581
582 /* A BBO_MASK with the y bit of the BO field removed. This permits
583 matching a conditional branch regardless of the setting of the y
584 bit. Similarly for the 'at' bits used for power4 branch hints. */
585 #define Y_MASK (((unsigned long) 1) << 21)
586 #define AT1_MASK (((unsigned long) 3) << 21)
587 #define AT2_MASK (((unsigned long) 9) << 21)
588 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
589 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
590
591 /* A B form instruction setting the BO field and the condition bits of
592 the BI field. */
593 #define BBOCB(op, bo, cb, aa, lk) \
594 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
595 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
596
597 /* A BBOCB_MASK with the y bit of the BO field removed. */
598 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
599 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
600 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
601
602 /* A BBOYCB_MASK in which the BI field is fixed. */
603 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
604 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
605
606 /* An Context form instruction. */
607 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
608 #define CTX_MASK CTX(0x3f, 0x7)
609
610 /* An User Context form instruction. */
611 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
612 #define UCTX_MASK UCTX(0x3f, 0x1f)
613
614 /* The main opcode mask with the RA field clear. */
615 #define DRA_MASK (OP_MASK | RA_MASK)
616
617 /* A DS form instruction. */
618 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
619 #define DS_MASK DSO (0x3f, 3)
620
621 /* A DE form instruction. */
622 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
623 #define DE_MASK DEO (0x3e, 0xf)
624
625 /* An EVSEL form instruction. */
626 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
627 #define EVSEL_MASK EVSEL(0x3f, 0xff)
628
629 /* An M form instruction. */
630 #define M(op, rc) (OP (op) | ((rc) & 1))
631 #define M_MASK M (0x3f, 1)
632
633 /* An M form instruction with the ME field specified. */
634 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
635
636 /* An M_MASK with the MB and ME fields fixed. */
637 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
638
639 /* An M_MASK with the SH and ME fields fixed. */
640 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
641
642 /* An MD form instruction. */
643 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
644 #define MD_MASK MD (0x3f, 0x7, 1)
645
646 /* An MD_MASK with the MB field fixed. */
647 #define MDMB_MASK (MD_MASK | MB6_MASK)
648
649 /* An MD_MASK with the SH field fixed. */
650 #define MDSH_MASK (MD_MASK | SH6_MASK)
651
652 /* An MDS form instruction. */
653 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
654 #define MDS_MASK MDS (0x3f, 0xf, 1)
655
656 /* An MDS_MASK with the MB field fixed. */
657 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
658
659 /* An SC form instruction. */
660 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
661 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
662
663 /* An VX form instruction. */
664 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
665
666 /* The mask for an VX form instruction. */
667 #define VX_MASK VX(0x3f, 0x7ff)
668
669 /* An VA form instruction. */
670 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
671
672 /* The mask for an VA form instruction. */
673 #define VXA_MASK VXA(0x3f, 0x3f)
674
675 /* An VXR form instruction. */
676 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
677
678 /* The mask for a VXR form instruction. */
679 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
680
681 /* An X form instruction. */
682 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
683
684 /* A Z form instruction. */
685 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
686
687 /* An X form instruction with the RC bit specified. */
688 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
689
690 /* A Z form instruction with the RC bit specified. */
691 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
692
693 /* The mask for an X form instruction. */
694 #define X_MASK XRC (0x3f, 0x3ff, 1)
695
696 /* The mask for a Z form instruction. */
697 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
698 #define Z2_MASK ZRC (0x3f, 0xff, 1)
699
700 /* An X_MASK with the RA field fixed. */
701 #define XRA_MASK (X_MASK | RA_MASK)
702
703 /* An XRA_MASK with the W field clear. */
704 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
705
706 /* An X_MASK with the RB field fixed. */
707 #define XRB_MASK (X_MASK | RB_MASK)
708
709 /* An X_MASK with the RT field fixed. */
710 #define XRT_MASK (X_MASK | RT_MASK)
711
712 /* An XRT_MASK mask with the L bits clear. */
713 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
714
715 /* An X_MASK with the RA and RB fields fixed. */
716 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
717
718 /* An XRARB_MASK, but with the L bit clear. */
719 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
720
721 /* An X_MASK with the RT and RA fields fixed. */
722 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
723
724 /* An XRTRA_MASK, but with L bit clear. */
725 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
726
727 /* An X form instruction with the L bit specified. */
728 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
729
730 /* The mask for an X form comparison instruction. */
731 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
732
733 /* The mask for an X form comparison instruction with the L field
734 fixed. */
735 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
736
737 /* An X form trap instruction with the TO field specified. */
738 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
739 #define XTO_MASK (X_MASK | TO_MASK)
740
741 /* An X form tlb instruction with the SH field specified. */
742 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
743 #define XTLB_MASK (X_MASK | SH_MASK)
744
745 /* An X form sync instruction. */
746 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
747
748 /* An X form sync instruction with everything filled in except the LS field. */
749 #define XSYNC_MASK (0xff9fffff)
750
751 /* An X_MASK, but with the EH bit clear. */
752 #define XEH_MASK (X_MASK & ~((unsigned long )1))
753
754 /* An X form AltiVec dss instruction. */
755 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
756 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
757
758 /* An XFL form instruction. */
759 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
760 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
761
762 /* An X form isel instruction. */
763 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
764 #define XISEL_MASK XISEL(0x3f, 0x1f)
765
766 /* An XL form instruction with the LK field set to 0. */
767 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
768
769 /* An XL form instruction which uses the LK field. */
770 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
771
772 /* The mask for an XL form instruction. */
773 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
774
775 /* An XL form instruction which explicitly sets the BO field. */
776 #define XLO(op, bo, xop, lk) \
777 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
778 #define XLO_MASK (XL_MASK | BO_MASK)
779
780 /* An XL form instruction which explicitly sets the y bit of the BO
781 field. */
782 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
783 #define XLYLK_MASK (XL_MASK | Y_MASK)
784
785 /* An XL form instruction which sets the BO field and the condition
786 bits of the BI field. */
787 #define XLOCB(op, bo, cb, xop, lk) \
788 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
789 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
790
791 #define BB_MASK (0x1f << 11)
792 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
793 #define XLBB_MASK (XL_MASK | BB_MASK)
794 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
795 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
796
797 /* A mask for branch instructions using the BH field. */
798 #define XLBH_MASK (XL_MASK | (0x1c << 11))
799
800 /* An XL_MASK with the BO and BB fields fixed. */
801 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
802
803 /* An XL_MASK with the BO, BI and BB fields fixed. */
804 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
805
806 /* An XO form instruction. */
807 #define XO(op, xop, oe, rc) \
808 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
809 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
810
811 /* An XO_MASK with the RB field fixed. */
812 #define XORB_MASK (XO_MASK | RB_MASK)
813
814 /* An XS form instruction. */
815 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
816 #define XS_MASK XS (0x3f, 0x1ff, 1)
817
818 /* A mask for the FXM version of an XFX form instruction. */
819 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
820
821 /* An XFX form instruction with the FXM field filled in. */
822 #define XFXM(op, xop, fxm, p4) \
823 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
824 | ((unsigned long)(p4) << 20))
825
826 #define SPR_MASK (0x3ff << 11)
827 /* An XFX form instruction with the SPR field filled in. */
828 #define XSPR(op, xop, spr) \
829 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
830 #define XSPR_MASK (X_MASK | SPR_MASK)
831
832 /* An XFX form instruction with the SPR field filled in except for the
833 SPRBAT field. */
834 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
835
836 /* An XFX form instruction with the SPR field filled in except for the
837 SPRG field. */
838 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
839
840 /* An X form instruction with everything filled in except the E field. */
841 #define XE_MASK (0xffff7fff)
842
843 /* An X form user context instruction. */
844 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
845 #define XUC_MASK XUC(0x3f, 0x1f)
846
847 /* The BO encodings used in extended conditional branch mnemonics. */
848 #define BODNZF (0x0)
849 #define BODNZFP (0x1)
850 #define BODZF (0x2)
851 #define BODZFP (0x3)
852 #define BODNZT (0x8)
853 #define BODNZTP (0x9)
854 #define BODZT (0xa)
855 #define BODZTP (0xb)
856
857 #define BOF (0x4)
858 #define BOFP (0x5)
859 #define BOFM4 (0x6)
860 #define BOFP4 (0x7)
861 #define BOT (0xc)
862 #define BOTP (0xd)
863 #define BOTM4 (0xe)
864 #define BOTP4 (0xf)
865
866 #define BODNZ (0x10)
867 #define BODNZP (0x11)
868 #define BODZ (0x12)
869 #define BODZP (0x13)
870 #define BODNZM4 (0x18)
871 #define BODNZP4 (0x19)
872 #define BODZM4 (0x1a)
873 #define BODZP4 (0x1b)
874
875 #define BOU (0x14)
876
877 /* The BI condition bit encodings used in extended conditional branch
878 mnemonics. */
879 #define CBLT (0)
880 #define CBGT (1)
881 #define CBEQ (2)
882 #define CBSO (3)
883
884 /* The TO encodings used in extended trap mnemonics. */
885 #define TOLGT (0x1)
886 #define TOLLT (0x2)
887 #define TOEQ (0x4)
888 #define TOLGE (0x5)
889 #define TOLNL (0x5)
890 #define TOLLE (0x6)
891 #define TOLNG (0x6)
892 #define TOGT (0x8)
893 #define TOGE (0xc)
894 #define TONL (0xc)
895 #define TOLT (0x10)
896 #define TOLE (0x14)
897 #define TONG (0x14)
898 #define TONE (0x18)
899 #define TOU (0x1f)
900
901 /* Smaller names for the flags so each entry in the opcodes table will
902 fit on a single line. */
903 #undef PPC
904 #define PPC PPC_OPCODE_PPC
905 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
906 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
907 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
908 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
909
910 /* The opcode table.
911
912 The format of the opcode table is:
913
914 NAME OPCODE MASK FLAGS { OPERANDS }
915
916 NAME is the name of the instruction.
917 OPCODE is the instruction opcode.
918 MASK is the opcode mask; this is used to tell the disassembler
919 which bits in the actual opcode must match OPCODE.
920 FLAGS are flags indicated what processors support the instruction.
921 OPERANDS is the list of operands.
922
923 The disassembler reads the table in order and prints the first
924 instruction which matches, so this table is sorted to put more
925 specific instructions before more general instructions. It is also
926 sorted by major opcode. */
927
928 static const struct powerpc_opcode powerpc_opcodes[] = {
929
930 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
931 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
932 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
933 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
934 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
935
936 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
937 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SI } },
938
939 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
940 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SI } },
941 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
942 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
943 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
944 { "b", B(18,0,0), B_MASK, COM, { LI } },
945 { "bl", B(18,0,1), B_MASK, COM, { LI } },
946 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
947 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
948 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
949
950 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
951 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
952 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
953 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
954 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
955 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
956 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
957 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
958 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
959 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
960 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
961 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
962 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
963 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
964 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
965 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
966 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
967 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
968 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
969 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
970 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
971 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
972 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
973 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
974 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
975 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
976 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
977 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
978 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
979 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
980 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
981 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
982
983 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
984 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
985 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
986 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
987 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
988 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
989 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
990 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
991 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
992 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
993 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
994 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
995
996 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
997 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
998 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
999 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
1000 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
1001 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
1002 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
1003 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
1004 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
1005 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
1006 };
1007
1008 static const int powerpc_num_opcodes =
1009 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
1010