1 /*****************************************************************************
2 *
3 * Yamaha YM2151 driver (version 2.150 final beta)
4 *
5 ******************************************************************************/
6
7 #include <stdio.h>
8 #include <stdlib.h>
9 #include <string.h>
10 #include <math.h>
11
12 #include "MameYM2151.h"
13 #include "SaveState.h"
14
15
16 /* struct describing a single operator */
17 typedef struct
18 {
19 UInt32 phase; /* accumulated operator phase */
20 UInt32 freq; /* operator frequency count */
21 Int32 dt1; /* current DT1 (detune 1 phase inc/decrement) value */
22 UInt32 mul; /* frequency count multiply */
23 UInt32 dt1_i; /* DT1 index * 32 */
24 UInt32 dt2; /* current DT2 (detune 2) value */
25
26 Int32 mem_value; /* delayed sample (MEM) value */
27
28 /* channel specific data; note: each operator number 0 contains channel specific data */
29 UInt32 fb_shift; /* feedback shift value for operators 0 in each channel */
30 Int32 fb_out_curr; /* operator feedback value (used only by operators 0) */
31 Int32 fb_out_prev; /* previous feedback value (used only by operators 0) */
32 UInt32 kc; /* channel KC (copied to all operators) */
33 UInt32 kc_i; /* just for speedup */
34 UInt32 pms; /* channel PMS */
35 UInt32 ams; /* channel AMS */
36 /* end of channel specific data */
37
38 UInt32 AMmask; /* LFO Amplitude Modulation enable mask */
39 UInt32 state; /* Envelope state: 4-attack(AR) 3-decay(D1R) 2-sustain(D2R) 1-release(RR) 0-off */
40 UInt8 eg_sh_ar; /* (attack state) */
41 UInt8 eg_sel_ar; /* (attack state) */
42 UInt32 tl; /* Total attenuation Level */
43 Int32 volume; /* current envelope attenuation level */
44 UInt8 eg_sh_d1r; /* (decay state) */
45 UInt8 eg_sel_d1r; /* (decay state) */
46 UInt32 d1l; /* envelope switches to sustain state after reaching this level */
47 UInt8 eg_sh_d2r; /* (sustain state) */
48 UInt8 eg_sel_d2r; /* (sustain state) */
49 UInt8 eg_sh_rr; /* (release state) */
50 UInt8 eg_sel_rr; /* (release state) */
51
52 UInt32 key; /* 0=last key was KEY OFF, 1=last key was KEY ON */
53
54 UInt32 ks; /* key scale */
55 UInt32 ar; /* attack rate */
56 UInt32 d1r; /* decay rate */
57 UInt32 d2r; /* sustain rate */
58 UInt32 rr; /* release rate */
59
60 signed int *connect; /* operator output 'direction' */
61 signed int *mem_connect; /* where to put the delayed sample (MEM) */
62
63 UInt32 reserved0; /**/
64 UInt32 reserved1; /**/
65 } YM2151Operator;
66
67 struct MameYm2151
68 {
69 void* ref;
70
71 YM2151Operator oper[32]; /* the 32 operators */
72
73 UInt32 pan[16]; /* channels output masks (0xffffffff = enable) */
74
75 UInt32 eg_cnt; /* global envelope generator counter */
76 UInt32 eg_timer; /* global envelope generator counter works at frequency = chipclock/64/3 */
77 UInt32 eg_timer_add; /* step of eg_timer */
78 UInt32 eg_timer_overflow; /* envelope generator timer overlfows every 3 samples (on real chip) */
79
80 UInt32 lfo_phase; /* accumulated LFO phase (0 to 255) */
81 UInt32 lfo_timer; /* LFO timer */
82 UInt32 lfo_timer_add; /* step of lfo_timer */
83 UInt32 lfo_overflow; /* LFO generates new output when lfo_timer reaches this value */
84 UInt32 lfo_counter; /* LFO phase increment counter */
85 UInt32 lfo_counter_add; /* step of lfo_counter */
86 UInt8 lfo_wsel; /* LFO waveform (0-saw, 1-square, 2-triangle, 3-random noise) */
87 UInt8 amd; /* LFO Amplitude Modulation Depth */
88 Int8 pmd; /* LFO Phase Modulation Depth */
89 UInt32 lfa; /* LFO current AM output */
90 Int32 lfp; /* LFO current PM output */
91
92 UInt8 test; /* TEST register */
93 UInt8 ct; /* output control pins (bit1-CT2, bit0-CT1) */
94
95 UInt32 noise; /* noise enable/period register (bit 7 - noise enable, bits 4-0 - noise period */
96 UInt32 noise_rng; /* 17 bit noise shift register */
97 UInt32 noise_p; /* current noise 'phase'*/
98 UInt32 noise_f; /* current noise period */
99
100 UInt32 csm_req; /* CSM KEY ON / KEY OFF sequence request */
101
102 UInt32 irq_enable; /* IRQ enable for timer B (bit 3) and timer A (bit 2); bit 7 - CSM mode (keyon to all slots, everytime timer A overflows) */
103 UInt32 status; /* chip status (BUSY, IRQ Flags) */
104 UInt8 connect[8]; /* channels connections */
105
106 UInt16 timer_A_val;
107
108 /* Frequency-deltas to get the closest frequency possible.
109 * There are 11 octaves because of DT2 (max 950 cents over base frequency)
110 * and LFO phase modulation (max 800 cents below AND over base frequency)
111 * Summary: octave explanation
112 * 0 note code - LFO PM
113 * 1 note code
114 * 2 note code
115 * 3 note code
116 * 4 note code
117 * 5 note code
118 * 6 note code
119 * 7 note code
120 * 8 note code
121 * 9 note code + DT2 + LFO PM
122 * 10 note code + DT2 + LFO PM
123 */
124 UInt32 freq[11*768]; /* 11 octaves, 768 'cents' per octave */ // No Save
125
126 /* Frequency deltas for DT1. These deltas alter operator frequency
127 * after it has been taken from frequency-deltas table.
128 */
129 Int32 dt1_freq[8*32]; /* 8 DT1 levels, 32 KC values */ // No Save
130 UInt32 noise_tab[32]; /* 17bit Noise Generator periods */ // No Save
131
132 unsigned int clock; /* chip clock in Hz (passed from 2151intf.c) */
133 unsigned int sampfreq; /* sampling frequency in Hz (passed from 2151intf.c) */
134
135 signed int chanout[8];
136 signed int m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
137 signed int mem; /* one sample delay memory */
138 };
139
140 extern void ym2151TimerSet(void* ref, int timer, int count);
141 extern void ym2151TimerStart(void* ref, int timer, int start);
142 extern void ym2151ClearIrq(void* ref, int irq);
143 extern void ym2151SetIrq(void* ref, int irq);
144 extern void ym2151WritePortCallback(void* ref, UInt32 port, UInt8 value);
145
146 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
147 #define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
148 #define LFO_SH 10 /* 22.10 fixed point (LFO calculations) */
149 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
150
151 #define FREQ_MASK ((1<<FREQ_SH)-1)
152
153 #define ENV_BITS 10
154 #define ENV_LEN (1<<ENV_BITS)
155 #define ENV_STEP (128.0/ENV_LEN)
156
157 #define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
158 #define MIN_ATT_INDEX (0) /* 0 */
159
160 #define EG_ATT 4
161 #define EG_DEC 3
162 #define EG_SUS 2
163 #define EG_REL 1
164 #define EG_OFF 0
165
166 #define SIN_BITS 10
167 #define SIN_LEN (1<<SIN_BITS)
168 #define SIN_MASK (SIN_LEN-1)
169
170 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
171
172
173 #define FINAL_SH (0)
174 #define MAXOUT (+32767)
175 #define MINOUT (-32768)
176
177
178 /* TL_TAB_LEN is calculated as:
179 * 13 - sinus amplitude bits (Y axis)
180 * 2 - sinus sign bit (Y axis)
181 * TL_RES_LEN - sinus resolution (X axis)
182 */
183 #define TL_TAB_LEN (13*2*TL_RES_LEN)
184 static signed int tl_tab[TL_TAB_LEN];
185
186 #define ENV_QUIET (TL_TAB_LEN>>3)
187
188 /* sin waveform table in 'decibel' scale */
189 static unsigned int sin_tab[SIN_LEN];
190
191
192 /* translate from D1L to volume index (16 D1L levels) */
193 static UInt32 d1l_tab[16];
194
195
196 #define RATE_STEPS (8)
197 static UInt8 eg_inc[19*RATE_STEPS]={
198
199 /*cycle:0 1 2 3 4 5 6 7*/
200
201 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..11 0 (increment by 0 or 1) */
202 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..11 1 */
203 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..11 2 */
204 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..11 3 */
205
206 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 12 0 (increment by 1) */
207 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 12 1 */
208 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 12 2 */
209 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 12 3 */
210
211 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 13 0 (increment by 2) */
212 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 13 1 */
213 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 13 2 */
214 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 13 3 */
215
216 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rate 14 0 (increment by 4) */
217 /*13 */ 4,4, 4,8, 4,4, 4,8, /* rate 14 1 */
218 /*14 */ 4,8, 4,8, 4,8, 4,8, /* rate 14 2 */
219 /*15 */ 4,8, 8,8, 4,8, 8,8, /* rate 14 3 */
220
221 /*16 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
222 /*17 */ 16,16,16,16,16,16,16,16, /* rates 15 2, 15 3 for attack */
223 /*18 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
224 };
225
226
227 #define O(a) (a*RATE_STEPS)
228
229 /*note that there is no O(17) in this table - it's directly in the code */
230 static UInt8 eg_rate_select[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
231 /* 32 dummy (infinite time) rates */
232 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
233 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
234 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
235 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
236
237 /* rates 00-11 */
238 O( 0),O( 1),O( 2),O( 3),
239 O( 0),O( 1),O( 2),O( 3),
240 O( 0),O( 1),O( 2),O( 3),
241 O( 0),O( 1),O( 2),O( 3),
242 O( 0),O( 1),O( 2),O( 3),
243 O( 0),O( 1),O( 2),O( 3),
244 O( 0),O( 1),O( 2),O( 3),
245 O( 0),O( 1),O( 2),O( 3),
246 O( 0),O( 1),O( 2),O( 3),
247 O( 0),O( 1),O( 2),O( 3),
248 O( 0),O( 1),O( 2),O( 3),
249 O( 0),O( 1),O( 2),O( 3),
250
251 /* rate 12 */
252 O( 4),O( 5),O( 6),O( 7),
253
254 /* rate 13 */
255 O( 8),O( 9),O(10),O(11),
256
257 /* rate 14 */
258 O(12),O(13),O(14),O(15),
259
260 /* rate 15 */
261 O(16),O(16),O(16),O(16),
262
263 /* 32 dummy rates (same as 15 3) */
264 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
265 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
266 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
267 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
268
269 };
270 #undef O
271
272 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15*/
273 /*shift 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0 */
274 /*mask 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0, 0 */
275
276 #define O(a) (a*1)
277 static UInt8 eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
278 /* 32 infinite time rates */
279 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
280 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
281 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
282 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
283
284
285 /* rates 00-11 */
286 O(11),O(11),O(11),O(11),
287 O(10),O(10),O(10),O(10),
288 O( 9),O( 9),O( 9),O( 9),
289 O( 8),O( 8),O( 8),O( 8),
290 O( 7),O( 7),O( 7),O( 7),
291 O( 6),O( 6),O( 6),O( 6),
292 O( 5),O( 5),O( 5),O( 5),
293 O( 4),O( 4),O( 4),O( 4),
294 O( 3),O( 3),O( 3),O( 3),
295 O( 2),O( 2),O( 2),O( 2),
296 O( 1),O( 1),O( 1),O( 1),
297 O( 0),O( 0),O( 0),O( 0),
298
299 /* rate 12 */
300 O( 0),O( 0),O( 0),O( 0),
301
302 /* rate 13 */
303 O( 0),O( 0),O( 0),O( 0),
304
305 /* rate 14 */
306 O( 0),O( 0),O( 0),O( 0),
307
308 /* rate 15 */
309 O( 0),O( 0),O( 0),O( 0),
310
311 /* 32 dummy rates (same as 15 3) */
312 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
313 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
314 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
315 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0)
316
317 };
318 #undef O
319
320 /* DT2 defines offset in cents from base note
321 *
322 * This table defines offset in frequency-deltas table.
323 * User's Manual page 22
324 *
325 * Values below were calculated using formula: value = orig.val / 1.5625
326 *
327 * DT2=0 DT2=1 DT2=2 DT2=3
328 * 0 600 781 950
329 */
330 static UInt32 dt2_tab[4] = { 0, 384, 500, 608 };
331
332 /* DT1 defines offset in Hertz from base note
333 * This table is converted while initialization...
334 * Detune table shown in YM2151 User's Manual is wrong (verified on the real chip)
335 */
336
337 static UInt8 dt1_tab[4*32] = { /* 4*32 DT1 values */
338 /* DT1=0 */
339 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
340 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
341
342 /* DT1=1 */
343 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
344 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
345
346 /* DT1=2 */
347 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
348 5, 6, 6, 7, 8, 8, 9,10,11,12,13,14,16,16,16,16,
349
350 /* DT1=3 */
351 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
352 8, 8, 9,10,11,12,13,14,16,17,19,20,22,22,22,22
353 };
354
355 static UInt16 phaseinc_rom[768]={
356 1299,1300,1301,1302,1303,1304,1305,1306,1308,1309,1310,1311,1313,1314,1315,1316,
357 1318,1319,1320,1321,1322,1323,1324,1325,1327,1328,1329,1330,1332,1333,1334,1335,
358 1337,1338,1339,1340,1341,1342,1343,1344,1346,1347,1348,1349,1351,1352,1353,1354,
359 1356,1357,1358,1359,1361,1362,1363,1364,1366,1367,1368,1369,1371,1372,1373,1374,
360 1376,1377,1378,1379,1381,1382,1383,1384,1386,1387,1388,1389,1391,1392,1393,1394,
361 1396,1397,1398,1399,1401,1402,1403,1404,1406,1407,1408,1409,1411,1412,1413,1414,
362 1416,1417,1418,1419,1421,1422,1423,1424,1426,1427,1429,1430,1431,1432,1434,1435,
363 1437,1438,1439,1440,1442,1443,1444,1445,1447,1448,1449,1450,1452,1453,1454,1455,
364 1458,1459,1460,1461,1463,1464,1465,1466,1468,1469,1471,1472,1473,1474,1476,1477,
365 1479,1480,1481,1482,1484,1485,1486,1487,1489,1490,1492,1493,1494,1495,1497,1498,
366 1501,1502,1503,1504,1506,1507,1509,1510,1512,1513,1514,1515,1517,1518,1520,1521,
367 1523,1524,1525,1526,1528,1529,1531,1532,1534,1535,1536,1537,1539,1540,1542,1543,
368 1545,1546,1547,1548,1550,1551,1553,1554,1556,1557,1558,1559,1561,1562,1564,1565,
369 1567,1568,1569,1570,1572,1573,1575,1576,1578,1579,1580,1581,1583,1584,1586,1587,
370 1590,1591,1592,1593,1595,1596,1598,1599,1601,1602,1604,1605,1607,1608,1609,1610,
371 1613,1614,1615,1616,1618,1619,1621,1622,1624,1625,1627,1628,1630,1631,1632,1633,
372 1637,1638,1639,1640,1642,1643,1645,1646,1648,1649,1651,1652,1654,1655,1656,1657,
373 1660,1661,1663,1664,1666,1667,1669,1670,1672,1673,1675,1676,1678,1679,1681,1682,
374 1685,1686,1688,1689,1691,1692,1694,1695,1697,1698,1700,1701,1703,1704,1706,1707,
375 1709,1710,1712,1713,1715,1716,1718,1719,1721,1722,1724,1725,1727,1728,1730,1731,
376 1734,1735,1737,1738,1740,1741,1743,1744,1746,1748,1749,1751,1752,1754,1755,1757,
377 1759,1760,1762,1763,1765,1766,1768,1769,1771,1773,1774,1776,1777,1779,1780,1782,
378 1785,1786,1788,1789,1791,1793,1794,1796,1798,1799,1801,1802,1804,1806,1807,1809,
379 1811,1812,1814,1815,1817,1819,1820,1822,1824,1825,1827,1828,1830,1832,1833,1835,
380 1837,1838,1840,1841,1843,1845,1846,1848,1850,1851,1853,1854,1856,1858,1859,1861,
381 1864,1865,1867,1868,1870,1872,1873,1875,1877,1879,1880,1882,1884,1885,1887,1888,
382 1891,1892,1894,1895,1897,1899,1900,1902,1904,1906,1907,1909,1911,1912,1914,1915,
383 1918,1919,1921,1923,1925,1926,1928,1930,1932,1933,1935,1937,1939,1940,1942,1944,
384 1946,1947,1949,1951,1953,1954,1956,1958,1960,1961,1963,1965,1967,1968,1970,1972,
385 1975,1976,1978,1980,1982,1983,1985,1987,1989,1990,1992,1994,1996,1997,1999,2001,
386 2003,2004,2006,2008,2010,2011,2013,2015,2017,2019,2021,2022,2024,2026,2028,2029,
387 2032,2033,2035,2037,2039,2041,2043,2044,2047,2048,2050,2052,2054,2056,2058,2059,
388 2062,2063,2065,2067,2069,2071,2073,2074,2077,2078,2080,2082,2084,2086,2088,2089,
389 2092,2093,2095,2097,2099,2101,2103,2104,2107,2108,2110,2112,2114,2116,2118,2119,
390 2122,2123,2125,2127,2129,2131,2133,2134,2137,2139,2141,2142,2145,2146,2148,2150,
391 2153,2154,2156,2158,2160,2162,2164,2165,2168,2170,2172,2173,2176,2177,2179,2181,
392 2185,2186,2188,2190,2192,2194,2196,2197,2200,2202,2204,2205,2208,2209,2211,2213,
393 2216,2218,2220,2222,2223,2226,2227,2230,2232,2234,2236,2238,2239,2242,2243,2246,
394 2249,2251,2253,2255,2256,2259,2260,2263,2265,2267,2269,2271,2272,2275,2276,2279,
395 2281,2283,2285,2287,2288,2291,2292,2295,2297,2299,2301,2303,2304,2307,2308,2311,
396 2315,2317,2319,2321,2322,2325,2326,2329,2331,2333,2335,2337,2338,2341,2342,2345,
397 2348,2350,2352,2354,2355,2358,2359,2362,2364,2366,2368,2370,2371,2374,2375,2378,
398 2382,2384,2386,2388,2389,2392,2393,2396,2398,2400,2402,2404,2407,2410,2411,2414,
399 2417,2419,2421,2423,2424,2427,2428,2431,2433,2435,2437,2439,2442,2445,2446,2449,
400 2452,2454,2456,2458,2459,2462,2463,2466,2468,2470,2472,2474,2477,2480,2481,2484,
401 2488,2490,2492,2494,2495,2498,2499,2502,2504,2506,2508,2510,2513,2516,2517,2520,
402 2524,2526,2528,2530,2531,2534,2535,2538,2540,2542,2544,2546,2549,2552,2553,2556,
403 2561,2563,2565,2567,2568,2571,2572,2575,2577,2579,2581,2583,2586,2589,2590,2593
404 };
405
406
407 /*
408 Noise LFO waveform.
409
410 Here are just 256 samples out of much longer data.
411
412 It does NOT repeat every 256 samples on real chip and I wasnt able to find
413 the point where it repeats (even in strings as long as 131072 samples).
414
415 I only put it here because its better than nothing and perhaps
416 someone might be able to figure out the real algorithm.
417
418
419 Note that (due to the way the LFO output is calculated) it is quite
420 possible that two values: 0x80 and 0x00 might be wrong in this table.
421 To be exact:
422 some 0x80 could be 0x81 as well as some 0x00 could be 0x01.
423 */
424
425 static UInt8 lfo_noise_waveform[256] = {
426 0xFF,0xEE,0xD3,0x80,0x58,0xDA,0x7F,0x94,0x9E,0xE3,0xFA,0x00,0x4D,0xFA,0xFF,0x6A,
427 0x7A,0xDE,0x49,0xF6,0x00,0x33,0xBB,0x63,0x91,0x60,0x51,0xFF,0x00,0xD8,0x7F,0xDE,
428 0xDC,0x73,0x21,0x85,0xB2,0x9C,0x5D,0x24,0xCD,0x91,0x9E,0x76,0x7F,0x20,0xFB,0xF3,
429 0x00,0xA6,0x3E,0x42,0x27,0x69,0xAE,0x33,0x45,0x44,0x11,0x41,0x72,0x73,0xDF,0xA2,
430
431 0x32,0xBD,0x7E,0xA8,0x13,0xEB,0xD3,0x15,0xDD,0xFB,0xC9,0x9D,0x61,0x2F,0xBE,0x9D,
432 0x23,0x65,0x51,0x6A,0x84,0xF9,0xC9,0xD7,0x23,0xBF,0x65,0x19,0xDC,0x03,0xF3,0x24,
433 0x33,0xB6,0x1E,0x57,0x5C,0xAC,0x25,0x89,0x4D,0xC5,0x9C,0x99,0x15,0x07,0xCF,0xBA,
434 0xC5,0x9B,0x15,0x4D,0x8D,0x2A,0x1E,0x1F,0xEA,0x2B,0x2F,0x64,0xA9,0x50,0x3D,0xAB,
435
436 0x50,0x77,0xE9,0xC0,0xAC,0x6D,0x3F,0xCA,0xCF,0x71,0x7D,0x80,0xA6,0xFD,0xFF,0xB5,
437 0xBD,0x6F,0x24,0x7B,0x00,0x99,0x5D,0xB1,0x48,0xB0,0x28,0x7F,0x80,0xEC,0xBF,0x6F,
438 0x6E,0x39,0x90,0x42,0xD9,0x4E,0x2E,0x12,0x66,0xC8,0xCF,0x3B,0x3F,0x10,0x7D,0x79,
439 0x00,0xD3,0x1F,0x21,0x93,0x34,0xD7,0x19,0x22,0xA2,0x08,0x20,0xB9,0xB9,0xEF,0x51,
440
441 0x99,0xDE,0xBF,0xD4,0x09,0x75,0xE9,0x8A,0xEE,0xFD,0xE4,0x4E,0x30,0x17,0xDF,0xCE,
442 0x11,0xB2,0x28,0x35,0xC2,0x7C,0x64,0xEB,0x91,0x5F,0x32,0x0C,0x6E,0x00,0xF9,0x92,
443 0x19,0xDB,0x8F,0xAB,0xAE,0xD6,0x12,0xC4,0x26,0x62,0xCE,0xCC,0x0A,0x03,0xE7,0xDD,
444 0xE2,0x4D,0x8A,0xA6,0x46,0x95,0x0F,0x8F,0xF5,0x15,0x97,0x32,0xD4,0x28,0x1E,0x55
445 };
446
447
448
449
450 /* these variables stay here for speedup purposes only */
451 static MameYm2151 * PSG;
452
453
454 /* own PI definition */
455 #ifdef PI
456 #undef PI
457 #endif
458 #define PI 3.14159265358979323846
459
460
461
init_tables(void)462 static void init_tables(void)
463 {
464 signed int i,x,n;
465 DoubleT o,m;
466
467 for (x=0; x<TL_RES_LEN; x++)
468 {
469 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
470 m = floor(m);
471
472 /* we never reach (1<<16) here due to the (x+1) */
473 /* result fits within 16 bits at maximum */
474
475 n = (int)m; /* 16 bits here */
476 n >>= 4; /* 12 bits here */
477 if (n&1) /* round to closest */
478 n = (n>>1)+1;
479 else
480 n = n>>1;
481 /* 11 bits here (rounded) */
482 n <<= 2; /* 13 bits here (as in real chip) */
483 tl_tab[ x*2 + 0 ] = n;
484 tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
485
486 for (i=1; i<13; i++)
487 {
488 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
489 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
490 }
491 #if 0
492 logerror("tl %04i", x*2);
493 for (i=0; i<13; i++)
494 logerror(", [%02i] %4i", i*2, tl_tab[ x*2 /*+1*/ + i*2*TL_RES_LEN ]);
495 logerror("\n");
496 #endif
497 }
498 /*logerror("TL_TAB_LEN = %i (%i bytes)\n",TL_TAB_LEN, (int)sizeof(tl_tab));*/
499 /*logerror("ENV_QUIET= %i\n",ENV_QUIET );*/
500
501
502 for (i=0; i<SIN_LEN; i++)
503 {
504 /* non-standard sinus */
505 m = sin( ((i*2)+1) * PI / SIN_LEN ); /* verified on the real chip */
506
507 /* we never reach zero here due to ((i*2)+1) */
508
509 if (m>0.0)
510 o = 8*log(1.0/m)/log(2); /* convert to 'decibels' */
511 else
512 o = 8*log(-1.0/m)/log(2); /* convert to 'decibels' */
513
514 o = o / (ENV_STEP/4);
515
516 n = (int)(2.0*o);
517 if (n&1) /* round to closest */
518 n = (n>>1)+1;
519 else
520 n = n>>1;
521
522 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
523 /*logerror("sin [0x%4x]= %4i (tl_tab value=%8x)\n", i, sin_tab[i],tl_tab[sin_tab[i]]);*/
524 }
525
526
527 /* calculate d1l_tab table */
528 for (i=0; i<16; i++)
529 {
530 m = (UInt32)((i!=15 ? i : i+16) * (4.0/ENV_STEP)); /* every 3 'dB' except for all bits = 1 = 45+48 'dB' */
531 d1l_tab[i] = (UInt32)(m);
532 /*logerror("d1l_tab[%02x]=%08x\n",i,d1l_tab[i] );*/
533 }
534 }
535
536
init_chip_tables(MameYm2151 * chip)537 static void init_chip_tables(MameYm2151 *chip)
538 {
539 int i,j;
540 DoubleT mult,phaseinc,Hz;
541 DoubleT scaler;
542
543 scaler = ( (DoubleT)chip->clock / 64.0 ) / ( (DoubleT)chip->sampfreq );
544 /*logerror("scaler = %20.15f\n", scaler);*/
545
546
547 /* this loop calculates Hertz values for notes from c-0 to b-7 */
548 /* including 64 'cents' (100/64 that is 1.5625 of real cent) per note */
549 /* i*100/64/1200 is equal to i/768 */
550
551 /* real chip works with 10 bits fixed point values (10.10) */
552 mult = (1<<(FREQ_SH-10)); /* -10 because phaseinc_rom table values are already in 10.10 format */
553
554 for (i=0; i<768; i++)
555 {
556 /* 3.4375 Hz is note A; C# is 4 semitones higher */
557 Hz = 1000;
558
559 phaseinc = phaseinc_rom[i]; /* real chip phase increment */
560 phaseinc *= scaler; /* adjust */
561
562
563 /* octave 2 - reference octave */
564 chip->freq[ 768+2*768+i ] = ((int)(phaseinc*mult)) & 0xffffffc0; /* adjust to X.10 fixed point */
565 /* octave 0 and octave 1 */
566 for (j=0; j<2; j++)
567 {
568 chip->freq[768 + j*768 + i] = (chip->freq[ 768+2*768+i ] >> (2-j) ) & 0xffffffc0; /* adjust to X.10 fixed point */
569 }
570 /* octave 3 to 7 */
571 for (j=3; j<8; j++)
572 {
573 chip->freq[768 + j*768 + i] = chip->freq[ 768+2*768+i ] << (j-2);
574 }
575 }
576
577 /* octave -1 (all equal to: oct 0, _KC_00_, _KF_00_) */
578 for (i=0; i<768; i++)
579 {
580 chip->freq[ 0*768 + i ] = chip->freq[1*768+0];
581 }
582
583 /* octave 8 and 9 (all equal to: oct 7, _KC_14_, _KF_63_) */
584 for (j=8; j<10; j++)
585 {
586 for (i=0; i<768; i++)
587 {
588 chip->freq[768+ j*768 + i ] = chip->freq[768 + 8*768 -1];
589 }
590 }
591
592 mult = (1<<FREQ_SH);
593 for (j=0; j<4; j++)
594 {
595 for (i=0; i<32; i++)
596 {
597 Hz = ( (DoubleT)dt1_tab[j*32+i] * ((DoubleT)chip->clock/64.0) ) / (DoubleT)(1<<20);
598
599 /*calculate phase increment*/
600 phaseinc = (Hz*SIN_LEN) / (DoubleT)chip->sampfreq;
601
602 /*positive and negative values*/
603 chip->dt1_freq[ (j+0)*32 + i ] = (Int32)(phaseinc * mult);
604 chip->dt1_freq[ (j+4)*32 + i ] = -chip->dt1_freq[ (j+0)*32 + i ];
605 }
606 }
607
608 chip->timer_A_val = 0;
609
610 /* calculate noise periods table */
611 scaler = ( (DoubleT)chip->clock / 64.0 ) / ( (DoubleT)chip->sampfreq );
612 for (i=0; i<32; i++)
613 {
614 j = (i!=31 ? i : 30); /* rate 30 and 31 are the same */
615 j = 32-j;
616 j = (int)(65536.0 / (DoubleT)(j*32.0)); /* number of samples per one shift of the shift register */
617 /*chip->noise_tab[i] = j * 64;*/ /* number of chip clock cycles per one shift */
618 chip->noise_tab[i] = (UInt32)(j * 64 * scaler);
619 /*logerror("noise_tab[%02x]=%08x\n", i, chip->noise_tab[i]);*/
620 }
621 }
622
623 #define KEY_ON(op, key_set){ \
624 if (!(op)->key) \
625 { \
626 (op)->phase = 0; /* clear phase */ \
627 (op)->state = EG_ATT; /* KEY ON = attack */ \
628 (op)->volume += (~(op)->volume * \
629 (eg_inc[(op)->eg_sel_ar + ((PSG->eg_cnt>>(op)->eg_sh_ar)&7)]) \
630 ) >>4; \
631 if ((op)->volume <= MIN_ATT_INDEX) \
632 { \
633 (op)->volume = MIN_ATT_INDEX; \
634 (op)->state = EG_DEC; \
635 } \
636 } \
637 (op)->key |= key_set; \
638 }
639
640 #define KEY_OFF(op, key_clr){ \
641 if ((op)->key) \
642 { \
643 (op)->key &= key_clr; \
644 if (!(op)->key) \
645 { \
646 if ((op)->state>EG_REL) \
647 (op)->state = EG_REL;/* KEY OFF = release */\
648 } \
649 } \
650 }
651
envelope_KONKOFF(YM2151Operator * op,int v)652 static void envelope_KONKOFF(YM2151Operator * op, int v)
653 {
654 if (v&0x08) /* M1 */
655 KEY_ON (op+0, 1)
656 else
657 KEY_OFF(op+0,~1)
658
659 if (v&0x20) /* M2 */
660 KEY_ON (op+1, 1)
661 else
662 KEY_OFF(op+1,~1)
663
664 if (v&0x10) /* C1 */
665 KEY_ON (op+2, 1)
666 else
667 KEY_OFF(op+2,~1)
668
669 if (v&0x40) /* C2 */
670 KEY_ON (op+3, 1)
671 else
672 KEY_OFF(op+3,~1)
673 }
674
YM2151TimerCallback(MameYm2151 * chip,int timer)675 void YM2151TimerCallback(MameYm2151 *chip, int timer)
676 {
677 if (timer == 0) {
678 if (chip->irq_enable & 0x04)
679 {
680 if ((chip->status & 3) == 0) ym2151SetIrq(chip->ref, 1);
681 chip->status |= 1;
682 }
683 if (chip->irq_enable & 0x80)
684 chip->csm_req = 2; /* request KEY ON / KEY OFF sequence */
685 }
686 if (timer == 1) {
687 if (chip->irq_enable & 0x08)
688 {
689 if ((chip->status & 3) == 0) ym2151SetIrq(chip->ref, 2);
690 chip->status |= 2;
691 }
692 }
693 }
694
695
set_connect(MameYm2151 * chip,YM2151Operator * om1,int cha,int v)696 static void set_connect( MameYm2151 *chip, YM2151Operator *om1, int cha, int v)
697 {
698 YM2151Operator *om2 = om1+1;
699 YM2151Operator *oc1 = om1+2;
700
701 /* set connect algorithm */
702
703 /* MEM is simply one sample delay */
704
705 switch( v&7 )
706 {
707 case 0:
708 /* M1---C1---MEM---M2---C2---OUT */
709 om1->connect = &chip->c1;
710 oc1->connect = &chip->mem;
711 om2->connect = &chip->c2;
712 om1->mem_connect = &chip->m2;
713 break;
714
715 case 1:
716 /* M1------+-MEM---M2---C2---OUT */
717 /* C1-+ */
718 om1->connect = &chip->mem;
719 oc1->connect = &chip->mem;
720 om2->connect = &chip->c2;
721 om1->mem_connect = &chip->m2;
722 break;
723
724 case 2:
725 /* M1-----------------+-C2---OUT */
726 /* C1---MEM---M2-+ */
727 om1->connect = &chip->c2;
728 oc1->connect = &chip->mem;
729 om2->connect = &chip->c2;
730 om1->mem_connect = &chip->m2;
731 break;
732
733 case 3:
734 /* M1---C1---MEM------+-C2---OUT */
735 /* M2-+ */
736 om1->connect = &chip->c1;
737 oc1->connect = &chip->mem;
738 om2->connect = &chip->c2;
739 om1->mem_connect = &chip->c2;
740 break;
741
742 case 4:
743 /* M1---C1-+-OUT */
744 /* M2---C2-+ */
745 /* MEM: not used */
746 om1->connect = &chip->c1;
747 oc1->connect = &chip->chanout[cha];
748 om2->connect = &chip->c2;
749 om1->mem_connect = &chip->mem; /* store it anywhere where it will not be used */
750 break;
751
752 case 5:
753 /* +----C1----+ */
754 /* M1-+-MEM---M2-+-OUT */
755 /* +----C2----+ */
756 om1->connect = 0; /* special mark */
757 oc1->connect = &chip->chanout[cha];
758 om2->connect = &chip->chanout[cha];
759 om1->mem_connect = &chip->m2;
760 break;
761
762 case 6:
763 /* M1---C1-+ */
764 /* M2-+-OUT */
765 /* C2-+ */
766 /* MEM: not used */
767 om1->connect = &chip->c1;
768 oc1->connect = &chip->chanout[cha];
769 om2->connect = &chip->chanout[cha];
770 om1->mem_connect = &chip->mem; /* store it anywhere where it will not be used */
771 break;
772
773 case 7:
774 /* M1-+ */
775 /* C1-+-OUT */
776 /* M2-+ */
777 /* C2-+ */
778 /* MEM: not used*/
779 om1->connect = &chip->chanout[cha];
780 oc1->connect = &chip->chanout[cha];
781 om2->connect = &chip->chanout[cha];
782 om1->mem_connect = &chip->mem; /* store it anywhere where it will not be used */
783 break;
784 }
785 }
786
787
refresh_EG(YM2151Operator * op)788 static void refresh_EG(YM2151Operator * op)
789 {
790 UInt32 kc;
791 UInt32 v;
792
793 kc = op->kc;
794
795 /* v = 32 + 2*RATE + RKS = max 126 */
796
797 v = kc >> op->ks;
798 if ((op->ar+v) < 32+62)
799 {
800 op->eg_sh_ar = eg_rate_shift [op->ar + v ];
801 op->eg_sel_ar = eg_rate_select[op->ar + v ];
802 }
803 else
804 {
805 op->eg_sh_ar = 0;
806 op->eg_sel_ar = 17*RATE_STEPS;
807 }
808 op->eg_sh_d1r = eg_rate_shift [op->d1r + v];
809 op->eg_sel_d1r= eg_rate_select[op->d1r + v];
810 op->eg_sh_d2r = eg_rate_shift [op->d2r + v];
811 op->eg_sel_d2r= eg_rate_select[op->d2r + v];
812 op->eg_sh_rr = eg_rate_shift [op->rr + v];
813 op->eg_sel_rr = eg_rate_select[op->rr + v];
814
815
816 op+=1;
817
818 v = kc >> op->ks;
819 if ((op->ar+v) < 32+62)
820 {
821 op->eg_sh_ar = eg_rate_shift [op->ar + v ];
822 op->eg_sel_ar = eg_rate_select[op->ar + v ];
823 }
824 else
825 {
826 op->eg_sh_ar = 0;
827 op->eg_sel_ar = 17*RATE_STEPS;
828 }
829 op->eg_sh_d1r = eg_rate_shift [op->d1r + v];
830 op->eg_sel_d1r= eg_rate_select[op->d1r + v];
831 op->eg_sh_d2r = eg_rate_shift [op->d2r + v];
832 op->eg_sel_d2r= eg_rate_select[op->d2r + v];
833 op->eg_sh_rr = eg_rate_shift [op->rr + v];
834 op->eg_sel_rr = eg_rate_select[op->rr + v];
835
836 op+=1;
837
838 v = kc >> op->ks;
839 if ((op->ar+v) < 32+62)
840 {
841 op->eg_sh_ar = eg_rate_shift [op->ar + v ];
842 op->eg_sel_ar = eg_rate_select[op->ar + v ];
843 }
844 else
845 {
846 op->eg_sh_ar = 0;
847 op->eg_sel_ar = 17*RATE_STEPS;
848 }
849 op->eg_sh_d1r = eg_rate_shift [op->d1r + v];
850 op->eg_sel_d1r= eg_rate_select[op->d1r + v];
851 op->eg_sh_d2r = eg_rate_shift [op->d2r + v];
852 op->eg_sel_d2r= eg_rate_select[op->d2r + v];
853 op->eg_sh_rr = eg_rate_shift [op->rr + v];
854 op->eg_sel_rr = eg_rate_select[op->rr + v];
855
856 op+=1;
857
858 v = kc >> op->ks;
859 if ((op->ar+v) < 32+62)
860 {
861 op->eg_sh_ar = eg_rate_shift [op->ar + v ];
862 op->eg_sel_ar = eg_rate_select[op->ar + v ];
863 }
864 else
865 {
866 op->eg_sh_ar = 0;
867 op->eg_sel_ar = 17*RATE_STEPS;
868 }
869 op->eg_sh_d1r = eg_rate_shift [op->d1r + v];
870 op->eg_sel_d1r= eg_rate_select[op->d1r + v];
871 op->eg_sh_d2r = eg_rate_shift [op->d2r + v];
872 op->eg_sel_d2r= eg_rate_select[op->d2r + v];
873 op->eg_sh_rr = eg_rate_shift [op->rr + v];
874 op->eg_sel_rr = eg_rate_select[op->rr + v];
875 }
876
877
878 /* write a register on YM2151 chip number 'n' */
YM2151WriteReg(MameYm2151 * chip,int r,int v)879 void YM2151WriteReg(MameYm2151 *chip, int r, int v)
880 {
881 YM2151Operator *op = &chip->oper[ (r&0x07)*4+((r&0x18)>>3) ];
882
883 /* adjust bus to 8 bits */
884 r &= 0xff;
885 v &= 0xff;
886
887 switch(r & 0xe0){
888 case 0x00:
889 switch(r){
890 case 0x01: /* LFO reset(bit 1), Test Register (other bits) */
891 chip->test = v;
892 if (v&2) chip->lfo_phase = 0;
893 break;
894
895 case 0x08:
896 PSG = chip; /* PSG is used in KEY_ON macro */
897 envelope_KONKOFF(&chip->oper[ (v&7)*4 ], v );
898 break;
899
900 case 0x0f: /* noise mode enable, noise period */
901 chip->noise = v;
902 chip->noise_f = chip->noise_tab[ v & 0x1f ];
903 break;
904
905 case 0x10:
906 chip->timer_A_val &= 0x03;
907 chip->timer_A_val |= v << 2;
908 ym2151TimerSet(chip->ref, 0, 1 * (1024 - chip->timer_A_val));
909 break;
910
911 case 0x11:
912 chip->timer_A_val &= 0x03fc;
913 chip->timer_A_val |= v & 3;
914 ym2151TimerSet(chip->ref, 0, 1 * (1024 - chip->timer_A_val));
915 break;
916
917 case 0x12:
918 ym2151TimerSet(chip->ref, 1, 16 * (256 - v));
919 break;
920
921 case 0x14: /* CSM, irq flag reset, irq enable, timer start/stop */
922
923 chip->irq_enable = v; /* bit 3-timer B, bit 2-timer A, bit 7 - CSM */
924
925 if (v&0x10) /* reset timer A irq flag */
926 {
927 chip->status &= ~1;
928 if ((chip->status & 3) == 0) ym2151ClearIrq(chip->ref, 1);
929 }
930
931 if (v&0x20) /* reset timer B irq flag */
932 {
933 chip->status &= ~2;
934 if ((chip->status & 3) == 0) ym2151ClearIrq(chip->ref, 2);
935 }
936
937 ym2151TimerStart(chip->ref, 1, v & 2);
938 ym2151TimerStart(chip->ref, 0, v & 1);
939 break;
940
941 case 0x18: /* LFO frequency */
942 {
943 chip->lfo_overflow = ( 1 << ((15-(v>>4))+3) ) * (1<<LFO_SH);
944 chip->lfo_counter_add = 0x10 + (v & 0x0f);
945 }
946 break;
947
948 case 0x19: /* PMD (bit 7==1) or AMD (bit 7==0) */
949 if (v&0x80)
950 chip->pmd = v & 0x7f;
951 else
952 chip->amd = v & 0x7f;
953 break;
954
955 case 0x1b: /* CT2, CT1, LFO waveform */
956 chip->ct = v >> 6;
957 chip->lfo_wsel = v & 3;
958
959 ym2151WritePortCallback(chip->ref, 0 , chip->ct);
960 break;
961
962 default:
963 break;
964 }
965 break;
966
967 case 0x20:
968 op = &chip->oper[ (r&7) * 4 ];
969 switch(r & 0x18){
970 case 0x00: /* RL enable, Feedback, Connection */
971 op->fb_shift = ((v>>3)&7) ? ((v>>3)&7)+6:0;
972 chip->pan[ (r&7)*2 ] = (v & 0x40) ? ~0 : 0;
973 chip->pan[ (r&7)*2 +1 ] = (v & 0x80) ? ~0 : 0;
974 chip->connect[r&7] = v&7;
975 set_connect(chip, op, r&7, v&7);
976 break;
977
978 case 0x08: /* Key Code */
979 v &= 0x7f;
980 if (v != op->kc)
981 {
982 UInt32 kc, kc_channel;
983
984 kc_channel = (v - (v>>2))*64;
985 kc_channel += 768;
986 kc_channel |= (op->kc_i & 63);
987
988 (op+0)->kc = v;
989 (op+0)->kc_i = kc_channel;
990 (op+1)->kc = v;
991 (op+1)->kc_i = kc_channel;
992 (op+2)->kc = v;
993 (op+2)->kc_i = kc_channel;
994 (op+3)->kc = v;
995 (op+3)->kc_i = kc_channel;
996
997 kc = v>>2;
998
999 (op+0)->dt1 = chip->dt1_freq[ (op+0)->dt1_i + kc ];
1000 (op+0)->freq = ( (chip->freq[ kc_channel + (op+0)->dt2 ] + (op+0)->dt1) * (op+0)->mul ) >> 1;
1001
1002 (op+1)->dt1 = chip->dt1_freq[ (op+1)->dt1_i + kc ];
1003 (op+1)->freq = ( (chip->freq[ kc_channel + (op+1)->dt2 ] + (op+1)->dt1) * (op+1)->mul ) >> 1;
1004
1005 (op+2)->dt1 = chip->dt1_freq[ (op+2)->dt1_i + kc ];
1006 (op+2)->freq = ( (chip->freq[ kc_channel + (op+2)->dt2 ] + (op+2)->dt1) * (op+2)->mul ) >> 1;
1007
1008 (op+3)->dt1 = chip->dt1_freq[ (op+3)->dt1_i + kc ];
1009 (op+3)->freq = ( (chip->freq[ kc_channel + (op+3)->dt2 ] + (op+3)->dt1) * (op+3)->mul ) >> 1;
1010
1011 refresh_EG( op );
1012 }
1013 break;
1014
1015 case 0x10: /* Key Fraction */
1016 v >>= 2;
1017 if (v != (op->kc_i & 63))
1018 {
1019 UInt32 kc_channel;
1020
1021 kc_channel = v;
1022 kc_channel |= (op->kc_i & ~63);
1023
1024 (op+0)->kc_i = kc_channel;
1025 (op+1)->kc_i = kc_channel;
1026 (op+2)->kc_i = kc_channel;
1027 (op+3)->kc_i = kc_channel;
1028
1029 (op+0)->freq = ( (chip->freq[ kc_channel + (op+0)->dt2 ] + (op+0)->dt1) * (op+0)->mul ) >> 1;
1030 (op+1)->freq = ( (chip->freq[ kc_channel + (op+1)->dt2 ] + (op+1)->dt1) * (op+1)->mul ) >> 1;
1031 (op+2)->freq = ( (chip->freq[ kc_channel + (op+2)->dt2 ] + (op+2)->dt1) * (op+2)->mul ) >> 1;
1032 (op+3)->freq = ( (chip->freq[ kc_channel + (op+3)->dt2 ] + (op+3)->dt1) * (op+3)->mul ) >> 1;
1033 }
1034 break;
1035
1036 case 0x18: /* PMS, AMS */
1037 op->pms = (v>>4) & 7;
1038 op->ams = (v & 3);
1039 break;
1040 }
1041 break;
1042
1043 case 0x40: /* DT1, MUL */
1044 {
1045 UInt32 olddt1_i = op->dt1_i;
1046 UInt32 oldmul = op->mul;
1047
1048 op->dt1_i = (v&0x70)<<1;
1049 op->mul = (v&0x0f) ? (v&0x0f)<<1: 1;
1050
1051 if (olddt1_i != op->dt1_i)
1052 op->dt1 = chip->dt1_freq[ op->dt1_i + (op->kc>>2) ];
1053
1054 if ( (olddt1_i != op->dt1_i) || (oldmul != op->mul) )
1055 op->freq = ( (chip->freq[ op->kc_i + op->dt2 ] + op->dt1) * op->mul ) >> 1;
1056 }
1057 break;
1058
1059 case 0x60: /* TL */
1060 op->tl = (v&0x7f)<<(ENV_BITS-7); /* 7bit TL */
1061 break;
1062
1063 case 0x80: /* KS, AR */
1064 {
1065 UInt32 oldks = op->ks;
1066 UInt32 oldar = op->ar;
1067
1068 op->ks = 5-(v>>6);
1069 op->ar = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1070
1071 if ( (op->ar != oldar) || (op->ks != oldks) )
1072 {
1073 if ((op->ar + (op->kc>>op->ks)) < 32+62)
1074 {
1075 op->eg_sh_ar = eg_rate_shift [op->ar + (op->kc>>op->ks) ];
1076 op->eg_sel_ar = eg_rate_select[op->ar + (op->kc>>op->ks) ];
1077 }
1078 else
1079 {
1080 op->eg_sh_ar = 0;
1081 op->eg_sel_ar = 17*RATE_STEPS;
1082 }
1083 }
1084
1085 if (op->ks != oldks)
1086 {
1087 op->eg_sh_d1r = eg_rate_shift [op->d1r + (op->kc>>op->ks) ];
1088 op->eg_sel_d1r= eg_rate_select[op->d1r + (op->kc>>op->ks) ];
1089 op->eg_sh_d2r = eg_rate_shift [op->d2r + (op->kc>>op->ks) ];
1090 op->eg_sel_d2r= eg_rate_select[op->d2r + (op->kc>>op->ks) ];
1091 op->eg_sh_rr = eg_rate_shift [op->rr + (op->kc>>op->ks) ];
1092 op->eg_sel_rr = eg_rate_select[op->rr + (op->kc>>op->ks) ];
1093 }
1094 }
1095 break;
1096
1097 case 0xa0: /* LFO AM enable, D1R */
1098 op->AMmask = (v&0x80) ? ~0 : 0;
1099 op->d1r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1100 op->eg_sh_d1r = eg_rate_shift [op->d1r + (op->kc>>op->ks) ];
1101 op->eg_sel_d1r= eg_rate_select[op->d1r + (op->kc>>op->ks) ];
1102 break;
1103
1104 case 0xc0: /* DT2, D2R */
1105 {
1106 UInt32 olddt2 = op->dt2;
1107 op->dt2 = dt2_tab[ v>>6 ];
1108 if (op->dt2 != olddt2)
1109 op->freq = ( (chip->freq[ op->kc_i + op->dt2 ] + op->dt1) * op->mul ) >> 1;
1110 }
1111 op->d2r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1112 op->eg_sh_d2r = eg_rate_shift [op->d2r + (op->kc>>op->ks) ];
1113 op->eg_sel_d2r= eg_rate_select[op->d2r + (op->kc>>op->ks) ];
1114 break;
1115
1116 case 0xe0: /* D1L, RR */
1117 op->d1l = d1l_tab[ v>>4 ];
1118 op->rr = 34 + ((v&0x0f)<<2);
1119 op->eg_sh_rr = eg_rate_shift [op->rr + (op->kc>>op->ks) ];
1120 op->eg_sel_rr = eg_rate_select[op->rr + (op->kc>>op->ks) ];
1121 break;
1122 }
1123 }
1124
1125
1126
YM2151ReadStatus(MameYm2151 * chip)1127 int YM2151ReadStatus(MameYm2151 *chip)
1128 {
1129 return chip->status;
1130 }
1131
1132
ym2151_state_save_register(MameYm2151 * chip)1133 static void ym2151_state_save_register( MameYm2151 *chip )
1134 {
1135 }
1136
YM2151Create(void * ref,int clock,int rate)1137 MameYm2151* YM2151Create(void* ref, int clock, int rate)
1138 {
1139 MameYm2151 *chip = (MameYm2151 *)calloc(1, sizeof(MameYm2151));
1140
1141 chip->ref = ref;
1142
1143 init_tables();
1144
1145 chip->clock = clock;
1146 /*rate = clock/64;*/
1147 chip->sampfreq = rate ? rate : 44100; /* avoid division by 0 in init_chip_tables() */
1148 init_chip_tables(chip);
1149
1150 chip->lfo_timer_add = (UInt32)((1<<LFO_SH) * (clock/64.0) / chip->sampfreq);
1151
1152 chip->eg_timer_add = (UInt32)((1<<EG_SH) * (clock/64.0) / chip->sampfreq);
1153 chip->eg_timer_overflow = ( 3 ) * (1<<EG_SH);
1154
1155 YM2151ResetChip(chip);
1156
1157 return chip;
1158 }
1159
YM2151Destroy(MameYm2151 * chip)1160 void YM2151Destroy(MameYm2151* chip)
1161 {
1162 free(chip);
1163 }
1164
1165
YM2151ResetChip(MameYm2151 * chip)1166 void YM2151ResetChip(MameYm2151 *chip)
1167 {
1168 int i;
1169
1170
1171 /* initialize hardware registers */
1172 for (i=0; i<32; i++)
1173 {
1174 memset(&chip->oper[i],'\0',sizeof(YM2151Operator));
1175 chip->oper[i].volume = MAX_ATT_INDEX;
1176 chip->oper[i].kc_i = 768; // min kc_i value
1177 }
1178
1179 chip->eg_timer = 0;
1180 chip->eg_cnt = 0;
1181
1182 chip->lfo_timer = 0;
1183 chip->lfo_counter= 0;
1184 chip->lfo_phase = 0;
1185 chip->lfo_wsel = 0;
1186 chip->pmd = 0;
1187 chip->amd = 0;
1188 chip->lfa = 0;
1189 chip->lfp = 0;
1190
1191 chip->test= 0;
1192
1193 chip->irq_enable = 0;
1194 ym2151TimerStart(chip->ref, 0, 0);
1195 ym2151TimerStart(chip->ref, 1, 0);
1196
1197 chip->noise = 0;
1198 chip->noise_rng = 0;
1199 chip->noise_p = 0;
1200 chip->noise_f = chip->noise_tab[0];
1201
1202 chip->csm_req = 0;
1203 chip->status = 0;
1204
1205 YM2151WriteReg(chip, 0x1b, 0); /* only because of CT1, CT2 output pins */
1206 YM2151WriteReg(chip, 0x18, 0); /* set LFO frequency */
1207 for (i=0x20; i<0x100; i++) /* set the operators */
1208 {
1209 YM2151WriteReg(chip, i, 0);
1210 }
1211 }
1212
1213
1214
op_calc(YM2151Operator * OP,unsigned int env,signed int pm)1215 static signed int op_calc(YM2151Operator * OP, unsigned int env, signed int pm)
1216 {
1217 UInt32 p;
1218
1219
1220 p = (env<<3) + sin_tab[ ( ((signed int)((OP->phase & ~FREQ_MASK) + (pm<<15))) >> FREQ_SH ) & SIN_MASK ];
1221
1222 if (p >= TL_TAB_LEN)
1223 return 0;
1224
1225 return tl_tab[p];
1226 }
1227
op_calc1(YM2151Operator * OP,unsigned int env,signed int pm)1228 static signed int op_calc1(YM2151Operator * OP, unsigned int env, signed int pm)
1229 {
1230 UInt32 p;
1231 Int32 i;
1232
1233
1234 i = (OP->phase & ~FREQ_MASK) + pm;
1235
1236 /*logerror("i=%08x (i>>16)&511=%8i phase=%i [pm=%08x] ",i, (i>>16)&511, OP->phase>>FREQ_SH, pm);*/
1237
1238 p = (env<<3) + sin_tab[ (i>>FREQ_SH) & SIN_MASK];
1239
1240 /*logerror("(p&255=%i p>>8=%i) out= %i\n", p&255,p>>8, tl_tab[p&255]>>(p>>8) );*/
1241
1242 if (p >= TL_TAB_LEN)
1243 return 0;
1244
1245 return tl_tab[p];
1246 }
1247
1248
1249
1250 #define volume_calc(OP) ((OP)->tl + ((UInt32)(OP)->volume) + (AM & (OP)->AMmask))
1251
chan_calc(MameYm2151 * chip,unsigned int chan)1252 static void chan_calc(MameYm2151* chip, unsigned int chan)
1253 {
1254 YM2151Operator *op;
1255 unsigned int env;
1256 UInt32 AM = 0;
1257
1258 chip->m2 = chip->c1 = chip->c2 = chip->mem = 0;
1259 op = &PSG->oper[chan*4]; /* M1 */
1260
1261 *op->mem_connect = op->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
1262
1263 if (op->ams)
1264 AM = PSG->lfa << (op->ams-1);
1265 env = volume_calc(op);
1266 {
1267 Int32 out = op->fb_out_prev + op->fb_out_curr;
1268 op->fb_out_prev = op->fb_out_curr;
1269
1270 if (!op->connect)
1271 /* algorithm 5 */
1272 chip->mem = chip->c1 = chip->c2 = op->fb_out_prev;
1273 else
1274 /* other algorithms */
1275 *op->connect = op->fb_out_prev;
1276
1277 op->fb_out_curr = 0;
1278 if (env < ENV_QUIET)
1279 {
1280 if (!op->fb_shift)
1281 out=0;
1282 op->fb_out_curr = op_calc1(op, env, (out<<op->fb_shift) );
1283 }
1284 }
1285
1286 env = volume_calc(op+1); /* M2 */
1287 if (env < ENV_QUIET)
1288 *(op+1)->connect += op_calc(op+1, env, chip->m2);
1289
1290 env = volume_calc(op+2); /* C1 */
1291 if (env < ENV_QUIET)
1292 *(op+2)->connect += op_calc(op+2, env, chip->c1);
1293
1294 env = volume_calc(op+3); /* C2 */
1295 if (env < ENV_QUIET)
1296 chip->chanout[chan] += op_calc(op+3, env, chip->c2);
1297
1298 /* M1 */
1299 op->mem_value = chip->mem;
1300 }
chan7_calc(MameYm2151 * chip)1301 static void chan7_calc(MameYm2151* chip)
1302 {
1303 YM2151Operator *op;
1304 unsigned int env;
1305 UInt32 AM = 0;
1306
1307 chip->m2 = chip->c1 = chip->c2 = chip->mem = 0;
1308 op = &PSG->oper[7*4]; /* M1 */
1309
1310 *op->mem_connect = op->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
1311
1312 if (op->ams)
1313 AM = PSG->lfa << (op->ams-1);
1314 env = volume_calc(op);
1315 {
1316 Int32 out = op->fb_out_prev + op->fb_out_curr;
1317 op->fb_out_prev = op->fb_out_curr;
1318
1319 if (!op->connect)
1320 /* algorithm 5 */
1321 chip->mem = chip->c1 = chip->c2 = op->fb_out_prev;
1322 else
1323 /* other algorithms */
1324 *op->connect = op->fb_out_prev;
1325
1326 op->fb_out_curr = 0;
1327 if (env < ENV_QUIET)
1328 {
1329 if (!op->fb_shift)
1330 out=0;
1331 op->fb_out_curr = op_calc1(op, env, (out<<op->fb_shift) );
1332 }
1333 }
1334
1335 env = volume_calc(op+1); /* M2 */
1336 if (env < ENV_QUIET)
1337 *(op+1)->connect += op_calc(op+1, env, chip->m2);
1338
1339 env = volume_calc(op+2); /* C1 */
1340 if (env < ENV_QUIET)
1341 *(op+2)->connect += op_calc(op+2, env, chip->c1);
1342
1343 env = volume_calc(op+3); /* C2 */
1344 if (PSG->noise & 0x80)
1345 {
1346 UInt32 noiseout;
1347
1348 noiseout = 0;
1349 if (env < 0x3ff)
1350 noiseout = (env ^ 0x3ff) * 2; /* range of the YM2151 noise output is -2044 to 2040 */
1351 chip->chanout[7] += ((PSG->noise_rng&0x10000) ? noiseout: (UInt32)-(Int32)noiseout); /* bit 16 -> output */
1352 }
1353 else
1354 {
1355 if (env < ENV_QUIET)
1356 chip->chanout[7] += op_calc(op+3, env, chip->c2);
1357 }
1358 /* M1 */
1359 op->mem_value = chip->mem;
1360 }
1361
1362
1363
1364
1365
1366
1367 /*
1368 The 'rate' is calculated from following formula (example on decay rate):
1369 rks = notecode after key scaling (a value from 0 to 31)
1370 DR = value written to the chip register
1371 rate = 2*DR + rks; (max rate = 2*31+31 = 93)
1372 Four MSBs of the 'rate' above are the 'main' rate (from 00 to 15)
1373 Two LSBs of the 'rate' above are the value 'x' (the shape type).
1374 (eg. '11 2' means that 'rate' is 11*4+2=46)
1375
1376 NOTE: A 'sample' in the description below is actually 3 output samples,
1377 thats because the Envelope Generator clock is equal to internal_clock/3.
1378
1379 Single '-' (minus) character in the diagrams below represents one sample
1380 on the output; this is for rates 11 x (11 0, 11 1, 11 2 and 11 3)
1381
1382 these 'main' rates:
1383 00 x: single '-' = 2048 samples; (ie. level can change every 2048 samples)
1384 01 x: single '-' = 1024 samples;
1385 02 x: single '-' = 512 samples;
1386 03 x: single '-' = 256 samples;
1387 04 x: single '-' = 128 samples;
1388 05 x: single '-' = 64 samples;
1389 06 x: single '-' = 32 samples;
1390 07 x: single '-' = 16 samples;
1391 08 x: single '-' = 8 samples;
1392 09 x: single '-' = 4 samples;
1393 10 x: single '-' = 2 samples;
1394 11 x: single '-' = 1 sample; (ie. level can change every 1 sample)
1395
1396 Shapes for rates 11 x look like this:
1397 rate: step:
1398 11 0 01234567
1399
1400 level:
1401 0 --
1402 1 --
1403 2 --
1404 3 --
1405
1406 rate: step:
1407 11 1 01234567
1408
1409 level:
1410 0 --
1411 1 --
1412 2 -
1413 3 -
1414 4 --
1415
1416 rate: step:
1417 11 2 01234567
1418
1419 level:
1420 0 --
1421 1 -
1422 2 -
1423 3 --
1424 4 -
1425 5 -
1426
1427 rate: step:
1428 11 3 01234567
1429
1430 level:
1431 0 --
1432 1 -
1433 2 -
1434 3 -
1435 4 -
1436 5 -
1437 6 -
1438
1439
1440 For rates 12 x, 13 x, 14 x and 15 x output level changes on every
1441 sample - this means that the waveform looks like this: (but the level
1442 changes by different values on different steps)
1443 12 3 01234567
1444
1445 0 -
1446 2 -
1447 4 -
1448 8 -
1449 10 -
1450 12 -
1451 14 -
1452 18 -
1453 20 -
1454
1455 Notes about the timing:
1456 ----------------------
1457
1458 1. Synchronism
1459
1460 Output level of each two (or more) voices running at the same 'main' rate
1461 (eg 11 0 and 11 1 in the diagram below) will always be changing in sync,
1462 even if there're started with some delay.
1463
1464 Note that, in the diagram below, the decay phase in channel 0 starts at
1465 sample #2, while in channel 1 it starts at sample #6. Anyway, both channels
1466 will always change their levels at exactly the same (following) samples.
1467
1468 (S - start point of this channel, A-attack phase, D-decay phase):
1469
1470 step:
1471 01234567012345670123456
1472
1473 channel 0:
1474 --
1475 | --
1476 | -
1477 | -
1478 | --
1479 | --
1480 | --
1481 | -
1482 | -
1483 | --
1484 AADDDDDDDDDDDDDDDD
1485 S
1486
1487 01234567012345670123456
1488 channel 1:
1489 -
1490 | -
1491 | --
1492 | --
1493 | --
1494 | -
1495 | -
1496 | --
1497 | --
1498 | --
1499 AADDDDDDDDDDDDDDDD
1500 S
1501 01234567012345670123456
1502
1503
1504 2. Shifted (delayed) synchronism
1505
1506 Output of each two (or more) voices running at different 'main' rate
1507 (9 1, 10 1 and 11 1 in the diagrams below) will always be changing
1508 in 'delayed-sync' (even if there're started with some delay as in "1.")
1509
1510 Note that the shapes are delayed by exactly one sample per one 'main' rate
1511 increment. (Normally one would expect them to start at the same samples.)
1512
1513 See diagram below (* - start point of the shape).
1514
1515 cycle:
1516 0123456701234567012345670123456701234567012345670123456701234567
1517
1518 rate 09 1
1519 *-------
1520 --------
1521 ----
1522 ----
1523 --------
1524 *-------
1525 | --------
1526 | ----
1527 | ----
1528 | --------
1529 rate 10 1 |
1530 -- |
1531 *--- |
1532 ---- |
1533 -- |
1534 -- |
1535 ---- |
1536 *--- |
1537 | ---- |
1538 | -- | | <- one step (two samples) delay between 9 1 and 10 1
1539 | -- | |
1540 | ----|
1541 | *---
1542 | ----
1543 | --
1544 | --
1545 | ----
1546 rate 11 1 |
1547 - |
1548 -- |
1549 *- |
1550 -- |
1551 - |
1552 - |
1553 -- |
1554 *- |
1555 -- |
1556 - || <- one step (one sample) delay between 10 1 and 11 1
1557 - ||
1558 --|
1559 *-
1560 --
1561 -
1562 -
1563 --
1564 *-
1565 --
1566 -
1567 -
1568 --
1569 */
1570
advance_eg(void)1571 static void advance_eg(void)
1572 {
1573 YM2151Operator *op;
1574 unsigned int i;
1575
1576
1577
1578 PSG->eg_timer += PSG->eg_timer_add;
1579
1580 while (PSG->eg_timer >= PSG->eg_timer_overflow)
1581 {
1582 PSG->eg_timer -= PSG->eg_timer_overflow;
1583
1584 PSG->eg_cnt++;
1585
1586 /* envelope generator */
1587 op = &PSG->oper[0]; /* CH 0 M1 */
1588 i = 32;
1589 do
1590 {
1591 switch(op->state)
1592 {
1593 case EG_ATT: /* attack phase */
1594 if ( !(PSG->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
1595 {
1596 op->volume += (~op->volume *
1597 (eg_inc[op->eg_sel_ar + ((PSG->eg_cnt>>op->eg_sh_ar)&7)])
1598 ) >>4;
1599
1600 if (op->volume <= MIN_ATT_INDEX)
1601 {
1602 op->volume = MIN_ATT_INDEX;
1603 op->state = EG_DEC;
1604 }
1605
1606 }
1607 break;
1608
1609 case EG_DEC: /* decay phase */
1610 if ( !(PSG->eg_cnt & ((1<<op->eg_sh_d1r)-1) ) )
1611 {
1612 op->volume += eg_inc[op->eg_sel_d1r + ((PSG->eg_cnt>>op->eg_sh_d1r)&7)];
1613
1614 if ( (UInt32)op->volume >= op->d1l )
1615 op->state = EG_SUS;
1616
1617 }
1618 break;
1619
1620 case EG_SUS: /* sustain phase */
1621 if ( !(PSG->eg_cnt & ((1<<op->eg_sh_d2r)-1) ) )
1622 {
1623 op->volume += eg_inc[op->eg_sel_d2r + ((PSG->eg_cnt>>op->eg_sh_d2r)&7)];
1624
1625 if ( op->volume >= MAX_ATT_INDEX )
1626 {
1627 op->volume = MAX_ATT_INDEX;
1628 op->state = EG_OFF;
1629 }
1630
1631 }
1632 break;
1633
1634 case EG_REL: /* release phase */
1635 if ( !(PSG->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
1636 {
1637 op->volume += eg_inc[op->eg_sel_rr + ((PSG->eg_cnt>>op->eg_sh_rr)&7)];
1638
1639 if ( op->volume >= MAX_ATT_INDEX )
1640 {
1641 op->volume = MAX_ATT_INDEX;
1642 op->state = EG_OFF;
1643 }
1644
1645 }
1646 break;
1647 }
1648 op++;
1649 i--;
1650 }while (i);
1651 }
1652 }
1653
1654
advance(void)1655 static void advance(void)
1656 {
1657 YM2151Operator *op;
1658 unsigned int i;
1659 int a,p;
1660
1661 /* LFO */
1662 if (PSG->test&2)
1663 PSG->lfo_phase = 0;
1664 else
1665 {
1666 PSG->lfo_timer += PSG->lfo_timer_add;
1667 if (PSG->lfo_timer >= PSG->lfo_overflow)
1668 {
1669 PSG->lfo_timer -= PSG->lfo_overflow;
1670 PSG->lfo_counter += PSG->lfo_counter_add;
1671 PSG->lfo_phase += (PSG->lfo_counter>>4);
1672 PSG->lfo_phase &= 255;
1673 PSG->lfo_counter &= 15;
1674 }
1675 }
1676
1677 i = PSG->lfo_phase;
1678 /* calculate LFO AM and PM waveform value (all verified on real chip, except for noise algorithm which is impossible to analyse)*/
1679 switch (PSG->lfo_wsel)
1680 {
1681 case 0:
1682 /* saw */
1683 /* AM: 255 down to 0 */
1684 /* PM: 0 to 127, -127 to 0 (at PMD=127: LFP = 0 to 126, -126 to 0) */
1685 a = 255 - i;
1686 if (i<128)
1687 p = i;
1688 else
1689 p = i - 255;
1690 break;
1691 case 1:
1692 /* square */
1693 /* AM: 255, 0 */
1694 /* PM: 128,-128 (LFP = exactly +PMD, -PMD) */
1695 if (i<128){
1696 a = 255;
1697 p = 128;
1698 }else{
1699 a = 0;
1700 p = -128;
1701 }
1702 break;
1703 case 2:
1704 /* triangle */
1705 /* AM: 255 down to 1 step -2; 0 up to 254 step +2 */
1706 /* PM: 0 to 126 step +2, 127 to 1 step -2, 0 to -126 step -2, -127 to -1 step +2*/
1707 if (i<128)
1708 a = 255 - (i*2);
1709 else
1710 a = (i*2) - 256;
1711
1712 if (i<64) /* i = 0..63 */
1713 p = i*2; /* 0 to 126 step +2 */
1714 else if (i<128) /* i = 64..127 */
1715 p = 255 - i*2; /* 127 to 1 step -2 */
1716 else if (i<192) /* i = 128..191 */
1717 p = 256 - i*2; /* 0 to -126 step -2*/
1718 else /* i = 192..255 */
1719 p = i*2 - 511; /*-127 to -1 step +2*/
1720 break;
1721 case 3:
1722 default: /*keep the compiler happy*/
1723 /* random */
1724 /* the real algorithm is unknown !!!
1725 We just use a snapshot of data from real chip */
1726
1727 /* AM: range 0 to 255 */
1728 /* PM: range -128 to 127 */
1729
1730 a = lfo_noise_waveform[i];
1731 p = a-128;
1732 break;
1733 }
1734 PSG->lfa = a * PSG->amd / 128;
1735 PSG->lfp = p * PSG->pmd / 128;
1736
1737
1738 /* The Noise Generator of the YM2151 is 17-bit shift register.
1739 * Input to the bit16 is negated (bit0 XOR bit3) (EXNOR).
1740 * Output of the register is negated (bit0 XOR bit3).
1741 * Simply use bit16 as the noise output.
1742 */
1743 PSG->noise_p += PSG->noise_f;
1744 i = (PSG->noise_p>>16); /* number of events (shifts of the shift register) */
1745 PSG->noise_p &= 0xffff;
1746 while (i)
1747 {
1748 UInt32 j;
1749 j = ( (PSG->noise_rng ^ (PSG->noise_rng>>3) ) & 1) ^ 1;
1750 PSG->noise_rng = (j<<16) | (PSG->noise_rng>>1);
1751 i--;
1752 }
1753
1754
1755 /* phase generator */
1756 op = &PSG->oper[0]; /* CH 0 M1 */
1757 i = 8;
1758 do
1759 {
1760 if (op->pms) /* only when phase modulation from LFO is enabled for this channel */
1761 {
1762 Int32 mod_ind = PSG->lfp; /* -128..+127 (8bits signed) */
1763 if (op->pms < 6)
1764 mod_ind >>= (6 - op->pms);
1765 else
1766 mod_ind <<= (op->pms - 5);
1767
1768 if (mod_ind)
1769 {
1770 UInt32 kc_channel = op->kc_i + mod_ind;
1771 (op+0)->phase += ( (PSG->freq[ kc_channel + (op+0)->dt2 ] + (op+0)->dt1) * (op+0)->mul ) >> 1;
1772 (op+1)->phase += ( (PSG->freq[ kc_channel + (op+1)->dt2 ] + (op+1)->dt1) * (op+1)->mul ) >> 1;
1773 (op+2)->phase += ( (PSG->freq[ kc_channel + (op+2)->dt2 ] + (op+2)->dt1) * (op+2)->mul ) >> 1;
1774 (op+3)->phase += ( (PSG->freq[ kc_channel + (op+3)->dt2 ] + (op+3)->dt1) * (op+3)->mul ) >> 1;
1775 }
1776 else /* phase modulation from LFO is equal to zero */
1777 {
1778 (op+0)->phase += (op+0)->freq;
1779 (op+1)->phase += (op+1)->freq;
1780 (op+2)->phase += (op+2)->freq;
1781 (op+3)->phase += (op+3)->freq;
1782 }
1783 }
1784 else /* phase modulation from LFO is disabled */
1785 {
1786 (op+0)->phase += (op+0)->freq;
1787 (op+1)->phase += (op+1)->freq;
1788 (op+2)->phase += (op+2)->freq;
1789 (op+3)->phase += (op+3)->freq;
1790 }
1791
1792 op+=4;
1793 i--;
1794 }while (i);
1795
1796
1797 /* CSM is calculated *after* the phase generator calculations (verified on real chip)
1798 * CSM keyon line seems to be ORed with the KO line inside of the chip.
1799 * The result is that it only works when KO (register 0x08) is off, ie. 0
1800 *
1801 * Interesting effect is that when timer A is set to 1023, the KEY ON happens
1802 * on every sample, so there is no KEY OFF at all - the result is that
1803 * the sound played is the same as after normal KEY ON.
1804 */
1805
1806 if (PSG->csm_req) /* CSM KEYON/KEYOFF seqeunce request */
1807 {
1808 if (PSG->csm_req==2) /* KEY ON */
1809 {
1810 op = &PSG->oper[0]; /* CH 0 M1 */
1811 i = 32;
1812 do
1813 {
1814 KEY_ON(op, 2);
1815 op++;
1816 i--;
1817 }while (i);
1818 PSG->csm_req = 1;
1819 }
1820 else /* KEY OFF */
1821 {
1822 op = &PSG->oper[0]; /* CH 0 M1 */
1823 i = 32;
1824 do
1825 {
1826 KEY_OFF(op,~2);
1827 op++;
1828 i--;
1829 }while (i);
1830 PSG->csm_req = 0;
1831 }
1832 }
1833 }
1834
1835
1836
1837 /* Generate samples for one of the YM2151's
1838 *
1839 * 'num' is the number of virtual YM2151
1840 * '**buffers' is table of pointers to the buffers: left and right
1841 * 'length' is the number of samples that should be generated
1842 */
YM2151UpdateOne(MameYm2151 * chip,Int16 * bufL,Int16 * bufR,int length)1843 void YM2151UpdateOne(MameYm2151* chip, Int16* bufL, Int16* bufR, int length)
1844 {
1845 int i;
1846 signed int outl,outr;
1847
1848 PSG = chip;
1849
1850 for (i=0; i<length; i++)
1851 {
1852 advance_eg();
1853
1854 chip->chanout[0] = 0;
1855 chip->chanout[1] = 0;
1856 chip->chanout[2] = 0;
1857 chip->chanout[3] = 0;
1858 chip->chanout[4] = 0;
1859 chip->chanout[5] = 0;
1860 chip->chanout[6] = 0;
1861 chip->chanout[7] = 0;
1862
1863 chan_calc(chip, 0);
1864 chan_calc(chip, 1);
1865 chan_calc(chip, 2);
1866 chan_calc(chip, 3);
1867 chan_calc(chip, 4);
1868 chan_calc(chip, 5);
1869 chan_calc(chip, 6);
1870 chan7_calc(chip);
1871
1872 outl = chip->chanout[0] & PSG->pan[0];
1873 outr = chip->chanout[0] & PSG->pan[1];
1874 outl += (chip->chanout[1] & PSG->pan[2]);
1875 outr += (chip->chanout[1] & PSG->pan[3]);
1876 outl += (chip->chanout[2] & PSG->pan[4]);
1877 outr += (chip->chanout[2] & PSG->pan[5]);
1878 outl += (chip->chanout[3] & PSG->pan[6]);
1879 outr += (chip->chanout[3] & PSG->pan[7]);
1880 outl += (chip->chanout[4] & PSG->pan[8]);
1881 outr += (chip->chanout[4] & PSG->pan[9]);
1882 outl += (chip->chanout[5] & PSG->pan[10]);
1883 outr += (chip->chanout[5] & PSG->pan[11]);
1884 outl += (chip->chanout[6] & PSG->pan[12]);
1885 outr += (chip->chanout[6] & PSG->pan[13]);
1886 outl += (chip->chanout[7] & PSG->pan[14]);
1887 outr += (chip->chanout[7] & PSG->pan[15]);
1888
1889 outl >>= FINAL_SH;
1890 outr >>= FINAL_SH;
1891 if (outl > MAXOUT) outl = MAXOUT;
1892 else if (outl < MINOUT) outl = MINOUT;
1893 if (outr > MAXOUT) outr = MAXOUT;
1894 else if (outr < MINOUT) outr = MINOUT;
1895 ((Int16*)bufL)[i] = (Int16)outl;
1896 ((Int16*)bufR)[i] = (Int16)outr;
1897
1898 advance();
1899 }
1900 }
1901
1902
YM2151LoadState(MameYm2151 * chip)1903 void YM2151LoadState(MameYm2151* chip)
1904 {
1905 SaveState* state = saveStateOpenForRead("ym2151_core");
1906 char tag[32];
1907 int i;
1908 int tmp;
1909
1910 chip->eg_cnt = saveStateGet(state, "eg_cnt", 0);
1911 chip->eg_timer = saveStateGet(state, "eg_timer", 0);
1912 chip->eg_timer_add = saveStateGet(state, "eg_timer_add", 0);
1913 chip->eg_timer_overflow = saveStateGet(state, "eg_timer_overflow", 0);
1914 chip->lfo_phase = saveStateGet(state, "lfo_phase", 0);
1915 chip->lfo_timer = saveStateGet(state, "lfo_timer", 0);
1916 chip->lfo_timer_add = saveStateGet(state, "lfo_timer_add", 0);
1917 chip->lfo_overflow = saveStateGet(state, "lfo_overflow", 0);
1918 chip->lfo_counter = saveStateGet(state, "lfo_counter", 0);
1919 chip->lfo_counter_add = saveStateGet(state, "lfo_counter_add", 0);
1920 chip->lfo_wsel = (UInt8)saveStateGet(state, "lfo_wsel", 0);
1921 chip->amd = (UInt8)saveStateGet(state, "amd", 0);
1922 chip->pmd = (UInt8)saveStateGet(state, "pmd", 0);
1923 chip->lfa = saveStateGet(state, "lfa", 0);
1924 chip->lfp = saveStateGet(state, "lfp", 0);
1925 chip->test = (UInt8)saveStateGet(state, "test", 0);
1926 chip->ct = (UInt8)saveStateGet(state, "ct", 0);
1927 chip->noise = saveStateGet(state, "noise", 0);
1928 chip->noise_rng = saveStateGet(state, "noise_rng", 0);
1929 chip->noise_p = saveStateGet(state, "noise_p", 0);
1930 chip->noise_f = saveStateGet(state, "noise_f", 0);
1931 chip->csm_req = saveStateGet(state, "csm_req", 0);
1932 chip->irq_enable = saveStateGet(state, "irq_enable", 0);
1933 chip->status = saveStateGet(state, "status", 0);
1934 chip->timer_A_val = (UInt16)saveStateGet(state, "timer_A_val", 0);
1935 chip->m2 = saveStateGet(state, "m2", 0);
1936 chip->c1 = saveStateGet(state, "c1", 0);
1937 chip->c2 = saveStateGet(state, "c2", 0);
1938 chip->mem = saveStateGet(state, "mem", 0);
1939
1940 for (i = 0; i < sizeof(chip->pan) / sizeof(chip->pan[0]); i++) {
1941 sprintf(tag, "pan%d", i);
1942 chip->pan[i] = saveStateGet(state, tag, 0);
1943 }
1944
1945 for (i = 0; i < sizeof(chip->connect) / sizeof(chip->connect[0]); i++) {
1946 sprintf(tag, "connect%d", i);
1947 chip->connect[i] = (UInt8)saveStateGet(state, tag, 0);
1948 }
1949
1950 for (i = 0; i < sizeof(chip->chanout) / sizeof(chip->chanout[0]); i++) {
1951 sprintf(tag, "chanout%d", i);
1952 chip->chanout[i] = (UInt8)saveStateGet(state, tag, 0);
1953 }
1954
1955 for (i = 0; i < sizeof(chip->oper) / sizeof(chip->oper[0]); i++) {
1956 sprintf(tag, "phase%d", i);
1957 chip->oper[i].phase = saveStateGet(state, tag, 0);
1958
1959 sprintf(tag, "freq%d", i);
1960 chip->oper[i].freq = saveStateGet(state, tag, 0);
1961
1962 sprintf(tag, "dt1%d", i);
1963 chip->oper[i].dt1 = saveStateGet(state, tag, 0);
1964
1965 sprintf(tag, "mul%d", i);
1966 chip->oper[i].mul = saveStateGet(state, tag, 0);
1967
1968 sprintf(tag, "dt1_i%d", i);
1969 chip->oper[i].dt1_i = saveStateGet(state, tag, 0);
1970
1971 sprintf(tag, "dt2%d", i);
1972 chip->oper[i].dt2 = saveStateGet(state, tag, 0);
1973
1974 sprintf(tag, "mem_value%d", i);
1975 chip->oper[i].mem_value = saveStateGet(state, tag, 0);
1976
1977 sprintf(tag, "fb_shift%d", i);
1978 chip->oper[i].fb_shift = saveStateGet(state, tag, 0);
1979
1980 sprintf(tag, "fb_out_curr%d", i);
1981 chip->oper[i].fb_out_curr = saveStateGet(state, tag, 0);
1982
1983 sprintf(tag, "fb_out_prev%d", i);
1984 chip->oper[i].fb_out_prev = saveStateGet(state, tag, 0);
1985
1986 sprintf(tag, "kc%d", i);
1987 chip->oper[i].kc = saveStateGet(state, tag, 0);
1988
1989 sprintf(tag, "kc_i%d", i);
1990 chip->oper[i].kc_i = saveStateGet(state, tag, 0);
1991
1992 sprintf(tag, "pms%d", i);
1993 chip->oper[i].pms = saveStateGet(state, tag, 0);
1994
1995 sprintf(tag, "ams%d", i);
1996 chip->oper[i].ams = saveStateGet(state, tag, 0);
1997
1998 sprintf(tag, "AMmask%d", i);
1999 chip->oper[i].AMmask = saveStateGet(state, tag, 0);
2000
2001 sprintf(tag, "state%d", i);
2002 chip->oper[i].state = saveStateGet(state, tag, 0);
2003
2004 sprintf(tag, "eg_sh_ar%d", i);
2005 chip->oper[i].eg_sh_ar = (UInt8)saveStateGet(state, tag, 0);
2006
2007 sprintf(tag, "eg_sel_ar%d", i);
2008 chip->oper[i].eg_sel_ar = (UInt8)saveStateGet(state, tag, 0);
2009
2010 sprintf(tag, "tl%d", i);
2011 chip->oper[i].tl = saveStateGet(state, tag, 0);
2012
2013 sprintf(tag, "volume%d", i);
2014 chip->oper[i].volume = saveStateGet(state, tag, 0);
2015
2016 sprintf(tag, "eg_sh_d1r%d", i);
2017 chip->oper[i].eg_sh_d1r = (UInt8)saveStateGet(state, tag, 0);
2018
2019 sprintf(tag, "eg_sel_d1r%d", i);
2020 chip->oper[i].eg_sel_d1r = (UInt8)saveStateGet(state, tag, 0);
2021
2022 sprintf(tag, "d1l%d", i);
2023 chip->oper[i].d1l = saveStateGet(state, tag, 0);
2024
2025 sprintf(tag, "eg_sh_d2r%d", i);
2026 chip->oper[i].eg_sh_d2r = (UInt8)saveStateGet(state, tag, 0);
2027
2028 sprintf(tag, "eg_sel_d2r%d", i);
2029 chip->oper[i].eg_sel_d2r = (UInt8)saveStateGet(state, tag, 0);
2030
2031 sprintf(tag, "eg_sh_rr%d", i);
2032 chip->oper[i].eg_sh_rr = (UInt8)saveStateGet(state, tag, 0);
2033
2034 sprintf(tag, "eg_sel_rr%d", i);
2035 chip->oper[i].eg_sel_rr = (UInt8)saveStateGet(state, tag, 0);
2036
2037 sprintf(tag, "key%d", i);
2038 chip->oper[i].key = saveStateGet(state, tag, 0);
2039
2040 sprintf(tag, "ks%d", i);
2041 chip->oper[i].ks = saveStateGet(state, tag, 0);
2042
2043 sprintf(tag, "ar%d", i);
2044 chip->oper[i].ar = saveStateGet(state, tag, 0);
2045
2046 sprintf(tag, "d1r%d", i);
2047 chip->oper[i].d1r = saveStateGet(state, tag, 0);
2048
2049 sprintf(tag, "d2r%d", i);
2050 chip->oper[i].d2r = saveStateGet(state, tag, 0);
2051
2052 sprintf(tag, "rr%d", i);
2053 chip->oper[i].rr = saveStateGet(state, tag, 0);
2054
2055 sprintf(tag, "connect%d", i);
2056 tmp = saveStateGet(state, tag, -1);
2057 if (tmp < 0) {
2058 chip->oper[i].connect = NULL;
2059 }
2060 else {
2061 chip->oper[i].connect = (int*)chip + tmp;
2062 }
2063
2064 sprintf(tag, "mem_connect%d", i);
2065 tmp = saveStateGet(state, tag, -1);
2066 if (tmp < 0) {
2067 chip->oper[i].mem_connect = NULL;
2068 }
2069 else {
2070 chip->oper[i].mem_connect = (int*)chip + tmp;
2071 }
2072 }
2073
2074 saveStateClose(state);
2075 }
2076
YM2151SaveState(MameYm2151 * chip)2077 void YM2151SaveState(MameYm2151* chip)
2078 {
2079 SaveState* state = saveStateOpenForWrite("ym2151_core");
2080 char tag[32];
2081 int i;
2082
2083 saveStateSet(state, "eg_cnt", chip->eg_cnt);
2084 saveStateSet(state, "eg_timer", chip->eg_timer);
2085 saveStateSet(state, "eg_timer_add", chip->eg_timer_add);
2086 saveStateSet(state, "eg_timer_overflow", chip->eg_timer_overflow);
2087 saveStateSet(state, "lfo_phase", chip->lfo_phase);
2088 saveStateSet(state, "lfo_timer", chip->lfo_timer);
2089 saveStateSet(state, "lfo_timer_add", chip->lfo_timer_add);
2090 saveStateSet(state, "lfo_overflow", chip->lfo_overflow);
2091 saveStateSet(state, "lfo_counter", chip->lfo_counter);
2092 saveStateSet(state, "lfo_counter_add", chip->lfo_counter_add);
2093 saveStateSet(state, "lfo_wsel", chip->lfo_wsel);
2094 saveStateSet(state, "amd", chip->amd);
2095 saveStateSet(state, "pmd", chip->pmd);
2096 saveStateSet(state, "lfa", chip->lfa);
2097 saveStateSet(state, "lfp", chip->lfp);
2098 saveStateSet(state, "test", chip->test);
2099 saveStateSet(state, "ct", chip->ct);
2100 saveStateSet(state, "noise", chip->noise);
2101 saveStateSet(state, "noise_rng", chip->noise_rng);
2102 saveStateSet(state, "noise_p", chip->noise_p);
2103 saveStateSet(state, "noise_f", chip->noise_f);
2104 saveStateSet(state, "csm_req", chip->csm_req);
2105 saveStateSet(state, "irq_enable", chip->irq_enable);
2106 saveStateSet(state, "status", chip->status);
2107 saveStateSet(state, "timer_A_val", chip->timer_A_val);
2108 saveStateSet(state, "m2", chip->m2);
2109 saveStateSet(state, "c1", chip->c1);
2110 saveStateSet(state, "c2", chip->c2);
2111 saveStateSet(state, "mem", chip->mem);
2112
2113 for (i = 0; i < sizeof(chip->pan) / sizeof(chip->pan[0]); i++) {
2114 sprintf(tag, "pan%d", i);
2115 saveStateSet(state, tag, chip->pan[i]);
2116 }
2117
2118 for (i = 0; i < sizeof(chip->connect) / sizeof(chip->connect[0]); i++) {
2119 sprintf(tag, "connect%d", i);
2120 saveStateSet(state, tag, chip->connect[i]);
2121 }
2122
2123 for (i = 0; i < sizeof(chip->chanout) / sizeof(chip->chanout[0]); i++) {
2124 sprintf(tag, "chanout%d", i);
2125 saveStateSet(state, tag, chip->chanout[i]);
2126 }
2127
2128 for (i = 0; i < sizeof(chip->oper) / sizeof(chip->oper[0]); i++) {
2129 sprintf(tag, "phase%d", i);
2130 saveStateSet(state, tag, chip->oper[i].phase);
2131
2132 sprintf(tag, "freq%d", i);
2133 saveStateSet(state, tag, chip->oper[i].freq);
2134
2135 sprintf(tag, "dt1%d", i);
2136 saveStateSet(state, tag, chip->oper[i].dt1);
2137
2138 sprintf(tag, "mul%d", i);
2139 saveStateSet(state, tag, chip->oper[i].mul);
2140
2141 sprintf(tag, "dt1_i%d", i);
2142 saveStateSet(state, tag, chip->oper[i].dt1_i);
2143
2144 sprintf(tag, "dt2%d", i);
2145 saveStateSet(state, tag, chip->oper[i].dt2);
2146
2147 sprintf(tag, "mem_value%d", i);
2148 saveStateSet(state, tag, chip->oper[i].mem_value);
2149
2150 sprintf(tag, "fb_shift%d", i);
2151 saveStateSet(state, tag, chip->oper[i].fb_shift);
2152
2153 sprintf(tag, "fb_out_curr%d", i);
2154 saveStateSet(state, tag, chip->oper[i].fb_out_curr);
2155
2156 sprintf(tag, "fb_out_prev%d", i);
2157 saveStateSet(state, tag, chip->oper[i].fb_out_prev);
2158
2159 sprintf(tag, "kc%d", i);
2160 saveStateSet(state, tag, chip->oper[i].kc);
2161
2162 sprintf(tag, "kc_i%d", i);
2163 saveStateSet(state, tag, chip->oper[i].kc_i);
2164
2165 sprintf(tag, "pms%d", i);
2166 saveStateSet(state, tag, chip->oper[i].pms);
2167
2168 sprintf(tag, "ams%d", i);
2169 saveStateSet(state, tag, chip->oper[i].ams);
2170
2171 sprintf(tag, "AMmask%d", i);
2172 saveStateSet(state, tag, chip->oper[i].AMmask);
2173
2174 sprintf(tag, "state%d", i);
2175 saveStateSet(state, tag, chip->oper[i].state);
2176
2177 sprintf(tag, "eg_sh_ar%d", i);
2178 saveStateSet(state, tag, chip->oper[i].eg_sh_ar);
2179
2180 sprintf(tag, "eg_sel_ar%d", i);
2181 saveStateSet(state, tag, chip->oper[i].eg_sel_ar);
2182
2183 sprintf(tag, "tl%d", i);
2184 saveStateSet(state, tag, chip->oper[i].tl);
2185
2186 sprintf(tag, "volume%d", i);
2187 saveStateSet(state, tag, chip->oper[i].volume);
2188
2189 sprintf(tag, "eg_sh_d1r%d", i);
2190 saveStateSet(state, tag, chip->oper[i].eg_sh_d1r);
2191
2192 sprintf(tag, "eg_sel_d1r%d", i);
2193 saveStateSet(state, tag, chip->oper[i].eg_sel_d1r);
2194
2195 sprintf(tag, "d1l%d", i);
2196 saveStateSet(state, tag, chip->oper[i].d1l);
2197
2198 sprintf(tag, "eg_sh_d2r%d", i);
2199 saveStateSet(state, tag, chip->oper[i].eg_sh_d2r);
2200
2201 sprintf(tag, "eg_sel_d2r%d", i);
2202 saveStateSet(state, tag, chip->oper[i].eg_sel_d2r);
2203
2204 sprintf(tag, "eg_sh_rr%d", i);
2205 saveStateSet(state, tag, chip->oper[i].eg_sh_rr);
2206
2207 sprintf(tag, "eg_sel_rr%d", i);
2208 saveStateSet(state, tag, chip->oper[i].eg_sel_rr);
2209
2210 sprintf(tag, "key%d", i);
2211 saveStateSet(state, tag, chip->oper[i].key);
2212
2213 sprintf(tag, "ks%d", i);
2214 saveStateSet(state, tag, chip->oper[i].ks);
2215
2216 sprintf(tag, "ar%d", i);
2217 saveStateSet(state, tag, chip->oper[i].ar);
2218
2219 sprintf(tag, "d1r%d", i);
2220 saveStateSet(state, tag, chip->oper[i].d1r);
2221
2222 sprintf(tag, "d2r%d", i);
2223 saveStateSet(state, tag, chip->oper[i].d2r);
2224
2225 sprintf(tag, "rr%d", i);
2226 saveStateSet(state, tag, chip->oper[i].rr);
2227
2228 sprintf(tag, "connect%d", i);
2229 if (chip->oper[i].connect != NULL) {
2230 saveStateSet(state, tag, (int*)chip->oper[i].connect - (int*)chip);
2231 }
2232 else {
2233 saveStateSet(state, tag, -1);
2234 }
2235
2236 sprintf(tag, "mem_connect%d", i);
2237 if (chip->oper[i].mem_connect != NULL) {
2238 saveStateSet(state, tag, (int*)chip->oper[i].mem_connect - (int*)chip);
2239 }
2240 else {
2241 saveStateSet(state, tag, -1);
2242 }
2243 }
2244
2245 saveStateClose(state);
2246 }
2247