1 /*
2 Based on MAME sources by R. Belmont, Olivier Galibert, hap
3
4 YMF278B FM + Wave table Synthesizer (OPL4)
5
6 Timer and PCM YMF278B. The FM will be shared with the ymf262, eventually.
7
8 This chip roughly splits the difference between the Sega 315-5560 MultiPCM
9 (Multi32, Model 1/2) and YMF 292-F SCSP (later Model 2, STV, Saturn, Model 3).
10
11 Features as listed in LSI-4MF2782 data sheet:
12 FM Synthesis (same as YMF262)
13 1. Sound generation mode
14 Two-operater mode
15 Generates eighteen voices or fifteen voices plus five rhythm sounds simultaneously
16 Four-operator mode
17 Generates six voices in four-operator mode plus six voices in two-operator mode simultaneously,
18 or generates six voices in four-operator mode plus three voices in two-operator mode plus five
19 rhythm sounds simultaneously
20 2. Eight selectable waveforms
21 3. Stereo output
22 Wave Table Synthesis
23 1. Generates twenty-four voices simultaneously
24 2. 44.1kHz sampling rate for output sound data
25 3. Selectable from 8-bit, 12-bit and 16-bit word lengths for wave data
26 4. Stereo output (16-stage panpot for each voice)
27 Wave Data
28 1. Accepts 32M bit external memory at maximum
29 2. Up to 512 wave tables
30 3. External ROM or SRAM can be connected. With SRAM connected, the CPU can download wave data
31 4. Outputs chip select signals for 1Mbit, 4Mbit, 8Mbit or 16Mbit memory
32 5. Can be directly connected to the Yamaha YRW801 (Wave data ROM)
33 Features of YRW801 as listed in LSI 4RW801A2
34 Built-in wave data of tones which comply with GM system Level 1
35 Melody tone ....... 128 tones
36 Percussion tone ... 47 tones
37 16Mbit capacity (2,097,152word x 8)
38
39 By R. Belmont and O. Galibert.
40
41 Copyright R. Belmont and O. Galibert.
42
43 This software is dual-licensed: it may be used in MAME and properly licensed
44 MAME derivatives under the terms of the MAME license. For use outside of
45 MAME and properly licensed derivatives, it is available under the
46 terms of the GNU Lesser General Public License (LGPL), version 2.1.
47 You may read the LGPL at http://www.gnu.org/licenses/lgpl.html
48
49 Changelog:
50 Sep. 8, 2002 - fixed ymf278b_compute_rate when octave is negative (RB)
51 Dec. 11, 2002 - added ability to set non-standard clock rates (RB)
52 fixed envelope target for release (fixes missing
53 instruments in hotdebut).
54 Thanks to Team Japump! for MP3s from a real PCB.
55 fixed crash if MAME is run with no sound.
56 June 4, 2003 - Changed to dual-license with LGPL for use in openMSX.
57 openMSX contributed a bugfix where looped samples were
58 not being addressed properly, causing pitch fluctuation.
59
60 With further improvements over the years by MAME team.
61
62 TODO:
63 - accurate timing of envelopes
64 - LFO (vibrato, tremolo)
65 - integrate YMF262 (used by Fuuki games, not used by Psikyo and Metro games)
66 - able to hook up "Moonsound", supporting mixed ROM+RAM (for MSX driver in MESS)
67 */
68
69 #include <math.h>
70 #include "driver.h"
71 #include "ymf278b.h"
72 #include "state.h"
73
74 #define YMF278B_STD_CLOCK (33868800) /* standard clock for OPL4 */
75
76 #define LOG(x) logerror x;
77
78 typedef struct
79 {
80 INT16 wave; /* wavetable number */
81 INT16 F_NUMBER; /* frequency */
82 INT8 octave; /* octave */
83 INT8 preverb; /* pseudo-reverb */
84 INT8 DAMP; /* damping */
85 INT8 CH; /* output channel */
86 INT8 LD; /* level direct */
87 INT8 TL; /* total level */
88 INT8 pan; /* panpot */
89 INT8 LFO; /* LFO */
90 INT8 VIB; /* vibrato */
91 INT8 AM; /* tremolo */
92
93 INT8 AR; /* attack rate */
94 INT8 D1R; /* decay 1 rate */
95 INT8 DL; /* decay level */
96 INT8 D2R; /* decay 2 rate */
97 INT8 RC; /* rate correction */
98 INT8 RR; /* release rate */
99
100 UINT32 step; /* fixed-point frequency step */
101 UINT64 stepptr; /* fixed-point pointer into the sample */
102
103 INT8 active; /* channel is playing */
104 INT8 KEY_ON; /* slot keyed on */
105 INT8 bits; /* width of the samples */
106 UINT32 startaddr;
107 UINT32 loopaddr;
108 UINT32 endaddr;
109
110 INT32 env_step;
111 UINT32 env_vol;
112 UINT32 env_vol_step;
113 UINT32 env_vol_lim;
114 INT8 env_preverb;
115
116 INT32 num; /* slot number (for debug only) */
117 } YMF278BSlot;
118
119 // internal state
120 UINT8 m_pcmregs[256];
121 YMF278BSlot m_slots[24];
122 INT8 m_wavetblhdr;
123 INT8 m_memmode;
124 INT32 m_memadr;
125
126 UINT8 m_status_busy, m_status_ld;
127 void *m_timer_busy;
128 void *m_timer_ld;
129 UINT8 m_exp;
130
131 INT32 m_fm_l, m_fm_r;
132 INT32 m_pcm_l, m_pcm_r;
133
134 //attotime m_timer_base;
135 UINT8 m_timer_a_count, m_timer_b_count;
136 UINT8 m_enable, m_current_irq;
137 int m_irq_line;
138
139 UINT8 m_port_C, m_port_A, m_port_B, m_lastport;
140
141 // precomputed tables
142 UINT32 m_lut_ar[64]; // attack rate
143 UINT32 m_lut_dr[64]; // decay rate
144 INT32 m_volume[256*4]; // precalculated attenuation values with some margin for envelope and pan levels
145 int m_pan_left[16],m_pan_right[16]; // pan volume offsets
146 INT32 m_mix_level[8];
147
148 void *m_timer_a, *m_timer_b;
149 const UINT8 *m_rom;
150 UINT32 m_romsize;
151 int m_clock;
152
153 //sound_stream * m_stream;
154 INT32 *m_mix_buffer;
155 //devcb2_write_line m_irq_handler;
156 void (*m_irq_handler)(INT32, INT32);
157 void (*timer_callback)(INT32, INT32, double);
158 float m_clock_ratio;
159 static int ymf278b_chip_in_reset = 0;
160
write_memory(UINT32 offset,UINT8 data)161 void write_memory(UINT32 offset, UINT8 data)
162 {
163 LOG(("YMF278B: Memory write %02x to %x\n", data, offset));
164 }
165
read_memory(UINT32 offset)166 UINT8 read_memory(UINT32 offset)
167 {
168 if (offset >= m_romsize)
169 {
170 // LOG(("YMF278B: Memory read overflow %x\n", offset));
171 return 0xff;
172 }
173 return m_rom[offset];
174 }
175
176
177 /**************************************************************************/
178
compute_rate(YMF278BSlot * slot,int val)179 static int compute_rate(YMF278BSlot *slot, int val)
180 {
181 int res, oct;
182
183 if(val == 0)
184 return 0;
185 if(val == 15)
186 return 63;
187 if(slot->RC != 15)
188 {
189 oct = slot->octave;
190 if (oct & 8)
191 oct |= -8;
192
193 res = (oct+slot->RC)*2 + (slot->F_NUMBER & 0x200 ? 1 : 0) + val*4;
194 }
195 else
196 res = val * 4;
197 if(res < 0)
198 res = 0;
199 else if(res > 63)
200 res = 63;
201
202 return res;
203 }
204
compute_decay_env_vol_step(YMF278BSlot * slot,int val)205 static UINT32 compute_decay_env_vol_step(YMF278BSlot *slot, int val)
206 {
207 int rate;
208 UINT32 res;
209
210 // rate override with damping/pseudo reverb
211 if (slot->DAMP)
212 rate = 56; // approximate, datasheet says it's slightly curved though
213 else if (slot->preverb && slot->env_vol > ((6*8)<<23))
214 {
215 // pseudo reverb starts at -18dB (6 in voltab)
216 slot->env_preverb = 1;
217 rate = 5;
218 }
219 else
220 rate = compute_rate(slot, val);
221
222 if (rate < 4)
223 res = 0;
224 else
225 res = (256U<<23) / m_lut_dr[rate];
226
227 return res;
228 }
229
compute_freq_step(YMF278BSlot * slot)230 static void compute_freq_step(YMF278BSlot *slot)
231 {
232 UINT32 step;
233 int oct;
234
235 oct = slot->octave;
236 if(oct & 8)
237 oct |= -8;
238
239 step = (slot->F_NUMBER | 1024) << (oct + 8);
240 slot->step = step >> 3;
241 }
242
compute_envelope(YMF278BSlot * slot)243 static void compute_envelope(YMF278BSlot *slot)
244 {
245 switch (slot->env_step)
246 {
247 // Attack
248 case 0:
249 {
250 // Attack
251 int rate = compute_rate(slot, slot->AR);
252 slot->env_vol = 256U<<23;
253 slot->env_vol_lim = (256U<<23) - 1;
254
255 if (rate==63)
256 {
257 // immediate
258 LOG(("YMF278B: Attack skipped - "));
259 slot->env_vol = 0;
260 slot->env_step++;
261 compute_envelope(slot);
262 }
263 else if (rate<4)
264 {
265 slot->env_vol_step = 0;
266 }
267 else
268 {
269 // NOTE: attack rate is linear here, but datasheet shows a smooth curve
270 LOG(("YMF278B: Attack, val = %d, rate = %d, delay = %g\n", slot->AR, rate, m_lut_ar[rate]*1000.0));
271 slot->env_vol_step = ~((256U<<23) / m_lut_ar[rate]);
272 }
273
274 break;
275 }
276
277 // Decay 1
278 case 1:
279 if(slot->DL)
280 {
281 LOG(("YMF278B: Decay step 1, dl=%d, val = %d rate = %d, delay = %g, PRVB = %d, DAMP = %d\n", slot->DL, slot->D1R, compute_rate(slot, slot->D1R), m_lut_dr[compute_rate(slot, slot->D1R)]*1000.0, slot->preverb, slot->DAMP));
282 slot->env_vol_step = compute_decay_env_vol_step(slot, slot->D1R);
283 slot->env_vol_lim = (slot->DL*8)<<23;
284 }
285 else
286 {
287 LOG(("YMF278B: Decay 1 skipped - "));
288 slot->env_step++;
289 compute_envelope(slot);
290 }
291
292 break;
293
294 // Decay 2
295 case 2:
296 LOG(("YMF278B: Decay step 2, val = %d, rate = %d, delay = %g, , PRVB = %d, DAMP = %d, current vol = %d\n", slot->D2R, compute_rate(slot, slot->D2R), m_lut_dr[compute_rate(slot, slot->D2R)]*1000.0, slot->preverb, slot->DAMP, slot->env_vol >> 23));
297 slot->env_vol_step = compute_decay_env_vol_step(slot, slot->D2R);
298 slot->env_vol_lim = 256U<<23;
299 break;
300
301 // Decay 2 reached -96dB
302 case 3:
303 LOG(("YMF278B: Voice cleared because of decay 2\n"));
304 slot->env_vol = 256U<<23;
305 slot->env_vol_step = 0;
306 slot->env_vol_lim = 0;
307 slot->active = 0;
308 break;
309
310 // Release
311 case 4:
312 LOG(("YMF278B: Release, val = %d, rate = %d, delay = %g, PRVB = %d, DAMP = %d\n", slot->RR, compute_rate(slot, slot->RR), m_lut_dr[compute_rate(slot, slot->RR)]*1000.0, slot->preverb, slot->DAMP));
313 slot->env_vol_step = compute_decay_env_vol_step(slot, slot->RR);
314 slot->env_vol_lim = 256U<<23;
315 break;
316
317 // Release reached -96dB
318 case 5:
319 LOG(("YMF278B: Release ends\n"));
320 slot->env_vol = 256U<<23;
321 slot->env_vol_step = 0;
322 slot->env_vol_lim = 0;
323 slot->active = 0;
324 break;
325
326 default: break;
327 }
328 }
329
330 //-------------------------------------------------
331 // sound_stream_update - handle a stream update
332 //-------------------------------------------------
333
ymf278b_pcm_update(int num,INT16 ** outputs,int samples)334 void ymf278b_pcm_update(int num, INT16 **outputs, int samples)
335 {
336 int i, j;
337 YMF278BSlot *slot = NULL;
338 INT16 sample = 0;
339 INT32 *mixp;
340 INT32 vl, vr;
341
342 memset(m_mix_buffer, 0, sizeof(m_mix_buffer[0])*samples*2);
343
344 for (i = 0; i < 24; i++)
345 {
346 slot = &m_slots[i];
347
348 if (slot->active)
349 {
350 mixp = m_mix_buffer;
351
352 for (j = 0; j < samples; j++)
353 {
354 if (slot->stepptr >= slot->endaddr)
355 {
356 slot->stepptr = slot->stepptr - slot->endaddr + slot->loopaddr;
357
358 // NOTE: loop overflow is still possible here if (slot->stepptr >= slot->endaddr)
359 // This glitch may be (ab)used to your advantage to create pseudorandom noise.
360 }
361
362 switch (slot->bits)
363 {
364 // 8 bit
365 case 0:
366 sample = read_memory(slot->startaddr + (slot->stepptr>>16))<<8;
367 break;
368
369 // 12 bit
370 case 1:
371 if (slot->stepptr & 0x10000)
372 sample = read_memory(slot->startaddr + (slot->stepptr>>17)*3+2)<<8 |
373 (read_memory(slot->startaddr + (slot->stepptr>>17)*3+1) << 4 & 0xf0);
374 else
375 sample = read_memory(slot->startaddr + (slot->stepptr>>17)*3)<<8 |
376 (read_memory(slot->startaddr + (slot->stepptr>>17)*3+1) & 0xf0);
377 break;
378
379 // 16 bit
380 case 2:
381 sample = read_memory(slot->startaddr + ((slot->stepptr>>16)*2))<<8 |
382 read_memory(slot->startaddr + ((slot->stepptr>>16)*2)+1);
383 break;
384
385 // ?? bit, effect is unknown, datasheet says it's prohibited
386 case 3:
387 sample = 0;
388 break;
389 }
390
391 *mixp++ += (sample * m_volume[slot->TL+m_pan_left [slot->pan]+(slot->env_vol>>23)])>>17;
392 *mixp++ += (sample * m_volume[slot->TL+m_pan_right[slot->pan]+(slot->env_vol>>23)])>>17;
393
394 // update frequency
395 slot->stepptr += slot->step;
396
397 // update envelope
398 slot->env_vol += slot->env_vol_step;
399 if (((INT32)(slot->env_vol - slot->env_vol_lim)) >= 0)
400 {
401 slot->env_step++;
402 compute_envelope(slot);
403 }
404 else if (slot->preverb && !slot->env_preverb && slot->env_step && slot->env_vol > ((6*8)<<23))
405 compute_envelope(slot);
406 }
407 }
408 }
409
410 mixp = m_mix_buffer;
411 vl = m_mix_level[m_pcm_l];
412 vr = m_mix_level[m_pcm_r];
413 for (i = 0; i < samples; i++)
414 {
415 outputs[0][i] = (*mixp++ * vl) >> 16;
416 outputs[1][i] = (*mixp++ * vr) >> 16;
417 }
418 }
419
irq_check()420 static void irq_check()
421 {
422 int prev_line = m_irq_line;
423 m_irq_line = m_current_irq ? 1 : 0;
424 if (m_irq_line != prev_line && m_irq_handler && !ymf278b_chip_in_reset)
425 m_irq_handler(0, m_irq_line);
426 }
427
ymf278b_timer_over(int num,int timer)428 int ymf278b_timer_over(int num, int timer)
429 {
430 if(!(m_enable & (0x20 << timer)))
431 {
432 m_current_irq |= (0x20 << timer);
433 irq_check();
434 }
435
436 return 0;
437 }
438
ymf278b_timer_a_reset(int num)439 static void ymf278b_timer_a_reset(int num)
440 {
441 if(m_enable & 1)
442 {
443 double period = (256-m_timer_a_count) * 80.8 * m_clock_ratio;
444 timer_callback(num, 0, period);
445 }
446 else
447 timer_callback(num, 0, 0);
448 }
449
ymf278b_timer_b_reset(int num)450 static void ymf278b_timer_b_reset(int num)
451 {
452 if(m_enable & 2)
453 {
454 double period = (256-m_timer_b_count) * 323.1 * m_clock_ratio;
455 timer_callback(num, 1, period);
456 }
457 else
458 timer_callback(num, 1, 0);
459 }
460
461
462 /*
463 enum
464 {
465 TIMER_A = 0,
466 TIMER_B,
467 TIMER_BUSY_CLEAR,
468 TIMER_LD_CLEAR
469 };
470
471 void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
472 {
473 switch(id)
474 {
475 case TIMER_A:
476 if(!(m_enable & 0x40))
477 {
478 m_current_irq |= 0x40;
479 irq_check();
480 }
481 break;
482
483 case TIMER_B:
484 if(!(m_enable & 0x20))
485 {
486 m_current_irq |= 0x20;
487 irq_check();
488 }
489 break;
490
491 case TIMER_BUSY_CLEAR:
492 m_status_busy = 0;
493 break;
494
495 case TIMER_LD_CLEAR:
496 m_status_ld = 0;
497 break;
498 }
499 }*/
500
501
502 /**************************************************************************/
503
A_w(int num,UINT8 reg,UINT8 data)504 static void A_w(int num, UINT8 reg, UINT8 data)
505 {
506 // FM register array 0 (compatible with YMF262)
507 switch(reg)
508 {
509 // LSI TEST
510 case 0x00:
511 case 0x01:
512 break;
513
514 // timer a count
515 case 0x02:
516 //if (data != m_timer_a_count) - this breaks FBA if uncommented
517 {
518 m_timer_a_count = data;
519 if (!ymf278b_chip_in_reset)
520 ymf278b_timer_a_reset(num);
521
522 }
523 break;
524
525 // timer b count
526 case 0x03:
527 //if (data != m_timer_b_count) - same here.
528 {
529 m_timer_b_count = data;
530 if (!ymf278b_chip_in_reset)
531 ymf278b_timer_b_reset(num);
532 }
533 break;
534
535 // timer control
536 case 0x04:
537 if(data & 0x80)
538 m_current_irq = 0;
539 else
540 {
541 // reset timers
542 UINT8 old_enable = m_enable;
543 m_enable = data;
544 m_current_irq &= ~data;
545 if((old_enable ^ data) & 1 && !ymf278b_chip_in_reset)
546 ymf278b_timer_a_reset(num);
547 if((old_enable ^ data) & 2 && !ymf278b_chip_in_reset)
548 ymf278b_timer_b_reset(num);
549 }
550 irq_check();
551 break;
552
553 default:
554 LOG(("YMF278B: Port A write %02x, %02x\n", reg, data));
555 break;
556 }
557 }
558
B_w(int num,UINT8 reg,UINT8 data)559 static void B_w(int num, UINT8 reg, UINT8 data)
560 {
561 // FM register array 1 (compatible with YMF262)
562 switch(reg)
563 {
564 // LSI TEST
565 case 0x00:
566 case 0x01:
567 break;
568
569 // expansion register (NEW2/NEW)
570 case 0x05:
571 m_exp = data;
572 break;
573
574 default:
575 LOG(("YMF278B: Port B write %02x, %02x\n", reg, data));
576 break;
577 }
578 }
579
retrigger_note(YMF278BSlot * slot)580 static void retrigger_note(YMF278BSlot *slot)
581 {
582 // activate channel
583 if (slot->octave != 8)
584 slot->active = 1;
585
586 // reset sample pos and go to attack stage
587 slot->stepptr = 0;
588 slot->env_step = 0;
589 slot->env_preverb = 0;
590
591 compute_freq_step(slot);
592 compute_envelope(slot);
593 }
594
C_w(int num,UINT8 reg,UINT8 data)595 static void C_w(int num, UINT8 reg, UINT8 data)
596 {
597 // Handle slot registers specifically
598 if (reg >= 0x08 && reg <= 0xf7)
599 {
600 YMF278BSlot *slot = NULL;
601 int snum;
602 snum = (reg-8) % 24;
603 slot = &m_slots[snum];
604 switch((reg-8) / 24)
605 {
606 case 0:
607 {
608 //attotime period;
609 UINT32 offset;
610 UINT8 p[12];
611 int i;
612
613 slot->wave &= 0x100;
614 slot->wave |= data;
615
616 // load wavetable header
617 if(slot->wave < 384 || !m_wavetblhdr)
618 offset = slot->wave * 12;
619 else
620 offset = m_wavetblhdr*0x80000 + (slot->wave - 384) * 12;
621 for (i = 0; i < 12; i++)
622 p[i] = read_memory(offset+i);
623
624 slot->bits = (p[0]&0xc0)>>6;
625 slot->startaddr = (p[2] | (p[1]<<8) | ((p[0]&0x3f)<<16));
626 slot->loopaddr = (p[4]<<16) | (p[3]<<24);
627 slot->endaddr = (p[6]<<16) | (p[5]<<24);
628 slot->endaddr -= 0x00010000U;
629 slot->endaddr ^= 0xffff0000U;
630
631 // copy internal registers data
632 for (i = 7; i < 12; i++)
633 C_w(0, 8 + snum + (i-2) * 24, p[i]);
634
635 // status register LD bit is on for approx 300us
636 m_status_ld = 1;
637 //period = attotime::from_usec(300);
638 //if (m_clock != YMF278B_STD_CLOCK)
639 // period = (period * m_clock) / YMF278B_STD_CLOCK;
640 //m_timer_ld->adjust(period); !!!
641
642 // retrigger if key is on
643 if (slot->KEY_ON)
644 retrigger_note(slot);
645 else if (slot->active)
646 {
647 // deactivate channel
648 slot->env_step = 5;
649 compute_envelope(slot);
650 }
651
652 break;
653 }
654
655 case 1:
656 slot->wave &= 0xff;
657 slot->wave |= ((data&0x1)<<8);
658 slot->F_NUMBER &= 0x380;
659 slot->F_NUMBER |= (data>>1);
660 if (slot->active && (data ^ m_pcmregs[reg]) & 0xfe)
661 {
662 compute_freq_step(slot);
663 compute_envelope(slot);
664 }
665 break;
666
667 case 2:
668 slot->F_NUMBER &= 0x07f;
669 slot->F_NUMBER |= ((data&0x07)<<7);
670 slot->preverb = (data&0x8)>>3;
671 slot->octave = (data&0xf0)>>4;
672 if (data != m_pcmregs[reg])
673 {
674 // channel goes off if octave is set to -8 (datasheet says it's prohibited)
675 // (it is ok if this activates the channel while it was off: compute_envelope will reset it again if needed)
676 slot->active = (slot->octave != 8);
677
678 if (slot->active)
679 {
680 slot->env_preverb = 0;
681 compute_freq_step(slot);
682 compute_envelope(slot);
683 }
684 }
685 break;
686
687 case 3:
688 slot->TL = data>>1;
689 slot->LD = data&0x1;
690 break;
691
692 case 4:
693 slot->CH = (data&0x10)>>4;
694 // CH bit note: output to DO1 pin (1) or DO2 pin (0), this may
695 // silence the channel depending on how it's wired up on the PCB.
696 // For now, it's always enabled.
697 // (bit 5 (LFO reset) is also not hooked up yet)
698
699 slot->pan = data&0xf;
700 slot->DAMP = (data&0x40)>>6;
701 if (data & 0x80)
702 {
703 // don't retrigger if key was already on
704 if (slot->KEY_ON)
705 {
706 if ((data ^ m_pcmregs[reg]) & 0x40)
707 compute_envelope(slot);
708
709 break;
710 }
711
712 retrigger_note(slot);
713 }
714 else if (slot->active)
715 {
716 // release
717 slot->env_step = 4;
718 compute_envelope(slot);
719 }
720 slot->KEY_ON = (data&0x80)>>7;
721 break;
722
723 case 5:
724 // LFO and vibrato level, not hooked up yet
725 slot->LFO = (data>>3)&0x7;
726 slot->VIB = data&0x7;
727 break;
728
729 case 6:
730 slot->AR = data>>4;
731 slot->D1R = data&0xf;
732 if (slot->active && data != m_pcmregs[reg])
733 compute_envelope(slot);
734 break;
735
736 case 7:
737 slot->DL = data>>4;
738 slot->D2R = data&0xf;
739 if (slot->active && data != m_pcmregs[reg])
740 compute_envelope(slot);
741 break;
742
743 case 8:
744 slot->RC = data>>4;
745 slot->RR = data&0xf;
746 if (slot->active && data != m_pcmregs[reg])
747 compute_envelope(slot);
748 break;
749
750 case 9:
751 // tremolo level, not hooked up yet
752 slot->AM = data & 0x7;
753 break;
754 }
755 }
756 else
757 {
758 // All non-slot registers
759 switch (reg)
760 {
761 // LSI TEST
762 case 0x00:
763 case 0x01:
764 break;
765
766 case 0x02:
767 m_wavetblhdr = (data>>2)&0x7;
768 m_memmode = data&3;
769 break;
770
771 case 0x03:
772 data &= 0x3f; // !
773 break;
774 case 0x04:
775 break;
776 case 0x05:
777 // set memory address
778 m_memadr = m_pcmregs[3] << 16 | m_pcmregs[4] << 8 | data;
779 break;
780
781 case 0x06:
782 // memory data (ignored, we don't support RAM)
783 write_memory(m_memadr, data);
784 m_memadr = (m_memadr + 1) & 0x3fffff;
785 break;
786
787 case 0x07:
788 break; // unused
789
790 case 0xf8:
791 m_fm_l = data & 0x7;
792 m_fm_r = (data>>3)&0x7;
793 break;
794
795 case 0xf9:
796 m_pcm_l = data & 0x7;
797 m_pcm_r = (data>>3)&0x7;
798 break;
799
800 default:
801 LOG(("YMF278B: Port C write %02x, %02x\n", reg, data));
802 break;
803 }
804 }
805
806 m_pcmregs[reg] = data;
807 }
808
809 /*static void timer_busy_start(int is_pcm)
810 {
811 // status register BUSY bit is on for 56(FM) or 88(PCM) cycles
812 m_status_busy = 1;
813 //m_timer_busy->adjust(attotime::from_hz(m_clock / (is_pcm ? 88 : 56)));
814 }
815
816 WRITE8_MEMBER( ymf278b_device::write )
817 {
818 switch (offset)
819 {
820 case 0:
821 case 2:
822 timer_busy_start(0);
823 m_port_AB = data;
824 m_lastport = offset>>1 & 1;
825 break;
826
827 case 1:
828 case 3:
829 timer_busy_start(0);
830 if (m_lastport) B_w(m_port_AB, data);
831 else A_w(m_port_AB, data);
832 break;
833
834 case 4:
835 timer_busy_start(1);
836 m_port_C = data;
837 break;
838
839 case 5:
840 // PCM regs are only accessible if NEW2 is set
841 if (~m_exp & 2)
842 break;
843
844 //m_stream->update();
845
846 timer_busy_start(1);
847 C_w(m_port_C, data);
848 break;
849
850 default:
851 logerror("%s: unexpected write at offset %X to ymf278b = %02X\n", machine().describe_context(), offset, data);
852 break;
853 }
854 }
855
856
857 READ8_MEMBER( ymf278b_device::read )
858 {
859 UINT8 ret = 0;
860
861 switch (offset)
862 {
863 // status register
864 case 0:
865 {
866 // bits 0 and 1 are only valid if NEW2 is set
867 UINT8 newbits = 0;
868 if (m_exp & 2)
869 newbits = (m_status_ld << 1) | m_status_busy;
870
871 ret = newbits | m_current_irq | (m_irq_line ? 0x80 : 0x00);
872 break;
873 }
874
875 // FM regs can be read too (on contrary to what the datasheet says)
876 case 1:
877 case 3:
878 // but they're not implemented here yet
879 break;
880
881 // PCM regs
882 case 5:
883 // only accessible if NEW2 is set
884 if (~m_exp & 2)
885 break;
886
887 switch (m_port_C)
888 {
889 // special cases
890 case 2:
891 ret = (m_pcmregs[m_port_C] & 0x1f) | 0x20; // device ID in upper bits
892 break;
893 case 6:
894 ret = read_memory(m_memadr);
895 m_memadr = (m_memadr + 1) & 0x3fffff;
896 break;
897
898 default:
899 ret = m_pcmregs[m_port_C];
900 break;
901 }
902 break;
903
904 default:
905 logerror("%s: unexpected read at offset %X from ymf278b\n", machine().describe_context(), offset);
906 break;
907 }
908
909 return ret;
910 }*/
911
ymf278b_status_port_r(int num)912 static UINT8 ymf278b_status_port_r(int num)
913 {
914 return m_current_irq | (m_irq_line == ASSERT_LINE ? 0x80 : 0x00);
915 }
916
917 // Not implemented yet
ymf278b_data_port_r(int num)918 static UINT8 ymf278b_data_port_r(int num)
919 {
920 return 0;
921 }
922
ymf278b_control_port_A_w(int num,UINT8 data)923 static void ymf278b_control_port_A_w(int num, UINT8 data)
924 {
925 m_port_A = data;
926 }
927
ymf278b_data_port_A_w(int num,UINT8 data)928 static void ymf278b_data_port_A_w(int num, UINT8 data)
929 {
930 A_w(num, m_port_A, data);
931 }
932
ymf278b_control_port_B_w(int num,UINT8 data)933 static void ymf278b_control_port_B_w(int num, UINT8 data)
934 {
935 m_port_B = data;
936 }
937
ymf278b_data_port_B_w(int num,UINT8 data)938 static void ymf278b_data_port_B_w(int num, UINT8 data)
939 {
940 B_w(num, m_port_B, data);
941 }
942
ymf278b_control_port_C_w(int num,UINT8 data)943 static void ymf278b_control_port_C_w(int num, UINT8 data)
944 {
945 m_port_C = data;
946 }
947
ymf278b_data_port_C_w(int num,UINT8 data)948 static void ymf278b_data_port_C_w(int num, UINT8 data)
949 {
950 C_w(num, m_port_C, data);
951 }
952
953 /**************************************************************************/
954
955 //-------------------------------------------------
956 // device_reset - device-specific reset
957 //-------------------------------------------------
958
ymf278b_reset()959 void ymf278b_reset()
960 {
961 int i;
962
963 ymf278b_chip_in_reset = 1;
964 m_enable = 0; // w/o this, loading tengai then strikers ii/iii causes a hang at boot (must be above the A_w() for-loop) -dink
965 // clear registers
966 for (i = 0; i <= 4; i++)
967 A_w(0, i, 0);
968
969 B_w(0, 5, 0);
970 for (i = 0; i < 8; i++)
971 C_w(0, i, 0);
972 for (i = 0xff; i >= 8; i--)
973 C_w(0, i, 0);
974 C_w(0, 0xf8, 0x1b);
975
976 m_port_A = m_port_B = m_port_C = 0;
977 m_lastport = 0;
978 m_memadr = 0;
979
980 // init/silence channels
981 for (i = 0; i < 24 ; i++)
982 {
983 YMF278BSlot *slot = &m_slots[i];
984
985 slot->LFO = 0;
986 slot->VIB = 0;
987 slot->AR = 0;
988 slot->D1R = 0;
989 slot->DL = 0;
990 slot->D2R = 0;
991 slot->RC = 0;
992 slot->RR = 0;
993 slot->AM = 0;
994
995 slot->startaddr = 0;
996 slot->loopaddr = 0;
997 slot->endaddr = 0;
998
999 slot->env_step = 5;
1000 compute_envelope(slot);
1001 }
1002
1003 // ymf278b_timer_a_reset(0); - these are reset in burn_ymf278b.cpp -dink
1004 // ymf278b_timer_b_reset(0); ""
1005 //m_timer_a->reset();
1006 //m_timer_b->reset();
1007 /*m_timer_busy->reset();*/ m_status_busy = 0;
1008 /*m_timer_ld->reset();*/ m_status_ld = 0;
1009
1010 m_irq_line = 0;
1011 m_current_irq = 0;
1012 //if (m_irq_handler)
1013 // m_irq_handler(0, 0);
1014 ymf278b_chip_in_reset = 0;
1015 }
1016
precompute_rate_tables()1017 static void precompute_rate_tables()
1018 {
1019 int i;
1020
1021 // decay rate
1022 for (i = 0; i < 64; i++)
1023 {
1024 if (i <= 3)
1025 m_lut_dr[i] = 0;
1026 else if (i >= 60)
1027 m_lut_dr[i] = 15 << 4;
1028 else
1029 m_lut_dr[i] = (15 << (21 - i / 4)) / (4 + i % 4);
1030 }
1031
1032 // attack rate (manual shows curve instead of linear though, so this is not entirely accurate)
1033 for (i = 0; i < 64; i++)
1034 {
1035 if (i <= 3 || i == 63)
1036 m_lut_ar[i] = 0;
1037 else if (i >= 60)
1038 m_lut_ar[i] = 17;
1039 else
1040 m_lut_ar[i] = (67 << (15 - i / 4)) / (4 + i % 4);
1041 }
1042 }
1043
1044 /*void register_save_state()
1045 {
1046 int i;
1047
1048 save_item(NAME(m_pcmregs));
1049 save_item(NAME(m_wavetblhdr));
1050 save_item(NAME(m_memmode));
1051 save_item(NAME(m_memadr));
1052 save_item(NAME(m_status_busy));
1053 save_item(NAME(m_status_ld));
1054 save_item(NAME(m_exp));
1055 save_item(NAME(m_fm_l));
1056 save_item(NAME(m_fm_r));
1057 save_item(NAME(m_pcm_l));
1058 save_item(NAME(m_pcm_r));
1059 save_item(NAME(m_timer_a_count));
1060 save_item(NAME(m_timer_b_count));
1061 save_item(NAME(m_enable));
1062 save_item(NAME(m_current_irq));
1063 save_item(NAME(m_irq_line));
1064 save_item(NAME(m_port_AB));
1065 save_item(NAME(m_port_C));
1066 save_item(NAME(m_lastport));
1067
1068 for (i = 0; i < 24; ++i)
1069 {
1070 save_item(NAME(m_slots[i].wave), i);
1071 save_item(NAME(m_slots[i].F_NUMBER), i);
1072 save_item(NAME(m_slots[i].octave), i);
1073 save_item(NAME(m_slots[i].preverb), i);
1074 save_item(NAME(m_slots[i].DAMP), i);
1075 save_item(NAME(m_slots[i].CH), i);
1076 save_item(NAME(m_slots[i].LD), i);
1077 save_item(NAME(m_slots[i].TL), i);
1078 save_item(NAME(m_slots[i].pan), i);
1079 save_item(NAME(m_slots[i].LFO), i);
1080 save_item(NAME(m_slots[i].VIB), i);
1081 save_item(NAME(m_slots[i].AM), i);
1082
1083 save_item(NAME(m_slots[i].AR), i);
1084 save_item(NAME(m_slots[i].D1R), i);
1085 save_item(NAME(m_slots[i].DL), i);
1086 save_item(NAME(m_slots[i].D2R), i);
1087 save_item(NAME(m_slots[i].RC), i);
1088 save_item(NAME(m_slots[i].RR), i);
1089
1090 save_item(NAME(m_slots[i].step), i);
1091 save_item(NAME(m_slots[i].stepptr), i);
1092
1093 save_item(NAME(m_slots[i].active), i);
1094 save_item(NAME(m_slots[i].KEY_ON), i);
1095 save_item(NAME(m_slots[i].bits), i);
1096 save_item(NAME(m_slots[i].startaddr), i);
1097 save_item(NAME(m_slots[i].loopaddr), i);
1098 save_item(NAME(m_slots[i].endaddr), i);
1099
1100 save_item(NAME(m_slots[i].env_step), i);
1101 save_item(NAME(m_slots[i].env_vol), i);
1102 save_item(NAME(m_slots[i].env_vol_step), i);
1103 save_item(NAME(m_slots[i].env_vol_lim), i);
1104 save_item(NAME(m_slots[i].env_preverb), i);
1105 }
1106 }*/
1107
1108 //-------------------------------------------------
1109 // device_start - device-specific startup
1110 //-------------------------------------------------
1111
ymf278b_start(int num,UINT8 * rom,INT32 romsize,void (* irq_cb)(INT32,INT32),void (* timer_cb)(INT32,INT32,double),int clock)1112 int ymf278b_start(int num, UINT8 *rom, INT32 romsize, void (*irq_cb)(INT32, INT32), void (*timer_cb)(INT32, INT32, double), int clock)
1113 {
1114 int i;
1115
1116 m_rom = rom;
1117 m_romsize = romsize;
1118 m_clock = clock;
1119 m_irq_handler = irq_cb;
1120 timer_callback = timer_cb;
1121
1122 /*m_timer_base = attotime::from_hz(m_clock) * (19*36); - we use different timers -dink
1123 m_timer_a = timer_alloc(TIMER_A);
1124 m_timer_b = timer_alloc(TIMER_B);
1125 m_timer_busy = timer_alloc(TIMER_BUSY_CLEAR);
1126 m_timer_ld = timer_alloc(TIMER_LD_CLEAR); */
1127
1128 m_clock_ratio = (float)clock / (float)YMF278B_STD_CLOCK;
1129
1130 for (i = 0; i < 24; i++)
1131 {
1132 m_slots[i].num = i;
1133 }
1134
1135 //m_stream = machine().sound().stream_alloc(*this, 0, 2, clock()/768);
1136 m_mix_buffer = malloc(sizeof(INT32)*48000*2); // this driver only supports 44100, but set the buffersize to 48000 just incase someone uses this in their FBA settings.
1137
1138 // rate tables
1139 precompute_rate_tables();
1140
1141 // Volume table, 1 = -0.375dB, 8 = -3dB, 256 = -96dB
1142 for(i = 0; i < 256; i++)
1143 m_volume[i] = 65536*pow(2.0, (-0.375/6)*i);
1144 for(i = 256; i < 256*4; i++)
1145 m_volume[i] = 0;
1146
1147 // Pan values, units are -3dB, i.e. 8.
1148 for(i = 0; i < 16; i++)
1149 {
1150 m_pan_left[i] = i < 7 ? i*8 : i < 9 ? 256 : 0;
1151 m_pan_right[i] = i < 8 ? 0 : i < 10 ? 256 : (16-i)*8;
1152 }
1153
1154 // Mixing levels, units are -3dB, and add some margin to avoid clipping
1155 for(i=0; i<7; i++)
1156 m_mix_level[i] = m_volume[8*i+13];
1157 m_mix_level[7] = 0;
1158 ymf278b_chip_in_reset = 0;
1159
1160 // Register state for saving
1161 //register_save_state();
1162 return 0;
1163 }
1164
ymf278b_scan(INT32 nAction,INT32 * pnMin)1165 void ymf278b_scan(INT32 nAction, INT32* pnMin)
1166 {
1167 if (nAction & ACB_DRIVER_DATA) {
1168 // internal state - make for happy savestates -dink
1169 SCAN_VAR(m_pcmregs);
1170 SCAN_VAR(m_slots);
1171 SCAN_VAR(m_wavetblhdr);
1172 SCAN_VAR(m_memmode);
1173 SCAN_VAR(m_memadr);
1174 SCAN_VAR(m_exp);
1175
1176 SCAN_VAR(m_fm_l); SCAN_VAR(m_fm_r);
1177 SCAN_VAR(m_pcm_l); SCAN_VAR(m_pcm_r);
1178
1179 SCAN_VAR(m_timer_a_count); SCAN_VAR(m_timer_b_count);
1180 SCAN_VAR(m_enable); SCAN_VAR(m_current_irq);
1181 SCAN_VAR(m_irq_line);
1182
1183 SCAN_VAR(m_port_C); SCAN_VAR(m_port_A); SCAN_VAR(m_port_B);
1184 }
1185 }
1186
1187
1188 /*
1189 const device_type YMF278B = &device_creator<ymf278b_device>;
1190
1191 ymf278b_device::ymf278b_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
1192 : device_t(mconfig, YMF278B, "YMF278B", tag, owner, clock, "ymf278b", __FILE__),
1193 device_sound_interface(mconfig, *this),
1194 m_irq_handler(*this)
1195 {
1196 }
1197
1198 //-------------------------------------------------
1199 // device_config_complete - perform any
1200 // operations now that the configuration is
1201 // complete
1202 //-------------------------------------------------
1203
1204 void ymf278b_device::device_config_complete()
1205 {
1206 }
1207 */
YMF278B_sh_stop(void)1208 void YMF278B_sh_stop( void )
1209 {
1210 if(m_mix_buffer) {
1211 free(m_mix_buffer);
1212 m_mix_buffer = NULL;
1213 }
1214 }
1215
READ8_HANDLER(YMF278B_status_port_0_r)1216 READ8_HANDLER( YMF278B_status_port_0_r )
1217 {
1218 return ymf278b_status_port_r(0);
1219 }
1220
READ8_HANDLER(YMF278B_data_port_0_r)1221 READ8_HANDLER( YMF278B_data_port_0_r )
1222 {
1223 return ymf278b_data_port_r(0);
1224 }
1225
WRITE8_HANDLER(YMF278B_control_port_0_A_w)1226 WRITE8_HANDLER( YMF278B_control_port_0_A_w )
1227 {
1228 ymf278b_control_port_A_w(0, data);
1229 }
1230
WRITE8_HANDLER(YMF278B_data_port_0_A_w)1231 WRITE8_HANDLER( YMF278B_data_port_0_A_w )
1232 {
1233 ymf278b_data_port_A_w(0, data);
1234 }
1235
WRITE8_HANDLER(YMF278B_control_port_0_B_w)1236 WRITE8_HANDLER( YMF278B_control_port_0_B_w )
1237 {
1238 ymf278b_control_port_B_w(0, data);
1239 }
1240
WRITE8_HANDLER(YMF278B_data_port_0_B_w)1241 WRITE8_HANDLER( YMF278B_data_port_0_B_w )
1242 {
1243 ymf278b_data_port_B_w(0, data);
1244 }
1245
WRITE8_HANDLER(YMF278B_control_port_0_C_w)1246 WRITE8_HANDLER( YMF278B_control_port_0_C_w )
1247 {
1248 ymf278b_control_port_C_w(0, data);
1249 }
1250
WRITE8_HANDLER(YMF278B_data_port_0_C_w)1251 WRITE8_HANDLER( YMF278B_data_port_0_C_w )
1252 {
1253 ymf278b_data_port_C_w(0, data);
1254 }
1255
1256