1 /*****************************************************************************
2 *
3 * z180.c
4 * Portable Z180 emulator V0.3
5 *
6 * Copyright Juergen Buchmueller, all rights reserved.
7 * You can contact me at juergen@mame.net or pullmoll@stop1984.com
8 *
9 * - This source code is released as freeware for non-commercial purposes
10 * as part of the M.A.M.E. (Multiple Arcade Machine Emulator) project.
11 * The licensing terms of MAME apply to this piece of code for the MAME
12 * project and derviative works, as defined by the MAME license. You
13 * may opt to make modifications, improvements or derivative works under
14 * that same conditions, and the MAME project may opt to keep
15 * modifications, improvements or derivatives under their terms exclusively.
16 *
17 * - Alternatively you can choose to apply the terms of the "GPL" (see
18 * below) to this - and only this - piece of code or your derivative works.
19 * Note that in no case your choice can have any impact on any other
20 * source code of the MAME project, or binary, or executable, be it closely
21 * or losely related to this piece of code.
22 *
23 * - At your choice you are also free to remove either licensing terms from
24 * this file and continue to use it under only one of the two licenses. Do this
25 * if you think that licenses are not compatible (enough) for you, or if you
26 * consider either license 'too restrictive' or 'too free'.
27 *
28 * - GPL (GNU General Public License)
29 * This program is free software; you can redistribute it and/or
30 * modify it under the terms of the GNU General Public License
31 * as published by the Free Software Foundation; either version 2
32 * of the License, or (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
42 *
43 *
44 *****************************************************************************/
45
46 /*****************************************************************************
47
48 Z180 Info:
49
50 Known clock speeds (from ZiLOG): 6, 8, 10, 20 & 33MHz
51
52 ZiLOG Z180 codes:
53
54 Speed: 10 = 10MHZ
55 20 = 20MHz
56 33 = 33MHz
57 Package: P = 60-Pin Plastic DIP
58 V = 68-Pin PLCC
59 F = 80-Pin QFP
60 Temp: S = 0C to +70C
61 E = -40C to +85C
62
63 Environmanetal Flow: C = Plastic Standard
64
65
66 Example from Ms.Pac-Man/Galaga - 20 year Reunion hardare (see src/mame/drivers/20pacgal.c):
67
68 CPU is Z8S18020VSC = Z180, 20MHz, 68-Pin PLCC, 0C to +70C, Plastic Standard
69
70
71 Other CPUs that use a compatible Z180 core:
72
73 Hitachi HD647180 series:
74 Available in QFP80, PLCC84 & DIP90 packages (the QFP80 is not pinout compatible)
75 The HD647180 also has an internal ROM
76
77 *****************************************************************************/
78
79 #include "burnint.h"
80 #define Z180_INLINE static inline
81
82 #include "z180_intf.h"
83 #include <stddef.h>
84
85 /* interrupt priorities */
86 #define Z180_INT_TRAP 0 /* Undefined opcode */
87 #define Z180_INT_NMI 1 /* NMI */
88 #define Z180_INT_IRQ0 2 /* Execute IRQ1 */
89 #define Z180_INT_IRQ1 3 /* Execute IRQ1 */
90 #define Z180_INT_IRQ2 4 /* Execute IRQ2 */
91 #define Z180_INT_PRT0 5 /* Internal PRT channel 0 */
92 #define Z180_INT_PRT1 6 /* Internal PRT channel 1 */
93 #define Z180_INT_DMA0 7 /* Internal DMA channel 0 */
94 #define Z180_INT_DMA1 8 /* Internal DMA channel 1 */
95 #define Z180_INT_CSIO 9 /* Internal CSI/O */
96 #define Z180_INT_ASCI0 10 /* Internal ASCI channel 0 */
97 #define Z180_INT_ASCI1 11 /* Internal ASCI channel 1 */
98 #define Z180_INT_MAX Z180_INT_ASCI1
99
100 // in z180_intf.cpp
101 extern void __fastcall z180_cpu_write_handler(UINT32 address, UINT8 data);
102 extern UINT8 __fastcall z180_cpu_fetchop_handler(UINT32 address);
103 extern UINT8 __fastcall z180_cpu_fetcharg_handler(UINT32 address);
104 extern UINT8 __fastcall z180_cpu_read_handler(UINT32 address);
105 extern void __fastcall z180_cpu_write_port_handler(UINT32 address, UINT8 data);
106 extern UINT8 __fastcall z180_cpu_read_port_handler(UINT32 address);
107
108 #define cpu_readop(a) z180_cpu_fetchop_handler(a)
109 #define cpu_readop_arg(a) z180_cpu_fetcharg_handler(a)
110 #define program_read_byte_8le(a) z180_cpu_read_handler(a)
111 #define program_write_byte_8le(a,d) z180_cpu_write_handler(a,d)
112 #define io_read_byte_8le(a) z180_cpu_read_port_handler(a)
113 #define io_write_byte_8le(a,d) z180_cpu_write_port_handler(a,d)
114
115 #include "z80daisy.h"
116
117
118 /* execute main opcodes inside a big switch statement */
119 #ifndef BIG_SWITCH
120 #define BIG_SWITCH 0
121 #endif
122
123 /* use big flag arrays (4*64K) for ADD/ADC/SUB/SBC/CP results */
124 #define BIG_FLAGS_ARRAY 1
125
126
127 /****************************************************************************/
128 /* The Z180 registers. HALT is set to 1 when the CPU is halted, the refresh */
129 /* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */
130 /****************************************************************************/
131 typedef struct {
132 PAIR PREPC,PC,SP,AF,BC,DE,HL,IX,IY;
133 PAIR AF2,BC2,DE2,HL2;
134 UINT8 R,R2,IFF1,IFF2,HALT,IM,I;
135 UINT8 tmdr_latch; /* flag latched TMDR0H, TMDR1H values */
136 UINT8 read_tcr_tmdr[2]; /* flag to indicate that TCR or TMDR was read */
137 UINT32 iol; /* I/O line status bits */
138 UINT8 io[64]; /* 64 internal 8 bit registers */
139 UINT32 mmu[16]; /* MMU address translation */
140 UINT8 tmdrh[2]; /* latched TMDR0H and TMDR1H values */
141 UINT16 tmdr_value[2]; /* TMDR values used byt PRT0 and PRT1 as down counter */
142 UINT8 tif[2]; /* TIF0 and TIF1 values */
143
144 INT32 timer_cnt;
145 INT32 extra_cycles;
146
147 UINT8 nmi_state; /* nmi line state */
148 UINT8 nmi_pending; /* nmi pending */
149 UINT8 nmi_hold; /* nmi hold logic */
150 UINT8 irq_state[3]; /* irq line states (INT0,INT1,INT2) */
151 UINT8 irq_hold[3]; // irq hold logic */
152 UINT8 after_EI; /* are we in the EI shadow? */
153 UINT8 int_pending[Z180_INT_MAX + 1];
154 UINT32 total_cycles;
155 UINT32 current_cycles;
156 UINT32 EA;
157 INT32 icount;
158 INT32 end_run;
159
160 const struct z80_irq_daisy_chain *daisy;
161 int (*irq_callback)(int irqline);
162 } Z180_Regs;
163
164 #define CF 0x01
165 #define NF 0x02
166 #define PF 0x04
167 #define VF PF
168 #define XF 0x08
169 #define HF 0x10
170 #define YF 0x20
171 #define ZF 0x40
172 #define SF 0x80
173
174 /* I/O line status flags */
175 #define Z180_CKA0 0x00000001 /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
176 #define Z180_CKA1 0x00000002 /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
177 #define Z180_CKS 0x00000004 /* I/O serial clock (active high) */
178 #define Z180_CTS0 0x00000100 /* I clear to send 0 (active low) */
179 #define Z180_CTS1 0x00000200 /* I clear to send 1 (active low) or RXS (mux) */
180 #define Z180_DCD0 0x00000400 /* I data carrier detect (active low) */
181 #define Z180_DREQ0 0x00000800 /* I data request DMA ch 0 (active low) or CKA0 (mux) */
182 #define Z180_DREQ1 0x00001000 /* I data request DMA ch 1 (active low) */
183 #define Z180_RXA0 0x00002000 /* I asynchronous receive data 0 (active high) */
184 #define Z180_RXA1 0x00004000 /* I asynchronous receive data 1 (active high) */
185 #define Z180_RXS 0x00008000 /* I clocked serial receive data (active high) or CTS1 (mux) */
186 #define Z180_RTS0 0x00010000 /* O request to send (active low) */
187 #define Z180_TEND0 0x00020000 /* O transfer end 0 (active low) or CKA1 (mux) */
188 #define Z180_TEND1 0x00040000 /* O transfer end 1 (active low) */
189 #define Z180_A18_TOUT 0x00080000 /* O transfer out (PRT channel, active low) or A18 (mux) */
190 #define Z180_TXA0 0x00100000 /* O asynchronous transmit data 0 (active high) */
191 #define Z180_TXA1 0x00200000 /* O asynchronous transmit data 1 (active high) */
192 #define Z180_TXS 0x00400000 /* O clocked serial transmit data (active high) */
193
194 /*
195 * Prevent warnings on NetBSD. All identifiers beginning with an underscore
196 * followed by an uppercase letter are reserved by the C standard (ISO/IEC
197 * 9899:1999, 7.1.3) to be used by the implementation. It'd be best to rename
198 * all such instances, but this is less intrusive and error-prone.
199 */
200 #undef _B
201 #undef _C
202 #undef _L
203
204 #define _PPC Z180.PREPC.d /* previous program counter */
205
206 #define _PCD Z180.PC.d
207 #define _PC Z180.PC.w.l
208
209 #define _SPD Z180.SP.d
210 #define _SP Z180.SP.w.l
211
212 #define _AFD Z180.AF.d
213 #define _AF Z180.AF.w.l
214 #define _A Z180.AF.b.h
215 #define _F Z180.AF.b.l
216
217 #define _BCD Z180.BC.d
218 #define _BC Z180.BC.w.l
219 #define _B Z180.BC.b.h
220 #define _C Z180.BC.b.l
221
222 #define _DED Z180.DE.d
223 #define _DE Z180.DE.w.l
224 #define _D Z180.DE.b.h
225 #define _E Z180.DE.b.l
226
227 #define _HLD Z180.HL.d
228 #define _HL Z180.HL.w.l
229 #define _H Z180.HL.b.h
230 #define _L Z180.HL.b.l
231
232 #define _IXD Z180.IX.d
233 #define _IX Z180.IX.w.l
234 #define _HX Z180.IX.b.h
235 #define _LX Z180.IX.b.l
236
237 #define _IYD Z180.IY.d
238 #define _IY Z180.IY.w.l
239 #define _HY Z180.IY.b.h
240 #define _LY Z180.IY.b.l
241
242 #define _I Z180.I
243 #define _R Z180.R
244 #define _R2 Z180.R2
245 #define _IM Z180.IM
246 #define _IFF1 Z180.IFF1
247 #define _IFF2 Z180.IFF2
248 #define _HALT Z180.HALT
249
250 #define EA Z180.EA
251
252 #define IO(n) Z180.io[(n)-Z180_CNTLA0]
253 #define IO_CNTLA0 IO(Z180_CNTLA0)
254 #define IO_CNTLA1 IO(Z180_CNTLA1)
255 #define IO_CNTLB0 IO(Z180_CNTLB0)
256 #define IO_CNTLB1 IO(Z180_CNTLB1)
257 #define IO_STAT0 IO(Z180_STAT0)
258 #define IO_STAT1 IO(Z180_STAT1)
259 #define IO_TDR0 IO(Z180_TDR0)
260 #define IO_TDR1 IO(Z180_TDR1)
261 #define IO_RDR0 IO(Z180_RDR0)
262 #define IO_RDR1 IO(Z180_RDR1)
263 #define IO_CNTR IO(Z180_CNTR)
264 #define IO_TRDR IO(Z180_TRDR)
265 #define IO_TMDR0L IO(Z180_TMDR0L)
266 #define IO_TMDR0H IO(Z180_TMDR0H)
267 #define IO_RLDR0L IO(Z180_RLDR0L)
268 #define IO_RLDR0H IO(Z180_RLDR0H)
269 #define IO_TCR IO(Z180_TCR)
270 #define IO_IO11 IO(Z180_IO11)
271 #define IO_ASEXT0 IO(Z180_ASEXT0)
272 #define IO_ASEXT1 IO(Z180_ASEXT1)
273 #define IO_TMDR1L IO(Z180_TMDR1L)
274 #define IO_TMDR1H IO(Z180_TMDR1H)
275 #define IO_RLDR1L IO(Z180_RLDR1L)
276 #define IO_RLDR1H IO(Z180_RLDR1H)
277 #define IO_FRC IO(Z180_FRC)
278 #define IO_IO19 IO(Z180_IO19)
279 #define IO_ASTC0L IO(Z180_ASTC0L)
280 #define IO_ASTC0H IO(Z180_ASTC0H)
281 #define IO_ASTC1L IO(Z180_ASTC1L)
282 #define IO_ASTC1H IO(Z180_ASTC1H)
283 #define IO_CMR IO(Z180_CMR)
284 #define IO_CCR IO(Z180_CCR)
285 #define IO_SAR0L IO(Z180_SAR0L)
286 #define IO_SAR0H IO(Z180_SAR0H)
287 #define IO_SAR0B IO(Z180_SAR0B)
288 #define IO_DAR0L IO(Z180_DAR0L)
289 #define IO_DAR0H IO(Z180_DAR0H)
290 #define IO_DAR0B IO(Z180_DAR0B)
291 #define IO_BCR0L IO(Z180_BCR0L)
292 #define IO_BCR0H IO(Z180_BCR0H)
293 #define IO_MAR1L IO(Z180_MAR1L)
294 #define IO_MAR1H IO(Z180_MAR1H)
295 #define IO_MAR1B IO(Z180_MAR1B)
296 #define IO_IAR1L IO(Z180_IAR1L)
297 #define IO_IAR1H IO(Z180_IAR1H)
298 #define IO_IAR1B IO(Z180_IAR1B)
299 #define IO_BCR1L IO(Z180_BCR1L)
300 #define IO_BCR1H IO(Z180_BCR1H)
301 #define IO_DSTAT IO(Z180_DSTAT)
302 #define IO_DMODE IO(Z180_DMODE)
303 #define IO_DCNTL IO(Z180_DCNTL)
304 #define IO_IL IO(Z180_IL)
305 #define IO_ITC IO(Z180_ITC)
306 #define IO_IO35 IO(Z180_IO35)
307 #define IO_RCR IO(Z180_RCR)
308 #define IO_IO37 IO(Z180_IO37)
309 #define IO_CBR IO(Z180_CBR)
310 #define IO_BBR IO(Z180_BBR)
311 #define IO_CBAR IO(Z180_CBAR)
312 #define IO_IO3B IO(Z180_IO3B)
313 #define IO_IO3C IO(Z180_IO3C)
314 #define IO_IO3D IO(Z180_IO3D)
315 #define IO_OMCR IO(Z180_OMCR)
316 #define IO_IOCR IO(Z180_IOCR)
317
318 /* 00 ASCI control register A ch 0 */
319 #define Z180_CNTLA0_MPE 0x80
320 #define Z180_CNTLA0_RE 0x40
321 #define Z180_CNTLA0_TE 0x20
322 #define Z180_CNTLA0_RTS0 0x10
323 #define Z180_CNTLA0_MPBR_EFR 0x08
324 #define Z180_CNTLA0_MODE_DATA 0x04
325 #define Z180_CNTLA0_MODE_PARITY 0x02
326 #define Z180_CNTLA0_MODE_STOPB 0x01
327
328 #define Z180_CNTLA0_RESET 0x10
329 #define Z180_CNTLA0_RMASK 0xff
330 #define Z180_CNTLA0_WMASK 0xff
331
332 /* 01 ASCI control register A ch 1 */
333 #define Z180_CNTLA1_MPE 0x80
334 #define Z180_CNTLA1_RE 0x40
335 #define Z180_CNTLA1_TE 0x20
336 #define Z180_CNTLA1_CKA1D 0x10
337 #define Z180_CNTLA1_MPBR_EFR 0x08
338 #define Z180_CNTLA1_MODE 0x07
339
340 #define Z180_CNTLA1_RESET 0x10
341 #define Z180_CNTLA1_RMASK 0xff
342 #define Z180_CNTLA1_WMASK 0xff
343
344 /* 02 ASCI control register B ch 0 */
345 #define Z180_CNTLB0_MPBT 0x80
346 #define Z180_CNTLB0_MP 0x40
347 #define Z180_CNTLB0_CTS_PS 0x20
348 #define Z180_CNTLB0_PEO 0x10
349 #define Z180_CNTLB0_DR 0x08
350 #define Z180_CNTLB0_SS 0x07
351
352 #define Z180_CNTLB0_RESET 0x07
353 #define Z180_CNTLB0_RMASK 0xff
354 #define Z180_CNTLB0_WMASK 0xff
355
356 /* 03 ASCI control register B ch 1 */
357 #define Z180_CNTLB1_MPBT 0x80
358 #define Z180_CNTLB1_MP 0x40
359 #define Z180_CNTLB1_CTS_PS 0x20
360 #define Z180_CNTLB1_PEO 0x10
361 #define Z180_CNTLB1_DR 0x08
362 #define Z180_CNTLB1_SS 0x07
363
364 #define Z180_CNTLB1_RESET 0x07
365 #define Z180_CNTLB1_RMASK 0xff
366 #define Z180_CNTLB1_WMASK 0xff
367
368 /* 04 ASCI status register 0 */
369 #define Z180_STAT0_RDRF 0x80
370 #define Z180_STAT0_OVRN 0x40
371 #define Z180_STAT0_PE 0x20
372 #define Z180_STAT0_FE 0x10
373 #define Z180_STAT0_RIE 0x08
374 #define Z180_STAT0_DCD0 0x04
375 #define Z180_STAT0_TDRE 0x02
376 #define Z180_STAT0_TIE 0x01
377
378 #define Z180_STAT0_RESET 0x00
379 #define Z180_STAT0_RMASK 0xff
380 #define Z180_STAT0_WMASK 0x09
381
382 /* 05 ASCI status register 1 */
383 #define Z180_STAT1_RDRF 0x80
384 #define Z180_STAT1_OVRN 0x40
385 #define Z180_STAT1_PE 0x20
386 #define Z180_STAT1_FE 0x10
387 #define Z180_STAT1_RIE 0x08
388 #define Z180_STAT1_CTS1E 0x04
389 #define Z180_STAT1_TDRE 0x02
390 #define Z180_STAT1_TIE 0x01
391
392 #define Z180_STAT1_RESET 0x00
393 #define Z180_STAT1_RMASK 0xff
394 #define Z180_STAT1_WMASK 0x0d
395
396 /* 06 ASCI transmit data register 0 */
397 #define Z180_TDR0_TDR 0xff
398
399 #define Z180_TDR0_RESET 0x00
400 #define Z180_TDR0_RMASK 0xff
401 #define Z180_TDR0_WMASK 0xff
402
403 /* 07 ASCI transmit data register 1 */
404 #define Z180_TDR1_TDR 0xff
405
406 #define Z180_TDR1_RESET 0x00
407 #define Z180_TDR1_RMASK 0xff
408 #define Z180_TDR1_WMASK 0xff
409
410 /* 08 ASCI receive register 0 */
411 #define Z180_RDR0_RDR 0xff
412
413 #define Z180_RDR0_RESET 0x00
414 #define Z180_RDR0_RMASK 0xff
415 #define Z180_RDR0_WMASK 0xff
416
417 /* 09 ASCI receive register 1 */
418 #define Z180_RDR1_RDR 0xff
419
420 #define Z180_RDR1_RESET 0x00
421 #define Z180_RDR1_RMASK 0xff
422 #define Z180_RDR1_WMASK 0xff
423
424 /* 0a CSI/O control/status register */
425 #define Z180_CNTR_EF 0x80
426 #define Z180_CNTR_EIE 0x40
427 #define Z180_CNTR_RE 0x20
428 #define Z180_CNTR_TE 0x10
429 #define Z180_CNTR_SS 0x07
430
431 #define Z180_CNTR_RESET 0x07
432 #define Z180_CNTR_RMASK 0xff
433 #define Z180_CNTR_WMASK 0x4f
434
435 /* 0b CSI/O transmit/receive register */
436 #define Z180_TRDR_RESET 0x00
437 #define Z180_TRDR_RMASK 0xff
438 #define Z180_TRDR_WMASK 0xff
439
440 /* 0c TIMER data register ch 0 L */
441 #define Z180_TMDR0L_RESET 0x00
442 #define Z180_TMDR0L_RMASK 0xff
443 #define Z180_TMDR0L_WMASK 0xff
444
445 /* 0d TIMER data register ch 0 H */
446 #define Z180_TMDR0H_RESET 0x00
447 #define Z180_TMDR0H_RMASK 0xff
448 #define Z180_TMDR0H_WMASK 0xff
449
450 /* 0e TIMER reload register ch 0 L */
451 #define Z180_RLDR0L_RESET 0xff
452 #define Z180_RLDR0L_RMASK 0xff
453 #define Z180_RLDR0L_WMASK 0xff
454
455 /* 0f TIMER reload register ch 0 H */
456 #define Z180_RLDR0H_RESET 0xff
457 #define Z180_RLDR0H_RMASK 0xff
458 #define Z180_RLDR0H_WMASK 0xff
459
460 /* 10 TIMER control register */
461 #define Z180_TCR_TIF1 0x80
462 #define Z180_TCR_TIF0 0x40
463 #define Z180_TCR_TIE1 0x20
464 #define Z180_TCR_TIE0 0x10
465 #define Z180_TCR_TOC1 0x08
466 #define Z180_TCR_TOC0 0x04
467 #define Z180_TCR_TDE1 0x02
468 #define Z180_TCR_TDE0 0x01
469
470 #define Z180_TCR_RESET 0x00
471 #define Z180_TCR_RMASK 0xff
472 #define Z180_TCR_WMASK 0x3f
473
474 /* 11 reserved */
475 #define Z180_IO11_RESET 0x00
476 #define Z180_IO11_RMASK 0xff
477 #define Z180_IO11_WMASK 0xff
478
479 /* 12 (Z8S180/Z8L180) ASCI extension control register 0 */
480 #define Z180_ASEXT0_RDRF 0x80
481 #define Z180_ASEXT0_DCD0 0x40
482 #define Z180_ASEXT0_CTS0 0x20
483 #define Z180_ASEXT0_X1_BIT_CLK0 0x10
484 #define Z180_ASEXT0_BRG0_MODE 0x08
485 #define Z180_ASEXT0_BRK_EN 0x04
486 #define Z180_ASEXT0_BRK_DET 0x02
487 #define Z180_ASEXT0_BRK_SEND 0x01
488
489 #define Z180_ASEXT0_RESET 0x00
490 #define Z180_ASEXT0_RMASK 0xff
491 #define Z180_ASEXT0_WMASK 0xfd
492
493 /* 13 (Z8S180/Z8L180) ASCI extension control register 0 */
494 #define Z180_ASEXT1_RDRF 0x80
495 #define Z180_ASEXT1_X1_BIT_CLK1 0x10
496 #define Z180_ASEXT1_BRG1_MODE 0x08
497 #define Z180_ASEXT1_BRK_EN 0x04
498 #define Z180_ASEXT1_BRK_DET 0x02
499 #define Z180_ASEXT1_BRK_SEND 0x01
500
501 #define Z180_ASEXT1_RESET 0x00
502 #define Z180_ASEXT1_RMASK 0xff
503 #define Z180_ASEXT1_WMASK 0xfd
504
505
506 /* 14 TIMER data register ch 1 L */
507 #define Z180_TMDR1L_RESET 0x00
508 #define Z180_TMDR1L_RMASK 0xff
509 #define Z180_TMDR1L_WMASK 0xff
510
511 /* 15 TIMER data register ch 1 H */
512 #define Z180_TMDR1H_RESET 0x00
513 #define Z180_TMDR1H_RMASK 0xff
514 #define Z180_TMDR1H_WMASK 0xff
515
516 /* 16 TIMER reload register ch 1 L */
517 #define Z180_RLDR1L_RESET 0x00
518 #define Z180_RLDR1L_RMASK 0xff
519 #define Z180_RLDR1L_WMASK 0xff
520
521 /* 17 TIMER reload register ch 1 H */
522 #define Z180_RLDR1H_RESET 0x00
523 #define Z180_RLDR1H_RMASK 0xff
524 #define Z180_RLDR1H_WMASK 0xff
525
526 /* 18 free running counter */
527 #define Z180_FRC_RESET 0x00
528 #define Z180_FRC_RMASK 0xff
529 #define Z180_FRC_WMASK 0xff
530
531 /* 19 reserved */
532 #define Z180_IO19_RESET 0x00
533 #define Z180_IO19_RMASK 0xff
534 #define Z180_IO19_WMASK 0xff
535
536 /* 1a ASCI time constant ch 0 L */
537 #define Z180_ASTC0L_RESET 0x00
538 #define Z180_ASTC0L_RMASK 0xff
539 #define Z180_ASTC0L_WMASK 0xff
540
541 /* 1b ASCI time constant ch 0 H */
542 #define Z180_ASTC0H_RESET 0x00
543 #define Z180_ASTC0H_RMASK 0xff
544 #define Z180_ASTC0H_WMASK 0xff
545
546 /* 1c ASCI time constant ch 1 L */
547 #define Z180_ASTC1L_RESET 0x00
548 #define Z180_ASTC1L_RMASK 0xff
549 #define Z180_ASTC1L_WMASK 0xff
550
551 /* 1d ASCI time constant ch 1 H */
552 #define Z180_ASTC1H_RESET 0x00
553 #define Z180_ASTC1H_RMASK 0xff
554 #define Z180_ASTC1H_WMASK 0xff
555
556 /* 1e clock multiplier */
557 #define Z180_CMR_X2 0x80
558
559 #define Z180_CMR_RESET 0x7f
560 #define Z180_CMR_RMASK 0x80
561 #define Z180_CMR_WMASK 0x80
562
563 /* 1f chip control register */
564 #define Z180_CCR_CLOCK_DIVIDE 0x80
565 #define Z180_CCR_STDBY_IDLE1 0x40
566 #define Z180_CCR_BREXT 0x20
567 #define Z180_CCR_LNPHI 0x10
568 #define Z180_CCR_STDBY_IDLE0 0x08
569 #define Z180_CCR_LNIO 0x04
570 #define Z180_CCR_LNCPU_CTL 0x02
571 #define Z180_CCR_LNAD_DATA 0x01
572
573 #define Z180_CCR_RESET 0x00
574 #define Z180_CCR_RMASK 0xff
575 #define Z180_CCR_WMASK 0xff
576
577 /* 20 DMA source address register ch 0 L */
578 #define Z180_SAR0L_SAR 0xff
579
580 #define Z180_SAR0L_RESET 0x00
581 #define Z180_SAR0L_RMASK 0xff
582 #define Z180_SAR0L_WMASK 0xff
583
584 /* 21 DMA source address register ch 0 H */
585 #define Z180_SAR0H_SAR 0xff
586
587 #define Z180_SAR0H_RESET 0x00
588 #define Z180_SAR0H_RMASK 0xff
589 #define Z180_SAR0H_WMASK 0xff
590
591 /* 22 DMA source address register ch 0 B */
592 #define Z180_SAR0B_SAR 0x0f
593
594 #define Z180_SAR0B_RESET 0x00
595 #define Z180_SAR0B_RMASK 0x0f
596 #define Z180_SAR0B_WMASK 0x0f
597
598 /* 23 DMA destination address register ch 0 L */
599 #define Z180_DAR0L_DAR 0xff
600
601 #define Z180_DAR0L_RESET 0x00
602 #define Z180_DAR0L_RMASK 0xff
603 #define Z180_DAR0L_WMASK 0xff
604
605 /* 24 DMA destination address register ch 0 H */
606 #define Z180_DAR0H_DAR 0xff
607
608 #define Z180_DAR0H_RESET 0x00
609 #define Z180_DAR0H_RMASK 0xff
610 #define Z180_DAR0H_WMASK 0xff
611
612 /* 25 DMA destination address register ch 0 B */
613 #define Z180_DAR0B_DAR 0x00
614
615 #define Z180_DAR0B_RESET 0x00
616 #define Z180_DAR0B_RMASK 0x0f
617 #define Z180_DAR0B_WMASK 0x0f
618
619 /* 26 DMA byte count register ch 0 L */
620 #define Z180_BCR0L_BCR 0xff
621
622 #define Z180_BCR0L_RESET 0x00
623 #define Z180_BCR0L_RMASK 0xff
624 #define Z180_BCR0L_WMASK 0xff
625
626 /* 27 DMA byte count register ch 0 H */
627 #define Z180_BCR0H_BCR 0xff
628
629 #define Z180_BCR0H_RESET 0x00
630 #define Z180_BCR0H_RMASK 0xff
631 #define Z180_BCR0H_WMASK 0xff
632
633 /* 28 DMA memory address register ch 1 L */
634 #define Z180_MAR1L_MAR 0xff
635
636 #define Z180_MAR1L_RESET 0x00
637 #define Z180_MAR1L_RMASK 0xff
638 #define Z180_MAR1L_WMASK 0xff
639
640 /* 29 DMA memory address register ch 1 H */
641 #define Z180_MAR1H_MAR 0xff
642
643 #define Z180_MAR1H_RESET 0x00
644 #define Z180_MAR1H_RMASK 0xff
645 #define Z180_MAR1H_WMASK 0xff
646
647 /* 2a DMA memory address register ch 1 B */
648 #define Z180_MAR1B_MAR 0x0f
649
650 #define Z180_MAR1B_RESET 0x00
651 #define Z180_MAR1B_RMASK 0x0f
652 #define Z180_MAR1B_WMASK 0x0f
653
654 /* 2b DMA I/O address register ch 1 L */
655 #define Z180_IAR1L_IAR 0xff
656
657 #define Z180_IAR1L_RESET 0x00
658 #define Z180_IAR1L_RMASK 0xff
659 #define Z180_IAR1L_WMASK 0xff
660
661 /* 2c DMA I/O address register ch 1 H */
662 #define Z180_IAR1H_IAR 0xff
663
664 #define Z180_IAR1H_RESET 0x00
665 #define Z180_IAR1H_RMASK 0xff
666 #define Z180_IAR1H_WMASK 0xff
667
668 /* 2d (Z8S180/Z8L180) DMA I/O address register ch 1 B */
669 #define Z180_IAR1B_IAR 0x0f
670
671 #define Z180_IAR1B_RESET 0x00
672 #define Z180_IAR1B_RMASK 0x0f
673 #define Z180_IAR1B_WMASK 0x0f
674
675 /* 2e DMA byte count register ch 1 L */
676 #define Z180_BCR1L_BCR 0xff
677
678 #define Z180_BCR1L_RESET 0x00
679 #define Z180_BCR1L_RMASK 0xff
680 #define Z180_BCR1L_WMASK 0xff
681
682 /* 2f DMA byte count register ch 1 H */
683 #define Z180_BCR1H_BCR 0xff
684
685 #define Z180_BCR1H_RESET 0x00
686 #define Z180_BCR1H_RMASK 0xff
687 #define Z180_BCR1H_WMASK 0xff
688
689 /* 30 DMA status register */
690 #define Z180_DSTAT_DE1 0x80 /* DMA enable ch 1 */
691 #define Z180_DSTAT_DE0 0x40 /* DMA enable ch 0 */
692 #define Z180_DSTAT_DWE1 0x20 /* DMA write enable ch 0 (active low) */
693 #define Z180_DSTAT_DWE0 0x10 /* DMA write enable ch 1 (active low) */
694 #define Z180_DSTAT_DIE1 0x08 /* DMA IRQ enable ch 1 */
695 #define Z180_DSTAT_DIE0 0x04 /* DMA IRQ enable ch 0 */
696 #define Z180_DSTAT_DME 0x01 /* DMA enable (read only) */
697
698 #define Z180_DSTAT_RESET 0x30
699 #define Z180_DSTAT_RMASK 0xfd
700 #define Z180_DSTAT_WMASK 0xcc
701
702 /* 31 DMA mode register */
703 #define Z180_DMODE_DM 0x30
704 #define Z180_DMODE_SM 0x0c
705 #define Z180_DMODE_MMOD 0x02
706
707 #define Z180_DMODE_RESET 0x00
708 #define Z180_DMODE_RMASK 0x3e
709 #define Z180_DMODE_WMASK 0x3e
710
711 /* 32 DMA/WAIT control register */
712 #define Z180_DCNTL_MWI1 0x80
713 #define Z180_DCNTL_MWI0 0x40
714 #define Z180_DCNTL_IWI1 0x20
715 #define Z180_DCNTL_IWI0 0x10
716 #define Z180_DCNTL_DMS1 0x08
717 #define Z180_DCNTL_DMS0 0x04
718 #define Z180_DCNTL_DIM1 0x02
719 #define Z180_DCNTL_DIM0 0x01
720
721 #define Z180_DCNTL_RESET 0x00
722 #define Z180_DCNTL_RMASK 0xff
723 #define Z180_DCNTL_WMASK 0xff
724
725 /* 33 INT vector low register */
726 #define Z180_IL_IL 0xe0
727
728 #define Z180_IL_RESET 0x00
729 #define Z180_IL_RMASK 0xe0
730 #define Z180_IL_WMASK 0xe0
731
732 /* 34 INT/TRAP control register */
733 #define Z180_ITC_TRAP 0x80
734 #define Z180_ITC_UFO 0x40
735 #define Z180_ITC_ITE2 0x04
736 #define Z180_ITC_ITE1 0x02
737 #define Z180_ITC_ITE0 0x01
738
739 #define Z180_ITC_RESET 0x01
740 #define Z180_ITC_RMASK 0xc7
741 #define Z180_ITC_WMASK 0x87
742
743 /* 35 reserved */
744 #define Z180_IO35_RESET 0x00
745 #define Z180_IO35_RMASK 0xff
746 #define Z180_IO35_WMASK 0xff
747
748 /* 36 refresh control register */
749 #define Z180_RCR_REFE 0x80
750 #define Z180_RCR_REFW 0x40
751 #define Z180_RCR_CYC 0x03
752
753 #define Z180_RCR_RESET 0xc0
754 #define Z180_RCR_RMASK 0xc3
755 #define Z180_RCR_WMASK 0xc3
756
757 /* 37 reserved */
758 #define Z180_IO37_RESET 0x00
759 #define Z180_IO37_RMASK 0xff
760 #define Z180_IO37_WMASK 0xff
761
762 /* 38 MMU common base register */
763 #define Z180_CBR_CB 0xff
764
765 #define Z180_CBR_RESET 0x00
766 #define Z180_CBR_RMASK 0xff
767 #define Z180_CBR_WMASK 0xff
768
769 /* 39 MMU bank base register */
770 #define Z180_BBR_BB 0xff
771
772 #define Z180_BBR_RESET 0x00
773 #define Z180_BBR_RMASK 0xff
774 #define Z180_BBR_WMASK 0xff
775
776 /* 3a MMU common/bank area register */
777 #define Z180_CBAR_CA 0xf0
778 #define Z180_CBAR_BA 0x0f
779
780 #define Z180_CBAR_RESET 0xf0
781 #define Z180_CBAR_RMASK 0xff
782 #define Z180_CBAR_WMASK 0xff
783
784 /* 3b reserved */
785 #define Z180_IO3B_RESET 0x00
786 #define Z180_IO3B_RMASK 0xff
787 #define Z180_IO3B_WMASK 0xff
788
789 /* 3c reserved */
790 #define Z180_IO3C_RESET 0x00
791 #define Z180_IO3C_RMASK 0xff
792 #define Z180_IO3C_WMASK 0xff
793
794 /* 3d reserved */
795 #define Z180_IO3D_RESET 0x00
796 #define Z180_IO3D_RMASK 0xff
797 #define Z180_IO3D_WMASK 0xff
798
799 /* 3e operation mode control register */
800 #define Z180_OMCR_RESET 0x00
801 #define Z180_OMCR_RMASK 0xff
802 #define Z180_OMCR_WMASK 0xff
803
804 /* 3f I/O control register */
805 #define Z180_IOCR_RESET 0x00
806 #define Z180_IOCR_RMASK 0xff
807 #define Z180_IOCR_WMASK 0xff
808
809 static Z180_Regs Z180;
810
811 static UINT8 SZ[256]; /* zero and sign flags */
812 static UINT8 SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
813 static UINT8 SZP[256]; /* zero, sign and parity flags */
814 static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
815 static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
816
817 #if BIG_FLAGS_ARRAY
818 static UINT8 *SZHVC_add;
819 static UINT8 *SZHVC_sub;
820 #endif
821
z180_scan(INT32 nAction)822 void z180_scan(INT32 nAction)
823 {
824 if (nAction & ACB_DRIVER_DATA) {
825 struct BurnArea ba;
826
827 memset(&ba, 0, sizeof(ba));
828 ba.Data = &Z180;
829 ba.nLen = STRUCT_SIZE_HELPER(Z180_Regs, end_run);
830 ba.szName = "Z180 Registers";
831 BurnAcb(&ba);
832 }
833 }
834
835 static UINT8 z180_readcontrol(UINT32 port);
836 static void z180_writecontrol(UINT32 port, UINT8 data);
837 static int z180_dma0(int max_cycles);
838 static int z180_dma1(void);
839 static void z180_handle_io_timers(int cycles);
840
841 //static void z180_set_info(UINT32 state, cpuinfo *info);
842
843 #include "z180ops.h"
844 #include "z180tbl.h"
845
846 #include "z180cb.c"
847 #include "z180xy.c"
848 #include "z180dd.c"
849 #include "z180fd.c"
850 #include "z180ed.c"
851 #include "z180op.c"
852
z180_readcontrol(UINT32 port)853 static UINT8 z180_readcontrol(UINT32 port)
854 {
855 /* normal external readport */
856 UINT8 data = io_read_byte_8le(port);
857
858 /* remap internal I/O registers */
859 if((port & (IO_IOCR & 0xc0)) == (IO_IOCR & 0xc0))
860 port = port - (IO_IOCR & 0xc0);
861
862 /* but ignore the data and read the internal register */
863 switch (port + Z180_CNTLA0)
864 {
865 case Z180_CNTLA0:
866 data = IO_CNTLA0 & Z180_CNTLA0_RMASK;
867 break;
868
869 case Z180_CNTLA1:
870 data = IO_CNTLA1 & Z180_CNTLA1_RMASK;
871 break;
872
873 case Z180_CNTLB0:
874 data = IO_CNTLB0 & Z180_CNTLB0_RMASK;
875 break;
876
877 case Z180_CNTLB1:
878 data = IO_CNTLB1 & Z180_CNTLB1_RMASK;
879 break;
880
881 case Z180_STAT0:
882 data = IO_STAT0 & Z180_STAT0_RMASK;
883 data |= 0x02; // kludge for 20pacgal
884 break;
885
886 case Z180_STAT1:
887 data = IO_STAT1 & Z180_STAT1_RMASK;
888 break;
889
890 case Z180_TDR0:
891 data = IO_TDR0 & Z180_TDR0_RMASK;
892 break;
893
894 case Z180_TDR1:
895 data = IO_TDR1 & Z180_TDR1_RMASK;
896 break;
897
898 case Z180_RDR0:
899 data = IO_RDR0 & Z180_RDR0_RMASK;
900 break;
901
902 case Z180_RDR1:
903 data = IO_RDR1 & Z180_RDR1_RMASK;
904 break;
905
906 case Z180_CNTR:
907 data = IO_CNTR & Z180_CNTR_RMASK;
908 break;
909
910 case Z180_TRDR:
911 data = IO_TRDR & Z180_TRDR_RMASK;
912 break;
913
914 case Z180_TMDR0L:
915 data = Z180.tmdr_value[0] & Z180_TMDR0L_RMASK;
916 /* if timer is counting, latch the MSB and set the latch flag */
917 if ((IO_TCR & Z180_TCR_TDE0) == 0)
918 {
919 Z180.tmdr_latch |= 1;
920 Z180.tmdrh[0] = (Z180.tmdr_value[0] & 0xff00) >> 8;
921 }
922
923 if(Z180.read_tcr_tmdr[0])
924 {
925 Z180.tif[0] = 0; // reset TIF0
926 Z180.read_tcr_tmdr[0] = 0;
927 }
928 else
929 {
930 Z180.read_tcr_tmdr[0] = 1;
931 }
932 break;
933
934 case Z180_TMDR0H:
935 /* read latched value? */
936 if (Z180.tmdr_latch & 1)
937 {
938 Z180.tmdr_latch &= ~1;
939 data = Z180.tmdrh[0];
940 }
941 else
942 {
943 data = (Z180.tmdr_value[0] & 0xff00) >> 8;
944 }
945
946 if(Z180.read_tcr_tmdr[0])
947 {
948 Z180.tif[0] = 0; // reset TIF0
949 Z180.read_tcr_tmdr[0] = 0;
950 }
951 else
952 {
953 Z180.read_tcr_tmdr[0] = 1;
954 }
955 break;
956
957 case Z180_RLDR0L:
958 data = IO_RLDR0L & Z180_RLDR0L_RMASK;
959 break;
960
961 case Z180_RLDR0H:
962 data = IO_RLDR0H & Z180_RLDR0H_RMASK;
963 break;
964
965 case Z180_TCR:
966 data = (IO_TCR & Z180_TCR_RMASK) | (Z180.tif[0] << 6) | (Z180.tif[1] << 7);
967
968 if(Z180.read_tcr_tmdr[0])
969 {
970 Z180.tif[0] = 0; // reset TIF0
971 Z180.read_tcr_tmdr[0] = 0;
972 }
973 else
974 {
975 Z180.read_tcr_tmdr[0] = 1;
976 }
977
978 if(Z180.read_tcr_tmdr[1])
979 {
980 Z180.tif[1] = 0; // reset TIF1
981 Z180.read_tcr_tmdr[1] = 0;
982 }
983 else
984 {
985 Z180.read_tcr_tmdr[1] = 1;
986 }
987
988 break;
989
990 case Z180_IO11:
991 data = IO_IO11 & Z180_IO11_RMASK;
992 break;
993
994 case Z180_ASEXT0:
995 data = IO_ASEXT0 & Z180_ASEXT0_RMASK;
996 break;
997
998 case Z180_ASEXT1:
999 data = IO_ASEXT1 & Z180_ASEXT1_RMASK;
1000 break;
1001
1002 case Z180_TMDR1L:
1003 data = Z180.tmdr_value[1] & Z180_TMDR1L_RMASK;
1004 /* if timer is counting, latch the MSB and set the latch flag */
1005 if ((IO_TCR & Z180_TCR_TDE1) == 0)
1006 {
1007 Z180.tmdr_latch |= 2;
1008 Z180.tmdrh[1] = (Z180.tmdr_value[1] & 0xff00) >> 8;
1009 }
1010
1011 if(Z180.read_tcr_tmdr[1])
1012 {
1013 Z180.tif[1] = 0; // reset TIF1
1014 Z180.read_tcr_tmdr[1] = 0;
1015 }
1016 else
1017 {
1018 Z180.read_tcr_tmdr[1] = 1;
1019 }
1020 break;
1021
1022 case Z180_TMDR1H:
1023 /* read latched value? */
1024 if (Z180.tmdr_latch & 2)
1025 {
1026 Z180.tmdr_latch &= ~2;
1027 data = Z180.tmdrh[1];
1028 }
1029 else
1030 {
1031 data = (Z180.tmdr_value[1] & 0xff00) >> 8;
1032 }
1033
1034 if(Z180.read_tcr_tmdr[1])
1035 {
1036 Z180.tif[1] = 0; // reset TIF1
1037 Z180.read_tcr_tmdr[1] = 0;
1038 }
1039 else
1040 {
1041 Z180.read_tcr_tmdr[1] = 1;
1042 }
1043 break;
1044
1045 case Z180_RLDR1L:
1046 data = IO_RLDR1L & Z180_RLDR1L_RMASK;
1047 break;
1048
1049 case Z180_RLDR1H:
1050 data = IO_RLDR1H & Z180_RLDR1H_RMASK;
1051 break;
1052
1053 case Z180_FRC:
1054 data = IO_FRC & Z180_FRC_RMASK;
1055 break;
1056
1057 case Z180_IO19:
1058 data = IO_IO19 & Z180_IO19_RMASK;
1059 break;
1060
1061 case Z180_ASTC0L:
1062 data = IO_ASTC0L & Z180_ASTC0L_RMASK;
1063 break;
1064
1065 case Z180_ASTC0H:
1066 data = IO_ASTC0H & Z180_ASTC0H_RMASK;
1067 break;
1068
1069 case Z180_ASTC1L:
1070 data = IO_ASTC1L & Z180_ASTC1L_RMASK;
1071 break;
1072
1073 case Z180_ASTC1H:
1074 data = IO_ASTC1H & Z180_ASTC1H_RMASK;
1075 break;
1076
1077 case Z180_CMR:
1078 data = IO_CMR & Z180_CMR_RMASK;
1079 break;
1080
1081 case Z180_CCR:
1082 data = IO_CCR & Z180_CCR_RMASK;
1083 break;
1084
1085 case Z180_SAR0L:
1086 data = IO_SAR0L & Z180_SAR0L_RMASK;
1087 break;
1088
1089 case Z180_SAR0H:
1090 data = IO_SAR0H & Z180_SAR0H_RMASK;
1091 break;
1092
1093 case Z180_SAR0B:
1094 data = IO_SAR0B & Z180_SAR0B_RMASK;
1095 break;
1096
1097 case Z180_DAR0L:
1098 data = IO_DAR0L & Z180_DAR0L_RMASK;
1099 break;
1100
1101 case Z180_DAR0H:
1102 data = IO_DAR0H & Z180_DAR0H_RMASK;
1103 break;
1104
1105 case Z180_DAR0B:
1106 data = IO_DAR0B & Z180_DAR0B_RMASK;
1107 break;
1108
1109 case Z180_BCR0L:
1110 data = IO_BCR0L & Z180_BCR0L_RMASK;
1111 break;
1112
1113 case Z180_BCR0H:
1114 data = IO_BCR0H & Z180_BCR0H_RMASK;
1115 break;
1116
1117 case Z180_MAR1L:
1118 data = IO_MAR1L & Z180_MAR1L_RMASK;
1119 break;
1120
1121 case Z180_MAR1H:
1122 data = IO_MAR1H & Z180_MAR1H_RMASK;
1123 break;
1124
1125 case Z180_MAR1B:
1126 data = IO_MAR1B & Z180_MAR1B_RMASK;
1127 break;
1128
1129 case Z180_IAR1L:
1130 data = IO_IAR1L & Z180_IAR1L_RMASK;
1131 break;
1132
1133 case Z180_IAR1H:
1134 data = IO_IAR1H & Z180_IAR1H_RMASK;
1135 break;
1136
1137 case Z180_IAR1B:
1138 data = IO_IAR1B & Z180_IAR1B_RMASK;
1139 break;
1140
1141 case Z180_BCR1L:
1142 data = IO_BCR1L & Z180_BCR1L_RMASK;
1143 break;
1144
1145 case Z180_BCR1H:
1146 data = IO_BCR1H & Z180_BCR1H_RMASK;
1147 break;
1148
1149 case Z180_DSTAT:
1150 data = IO_DSTAT & Z180_DSTAT_RMASK;
1151 break;
1152
1153 case Z180_DMODE:
1154 data = IO_DMODE & Z180_DMODE_RMASK;
1155 break;
1156
1157 case Z180_DCNTL:
1158 data = IO_DCNTL & Z180_DCNTL_RMASK;
1159 break;
1160
1161 case Z180_IL:
1162 data = IO_IL & Z180_IL_RMASK;
1163 break;
1164
1165 case Z180_ITC:
1166 data = IO_ITC & Z180_ITC_RMASK;
1167 break;
1168
1169 case Z180_IO35:
1170 data = IO_IO35 & Z180_IO35_RMASK;
1171 break;
1172
1173 case Z180_RCR:
1174 data = IO_RCR & Z180_RCR_RMASK;
1175 break;
1176
1177 case Z180_IO37:
1178 data = IO_IO37 & Z180_IO37_RMASK;
1179 break;
1180
1181 case Z180_CBR:
1182 data = IO_CBR & Z180_CBR_RMASK;
1183 break;
1184
1185 case Z180_BBR:
1186 data = IO_BBR & Z180_BBR_RMASK;
1187 break;
1188
1189 case Z180_CBAR:
1190 data = IO_CBAR & Z180_CBAR_RMASK;
1191 break;
1192
1193 case Z180_IO3B:
1194 data = IO_IO3B & Z180_IO3B_RMASK;
1195 break;
1196
1197 case Z180_IO3C:
1198 data = IO_IO3C & Z180_IO3C_RMASK;
1199 break;
1200
1201 case Z180_IO3D:
1202 data = IO_IO3D & Z180_IO3D_RMASK;
1203 break;
1204
1205 case Z180_OMCR:
1206 data = IO_OMCR & Z180_OMCR_RMASK;
1207 break;
1208
1209 case Z180_IOCR:
1210 data = IO_IOCR & Z180_IOCR_RMASK;
1211 break;
1212 }
1213
1214 return data;
1215 }
1216
z180_writecontrol(UINT32 port,UINT8 data)1217 static void z180_writecontrol(UINT32 port, UINT8 data)
1218 {
1219 /* normal external write port */
1220 io_write_byte_8le(port, data);
1221
1222 /* remap internal I/O registers */
1223 if((port & (IO_IOCR & 0xc0)) == (IO_IOCR & 0xc0))
1224 port = port - (IO_IOCR & 0xc0);
1225
1226 /* store the data in the internal register */
1227 switch (port + Z180_CNTLA0)
1228 {
1229 case Z180_CNTLA0:
1230 IO_CNTLA0 = (IO_CNTLA0 & ~Z180_CNTLA0_WMASK) | (data & Z180_CNTLA0_WMASK);
1231 break;
1232
1233 case Z180_CNTLA1:
1234 IO_CNTLA1 = (IO_CNTLA1 & ~Z180_CNTLA1_WMASK) | (data & Z180_CNTLA1_WMASK);
1235 break;
1236
1237 case Z180_CNTLB0:
1238 IO_CNTLB0 = (IO_CNTLB0 & ~Z180_CNTLB0_WMASK) | (data & Z180_CNTLB0_WMASK);
1239 break;
1240
1241 case Z180_CNTLB1:
1242 IO_CNTLB1 = (IO_CNTLB1 & ~Z180_CNTLB1_WMASK) | (data & Z180_CNTLB1_WMASK);
1243 break;
1244
1245 case Z180_STAT0:
1246 IO_STAT0 = (IO_STAT0 & ~Z180_STAT0_WMASK) | (data & Z180_STAT0_WMASK);
1247 break;
1248
1249 case Z180_STAT1:
1250 IO_STAT1 = (IO_STAT1 & ~Z180_STAT1_WMASK) | (data & Z180_STAT1_WMASK);
1251 break;
1252
1253 case Z180_TDR0:
1254 IO_TDR0 = (IO_TDR0 & ~Z180_TDR0_WMASK) | (data & Z180_TDR0_WMASK);
1255 break;
1256
1257 case Z180_TDR1:
1258 IO_TDR1 = (IO_TDR1 & ~Z180_TDR1_WMASK) | (data & Z180_TDR1_WMASK);
1259 break;
1260
1261 case Z180_RDR0:
1262 IO_RDR0 = (IO_RDR0 & ~Z180_RDR0_WMASK) | (data & Z180_RDR0_WMASK);
1263 break;
1264
1265 case Z180_RDR1:
1266 IO_RDR1 = (IO_RDR1 & ~Z180_RDR1_WMASK) | (data & Z180_RDR1_WMASK);
1267 break;
1268
1269 case Z180_CNTR:
1270 IO_CNTR = (IO_CNTR & ~Z180_CNTR_WMASK) | (data & Z180_CNTR_WMASK);
1271 break;
1272
1273 case Z180_TRDR:
1274 IO_TRDR = (IO_TRDR & ~Z180_TRDR_WMASK) | (data & Z180_TRDR_WMASK);
1275 break;
1276
1277 case Z180_TMDR0L:
1278 IO_TMDR0L = data & Z180_TMDR0L_WMASK;
1279 Z180.tmdr_value[0] = (Z180.tmdr_value[0] & 0xff00) | IO_TMDR0L;
1280 break;
1281
1282 case Z180_TMDR0H:
1283 IO_TMDR0H = data & Z180_TMDR0H_WMASK;
1284 Z180.tmdr_value[0] = (Z180.tmdr_value[0] & 0x00ff) | (IO_TMDR0H << 8);
1285 break;
1286
1287 case Z180_RLDR0L:
1288 IO_RLDR0L = (IO_RLDR0L & ~Z180_RLDR0L_WMASK) | (data & Z180_RLDR0L_WMASK);
1289 break;
1290
1291 case Z180_RLDR0H:
1292 IO_RLDR0H = (IO_RLDR0H & ~Z180_RLDR0H_WMASK) | (data & Z180_RLDR0H_WMASK);
1293 break;
1294
1295 case Z180_TCR:
1296 {
1297 UINT16 old = IO_TCR;
1298 /* Force reload on state change */
1299 IO_TCR = (IO_TCR & ~Z180_TCR_WMASK) | (data & Z180_TCR_WMASK);
1300 if (!(old & Z180_TCR_TDE0) && (IO_TCR & Z180_TCR_TDE0))
1301 Z180.tmdr_value[0] = 0; //IO_RLDR0L | (IO_RLDR0H << 8);
1302 if (!(old & Z180_TCR_TDE1) && (IO_TCR & Z180_TCR_TDE1))
1303 Z180.tmdr_value[1] = 0; //IO_RLDR1L | (IO_RLDR1H << 8);
1304 }
1305 break;
1306
1307 case Z180_IO11:
1308 IO_IO11 = (IO_IO11 & ~Z180_IO11_WMASK) | (data & Z180_IO11_WMASK);
1309 break;
1310
1311 case Z180_ASEXT0:
1312 IO_ASEXT0 = (IO_ASEXT0 & ~Z180_ASEXT0_WMASK) | (data & Z180_ASEXT0_WMASK);
1313 break;
1314
1315 case Z180_ASEXT1:
1316 IO_ASEXT1 = (IO_ASEXT1 & ~Z180_ASEXT1_WMASK) | (data & Z180_ASEXT1_WMASK);
1317 break;
1318
1319 case Z180_TMDR1L:
1320 IO_TMDR1L = data & Z180_TMDR1L_WMASK;
1321 Z180.tmdr_value[1] = (Z180.tmdr_value[1] & 0xff00) | IO_TMDR1L;
1322 break;
1323
1324 case Z180_TMDR1H:
1325 IO_TMDR1H = data & Z180_TMDR1H_WMASK;
1326 Z180.tmdr_value[1] = (Z180.tmdr_value[1] & 0x00ff) | IO_TMDR1H;
1327 break;
1328
1329 case Z180_RLDR1L:
1330 IO_RLDR1L = (IO_RLDR1L & ~Z180_RLDR1L_WMASK) | (data & Z180_RLDR1L_WMASK);
1331 break;
1332
1333 case Z180_RLDR1H:
1334 IO_RLDR1H = (IO_RLDR1H & ~Z180_RLDR1H_WMASK) | (data & Z180_RLDR1H_WMASK);
1335 break;
1336
1337 case Z180_FRC:
1338 IO_FRC = (IO_FRC & ~Z180_FRC_WMASK) | (data & Z180_FRC_WMASK);
1339 break;
1340
1341 case Z180_IO19:
1342 IO_IO19 = (IO_IO19 & ~Z180_IO19_WMASK) | (data & Z180_IO19_WMASK);
1343 break;
1344
1345 case Z180_ASTC0L:
1346 IO_ASTC0L = (IO_ASTC0L & ~Z180_ASTC0L_WMASK) | (data & Z180_ASTC0L_WMASK);
1347 break;
1348
1349 case Z180_ASTC0H:
1350 IO_ASTC0H = (IO_ASTC0H & ~Z180_ASTC0H_WMASK) | (data & Z180_ASTC0H_WMASK);
1351 break;
1352
1353 case Z180_ASTC1L:
1354 IO_ASTC1L = (IO_ASTC1L & ~Z180_ASTC1L_WMASK) | (data & Z180_ASTC1L_WMASK);
1355 break;
1356
1357 case Z180_ASTC1H:
1358 IO_ASTC1H = (IO_ASTC1H & ~Z180_ASTC1H_WMASK) | (data & Z180_ASTC1H_WMASK);
1359 break;
1360
1361 case Z180_CMR:
1362 IO_CMR = (IO_CMR & ~Z180_CMR_WMASK) | (data & Z180_CMR_WMASK);
1363 break;
1364
1365 case Z180_CCR:
1366 IO_CCR = (IO_CCR & ~Z180_CCR_WMASK) | (data & Z180_CCR_WMASK);
1367 break;
1368
1369 case Z180_SAR0L:
1370 IO_SAR0L = (IO_SAR0L & ~Z180_SAR0L_WMASK) | (data & Z180_SAR0L_WMASK);
1371 break;
1372
1373 case Z180_SAR0H:
1374 IO_SAR0H = (IO_SAR0H & ~Z180_SAR0H_WMASK) | (data & Z180_SAR0H_WMASK);
1375 break;
1376
1377 case Z180_SAR0B:
1378 IO_SAR0B = (IO_SAR0B & ~Z180_SAR0B_WMASK) | (data & Z180_SAR0B_WMASK);
1379 break;
1380
1381 case Z180_DAR0L:
1382 IO_DAR0L = (IO_DAR0L & ~Z180_DAR0L_WMASK) | (data & Z180_DAR0L_WMASK);
1383 break;
1384
1385 case Z180_DAR0H:
1386 IO_DAR0H = (IO_DAR0H & ~Z180_DAR0H_WMASK) | (data & Z180_DAR0H_WMASK);
1387 break;
1388
1389 case Z180_DAR0B:
1390 IO_DAR0B = (IO_DAR0B & ~Z180_DAR0B_WMASK) | (data & Z180_DAR0B_WMASK);
1391 break;
1392
1393 case Z180_BCR0L:
1394 IO_BCR0L = (IO_BCR0L & ~Z180_BCR0L_WMASK) | (data & Z180_BCR0L_WMASK);
1395 break;
1396
1397 case Z180_BCR0H:
1398 IO_BCR0H = (IO_BCR0H & ~Z180_BCR0H_WMASK) | (data & Z180_BCR0H_WMASK);
1399 break;
1400
1401 case Z180_MAR1L:
1402 IO_MAR1L = (IO_MAR1L & ~Z180_MAR1L_WMASK) | (data & Z180_MAR1L_WMASK);
1403 break;
1404
1405 case Z180_MAR1H:
1406 IO_MAR1H = (IO_MAR1H & ~Z180_MAR1H_WMASK) | (data & Z180_MAR1H_WMASK);
1407 break;
1408
1409 case Z180_MAR1B:
1410 IO_MAR1B = (IO_MAR1B & ~Z180_MAR1B_WMASK) | (data & Z180_MAR1B_WMASK);
1411 break;
1412
1413 case Z180_IAR1L:
1414 IO_IAR1L = (IO_IAR1L & ~Z180_IAR1L_WMASK) | (data & Z180_IAR1L_WMASK);
1415 break;
1416
1417 case Z180_IAR1H:
1418 IO_IAR1H = (IO_IAR1H & ~Z180_IAR1H_WMASK) | (data & Z180_IAR1H_WMASK);
1419 break;
1420
1421 case Z180_IAR1B:
1422 IO_IAR1B = (IO_IAR1B & ~Z180_IAR1B_WMASK) | (data & Z180_IAR1B_WMASK);
1423 break;
1424
1425 case Z180_BCR1L:
1426 IO_BCR1L = (IO_BCR1L & ~Z180_BCR1L_WMASK) | (data & Z180_BCR1L_WMASK);
1427 break;
1428
1429 case Z180_BCR1H:
1430 IO_BCR1H = (IO_BCR1H & ~Z180_BCR1H_WMASK) | (data & Z180_BCR1H_WMASK);
1431 break;
1432
1433 case Z180_DSTAT:
1434 IO_DSTAT = (IO_DSTAT & ~Z180_DSTAT_WMASK) | (data & Z180_DSTAT_WMASK);
1435 if ((data & (Z180_DSTAT_DE1 | Z180_DSTAT_DWE1)) == Z180_DSTAT_DE1)
1436 IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
1437 if ((data & (Z180_DSTAT_DE0 | Z180_DSTAT_DWE0)) == Z180_DSTAT_DE0)
1438 IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
1439 break;
1440
1441 case Z180_DMODE:
1442 IO_DMODE = (IO_DMODE & ~Z180_DMODE_WMASK) | (data & Z180_DMODE_WMASK);
1443 break;
1444
1445 case Z180_DCNTL:
1446 IO_DCNTL = (IO_DCNTL & ~Z180_DCNTL_WMASK) | (data & Z180_DCNTL_WMASK);
1447 break;
1448
1449 case Z180_IL:
1450 IO_IL = (IO_IL & ~Z180_IL_WMASK) | (data & Z180_IL_WMASK);
1451 break;
1452
1453 case Z180_ITC:
1454 IO_ITC = (IO_ITC & ~Z180_ITC_WMASK) | (data & Z180_ITC_WMASK);
1455 break;
1456
1457 case Z180_IO35:
1458 IO_IO35 = (IO_IO35 & ~Z180_IO35_WMASK) | (data & Z180_IO35_WMASK);
1459 break;
1460
1461 case Z180_RCR:
1462 IO_RCR = (IO_RCR & ~Z180_RCR_WMASK) | (data & Z180_RCR_WMASK);
1463 break;
1464
1465 case Z180_IO37:
1466 IO_IO37 = (IO_IO37 & ~Z180_IO37_WMASK) | (data & Z180_IO37_WMASK);
1467 break;
1468
1469 case Z180_CBR:
1470 IO_CBR = (IO_CBR & ~Z180_CBR_WMASK) | (data & Z180_CBR_WMASK);
1471 z180_mmu();
1472 break;
1473
1474 case Z180_BBR:
1475 IO_BBR = (IO_BBR & ~Z180_BBR_WMASK) | (data & Z180_BBR_WMASK);
1476 z180_mmu();
1477 break;
1478
1479 case Z180_CBAR:
1480 IO_CBAR = (IO_CBAR & ~Z180_CBAR_WMASK) | (data & Z180_CBAR_WMASK);
1481 z180_mmu();
1482 break;
1483
1484 case Z180_IO3B:
1485 IO_IO3B = (IO_IO3B & ~Z180_IO3B_WMASK) | (data & Z180_IO3B_WMASK);
1486 break;
1487
1488 case Z180_IO3C:
1489 IO_IO3C = (IO_IO3C & ~Z180_IO3C_WMASK) | (data & Z180_IO3C_WMASK);
1490 break;
1491
1492 case Z180_IO3D:
1493 IO_IO3D = (IO_IO3D & ~Z180_IO3D_WMASK) | (data & Z180_IO3D_WMASK);
1494 break;
1495
1496 case Z180_OMCR:
1497 IO_OMCR = (IO_OMCR & ~Z180_OMCR_WMASK) | (data & Z180_OMCR_WMASK);
1498 break;
1499
1500 case Z180_IOCR:
1501 IO_IOCR = (IO_IOCR & ~Z180_IOCR_WMASK) | (data & Z180_IOCR_WMASK);
1502 break;
1503 }
1504 }
1505
z180_dma0(int max_cycles)1506 static int z180_dma0(int max_cycles)
1507 {
1508 UINT32 sar0 = 65536 * IO_SAR0B + 256 * IO_SAR0H + IO_SAR0L;
1509 UINT32 dar0 = 65536 * IO_DAR0B + 256 * IO_DAR0H + IO_DAR0L;
1510 int bcr0 = 256 * IO_BCR0H + IO_BCR0L;
1511
1512 if (bcr0 == 0)
1513 {
1514 bcr0 = 0x10000;
1515 }
1516
1517 int count = (IO_DMODE & Z180_DMODE_MMOD) ? bcr0 : 1;
1518 int cycles = 0;
1519
1520 if (!(IO_DSTAT & Z180_DSTAT_DE0))
1521 {
1522 return 0;
1523 }
1524
1525 while (count > 0)
1526 {
1527 Z180.extra_cycles = 0;
1528 /* last transfer happening now? */
1529 if (bcr0 == 1)
1530 {
1531 Z180.iol |= Z180_TEND0;
1532 }
1533 switch( IO_DMODE & (Z180_DMODE_SM | Z180_DMODE_DM) )
1534 {
1535 case 0x00: /* memory SAR0+1 to memory DAR0+1 */
1536 program_write_byte_8le(dar0++, program_read_byte_8le(sar0++));
1537 cycles += (IO_DCNTL >> 6) * 2; // memory wait states
1538 bcr0--;
1539 break;
1540 case 0x04: /* memory SAR0-1 to memory DAR0+1 */
1541 program_write_byte_8le(dar0++, program_read_byte_8le(sar0--));
1542 cycles += (IO_DCNTL >> 6) * 2; // memory wait states
1543 bcr0--;
1544 break;
1545 case 0x08: /* memory SAR0 fixed to memory DAR0+1 */
1546 program_write_byte_8le(dar0++, program_read_byte_8le(sar0));
1547 cycles += (IO_DCNTL >> 6) * 2; // memory wait states
1548 bcr0--;
1549 break;
1550 case 0x0c: /* I/O SAR0 fixed to memory DAR0+1 */
1551 if (Z180.iol & Z180_DREQ0)
1552 {
1553 program_write_byte_8le(dar0++, IN(sar0));
1554 cycles += IO_DCNTL >> 6; // memory wait states
1555 bcr0--;
1556 /* edge sensitive DREQ0 ? */
1557 if (IO_DCNTL & Z180_DCNTL_DMS0)
1558 {
1559 Z180.iol &= ~Z180_DREQ0;
1560 count = 0;
1561 }
1562 }
1563 break;
1564 case 0x10: /* memory SAR0+1 to memory DAR0-1 */
1565 program_write_byte_8le(dar0--, program_read_byte_8le(sar0++));
1566 cycles += (IO_DCNTL >> 6) * 2; // memory wait states
1567 bcr0--;
1568 break;
1569 case 0x14: /* memory SAR0-1 to memory DAR0-1 */
1570 program_write_byte_8le(dar0--, program_read_byte_8le(sar0--));
1571 cycles += (IO_DCNTL >> 6) * 2; // memory wait states
1572 bcr0--;
1573 break;
1574 case 0x18: /* memory SAR0 fixed to memory DAR0-1 */
1575 program_write_byte_8le(dar0--, program_read_byte_8le(sar0));
1576 cycles += (IO_DCNTL >> 6) * 2; // memory wait states
1577 bcr0--;
1578 break;
1579 case 0x1c: /* I/O SAR0 fixed to memory DAR0-1 */
1580 if (Z180.iol & Z180_DREQ0)
1581 {
1582 program_write_byte_8le(dar0--, IN(sar0));
1583 cycles += IO_DCNTL >> 6; // memory wait states
1584 bcr0--;
1585 /* edge sensitive DREQ0 ? */
1586 if (IO_DCNTL & Z180_DCNTL_DMS0)
1587 {
1588 Z180.iol &= ~Z180_DREQ0;
1589 count = 0;
1590 }
1591 }
1592 break;
1593 case 0x20: /* memory SAR0+1 to memory DAR0 fixed */
1594 program_write_byte_8le(dar0, program_read_byte_8le(sar0++));
1595 cycles += (IO_DCNTL >> 6) * 2; // memory wait states
1596 bcr0--;
1597 break;
1598 case 0x24: /* memory SAR0-1 to memory DAR0 fixed */
1599 program_write_byte_8le(dar0, program_read_byte_8le(sar0--));
1600 cycles += (IO_DCNTL >> 6) * 2; // memory wait states
1601 bcr0--;
1602 break;
1603 case 0x28: /* reserved */
1604 break;
1605 case 0x2c: /* reserved */
1606 break;
1607 case 0x30: /* memory SAR0+1 to I/O DAR0 fixed */
1608 if (Z180.iol & Z180_DREQ0)
1609 {
1610 OUT(dar0, program_read_byte_8le(sar0++));
1611 cycles += IO_DCNTL >> 6; // memory wait states
1612 bcr0--;
1613 /* edge sensitive DREQ0 ? */
1614 if (IO_DCNTL & Z180_DCNTL_DMS0)
1615 {
1616 Z180.iol &= ~Z180_DREQ0;
1617 count = 0;
1618 }
1619 }
1620 break;
1621 case 0x34: /* memory SAR0-1 to I/O DAR0 fixed */
1622 if (Z180.iol & Z180_DREQ0)
1623 {
1624 OUT(dar0, program_read_byte_8le(sar0--));
1625 cycles += IO_DCNTL >> 6; // memory wait states
1626 bcr0--;
1627 /* edge sensitive DREQ0 ? */
1628 if (IO_DCNTL & Z180_DCNTL_DMS0)
1629 {
1630 Z180.iol &= ~Z180_DREQ0;
1631 count = 0;
1632 }
1633 }
1634 break;
1635 case 0x38: /* reserved */
1636 break;
1637 case 0x3c: /* reserved */
1638 break;
1639 }
1640 count--;
1641 cycles += 6 + Z180.extra_cycles;
1642 if (cycles > max_cycles)
1643 break;
1644 }
1645
1646 IO_SAR0L = sar0;
1647 IO_SAR0H = sar0 >> 8;
1648 IO_SAR0B = sar0 >> 16;
1649 IO_DAR0L = dar0;
1650 IO_DAR0H = dar0 >> 8;
1651 IO_DAR0B = dar0 >> 16;
1652 IO_BCR0L = bcr0;
1653 IO_BCR0H = bcr0 >> 8;
1654
1655 /* DMA terminal count? */
1656 if (bcr0 == 0)
1657 {
1658 Z180.iol &= ~Z180_TEND0;
1659 IO_DSTAT &= ~Z180_DSTAT_DE0;
1660 /* terminal count interrupt enabled? */
1661 if (IO_DSTAT & Z180_DSTAT_DIE0 && _IFF1) {
1662 Z180.int_pending[Z180_INT_DMA0] = 1;
1663 }
1664 }
1665 return cycles;
1666 }
1667
z180_dma1(void)1668 static int z180_dma1(void)
1669 {
1670 UINT32 mar1 = 65536 * IO_MAR1B + 256 * IO_MAR1H + IO_MAR1L;
1671 UINT32 iar1 = 256 * IO_IAR1H + IO_IAR1L;
1672 int bcr1 = 256 * IO_BCR1H + IO_BCR1L;
1673
1674 if (bcr1 == 0)
1675 {
1676 bcr1 = 0x10000;
1677 }
1678
1679 int cycles = 0;
1680
1681 if ((Z180.iol & Z180_DREQ1) == 0)
1682 return 0;
1683
1684 if (!(IO_DSTAT & Z180_DSTAT_DE1))
1685 {
1686 return 0;
1687 }
1688
1689 /* last transfer happening now? */
1690 if (bcr1 == 1)
1691 {
1692 Z180.iol |= Z180_TEND1;
1693 }
1694
1695 Z180.extra_cycles = 0;
1696
1697 switch (IO_DCNTL & (Z180_DCNTL_DIM1 | Z180_DCNTL_DIM0))
1698 {
1699 case 0x00: /* memory MAR1+1 to I/O IAR1 fixed */
1700 io_write_byte_8le(iar1, program_read_byte_8le(mar1++));
1701 break;
1702 case 0x01: /* memory MAR1-1 to I/O IAR1 fixed */
1703 io_write_byte_8le(iar1, program_read_byte_8le(mar1--));
1704 break;
1705 case 0x02: /* I/O IAR1 fixed to memory MAR1+1 */
1706 program_write_byte_8le(mar1++, io_read_byte_8le(iar1));
1707 break;
1708 case 0x03: /* I/O IAR1 fixed to memory MAR1-1 */
1709 program_write_byte_8le(mar1--, io_read_byte_8le(iar1));
1710 break;
1711 }
1712
1713 cycles += IO_DCNTL >> 6; // memory wait states
1714 cycles += Z180.extra_cycles; // use extra_cycles for I/O wait states
1715
1716 /* edge sensitive DREQ1 ? */
1717 if (IO_DCNTL & Z180_DCNTL_DIM1)
1718 Z180.iol &= ~Z180_DREQ1;
1719
1720 IO_MAR1L = mar1;
1721 IO_MAR1H = mar1 >> 8;
1722 IO_MAR1B = mar1 >> 16;
1723 IO_BCR1L = bcr1;
1724 IO_BCR1H = bcr1 >> 8;
1725
1726 /* DMA terminal count? */
1727 if (bcr1 == 0)
1728 {
1729 Z180.iol &= ~Z180_TEND1;
1730 IO_DSTAT &= ~Z180_DSTAT_DE1;
1731 if (IO_DSTAT & Z180_DSTAT_DIE1 && _IFF1) {
1732 Z180.int_pending[Z180_INT_DMA1] = 1;
1733 }
1734 }
1735
1736 /* six cycles per transfer (minimum) */
1737 return 6 + cycles;
1738 }
1739
z180_write_iolines(UINT32 data)1740 void z180_write_iolines(UINT32 data)
1741 {
1742 UINT32 changes = Z180.iol ^ data;
1743
1744 /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
1745 if (changes & Z180_CKA0)
1746 {
1747 Z180.iol = (Z180.iol & ~Z180_CKA0) | (data & Z180_CKA0);
1748 }
1749
1750 /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
1751 if (changes & Z180_CKA1)
1752 {
1753 Z180.iol = (Z180.iol & ~Z180_CKA1) | (data & Z180_CKA1);
1754 }
1755
1756 /* I/O serial clock (active high) */
1757 if (changes & Z180_CKS)
1758 {
1759 Z180.iol = (Z180.iol & ~Z180_CKS) | (data & Z180_CKS);
1760 }
1761
1762 /* I clear to send 0 (active low) */
1763 if (changes & Z180_CTS0)
1764 {
1765 Z180.iol = (Z180.iol & ~Z180_CTS0) | (data & Z180_CTS0);
1766 }
1767
1768 /* I clear to send 1 (active low) or RXS (mux) */
1769 if (changes & Z180_CTS1)
1770 {
1771 Z180.iol = (Z180.iol & ~Z180_CTS1) | (data & Z180_CTS1);
1772 }
1773
1774 /* I data carrier detect (active low) */
1775 if (changes & Z180_DCD0)
1776 {
1777 Z180.iol = (Z180.iol & ~Z180_DCD0) | (data & Z180_DCD0);
1778 }
1779
1780 /* I data request DMA ch 0 (active low) or CKA0 (mux) */
1781 if (changes & Z180_DREQ0)
1782 {
1783 Z180.iol = (Z180.iol & ~Z180_DREQ0) | (data & Z180_DREQ0);
1784 }
1785
1786 /* I data request DMA ch 1 (active low) */
1787 if (changes & Z180_DREQ1)
1788 {
1789 Z180.iol = (Z180.iol & ~Z180_DREQ1) | (data & Z180_DREQ1);
1790 }
1791
1792 /* I asynchronous receive data 0 (active high) */
1793 if (changes & Z180_RXA0)
1794 {
1795 Z180.iol = (Z180.iol & ~Z180_RXA0) | (data & Z180_RXA0);
1796 }
1797
1798 /* I asynchronous receive data 1 (active high) */
1799 if (changes & Z180_RXA1)
1800 {
1801 Z180.iol = (Z180.iol & ~Z180_RXA1) | (data & Z180_RXA1);
1802 }
1803
1804 /* I clocked serial receive data (active high) or CTS1 (mux) */
1805 if (changes & Z180_RXS)
1806 {
1807 Z180.iol = (Z180.iol & ~Z180_RXS) | (data & Z180_RXS);
1808 }
1809
1810 /* O request to send (active low) */
1811 if (changes & Z180_RTS0)
1812 {
1813
1814 }
1815
1816 /* O transfer end 0 (active low) or CKA1 (mux) */
1817 if (changes & Z180_TEND0)
1818 {
1819
1820 }
1821
1822 /* O transfer end 1 (active low) */
1823 if (changes & Z180_TEND1)
1824 {
1825
1826 }
1827
1828 /* O transfer out (PRT channel, active low) or A18 (mux) */
1829 if (changes & Z180_A18_TOUT)
1830 {
1831
1832 }
1833
1834 /* O asynchronous transmit data 0 (active high) */
1835 if (changes & Z180_TXA0)
1836 {
1837
1838 }
1839
1840 /* O asynchronous transmit data 1 (active high) */
1841 if (changes & Z180_TXA1)
1842 {
1843
1844 }
1845
1846 /* O clocked serial transmit data (active high) */
1847 if (changes & Z180_TXS)
1848 {
1849
1850 }
1851 }
1852
z180_init(int index,int clock,int (* irqcallback)(int))1853 void z180_init(int index, int clock, /*const void *config,*/ int (*irqcallback)(int))
1854 {
1855 Z180.daisy = NULL;
1856 /*if (config)
1857 Z180.daisy = z80daisy_init(Machine, Machine->config->cpu[cpu_getactivecpu()].tag, config);*/
1858 Z180.irq_callback = irqcallback;
1859
1860 #if BIG_FLAGS_ARRAY
1861 /* allocate big flag arrays once */
1862 SZHVC_add = (UINT8 *)BurnMalloc(2*256*256*sizeof(UINT8));
1863 SZHVC_sub = (UINT8 *)BurnMalloc(2*256*256*sizeof(UINT8));
1864 #endif
1865 }
1866
z180_exit()1867 void z180_exit()
1868 {
1869 memset(&Z180, 0, sizeof(Z180));
1870
1871 #if BIG_FLAGS_ARRAY
1872 BurnFree(SZHVC_add);
1873 BurnFree(SZHVC_sub);
1874 #endif
1875 }
1876
1877 /****************************************************************************
1878 * Reset registers to their initial values
1879 ****************************************************************************/
z180_reset(void)1880 void z180_reset(void)
1881 {
1882 // z80_irq_daisy_chain *save_daisy;
1883 int (*save_irqcallback)(int);
1884 int i, p;
1885 #if BIG_FLAGS_ARRAY
1886 int oldval, newval, val;
1887 UINT8 *padd, *padc, *psub, *psbc;
1888 padd = &SZHVC_add[ 0*256];
1889 padc = &SZHVC_add[256*256];
1890 psub = &SZHVC_sub[ 0*256];
1891 psbc = &SZHVC_sub[256*256];
1892 for (oldval = 0; oldval < 256; oldval++)
1893 {
1894 for (newval = 0; newval < 256; newval++)
1895 {
1896 /* add or adc w/o carry set */
1897 val = newval - oldval;
1898 *padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
1899 *padd |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1900
1901 if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF;
1902 if( newval < oldval ) *padd |= CF;
1903 if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF;
1904 padd++;
1905
1906 /* adc with carry set */
1907 val = newval - oldval - 1;
1908 *padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
1909 *padc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1910 if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF;
1911 if( newval <= oldval ) *padc |= CF;
1912 if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF;
1913 padc++;
1914
1915 /* cp, sub or sbc w/o carry set */
1916 val = oldval - newval;
1917 *psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
1918 *psub |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1919 if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF;
1920 if( newval > oldval ) *psub |= CF;
1921 if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF;
1922 psub++;
1923
1924 /* sbc with carry set */
1925 val = oldval - newval - 1;
1926 *psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
1927 *psbc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1928 if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF;
1929 if( newval >= oldval ) *psbc |= CF;
1930 if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF;
1931 psbc++;
1932 }
1933 }
1934 #endif
1935 for (i = 0; i < 256; i++)
1936 {
1937 p = 0;
1938 if( i&0x01 ) ++p;
1939 if( i&0x02 ) ++p;
1940 if( i&0x04 ) ++p;
1941 if( i&0x08 ) ++p;
1942 if( i&0x10 ) ++p;
1943 if( i&0x20 ) ++p;
1944 if( i&0x40 ) ++p;
1945 if( i&0x80 ) ++p;
1946 SZ[i] = i ? i & SF : ZF;
1947 SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */
1948 SZ_BIT[i] = i ? i & SF : ZF | PF;
1949 SZ_BIT[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */
1950 SZP[i] = SZ[i] | ((p & 1) ? 0 : PF);
1951 SZHV_inc[i] = SZ[i];
1952 if( i == 0x80 ) SZHV_inc[i] |= VF;
1953 if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF;
1954 SZHV_dec[i] = SZ[i] | NF;
1955 if( i == 0x7f ) SZHV_dec[i] |= VF;
1956 if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF;
1957 }
1958
1959 //save_daisy = Z180.daisy;
1960 save_irqcallback = Z180.irq_callback;
1961 memset(&Z180, 0, sizeof(Z180));
1962 //Z180.daisy = save_daisy;
1963 Z180.irq_callback = save_irqcallback;
1964 _IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */
1965 _F = ZF; /* Zero flag is set */
1966 Z180.nmi_state = Z180_CLEAR_LINE;
1967 Z180.nmi_pending = 0;
1968 Z180.nmi_hold = 0;
1969 Z180.irq_state[0] = Z180_CLEAR_LINE;
1970 Z180.irq_state[1] = Z180_CLEAR_LINE;
1971 Z180.irq_state[2] = Z180_CLEAR_LINE;
1972 Z180.irq_hold[0] = 0;
1973 Z180.irq_hold[1] = 0;
1974 Z180.irq_hold[2] = 0;
1975 for (i=0; i <= Z180_INT_MAX; i++)
1976 {
1977 Z180.int_pending[i] = 0;
1978 }
1979 Z180.timer_cnt = 0;
1980 Z180.after_EI = 0;
1981 Z180.tif[0] = 0;
1982 Z180.tif[1] = 0;
1983 Z180.read_tcr_tmdr[0] = 0;
1984 Z180.read_tcr_tmdr[1] = 0;
1985 Z180.tmdr_value[0] = 0xffff;
1986 Z180.tmdr_value[1] = 0xffff;
1987
1988 /* reset io registers */
1989 IO_CNTLA0 = Z180_CNTLA0_RESET;
1990 IO_CNTLA1 = Z180_CNTLA1_RESET;
1991 IO_CNTLB0 = Z180_CNTLB0_RESET;
1992 IO_CNTLB1 = Z180_CNTLB1_RESET;
1993 IO_STAT0 = Z180_STAT0_RESET;
1994 IO_STAT1 = Z180_STAT1_RESET;
1995 IO_TDR0 = Z180_TDR0_RESET;
1996 IO_TDR1 = Z180_TDR1_RESET;
1997 IO_RDR0 = Z180_RDR0_RESET;
1998 IO_RDR1 = Z180_RDR1_RESET;
1999 IO_CNTR = Z180_CNTR_RESET;
2000 IO_TRDR = Z180_TRDR_RESET;
2001 IO_TMDR0L = Z180_TMDR0L_RESET;
2002 IO_TMDR0H = Z180_TMDR0H_RESET;
2003 IO_RLDR0L = Z180_RLDR0L_RESET;
2004 IO_RLDR0H = Z180_RLDR0H_RESET;
2005 IO_TCR = Z180_TCR_RESET;
2006 IO_IO11 = Z180_IO11_RESET;
2007 IO_ASEXT0 = Z180_ASEXT0_RESET;
2008 IO_ASEXT1 = Z180_ASEXT1_RESET;
2009 IO_TMDR1L = Z180_TMDR1L_RESET;
2010 IO_TMDR1H = Z180_TMDR1H_RESET;
2011 IO_RLDR1L = Z180_RLDR1L_RESET;
2012 IO_RLDR1H = Z180_RLDR1H_RESET;
2013 IO_FRC = Z180_FRC_RESET;
2014 IO_IO19 = Z180_IO19_RESET;
2015 IO_ASTC0L = Z180_ASTC0L_RESET;
2016 IO_ASTC0H = Z180_ASTC0H_RESET;
2017 IO_ASTC1L = Z180_ASTC1L_RESET;
2018 IO_ASTC1H = Z180_ASTC1H_RESET;
2019 IO_CMR = Z180_CMR_RESET;
2020 IO_CCR = Z180_CCR_RESET;
2021 IO_SAR0L = Z180_SAR0L_RESET;
2022 IO_SAR0H = Z180_SAR0H_RESET;
2023 IO_SAR0B = Z180_SAR0B_RESET;
2024 IO_DAR0L = Z180_DAR0L_RESET;
2025 IO_DAR0H = Z180_DAR0H_RESET;
2026 IO_DAR0B = Z180_DAR0B_RESET;
2027 IO_BCR0L = Z180_BCR0L_RESET;
2028 IO_BCR0H = Z180_BCR0H_RESET;
2029 IO_MAR1L = Z180_MAR1L_RESET;
2030 IO_MAR1H = Z180_MAR1H_RESET;
2031 IO_MAR1B = Z180_MAR1B_RESET;
2032 IO_IAR1L = Z180_IAR1L_RESET;
2033 IO_IAR1H = Z180_IAR1H_RESET;
2034 IO_IAR1B = Z180_IAR1B_RESET;
2035 IO_BCR1L = Z180_BCR1L_RESET;
2036 IO_BCR1H = Z180_BCR1H_RESET;
2037 IO_DSTAT = Z180_DSTAT_RESET;
2038 IO_DMODE = Z180_DMODE_RESET;
2039 IO_DCNTL = Z180_DCNTL_RESET;
2040 IO_IL = Z180_IL_RESET;
2041 IO_ITC = Z180_ITC_RESET;
2042 IO_IO35 = Z180_IO35_RESET;
2043 IO_RCR = Z180_RCR_RESET;
2044 IO_IO37 = Z180_IO37_RESET;
2045 IO_CBR = Z180_CBR_RESET;
2046 IO_BBR = Z180_BBR_RESET;
2047 IO_CBAR = Z180_CBAR_RESET;
2048 IO_IO3B = Z180_IO3B_RESET;
2049 IO_IO3C = Z180_IO3C_RESET;
2050 IO_IO3D = Z180_IO3D_RESET;
2051 IO_OMCR = Z180_OMCR_RESET;
2052 IO_IOCR = Z180_IOCR_RESET;
2053
2054 if (Z180.daisy)
2055 z80daisy_reset(Z180.daisy);
2056 z180_mmu();
2057
2058 Z180.total_cycles = 0;
2059 Z180.current_cycles = 0;
2060 }
2061
2062 /* Handle PRT timers, decreasing them after 20 clocks and returning the new icount base that needs to be used for the next check */
clock_timers()2063 static void clock_timers()
2064 {
2065 Z180.timer_cnt++;
2066 if (Z180.timer_cnt >= 20)
2067 {
2068 Z180.timer_cnt = 0;
2069 /* Programmable Reload Timer 0 */
2070 if(IO_TCR & Z180_TCR_TDE0)
2071 {
2072 if(Z180.tmdr_value[0] == 0)
2073 {
2074 Z180.tmdr_value[0] = IO_RLDR0L | (IO_RLDR0H << 8);
2075 Z180.tif[0] = 1;
2076 } else {
2077 Z180.tmdr_value[0]--;
2078 }
2079 }
2080
2081 /* Programmable Reload Timer 1 */
2082 if(IO_TCR & Z180_TCR_TDE1)
2083 {
2084 if(Z180.tmdr_value[1] == 0)
2085 {
2086 Z180.tmdr_value[1] = IO_RLDR1L | (IO_RLDR1H << 8);
2087 Z180.tif[1] = 1;
2088 } else {
2089 Z180.tmdr_value[1]--;
2090 }
2091 }
2092
2093 if((IO_TCR & Z180_TCR_TIE0) && Z180.tif[0])
2094 {
2095 // check if we can take the interrupt
2096 if(_IFF1 && !Z180.after_EI)
2097 {
2098 Z180.int_pending[Z180_INT_PRT0] = 1;
2099 }
2100 }
2101
2102 if((IO_TCR & Z180_TCR_TIE1) && Z180.tif[1])
2103 {
2104 // check if we can take the interrupt
2105 if(_IFF1 && !Z180.after_EI)
2106 {
2107 Z180.int_pending[Z180_INT_PRT1] = 1;
2108 }
2109 }
2110 }
2111 }
2112
check_interrupts(void)2113 static int check_interrupts(void)
2114 {
2115 int i;
2116 int cycles = 0;
2117
2118 /* check for IRQs before each instruction */
2119 if (_IFF1 && !Z180.after_EI)
2120 {
2121 if (Z180.irq_state[0] != Z180_CLEAR_LINE && (IO_ITC & Z180_ITC_ITE0) == Z180_ITC_ITE0)
2122 Z180.int_pending[Z180_INT_IRQ0] = 1;
2123
2124 if (Z180.irq_state[1] != Z180_CLEAR_LINE && (IO_ITC & Z180_ITC_ITE1) == Z180_ITC_ITE1)
2125 Z180.int_pending[Z180_INT_IRQ1] = 1;
2126
2127 if (Z180.irq_state[2] != Z180_CLEAR_LINE && (IO_ITC & Z180_ITC_ITE2) == Z180_ITC_ITE2)
2128 Z180.int_pending[Z180_INT_IRQ2] = 1;
2129 }
2130
2131 for (i = 0; i <= Z180_INT_MAX; i++)
2132 if (Z180.int_pending[i])
2133 {
2134 cycles += take_interrupt(i);
2135 Z180.int_pending[i] = 0;
2136 break;
2137 }
2138
2139 return cycles;
2140 }
2141
z180_write_internal_io(UINT32 port,UINT8 data)2142 void z180_write_internal_io(UINT32 port, UINT8 data)
2143 {
2144 if (port < 0x40) {
2145 Z180.io[port] = data;
2146 }
2147 }
2148
2149 /****************************************************************************
2150 * Handle I/O and timers
2151 ****************************************************************************/
2152
z180_handle_io_timers(int cycles)2153 static void z180_handle_io_timers(int cycles)
2154 {
2155 while (cycles-- > 0)
2156 {
2157 clock_timers();
2158 }
2159 }
2160
2161 /****************************************************************************
2162 * Execute 'cycles' T-states. Return number of T-states really executed
2163 ****************************************************************************/
z180_execute(int cycles)2164 int z180_execute(int cycles)
2165 {
2166 Z180.icount = cycles;
2167 Z180.current_cycles = cycles;
2168 INT32 curcycles = 0;
2169
2170 Z180.end_run = 0;
2171
2172 /* check for NMIs on the way in; they can only be set externally */
2173 /* via timers, and can't be dynamically enabled, so it is safe */
2174 /* to just check here */
2175 if (Z180.nmi_pending)
2176 {
2177 LEAVE_HALT; /* Check if processor was halted */
2178
2179 /* disable DMA transfers!! */
2180 IO_DSTAT &= ~Z180_DSTAT_DME;
2181
2182 _IFF2 = _IFF1;
2183 _IFF1 = 0;
2184 PUSH( PC );
2185 _PCD = 0x0066;
2186 Z180.icount -= 11;
2187 Z180.nmi_pending = 0;
2188 z180_handle_io_timers(11);
2189
2190 if (Z180.nmi_hold) {
2191 Z180.nmi_hold = 0;
2192 Z180.nmi_state = CPU_IRQSTATUS_NONE;
2193 }
2194 }
2195
2196 again:
2197 /* check if any DMA transfer is running */
2198 if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
2199 {
2200 /* check if DMA channel 0 is running and also is in burst mode */
2201 if ((IO_DSTAT & Z180_DSTAT_DE0) == Z180_DSTAT_DE0 &&
2202 (IO_DMODE & Z180_DMODE_MMOD) == Z180_DMODE_MMOD)
2203 {
2204 /* FIXME z180_dma0 should be handled in handle_io_timers */
2205 curcycles = z180_dma0(Z180.icount);
2206 Z180.icount -= curcycles;
2207 z180_handle_io_timers(curcycles);
2208 }
2209 else
2210 {
2211 do
2212 {
2213 curcycles = check_interrupts();
2214 Z180.icount -= curcycles;
2215 z180_handle_io_timers(curcycles);
2216 Z180.after_EI = 0;
2217
2218 _PPC = _PCD;
2219 if (!_HALT)
2220 {
2221 _R++;
2222 IO_FRC++; /* Added FRC counting, not implemented yet */
2223 Z180.extra_cycles = 0;
2224 EXEC_Z180_INLINE(op,ROP());
2225 } else {
2226 Z180.extra_cycles = 3;
2227 }
2228 Z180.icount -= Z180.extra_cycles;
2229 z180_handle_io_timers(Z180.extra_cycles);
2230
2231 /* if channel 0 was started in burst mode, go recheck the mode */
2232 if ((IO_DSTAT & Z180_DSTAT_DE0) == Z180_DSTAT_DE0 &&
2233 (IO_DMODE & Z180_DMODE_MMOD) == Z180_DMODE_MMOD)
2234 goto again;
2235
2236 curcycles = z180_dma0(6);
2237 Z180.icount -= curcycles;
2238 z180_handle_io_timers(curcycles);
2239
2240 curcycles = z180_dma1();
2241 Z180.icount -= curcycles;
2242 z180_handle_io_timers(curcycles);
2243
2244 /* If DMA is done break out to the faster loop */
2245 if ((IO_DSTAT & Z180_DSTAT_DME) != Z180_DSTAT_DME)
2246 break;
2247 } while( Z180.icount > 0 && !Z180.end_run);
2248 }
2249 }
2250
2251 if (Z180.icount > 0 && !Z180.end_run)
2252 {
2253 do
2254 {
2255 /* If DMA is started go to check the mode */
2256 if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
2257 goto again;
2258
2259 curcycles = check_interrupts();
2260 Z180.icount -= curcycles;
2261 z180_handle_io_timers(curcycles);
2262 Z180.after_EI = 0;
2263
2264 _PPC = _PCD;
2265
2266 if (!_HALT) {
2267 _R++;
2268 IO_FRC++; /* Added FRC counting, not implemented yet */
2269 Z180.extra_cycles = 0;
2270 EXEC_Z180_INLINE(op,ROP());
2271 } else {
2272 Z180.extra_cycles = 3;
2273 }
2274 Z180.icount -= Z180.extra_cycles;
2275 z180_handle_io_timers(Z180.extra_cycles);
2276 } while( Z180.icount > 0 && !Z180.end_run );
2277 }
2278
2279 Z180.total_cycles += cycles - Z180.icount;
2280
2281 INT32 ret = cycles - Z180.icount;
2282
2283 Z180.icount = Z180.current_cycles = 0;
2284
2285 return ret;
2286 }
2287
z180_idle(INT32 cyc)2288 INT32 z180_idle(INT32 cyc)
2289 {
2290 Z180.total_cycles += cyc;
2291
2292 return cyc;
2293 }
2294
z180_run_end()2295 void z180_run_end()
2296 {
2297 Z180.end_run = 1;
2298 }
2299
z180_total_cycles()2300 INT32 z180_total_cycles()
2301 {
2302 return Z180.total_cycles + (Z180.current_cycles - Z180.icount);
2303 }
2304
z180_new_frame()2305 void z180_new_frame()
2306 {
2307 Z180.total_cycles = 0;
2308 }
2309
2310 #if 0
2311 /****************************************************************************
2312 * Burn 'cycles' T-states. Adjust R register for the lost time
2313 ****************************************************************************/
2314 void z180_burn(int cycles)
2315 {
2316 if( cycles > 0 )
2317 {
2318 /* NOP takes 3 cycles per instruction */
2319 int n = (cycles + 2) / 3;
2320 _R += n;
2321 Z180.icount -= 3 * n;
2322 }
2323 }
2324 #endif
2325
2326 /****************************************************************************
2327 * Set IRQ line state
2328 ****************************************************************************/
z180_set_irq_line(int irqline,int state)2329 void z180_set_irq_line(int irqline, int state)
2330 {
2331 if (!((irqline >= 0 && irqline <= 2) || irqline == 0x20)) {
2332 bprintf(0, _T("z180_set_irq_line(%x, %x): unsupported irqline.\n"), irqline, state);
2333 return;
2334 }
2335
2336 if (state == CPU_IRQSTATUS_HOLD || state == CPU_IRQSTATUS_AUTO) {
2337 // irq hold logic -dink
2338 state = CPU_IRQSTATUS_ACK;
2339 if (irqline == 0x20) {
2340 Z180.nmi_hold = 1;
2341 } else {
2342 Z180.irq_hold[irqline] = 1;
2343 }
2344 }
2345
2346 if (irqline == 0x20)
2347 {
2348 /* mark an NMI pending on the rising edge */
2349 if (Z180.nmi_state == Z180_CLEAR_LINE && state != Z180_CLEAR_LINE)
2350 Z180.nmi_pending = 1;
2351 Z180.nmi_state = state;
2352 }
2353 else
2354 {
2355 /* update the IRQ state */
2356 Z180.irq_state[irqline] = state;
2357 if (Z180.daisy)
2358 Z180.irq_state[0] = z80daisy_update_irq_state(Z180.daisy);
2359
2360 /* the main execute loop will take the interrupt */
2361 }
2362 }
2363 #if 0
2364 /* logical to physical address translation */
2365 static int z180_translate(int space, int intention, UINT32 *addr)
2366 {
2367 if (space == ADDRESS_SPACE_PROGRAM)
2368 {
2369 *addr = MMU_REMAP_ADDR(*addr);
2370 }
2371 return TRUE;
2372 }
2373
2374 /**************************************************************************
2375 * Generic set_info
2376 **************************************************************************/
2377
2378 static void z180_set_info(UINT32 state, cpuinfo *info)
2379 {
2380 switch (state)
2381 {
2382 /* --- the following bits of info are set as 64-bit signed integers --- */
2383 case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(INPUT_LINE_NMI, info->i); break;
2384 case CPUINFO_INT_INPUT_STATE + Z180_INT0: set_irq_line(Z180_INT0, info->i); break;
2385 case CPUINFO_INT_INPUT_STATE + Z180_INT1: set_irq_line(Z180_INT1, info->i); break;
2386 case CPUINFO_INT_INPUT_STATE + Z180_INT2: set_irq_line(Z180_INT2, info->i); break;
2387
2388 case CPUINFO_INT_PC: _PC = info->i; z180_change_pc(_PCD); break;
2389 case CPUINFO_INT_REGISTER + Z180_PC: Z180.PC.w.l = info->i; break;
2390 case CPUINFO_INT_SP: _SP = info->i; break;
2391 case CPUINFO_INT_REGISTER + Z180_SP: Z180.SP.w.l = info->i; break;
2392 case CPUINFO_INT_REGISTER + Z180_AF: Z180.AF.w.l = info->i; break;
2393 case CPUINFO_INT_REGISTER + Z180_BC: Z180.BC.w.l = info->i; break;
2394 case CPUINFO_INT_REGISTER + Z180_DE: Z180.DE.w.l = info->i; break;
2395 case CPUINFO_INT_REGISTER + Z180_HL: Z180.HL.w.l = info->i; break;
2396 case CPUINFO_INT_REGISTER + Z180_IX: Z180.IX.w.l = info->i; break;
2397 case CPUINFO_INT_REGISTER + Z180_IY: Z180.IY.w.l = info->i; break;
2398 case CPUINFO_INT_REGISTER + Z180_R: Z180.R = info->i; Z180.R2 = info->i & 0x80; break;
2399 case CPUINFO_INT_REGISTER + Z180_I: Z180.I = info->i; break;
2400 case CPUINFO_INT_REGISTER + Z180_AF2: Z180.AF2.w.l = info->i; break;
2401 case CPUINFO_INT_REGISTER + Z180_BC2: Z180.BC2.w.l = info->i; break;
2402 case CPUINFO_INT_REGISTER + Z180_DE2: Z180.DE2.w.l = info->i; break;
2403 case CPUINFO_INT_REGISTER + Z180_HL2: Z180.HL2.w.l = info->i; break;
2404 case CPUINFO_INT_REGISTER + Z180_IM: Z180.IM = info->i; break;
2405 case CPUINFO_INT_REGISTER + Z180_IFF1: Z180.IFF1 = info->i; break;
2406 case CPUINFO_INT_REGISTER + Z180_IFF2: Z180.IFF2 = info->i; break;
2407 case CPUINFO_INT_REGISTER + Z180_HALT: Z180.HALT = info->i; break;
2408 case CPUINFO_INT_REGISTER + Z180_CNTLA0: Z180.io[0x00] = info->i; break;
2409 case CPUINFO_INT_REGISTER + Z180_CNTLA1: Z180.io[0x01] = info->i; break;
2410 case CPUINFO_INT_REGISTER + Z180_CNTLB0: Z180.io[0x02] = info->i; break;
2411 case CPUINFO_INT_REGISTER + Z180_CNTLB1: Z180.io[0x03] = info->i; break;
2412 case CPUINFO_INT_REGISTER + Z180_STAT0: Z180.io[0x04] = info->i; break;
2413 case CPUINFO_INT_REGISTER + Z180_STAT1: Z180.io[0x05] = info->i; break;
2414 case CPUINFO_INT_REGISTER + Z180_TDR0: Z180.io[0x06] = info->i; break;
2415 case CPUINFO_INT_REGISTER + Z180_TDR1: Z180.io[0x07] = info->i; break;
2416 case CPUINFO_INT_REGISTER + Z180_RDR0: Z180.io[0x08] = info->i; break;
2417 case CPUINFO_INT_REGISTER + Z180_RDR1: Z180.io[0x09] = info->i; break;
2418 case CPUINFO_INT_REGISTER + Z180_CNTR: Z180.io[0x0a] = info->i; break;
2419 case CPUINFO_INT_REGISTER + Z180_TRDR: Z180.io[0x0b] = info->i; break;
2420 case CPUINFO_INT_REGISTER + Z180_TMDR0L: Z180.io[0x0c] = info->i; break;
2421 case CPUINFO_INT_REGISTER + Z180_TMDR0H: Z180.io[0x0d] = info->i; break;
2422 case CPUINFO_INT_REGISTER + Z180_RLDR0L: Z180.io[0x0e] = info->i; break;
2423 case CPUINFO_INT_REGISTER + Z180_RLDR0H: Z180.io[0x0f] = info->i; break;
2424 case CPUINFO_INT_REGISTER + Z180_TCR: Z180.io[0x10] = info->i; break;
2425 case CPUINFO_INT_REGISTER + Z180_IO11: Z180.io[0x11] = info->i; break;
2426 case CPUINFO_INT_REGISTER + Z180_ASEXT0: Z180.io[0x12] = info->i; break;
2427 case CPUINFO_INT_REGISTER + Z180_ASEXT1: Z180.io[0x13] = info->i; break;
2428 case CPUINFO_INT_REGISTER + Z180_TMDR1L: Z180.io[0x14] = info->i; break;
2429 case CPUINFO_INT_REGISTER + Z180_TMDR1H: Z180.io[0x15] = info->i; break;
2430 case CPUINFO_INT_REGISTER + Z180_RLDR1L: Z180.io[0x16] = info->i; break;
2431 case CPUINFO_INT_REGISTER + Z180_RLDR1H: Z180.io[0x17] = info->i; break;
2432 case CPUINFO_INT_REGISTER + Z180_FRC: Z180.io[0x18] = info->i; break;
2433 case CPUINFO_INT_REGISTER + Z180_IO19: Z180.io[0x19] = info->i; break;
2434 case CPUINFO_INT_REGISTER + Z180_ASTC0L: Z180.io[0x1a] = info->i; break;
2435 case CPUINFO_INT_REGISTER + Z180_ASTC0H: Z180.io[0x1b] = info->i; break;
2436 case CPUINFO_INT_REGISTER + Z180_ASTC1L: Z180.io[0x1c] = info->i; break;
2437 case CPUINFO_INT_REGISTER + Z180_ASTC1H: Z180.io[0x1d] = info->i; break;
2438 case CPUINFO_INT_REGISTER + Z180_CMR: Z180.io[0x1e] = info->i; break;
2439 case CPUINFO_INT_REGISTER + Z180_CCR: Z180.io[0x1f] = info->i; break;
2440 case CPUINFO_INT_REGISTER + Z180_SAR0L: Z180.io[0x20] = info->i; break;
2441 case CPUINFO_INT_REGISTER + Z180_SAR0H: Z180.io[0x21] = info->i; break;
2442 case CPUINFO_INT_REGISTER + Z180_SAR0B: Z180.io[0x22] = info->i; break;
2443 case CPUINFO_INT_REGISTER + Z180_DAR0L: Z180.io[0x23] = info->i; break;
2444 case CPUINFO_INT_REGISTER + Z180_DAR0H: Z180.io[0x24] = info->i; break;
2445 case CPUINFO_INT_REGISTER + Z180_DAR0B: Z180.io[0x25] = info->i; break;
2446 case CPUINFO_INT_REGISTER + Z180_BCR0L: Z180.io[0x26] = info->i; break;
2447 case CPUINFO_INT_REGISTER + Z180_BCR0H: Z180.io[0x27] = info->i; break;
2448 case CPUINFO_INT_REGISTER + Z180_MAR1L: Z180.io[0x28] = info->i; break;
2449 case CPUINFO_INT_REGISTER + Z180_MAR1H: Z180.io[0x29] = info->i; break;
2450 case CPUINFO_INT_REGISTER + Z180_MAR1B: Z180.io[0x2a] = info->i; break;
2451 case CPUINFO_INT_REGISTER + Z180_IAR1L: Z180.io[0x2b] = info->i; break;
2452 case CPUINFO_INT_REGISTER + Z180_IAR1H: Z180.io[0x2c] = info->i; break;
2453 case CPUINFO_INT_REGISTER + Z180_IAR1B: Z180.io[0x2d] = info->i; break;
2454 case CPUINFO_INT_REGISTER + Z180_BCR1L: Z180.io[0x2e] = info->i; break;
2455 case CPUINFO_INT_REGISTER + Z180_BCR1H: Z180.io[0x2f] = info->i; break;
2456 case CPUINFO_INT_REGISTER + Z180_DSTAT: Z180.io[0x30] = info->i; break;
2457 case CPUINFO_INT_REGISTER + Z180_DMODE: Z180.io[0x31] = info->i; break;
2458 case CPUINFO_INT_REGISTER + Z180_DCNTL: Z180.io[0x32] = info->i; break;
2459 case CPUINFO_INT_REGISTER + Z180_IL: Z180.io[0x33] = info->i; break;
2460 case CPUINFO_INT_REGISTER + Z180_ITC: Z180.io[0x34] = info->i; break;
2461 case CPUINFO_INT_REGISTER + Z180_IO35: Z180.io[0x35] = info->i; break;
2462 case CPUINFO_INT_REGISTER + Z180_RCR: Z180.io[0x36] = info->i; break;
2463 case CPUINFO_INT_REGISTER + Z180_IO37: Z180.io[0x37] = info->i; break;
2464 case CPUINFO_INT_REGISTER + Z180_CBR: Z180.io[0x38] = info->i; z180_mmu(); break;
2465 case CPUINFO_INT_REGISTER + Z180_BBR: Z180.io[0x39] = info->i; z180_mmu(); break;
2466 case CPUINFO_INT_REGISTER + Z180_CBAR: Z180.io[0x3a] = info->i; z180_mmu(); break;
2467 case CPUINFO_INT_REGISTER + Z180_IO3B: Z180.io[0x3b] = info->i; break;
2468 case CPUINFO_INT_REGISTER + Z180_IO3C: Z180.io[0x3c] = info->i; break;
2469 case CPUINFO_INT_REGISTER + Z180_IO3D: Z180.io[0x3d] = info->i; break;
2470 case CPUINFO_INT_REGISTER + Z180_OMCR: Z180.io[0x3e] = info->i; break;
2471 case CPUINFO_INT_REGISTER + Z180_IOCR: Z180.io[0x3f] = info->i; break;
2472 case CPUINFO_INT_REGISTER + Z180_IOLINES: z180_write_iolines(info->i); break;
2473
2474 /* --- the following bits of info are set as pointers to data or functions --- */
2475 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_op: cc[Z180_TABLE_op] = info->p; break;
2476 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_cb: cc[Z180_TABLE_cb] = info->p; break;
2477 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_ed: cc[Z180_TABLE_ed] = info->p; break;
2478 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_xy: cc[Z180_TABLE_xy] = info->p; break;
2479 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_xycb: cc[Z180_TABLE_xycb] = info->p; break;
2480 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_ex: cc[Z180_TABLE_ex] = info->p; break;
2481 }
2482 }
2483
2484
2485 /**************************************************************************
2486 * Generic get_info
2487 **************************************************************************/
2488
2489 void z180_get_info(UINT32 state, cpuinfo *info)
2490 {
2491 switch (state)
2492 {
2493 /* --- the following bits of info are returned as 64-bit signed integers --- */
2494 case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(Z180); break;
2495 case CPUINFO_INT_INPUT_LINES: info->i = 3; break;
2496 case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
2497 case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
2498 case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
2499 case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
2500 case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
2501 case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
2502 case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
2503 case CPUINFO_INT_MAX_CYCLES: info->i = 16; break;
2504
2505 case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 8; break;
2506 case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 20; break;
2507 case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
2508 case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
2509 case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
2510 case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
2511 case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
2512 case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 16; break;
2513 case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
2514
2515 case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = Z180.nmi_state; break;
2516 case CPUINFO_INT_INPUT_STATE + Z180_INT0: info->i = Z180.irq_state[0]; break;
2517 case CPUINFO_INT_INPUT_STATE + Z180_INT1: info->i = Z180.irq_state[1]; break;
2518 case CPUINFO_INT_INPUT_STATE + Z180_INT2: info->i = Z180.irq_state[2]; break;
2519
2520 case CPUINFO_INT_PREVIOUSPC: info->i = Z180.PREPC.w.l; break;
2521
2522 case CPUINFO_INT_PC: info->i = _PCD; break;
2523 case CPUINFO_INT_REGISTER + Z180_PC: info->i = Z180.PC.w.l; break;
2524 case CPUINFO_INT_SP: info->i = _SPD; break;
2525 case CPUINFO_INT_REGISTER + Z180_SP: info->i = Z180.SP.w.l; break;
2526 case CPUINFO_INT_REGISTER + Z180_AF: info->i = Z180.AF.w.l; break;
2527 case CPUINFO_INT_REGISTER + Z180_BC: info->i = Z180.BC.w.l; break;
2528 case CPUINFO_INT_REGISTER + Z180_DE: info->i = Z180.DE.w.l; break;
2529 case CPUINFO_INT_REGISTER + Z180_HL: info->i = Z180.HL.w.l; break;
2530 case CPUINFO_INT_REGISTER + Z180_IX: info->i = Z180.IX.w.l; break;
2531 case CPUINFO_INT_REGISTER + Z180_IY: info->i = Z180.IY.w.l; break;
2532 case CPUINFO_INT_REGISTER + Z180_R: info->i = (Z180.R & 0x7f) | (Z180.R2 & 0x80); break;
2533 case CPUINFO_INT_REGISTER + Z180_I: info->i = Z180.I; break;
2534 case CPUINFO_INT_REGISTER + Z180_AF2: info->i = Z180.AF2.w.l; break;
2535 case CPUINFO_INT_REGISTER + Z180_BC2: info->i = Z180.BC2.w.l; break;
2536 case CPUINFO_INT_REGISTER + Z180_DE2: info->i = Z180.DE2.w.l; break;
2537 case CPUINFO_INT_REGISTER + Z180_HL2: info->i = Z180.HL2.w.l; break;
2538 case CPUINFO_INT_REGISTER + Z180_IM: info->i = Z180.IM; break;
2539 case CPUINFO_INT_REGISTER + Z180_IFF1: info->i = Z180.IFF1; break;
2540 case CPUINFO_INT_REGISTER + Z180_IFF2: info->i = Z180.IFF2; break;
2541 case CPUINFO_INT_REGISTER + Z180_HALT: info->i = Z180.HALT; break;
2542 case CPUINFO_INT_REGISTER + Z180_CNTLA0: info->i = Z180.io[0x00]; break;
2543 case CPUINFO_INT_REGISTER + Z180_CNTLA1: info->i = Z180.io[0x01]; break;
2544 case CPUINFO_INT_REGISTER + Z180_CNTLB0: info->i = Z180.io[0x02]; break;
2545 case CPUINFO_INT_REGISTER + Z180_CNTLB1: info->i = Z180.io[0x03]; break;
2546 case CPUINFO_INT_REGISTER + Z180_STAT0: info->i = Z180.io[0x04]; break;
2547 case CPUINFO_INT_REGISTER + Z180_STAT1: info->i = Z180.io[0x05]; break;
2548 case CPUINFO_INT_REGISTER + Z180_TDR0: info->i = Z180.io[0x06]; break;
2549 case CPUINFO_INT_REGISTER + Z180_TDR1: info->i = Z180.io[0x07]; break;
2550 case CPUINFO_INT_REGISTER + Z180_RDR0: info->i = Z180.io[0x08]; break;
2551 case CPUINFO_INT_REGISTER + Z180_RDR1: info->i = Z180.io[0x09]; break;
2552 case CPUINFO_INT_REGISTER + Z180_CNTR: info->i = Z180.io[0x0a]; break;
2553 case CPUINFO_INT_REGISTER + Z180_TRDR: info->i = Z180.io[0x0b]; break;
2554 case CPUINFO_INT_REGISTER + Z180_TMDR0L: info->i = Z180.io[0x0c]; break;
2555 case CPUINFO_INT_REGISTER + Z180_TMDR0H: info->i = Z180.io[0x0d]; break;
2556 case CPUINFO_INT_REGISTER + Z180_RLDR0L: info->i = Z180.io[0x0e]; break;
2557 case CPUINFO_INT_REGISTER + Z180_RLDR0H: info->i = Z180.io[0x0f]; break;
2558 case CPUINFO_INT_REGISTER + Z180_TCR: info->i = Z180.io[0x10]; break;
2559 case CPUINFO_INT_REGISTER + Z180_IO11: info->i = Z180.io[0x11]; break;
2560 case CPUINFO_INT_REGISTER + Z180_ASEXT0: info->i = Z180.io[0x12]; break;
2561 case CPUINFO_INT_REGISTER + Z180_ASEXT1: info->i = Z180.io[0x13]; break;
2562 case CPUINFO_INT_REGISTER + Z180_TMDR1L: info->i = Z180.io[0x14]; break;
2563 case CPUINFO_INT_REGISTER + Z180_TMDR1H: info->i = Z180.io[0x15]; break;
2564 case CPUINFO_INT_REGISTER + Z180_RLDR1L: info->i = Z180.io[0x16]; break;
2565 case CPUINFO_INT_REGISTER + Z180_RLDR1H: info->i = Z180.io[0x17]; break;
2566 case CPUINFO_INT_REGISTER + Z180_FRC: info->i = Z180.io[0x18]; break;
2567 case CPUINFO_INT_REGISTER + Z180_IO19: info->i = Z180.io[0x19]; break;
2568 case CPUINFO_INT_REGISTER + Z180_ASTC0L: info->i = Z180.io[0x1a]; break;
2569 case CPUINFO_INT_REGISTER + Z180_ASTC0H: info->i = Z180.io[0x1b]; break;
2570 case CPUINFO_INT_REGISTER + Z180_ASTC1L: info->i = Z180.io[0x1c]; break;
2571 case CPUINFO_INT_REGISTER + Z180_ASTC1H: info->i = Z180.io[0x1d]; break;
2572 case CPUINFO_INT_REGISTER + Z180_CMR: info->i = Z180.io[0x1e]; break;
2573 case CPUINFO_INT_REGISTER + Z180_CCR: info->i = Z180.io[0x1f]; break;
2574 case CPUINFO_INT_REGISTER + Z180_SAR0L: info->i = Z180.io[0x20]; break;
2575 case CPUINFO_INT_REGISTER + Z180_SAR0H: info->i = Z180.io[0x21]; break;
2576 case CPUINFO_INT_REGISTER + Z180_SAR0B: info->i = Z180.io[0x22]; break;
2577 case CPUINFO_INT_REGISTER + Z180_DAR0L: info->i = Z180.io[0x23]; break;
2578 case CPUINFO_INT_REGISTER + Z180_DAR0H: info->i = Z180.io[0x24]; break;
2579 case CPUINFO_INT_REGISTER + Z180_DAR0B: info->i = Z180.io[0x25]; break;
2580 case CPUINFO_INT_REGISTER + Z180_BCR0L: info->i = Z180.io[0x26]; break;
2581 case CPUINFO_INT_REGISTER + Z180_BCR0H: info->i = Z180.io[0x27]; break;
2582 case CPUINFO_INT_REGISTER + Z180_MAR1L: info->i = Z180.io[0x28]; break;
2583 case CPUINFO_INT_REGISTER + Z180_MAR1H: info->i = Z180.io[0x29]; break;
2584 case CPUINFO_INT_REGISTER + Z180_MAR1B: info->i = Z180.io[0x2a]; break;
2585 case CPUINFO_INT_REGISTER + Z180_IAR1L: info->i = Z180.io[0x2b]; break;
2586 case CPUINFO_INT_REGISTER + Z180_IAR1H: info->i = Z180.io[0x2c]; break;
2587 case CPUINFO_INT_REGISTER + Z180_IAR1B: info->i = Z180.io[0x2d]; break;
2588 case CPUINFO_INT_REGISTER + Z180_BCR1L: info->i = Z180.io[0x2e]; break;
2589 case CPUINFO_INT_REGISTER + Z180_BCR1H: info->i = Z180.io[0x2f]; break;
2590 case CPUINFO_INT_REGISTER + Z180_DSTAT: info->i = Z180.io[0x30]; break;
2591 case CPUINFO_INT_REGISTER + Z180_DMODE: info->i = Z180.io[0x31]; break;
2592 case CPUINFO_INT_REGISTER + Z180_DCNTL: info->i = Z180.io[0x32]; break;
2593 case CPUINFO_INT_REGISTER + Z180_IL: info->i = Z180.io[0x33]; break;
2594 case CPUINFO_INT_REGISTER + Z180_ITC: info->i = Z180.io[0x34]; break;
2595 case CPUINFO_INT_REGISTER + Z180_IO35: info->i = Z180.io[0x35]; break;
2596 case CPUINFO_INT_REGISTER + Z180_RCR: info->i = Z180.io[0x36]; break;
2597 case CPUINFO_INT_REGISTER + Z180_IO37: info->i = Z180.io[0x37]; break;
2598 case CPUINFO_INT_REGISTER + Z180_CBR: info->i = Z180.io[0x38]; break;
2599 case CPUINFO_INT_REGISTER + Z180_BBR: info->i = Z180.io[0x39]; break;
2600 case CPUINFO_INT_REGISTER + Z180_CBAR: info->i = Z180.io[0x3a]; break;
2601 case CPUINFO_INT_REGISTER + Z180_IO3B: info->i = Z180.io[0x3b]; break;
2602 case CPUINFO_INT_REGISTER + Z180_IO3C: info->i = Z180.io[0x3c]; break;
2603 case CPUINFO_INT_REGISTER + Z180_IO3D: info->i = Z180.io[0x3d]; break;
2604 case CPUINFO_INT_REGISTER + Z180_OMCR: info->i = Z180.io[0x3e]; break;
2605 case CPUINFO_INT_REGISTER + Z180_IOCR: info->i = Z180.io[0x3f]; break;
2606 case CPUINFO_INT_REGISTER + Z180_IOLINES: info->i = Z180.iol; break;
2607
2608 /* --- the following bits of info are returned as pointers to data or functions --- */
2609 case CPUINFO_PTR_SET_INFO: info->setinfo = z180_set_info; break;
2610 case CPUINFO_PTR_GET_CONTEXT: info->getcontext = z180_get_context; break;
2611 case CPUINFO_PTR_SET_CONTEXT: info->setcontext = z180_set_context; break;
2612 case CPUINFO_PTR_INIT: info->init = z180_init; break;
2613 case CPUINFO_PTR_RESET: info->reset = z180_reset; break;
2614 case CPUINFO_PTR_EXECUTE: info->execute = z180_execute; break;
2615 case CPUINFO_PTR_BURN: info->burn = z180_burn; break;
2616 case CPUINFO_PTR_DISASSEMBLE: info->disassemble = z180_dasm; break;
2617 case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &Z180.icount; break;
2618 case CPUINFO_PTR_TRANSLATE: info->translate = z180_translate; break;
2619 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_op: info->p = (void *)cc[Z180_TABLE_op]; break;
2620 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_cb: info->p = (void *)cc[Z180_TABLE_cb]; break;
2621 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_ed: info->p = (void *)cc[Z180_TABLE_ed]; break;
2622 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_xy: info->p = (void *)cc[Z180_TABLE_xy]; break;
2623 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_xycb: info->p = (void *)cc[Z180_TABLE_xycb]; break;
2624 case CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_ex: info->p = (void *)cc[Z180_TABLE_ex]; break;
2625
2626 /* --- the following bits of info are returned as NULL-terminated strings --- */
2627 case CPUINFO_STR_NAME: strcpy(info->s, "Z180"); break;
2628 case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Zilog Z8x180"); break;
2629 case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "0.4"); break;
2630 case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
2631 case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Juergen Buchmueller, all rights reserved."); break;
2632
2633 case CPUINFO_STR_FLAGS:
2634 sprintf(info->s, "%c%c%c%c%c%c%c%c",
2635 Z180.AF.b.l & 0x80 ? 'S':'.',
2636 Z180.AF.b.l & 0x40 ? 'Z':'.',
2637 Z180.AF.b.l & 0x20 ? '5':'.',
2638 Z180.AF.b.l & 0x10 ? 'H':'.',
2639 Z180.AF.b.l & 0x08 ? '3':'.',
2640 Z180.AF.b.l & 0x04 ? 'P':'.',
2641 Z180.AF.b.l & 0x02 ? 'N':'.',
2642 Z180.AF.b.l & 0x01 ? 'C':'.');
2643 break;
2644
2645 case CPUINFO_STR_REGISTER + Z180_PC: sprintf(info->s, "PC:%04X", Z180.PC.w.l); break;
2646 case CPUINFO_STR_REGISTER + Z180_SP: sprintf(info->s, "SP:%04X", Z180.SP.w.l); break;
2647 case CPUINFO_STR_REGISTER + Z180_AF: sprintf(info->s, "AF:%04X", Z180.AF.w.l); break;
2648 case CPUINFO_STR_REGISTER + Z180_BC: sprintf(info->s, "BC:%04X", Z180.BC.w.l); break;
2649 case CPUINFO_STR_REGISTER + Z180_DE: sprintf(info->s, "DE:%04X", Z180.DE.w.l); break;
2650 case CPUINFO_STR_REGISTER + Z180_HL: sprintf(info->s, "HL:%04X", Z180.HL.w.l); break;
2651 case CPUINFO_STR_REGISTER + Z180_IX: sprintf(info->s, "IX:%04X", Z180.IX.w.l); break;
2652 case CPUINFO_STR_REGISTER + Z180_IY: sprintf(info->s, "IY:%04X", Z180.IY.w.l); break;
2653 case CPUINFO_STR_REGISTER + Z180_R: sprintf(info->s, "R :%02X", (Z180.R & 0x7f) | (Z180.R2 & 0x80)); break;
2654 case CPUINFO_STR_REGISTER + Z180_I: sprintf(info->s, "I :%02X", Z180.I); break;
2655 case CPUINFO_STR_REGISTER + Z180_IL: sprintf(info->s, "IL :%02X", Z180.io[Z180_IL-Z180_CNTLA0]); break;
2656 case CPUINFO_STR_REGISTER + Z180_AF2: sprintf(info->s, "AF2:%04X", Z180.AF2.w.l); break;
2657 case CPUINFO_STR_REGISTER + Z180_BC2: sprintf(info->s, "BC2:%04X", Z180.BC2.w.l); break;
2658 case CPUINFO_STR_REGISTER + Z180_DE2: sprintf(info->s, "DE2:%04X", Z180.DE2.w.l); break;
2659 case CPUINFO_STR_REGISTER + Z180_HL2: sprintf(info->s, "HL2:%04X", Z180.HL2.w.l); break;
2660 case CPUINFO_STR_REGISTER + Z180_IM: sprintf(info->s, "IM :%X", Z180.IM); break;
2661 case CPUINFO_STR_REGISTER + Z180_IFF1: sprintf(info->s, "IFF1:%X", Z180.IFF1); break;
2662 case CPUINFO_STR_REGISTER + Z180_IFF2: sprintf(info->s, "IFF2:%X", Z180.IFF2); break;
2663 case CPUINFO_STR_REGISTER + Z180_HALT: sprintf(info->s, "HALT:%X", Z180.HALT); break;
2664 case CPUINFO_STR_REGISTER + Z180_CCR: sprintf(info->s, "CCR :%02X", Z180.io[Z180_CCR-Z180_CNTLA0]); break;
2665 case CPUINFO_STR_REGISTER + Z180_ITC: sprintf(info->s, "ITC :%02X", Z180.io[Z180_ITC-Z180_CNTLA0]); break;
2666 case CPUINFO_STR_REGISTER + Z180_CBR: sprintf(info->s, "CBR :%02X", Z180.io[Z180_CBR-Z180_CNTLA0]); break;
2667 case CPUINFO_STR_REGISTER + Z180_BBR: sprintf(info->s, "BBR :%02X", Z180.io[Z180_BBR-Z180_CNTLA0]); break;
2668 case CPUINFO_STR_REGISTER + Z180_CBAR: sprintf(info->s, "CBAR:%02X", Z180.io[Z180_CBAR-Z180_CNTLA0]); break;
2669 case CPUINFO_STR_REGISTER + Z180_OMCR: sprintf(info->s, "OMCR:%02X", Z180.io[Z180_OMCR-Z180_CNTLA0]); break;
2670 case CPUINFO_STR_REGISTER + Z180_IOCR: sprintf(info->s, "IOCR:%02X", Z180.io[Z180_IOCR-Z180_CNTLA0]); break;
2671 }
2672 }
2673 #endif