1 #include "../machine/gaplus.c" 2 #include "../vidhrdw/gaplus.c" 3 4 /*************************************************************************** 5 6 Gaplus (c) 1984 Namco 7 8 MAME driver by: 9 Manuel Abadia <manu@teleline.es> 10 Ernesto Corvi <someone@secureshell.com> 11 12 ***************************************************************************/ 13 14 #include "driver.h" 15 #include "vidhrdw/generic.h" 16 17 extern unsigned char *gaplus_snd_sharedram; 18 extern unsigned char *gaplus_sharedram; 19 extern unsigned char *gaplus_customio_1, *gaplus_customio_2, *gaplus_customio_3; 20 extern unsigned char *mappy_soundregs; 21 22 /* shared memory functions */ 23 READ_HANDLER( gaplus_sharedram_r ); 24 READ_HANDLER( gaplus_snd_sharedram_r ); 25 WRITE_HANDLER( gaplus_sharedram_w ); 26 WRITE_HANDLER( gaplus_snd_sharedram_w ); 27 28 /* custom IO chips functions */ 29 WRITE_HANDLER( gaplus_customio_1_w ); 30 WRITE_HANDLER( gaplus_customio_2_w ); 31 WRITE_HANDLER( gaplus_customio_3_w ); 32 READ_HANDLER( gaplus_customio_1_r ); 33 READ_HANDLER( gaplus_customio_2_r ); 34 READ_HANDLER( gaplus_customio_3_r ); 35 READ_HANDLER( gaplusa_customio_1_r ); 36 READ_HANDLER( gaplusa_customio_2_r ); 37 READ_HANDLER( gaplusa_customio_3_r ); 38 READ_HANDLER( galaga3_customio_1_r ); 39 READ_HANDLER( galaga3_customio_2_r ); 40 READ_HANDLER( galaga3_customio_3_r ); 41 42 extern int gaplus_interrupt_1(void); 43 WRITE_HANDLER( gaplus_reset_2_3_w ); 44 extern int gaplus_interrupt_2(void); 45 WRITE_HANDLER( gaplus_interrupt_ctrl_2_w ); 46 extern int gaplus_interrupt_3( void ); 47 WRITE_HANDLER( gaplus_interrupt_ctrl_3a_w ); 48 WRITE_HANDLER( gaplus_interrupt_ctrl_3b_w ); 49 50 extern int gaplus_vh_start( void ); 51 extern void gaplus_vh_stop( void ); 52 extern void gaplus_vh_convert_color_prom(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom); 53 extern void gaplus_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh); 54 extern void gaplus_init_machine(void); 55 WRITE_HANDLER( gaplus_starfield_control_w ); 56 57 static struct MemoryReadAddress readmem_cpu1[] = 58 { 59 { 0x0000, 0x03ff, videoram_r }, /* video RAM */ 60 { 0x0400, 0x07ff, colorram_r }, /* color RAM */ 61 { 0x0800, 0x1fff, gaplus_sharedram_r }, /* shared RAM with CPU #2 & spriteram */ 62 { 0x6040, 0x63ff, gaplus_snd_sharedram_r }, /* shared RAM with CPU #3 */ 63 { 0x6800, 0x680f, gaplus_customio_1_r }, /* custom I/O chip #1 interface */ 64 { 0x6810, 0x681f, gaplus_customio_2_r }, /* custom I/O chip #2 interface */ 65 { 0x6820, 0x682f, gaplus_customio_3_r }, /* custom I/O chip #3 interface */ 66 { 0x7820, 0x782f, MRA_RAM }, /* ??? */ 67 { 0x7c00, 0x7c01, MRA_NOP }, /* ??? */ 68 { 0xa000, 0xffff, MRA_ROM }, /* ROM */ 69 { -1 } 70 }; 71 72 static struct MemoryWriteAddress writemem_cpu1[] = 73 { 74 { 0x0000, 0x03ff, videoram_w, &videoram, &videoram_size }, /* video RAM */ 75 { 0x0400, 0x07ff, colorram_w, &colorram }, /* color RAM */ 76 { 0x0800, 0x1fff, gaplus_sharedram_w, &gaplus_sharedram }, /* shared RAM with CPU #2 */ 77 { 0x6040, 0x63ff, gaplus_snd_sharedram_w, &gaplus_snd_sharedram }, /* shared RAM with CPU #3 */ 78 { 0x6800, 0x680f, gaplus_customio_1_w, &gaplus_customio_1 },/* custom I/O chip #1 interface */ 79 { 0x6810, 0x681f, gaplus_customio_2_w, &gaplus_customio_2 },/* custom I/O chip #2 interface */ 80 { 0x6820, 0x682f, gaplus_customio_3_w, &gaplus_customio_3 },/* custom I/O chip #3 interface */ 81 { 0x7820, 0x782f, MWA_RAM }, /* ??? */ 82 // { 0x7c00, 0x7c00, MWA_NOP }, /* ??? */ 83 // { 0x8400, 0x8400, MWA_NOP }, /* ??? */ 84 { 0x8c00, 0x8c00, gaplus_reset_2_3_w }, /* reset CPU #2 y #3? */ 85 // { 0x9400, 0x9400, MWA_NOP }, /* ??? */ 86 // { 0x9c00, 0x9c00, MWA_NOP }, /* ??? */ 87 { 0xa000, 0xa003, gaplus_starfield_control_w }, /* starfield control */ 88 { 0xa000, 0xffff, MWA_ROM }, /* ROM */ 89 { -1 } 90 }; 91 92 static struct MemoryReadAddress readmem_cpu2[] = 93 { 94 { 0x0000, 0x03ff, videoram_r }, /* video RAM */ 95 { 0x0400, 0x07ff, colorram_r }, /* color RAM */ 96 { 0x0800, 0x1fff, gaplus_sharedram_r }, /* shared RAM with CPU #1 & spriteram */ 97 { 0xa000, 0xffff, MRA_ROM }, /* ROM */ 98 { -1 } 99 }; 100 101 static struct MemoryWriteAddress writemem_cpu2[] = 102 { 103 { 0x0000, 0x03ff, videoram_w }, /* video RAM */ 104 { 0x0400, 0x07ff, colorram_w }, /* color RAM */ 105 { 0x0800, 0x1fff, gaplus_sharedram_w }, /* shared RAM with CPU #1 */ 106 // { 0x500f, 0x500f, MWA_NOP }, /* ??? */ 107 // { 0x6001, 0x6001, MWA_NOP }, /* ??? */ 108 { 0x6080, 0x6081, gaplus_interrupt_ctrl_2_w },/* IRQ 2 enable */ 109 { 0xa000, 0xffff, MWA_ROM }, /* ROM */ 110 { -1 } 111 }; 112 113 static struct MemoryReadAddress readmem_cpu3[] = 114 { 115 { 0x0000, 0x003f, MRA_RAM }, /* sound registers? */ 116 { 0x0040, 0x03ff, gaplus_snd_sharedram_r }, /* shared RAM with CPU #1 */ 117 // { 0x3000, 0x3001, MRA_NOP }, /* ???*/ 118 { 0xe000, 0xffff, MRA_ROM }, /* ROM */ 119 { -1 } /* end of table */ 120 }; 121 122 /* CPU 3 (SOUND CPU) write addresses */ 123 static struct MemoryWriteAddress writemem_cpu3[] = 124 { 125 { 0x0000, 0x003f, mappy_sound_w, &mappy_soundregs },/* sound registers */ 126 { 0x0040, 0x03ff, gaplus_snd_sharedram_w }, /* shared RAM with the main CPU */ 127 // { 0x2007, 0x2007, MWA_NOP }, /* ??? */ 128 { 0x3000, 0x3000, watchdog_reset_w }, /* watchdog */ 129 { 0x4000, 0x4000, gaplus_interrupt_ctrl_3a_w }, /* interrupt enable */ 130 { 0x6000, 0x6000, gaplus_interrupt_ctrl_3b_w }, /* interrupt disable */ 131 { 0xe000, 0xffff, MWA_ROM }, /* ROM */ 132 { -1 } 133 }; 134 135 static struct MemoryReadAddress gaplusa_readmem_cpu1[] = 136 { 137 { 0x0000, 0x03ff, videoram_r }, /* video RAM */ 138 { 0x0400, 0x07ff, colorram_r }, /* color RAM */ 139 { 0x0800, 0x1fff, gaplus_sharedram_r }, /* shared RAM with CPU #2 & spriteram */ 140 { 0x6040, 0x63ff, gaplus_snd_sharedram_r }, /* shared RAM with CPU #3 */ 141 { 0x6800, 0x680f, gaplusa_customio_1_r }, /* custom I/O chip #1 interface */ 142 { 0x6810, 0x681f, gaplusa_customio_2_r }, /* custom I/O chip #2 interface */ 143 { 0x6820, 0x682f, gaplusa_customio_3_r }, /* custom I/O chip #3 interface */ 144 { 0x7820, 0x782f, MRA_RAM }, /* ??? */ 145 { 0x7c00, 0x7c01, MRA_NOP }, /* ??? */ 146 { 0xa000, 0xffff, MRA_ROM }, /* ROM */ 147 { -1 } 148 }; 149 150 static struct MemoryReadAddress galaga3_readmem_cpu1[] = 151 { 152 { 0x0000, 0x03ff, videoram_r }, /* video RAM */ 153 { 0x0400, 0x07ff, colorram_r }, /* color RAM */ 154 { 0x0800, 0x1fff, gaplus_sharedram_r }, /* shared RAM with CPU #2 & spriteram */ 155 { 0x6040, 0x63ff, gaplus_snd_sharedram_r }, /* shared RAM with CPU #3 */ 156 { 0x6800, 0x680f, galaga3_customio_1_r }, /* custom I/O chip #1 interface */ 157 { 0x6810, 0x681f, galaga3_customio_2_r }, /* custom I/O chip #2 interface */ 158 { 0x6820, 0x682f, galaga3_customio_3_r }, /* custom I/O chip #3 interface */ 159 { 0x7820, 0x782f, MRA_RAM }, /* ??? */ 160 { 0x7c00, 0x7c01, MRA_NOP }, /* ??? */ 161 { 0xa000, 0xffff, MRA_ROM }, /* ROM */ 162 { -1 } 163 }; 164 165 /* The dipswitches and player inputs are not memory mapped, they are handled by an I/O chip. */ 166 INPUT_PORTS_START( gaplus ) 167 PORT_START /* DSW0 */ 168 PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coin_A ) ) 169 PORT_DIPSETTING( 0x03, DEF_STR( 3C_1C ) ) 170 PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) ) 171 PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) 172 PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) ) 173 PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) ) 174 PORT_DIPSETTING( 0x04, "2" ) 175 PORT_DIPSETTING( 0x00, "3" ) 176 PORT_DIPSETTING( 0x08, "4" ) 177 PORT_DIPSETTING( 0x0c, "5" ) 178 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) 179 PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) 180 PORT_DIPSETTING( 0x00, DEF_STR( On ) ) 181 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Cabinet ) ) 182 PORT_DIPSETTING( 0x20, DEF_STR( Upright ) ) 183 PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) ) 184 PORT_DIPNAME( 0xc0, 0x00, DEF_STR( Coin_B ) ) 185 PORT_DIPSETTING( 0xc0, DEF_STR( 3C_1C ) ) 186 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) ) 187 PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) 188 PORT_DIPSETTING( 0x40, DEF_STR( 1C_2C ) ) 189 190 PORT_START /* DSW1 */ 191 PORT_DIPNAME( 0x07, 0x00, DEF_STR( Difficulty ) ) 192 PORT_DIPSETTING( 0x00, "0" ) 193 PORT_DIPSETTING( 0x01, "1" ) 194 PORT_DIPSETTING( 0x02, "2" ) 195 PORT_DIPSETTING( 0x03, "3" ) 196 PORT_DIPSETTING( 0x04, "4" ) 197 PORT_DIPSETTING( 0x05, "5" ) 198 PORT_DIPSETTING( 0x06, "6" ) 199 PORT_DIPSETTING( 0x07, "7" ) 200 PORT_SERVICE( 0x08, IP_ACTIVE_HIGH ) 201 PORT_BITX( 0x10, 0x00, IPT_DIPSWITCH_NAME | IPF_CHEAT, "Rack Test", KEYCODE_F1, IP_JOY_NONE ) 202 PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) 203 PORT_DIPSETTING( 0x10, DEF_STR( On ) ) 204 PORT_DIPNAME( 0xe0, 0xe0, DEF_STR( Bonus_Life ) ) 205 PORT_DIPSETTING( 0xe0, "30k 70k and every 70k" ) 206 PORT_DIPSETTING( 0xc0, "30k 100k and every 100k" ) 207 PORT_DIPSETTING( 0xa0, "30k 100k and every 200k" ) 208 PORT_DIPSETTING( 0x80, "50k 100k and every 100k" ) 209 PORT_DIPSETTING( 0x60, "50k 100k and every 200k" ) 210 PORT_DIPSETTING( 0x00, "50k 150k and every 150k" ) 211 PORT_DIPSETTING( 0x40, "50k 150k and every 300k" ) 212 PORT_DIPSETTING( 0x20, "50k 150k" ) 213 214 PORT_START /* IN0 */ 215 PORT_BIT_IMPULSE( 0x01, IP_ACTIVE_HIGH, IPT_START1, 1 ) 216 PORT_BIT_IMPULSE( 0x02, IP_ACTIVE_HIGH, IPT_START2, 1 ) 217 /* 0x08 service switch (not implemented yet) */ 218 PORT_BIT_IMPULSE( 0x10, IP_ACTIVE_HIGH, IPT_COIN1, 1 ) 219 PORT_BIT_IMPULSE( 0x20, IP_ACTIVE_HIGH, IPT_COIN2, 1 ) 220 221 PORT_START /* IN1 */ 222 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY ) 223 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY ) 224 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY ) 225 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY ) 226 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 ) 227 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 ) 228 PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 ) 229 PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 ) 230 231 PORT_START /* IN2 */ 232 PORT_BIT_IMPULSE( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1, 1 ) 233 PORT_BITX( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1, 0, IP_KEY_PREVIOUS, IP_JOY_PREVIOUS ) 234 PORT_BIT_IMPULSE( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_PLAYER2, 1 ) 235 PORT_BITX( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_PLAYER2, 0, IP_KEY_PREVIOUS, IP_JOY_PREVIOUS ) 236 INPUT_PORTS_END 237 238 INPUT_PORTS_START( galaga3 ) 239 PORT_START /* DSW0 */ 240 PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coin_A ) ) 241 PORT_DIPSETTING( 0x03, DEF_STR( 3C_1C ) ) 242 PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) ) 243 PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) 244 PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) ) 245 PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) ) 246 PORT_DIPSETTING( 0x04, "2" ) 247 PORT_DIPSETTING( 0x00, "3" ) 248 PORT_DIPSETTING( 0x08, "4" ) 249 PORT_DIPSETTING( 0x0c, "5" ) 250 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) 251 PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) 252 PORT_DIPSETTING( 0x00, DEF_STR( On ) ) 253 PORT_DIPNAME( 0x20, 0x00, DEF_STR( Cabinet ) ) 254 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) ) 255 PORT_DIPSETTING( 0x20, DEF_STR( Cocktail ) ) 256 PORT_DIPNAME( 0xc0, 0x00, DEF_STR( Coin_B ) ) 257 PORT_DIPSETTING( 0xc0, DEF_STR( 3C_1C ) ) 258 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) ) 259 PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) 260 PORT_DIPSETTING( 0x40, DEF_STR( 1C_2C ) ) 261 262 PORT_START /* DSW1 */ 263 PORT_DIPNAME( 0x07, 0x00, DEF_STR( Difficulty ) ) 264 PORT_DIPSETTING( 0x00, "0" ) 265 PORT_DIPSETTING( 0x01, "1" ) 266 PORT_DIPSETTING( 0x02, "2" ) 267 PORT_DIPSETTING( 0x03, "3" ) 268 PORT_DIPSETTING( 0x04, "4" ) 269 PORT_DIPSETTING( 0x05, "5" ) 270 PORT_DIPSETTING( 0x06, "6" ) 271 PORT_DIPSETTING( 0x07, "7" ) 272 PORT_SERVICE( 0x08, IP_ACTIVE_HIGH ) 273 PORT_BITX( 0x10, 0x00, IPT_DIPSWITCH_NAME | IPF_CHEAT, "Rack Test", KEYCODE_F1, IP_JOY_NONE ) 274 PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) 275 PORT_DIPSETTING( 0x10, DEF_STR( On ) ) 276 PORT_DIPNAME( 0xe0, 0xe0, DEF_STR( Bonus_Life ) ) 277 PORT_DIPSETTING( 0xa0, "30k 80k and every 100k" ) 278 PORT_DIPSETTING( 0x80, "30k 100k and every 100k" ) 279 PORT_DIPSETTING( 0x60, "30k 100k and every 150k" ) 280 PORT_DIPSETTING( 0x00, "30k 100k and every 200k" ) 281 PORT_DIPSETTING( 0x40, "30k 100k and every 300k" ) 282 PORT_DIPSETTING( 0xe0, "50k 150k and every 150k" ) 283 PORT_DIPSETTING( 0xc0, "50k 150k and every 200k" ) 284 PORT_DIPSETTING( 0x20, "30k 150k" ) 285 286 PORT_START /* IN0 */ 287 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) 288 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_PLAYER2) 289 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 ) 290 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START2 ) 291 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN1 ) 292 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN2 ) 293 /* 0x40 service switch (not implemented yet) */ 294 295 PORT_START /* IN1 */ 296 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY ) 297 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY ) 298 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY ) 299 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY ) 300 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 ) 301 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 ) 302 PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 ) 303 PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 ) 304 305 INPUT_PORTS_END 306 307 INPUT_PORTS_START( galaga3a ) 308 PORT_START /* DSW0 */ 309 PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coin_A ) ) 310 PORT_DIPSETTING( 0x03, DEF_STR( 3C_1C ) ) 311 PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) ) 312 PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) 313 PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) ) 314 PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) ) 315 PORT_DIPSETTING( 0x04, "2" ) 316 PORT_DIPSETTING( 0x00, "3" ) 317 PORT_DIPSETTING( 0x08, "4" ) 318 PORT_DIPSETTING( 0x0c, "5" ) 319 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) 320 PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) 321 PORT_DIPSETTING( 0x00, DEF_STR( On ) ) 322 PORT_DIPNAME( 0x20, 0x00, DEF_STR( Cabinet ) ) 323 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) ) 324 PORT_DIPSETTING( 0x20, DEF_STR( Cocktail ) ) 325 PORT_DIPNAME( 0xc0, 0x00, DEF_STR( Coin_B ) ) 326 PORT_DIPSETTING( 0xc0, DEF_STR( 3C_1C ) ) 327 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) ) 328 PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) 329 PORT_DIPSETTING( 0x40, DEF_STR( 1C_2C ) ) 330 331 PORT_START /* DSW1 */ 332 PORT_DIPNAME( 0x07, 0x00, DEF_STR( Difficulty ) ) 333 PORT_DIPSETTING( 0x00, "0" ) 334 PORT_DIPSETTING( 0x01, "1" ) 335 PORT_DIPSETTING( 0x02, "2" ) 336 PORT_DIPSETTING( 0x03, "3" ) 337 PORT_DIPSETTING( 0x04, "4" ) 338 PORT_DIPSETTING( 0x05, "5" ) 339 PORT_DIPSETTING( 0x06, "6" ) 340 PORT_DIPSETTING( 0x07, "7" ) 341 PORT_SERVICE( 0x08, IP_ACTIVE_HIGH ) 342 PORT_BITX( 0x10, 0x00, IPT_DIPSWITCH_NAME | IPF_CHEAT, "Rack Test", KEYCODE_F1, IP_JOY_NONE ) 343 PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) 344 PORT_DIPSETTING( 0x10, DEF_STR( On ) ) 345 PORT_DIPNAME( 0xe0, 0xe0, DEF_STR( Bonus_Life ) ) 346 PORT_DIPSETTING( 0xe0, "30k 150k and every 600k" ) 347 PORT_DIPSETTING( 0xc0, "50k 150k and every 300k" ) 348 PORT_DIPSETTING( 0x80, "50k 200k and every 300k" ) 349 PORT_DIPSETTING( 0xa0, "50k 150k and every 600k" ) 350 PORT_DIPSETTING( 0x60, "100k 300k and every 300k" ) 351 PORT_DIPSETTING( 0x00, "100k 300k and every 600k" ) 352 PORT_DIPSETTING( 0x40, "150k 400k and every 900k" ) 353 PORT_DIPSETTING( 0x20, "150k 400k" ) 354 355 PORT_START /* IN0 */ 356 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) 357 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_PLAYER2) 358 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 ) 359 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START2 ) 360 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN1 ) 361 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN2 ) 362 /* 0x40 service switch (not implemented yet) */ 363 364 PORT_START /* IN1 */ 365 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY ) 366 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY ) 367 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY ) 368 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY ) 369 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 ) 370 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 ) 371 PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 ) 372 PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 ) 373 INPUT_PORTS_END 374 375 static struct GfxLayout charlayout1 = 376 { 377 8,8, /* 8*8 characters */ 378 256, /* 256 characters */ 379 2, /* 2 bits per pixel */ 380 { 4, 6 }, /* the 2 bitplanes are packed into one nibble */ 381 { 16*8, 16*8+1, 24*8, 24*8+1, 0, 1, 8*8, 8*8+1 }, 382 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 }, 383 32*8 384 }; 385 386 static struct GfxLayout charlayout2 = 387 { 388 8,8, /* 8*8 characters */ 389 256, /* 256 characters */ 390 2, /* 2 bits per pixel */ 391 { 0, 2 }, /* the 2 bitplanes are packed into one nibble */ 392 { 16*8, 16*8+1, 24*8, 24*8+1, 0, 1, 8*8, 8*8+1 }, 393 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 }, 394 32*8 395 }; 396 397 static struct GfxLayout spritelayout1 = 398 { 399 16,16, /* 16*16 sprites */ 400 128, /* 128 sprites */ 401 3, /* 3 bits per pixel */ 402 { 0, 8192*8+0, 8192*8+4 }, 403 { 0, 1, 2, 3, 8*8, 8*8+1, 8*8+2, 8*8+3, 404 16*8+0, 16*8+1, 16*8+2, 16*8+3, 24*8+0, 24*8+1, 24*8+2, 24*8+3 }, 405 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 406 32*8, 33*8, 34*8, 35*8, 36*8, 37*8, 38*8, 39*8 }, 407 64*8 /* every sprite takes 64 bytes */ 408 }; 409 410 411 static struct GfxLayout spritelayout2 = 412 { 413 16,16, /* 16*16 sprites */ 414 128, /* 128 sprites */ 415 3, /* 3 bits per pixel */ 416 { 4, 8192*8*2+0, 8192*8*2+4 }, 417 { 0, 1, 2, 3, 8*8, 8*8+1, 8*8+2, 8*8+3, 418 16*8+0, 16*8+1, 16*8+2, 16*8+3, 24*8+0, 24*8+1, 24*8+2, 24*8+3 }, 419 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 420 32*8, 33*8, 34*8, 35*8, 36*8, 37*8, 38*8, 39*8 }, 421 64*8 /* every sprite takes 64 bytes */ 422 }; 423 424 static struct GfxLayout spritelayout3 = { 425 16,16, /* 16*16 sprites */ 426 128, /* 128 sprites */ 427 3, /* 3 bits per pixel (one is always 0) */ 428 { 8192*8+0, 0, 4 }, /* the two bitplanes are packed into one byte */ 429 { 0, 1, 2, 3, 8*8, 8*8+1, 8*8+2, 8*8+3, 430 16*8+0, 16*8+1, 16*8+2, 16*8+3, 24*8+0, 24*8+1, 24*8+2, 24*8+3 }, 431 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 432 32*8, 33*8, 34*8, 35*8, 36*8, 37*8, 38*8, 39*8 }, 433 64*8 /* every sprite takes 64 bytes */ 434 }; 435 436 static struct GfxDecodeInfo gfxdecodeinfo[] = 437 { 438 { REGION_GFX1, 0x0000, &charlayout1, 0, 64 }, 439 { REGION_GFX1, 0x0000, &charlayout2, 0, 64 }, 440 { REGION_GFX2, 0x0000, &spritelayout1, 64*4, 64 }, 441 { REGION_GFX2, 0x0000, &spritelayout2, 64*4, 64 }, 442 { REGION_GFX2, 0x6000, &spritelayout3, 64*4, 64 }, 443 { -1 } /* end of table */ 444 }; 445 446 static struct namco_interface namco_interface = 447 { 448 23920, /* sample rate (approximate value) */ 449 8, /* number of voices */ 450 100, /* playback volume */ 451 REGION_SOUND1 /* memory region */ 452 }; 453 454 static const char *gaplus_sample_names[] = 455 { 456 "*galaga", 457 "bang.wav", 458 0 /* end of array */ 459 }; 460 461 static struct Samplesinterface samples_interface = 462 { 463 1, /* one channel */ 464 80, /* volume */ 465 gaplus_sample_names 466 }; 467 468 469 470 static struct MachineDriver machine_driver_gaplus = 471 { 472 /* basic machine hardware */ 473 { 474 { 475 CPU_M6809, /* MAIN CPU */ 476 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 477 readmem_cpu1,writemem_cpu1,0,0, 478 gaplus_interrupt_1,1 479 }, 480 { 481 CPU_M6809, /* SUB CPU */ 482 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 483 readmem_cpu2,writemem_cpu2,0,0, 484 gaplus_interrupt_2,1 485 }, 486 { 487 CPU_M6809, /* SOUND CPU */ 488 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 489 readmem_cpu3,writemem_cpu3,0,0, 490 gaplus_interrupt_3,1 491 } 492 }, 493 60, DEFAULT_60HZ_VBLANK_DURATION, /* frames per second, vblank duration */ 494 100, /* a high value to ensure proper synchronization of the CPUs */ 495 gaplus_init_machine, 496 497 /* video hardware */ 498 36*8, 28*8, 499 { 0*8, 36*8-1, 0*8, 28*8-1 }, 500 gfxdecodeinfo, 501 256, 502 64*4+64*8, 503 gaplus_vh_convert_color_prom, 504 505 VIDEO_TYPE_RASTER, 506 0, 507 gaplus_vh_start, 508 gaplus_vh_stop, 509 gaplus_vh_screenrefresh, 510 511 /* sound hardware */ 512 0,0,0,0, 513 { 514 { 515 SOUND_NAMCO, 516 &namco_interface 517 }, 518 { 519 SOUND_SAMPLES, 520 &samples_interface 521 } 522 } 523 }; 524 525 static struct MachineDriver machine_driver_gaplusa = 526 { 527 /* basic machine hardware */ 528 { 529 { 530 CPU_M6809, /* MAIN CPU */ 531 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 532 gaplusa_readmem_cpu1,writemem_cpu1,0,0, 533 gaplus_interrupt_1,1 534 }, 535 { 536 CPU_M6809, /* SUB CPU */ 537 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 538 readmem_cpu2,writemem_cpu2,0,0, 539 gaplus_interrupt_2,1 540 }, 541 { 542 CPU_M6809, /* SOUND CPU */ 543 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 544 readmem_cpu3,writemem_cpu3,0,0, 545 gaplus_interrupt_3,1 546 } 547 }, 548 60, DEFAULT_60HZ_VBLANK_DURATION, /* frames per second, vblank duration */ 549 100, /* a high value to ensure proper synchronization of the CPUs */ 550 gaplus_init_machine, 551 552 /* video hardware */ 553 36*8, 28*8, 554 { 0*8, 36*8-1, 0*8, 28*8-1 }, 555 gfxdecodeinfo, 556 256, 557 64*4+64*8, 558 gaplus_vh_convert_color_prom, 559 560 VIDEO_TYPE_RASTER, 561 0, 562 gaplus_vh_start, 563 gaplus_vh_stop, 564 gaplus_vh_screenrefresh, 565 566 /* sound hardware */ 567 0,0,0,0, 568 { 569 { 570 SOUND_NAMCO, 571 &namco_interface 572 }, 573 { 574 SOUND_SAMPLES, 575 &samples_interface 576 } 577 } 578 }; 579 580 static struct MachineDriver machine_driver_galaga3 = 581 { 582 /* basic machine hardware */ 583 { 584 { 585 CPU_M6809, /* MAIN CPU */ 586 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 587 galaga3_readmem_cpu1,writemem_cpu1,0,0, 588 gaplus_interrupt_1,1 589 }, 590 { 591 CPU_M6809, /* SUB CPU */ 592 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 593 readmem_cpu2,writemem_cpu2,0,0, 594 gaplus_interrupt_2,1 595 }, 596 { 597 CPU_M6809, /* SOUND CPU */ 598 1536000, /* 24.576 Mhz / 16 = 1.536 Mhz */ 599 readmem_cpu3,writemem_cpu3,0,0, 600 gaplus_interrupt_3,1 601 } 602 }, 603 60, DEFAULT_60HZ_VBLANK_DURATION, /* frames per second, vblank duration */ 604 100, /* a high value to ensure proper synchronization of the CPUs */ 605 gaplus_init_machine, 606 607 /* video hardware */ 608 36*8, 28*8, 609 { 0*8, 36*8-1, 0*8, 28*8-1 }, 610 gfxdecodeinfo, 611 256, 612 64*4+64*8, 613 gaplus_vh_convert_color_prom, 614 615 VIDEO_TYPE_RASTER, 616 0, 617 gaplus_vh_start, 618 gaplus_vh_stop, 619 gaplus_vh_screenrefresh, 620 621 /* sound hardware */ 622 0,0,0,0, 623 { 624 { 625 SOUND_NAMCO, 626 &namco_interface 627 }, 628 { 629 SOUND_SAMPLES, 630 &samples_interface 631 } 632 } 633 }; 634 635 636 637 ROM_START( gaplus ) 638 ROM_REGION( 0x10000, REGION_CPU1 ) /* 64k for the MAIN CPU */ 639 ROM_LOAD( "gp2-4.64", 0xa000, 0x2000, 0x484f11e0 ) 640 ROM_LOAD( "gp2-3.64", 0xc000, 0x2000, 0xa74b0266 ) 641 ROM_LOAD( "gp2-2.64", 0xe000, 0x2000, 0x69fdfdb7 ) 642 643 ROM_REGION( 0x10000, REGION_CPU2 ) /* 64k for the SUB CPU */ 644 ROM_LOAD( "gp2-8.64", 0xa000, 0x2000, 0xbff601a6 ) 645 ROM_LOAD( "gp2-7.64", 0xc000, 0x2000, 0x0621f7df ) 646 ROM_LOAD( "gp2-6.64", 0xe000, 0x2000, 0x14cd61ea ) 647 648 ROM_REGION( 0x10000, REGION_CPU3 ) /* 64k for the SOUND CPU */ 649 ROM_LOAD( "gp2-1.64", 0xe000, 0x2000, 0xed8aa206 ) 650 651 ROM_REGION( 0x2000, REGION_GFX1 | REGIONFLAG_DISPOSE ) 652 ROM_LOAD( "gp2-5.64", 0x0000, 0x2000, 0xf3d19987 ) /* characters */ 653 654 ROM_REGION( 0xa000, REGION_GFX2 | REGIONFLAG_DISPOSE ) 655 ROM_LOAD( "gp2-9.64", 0x0000, 0x2000, 0xe6a9ae67 ) /* objects */ 656 ROM_LOAD( "gp2-11.64", 0x2000, 0x2000, 0x57740ff9 ) /* objects */ 657 ROM_LOAD( "gp2-10.64", 0x4000, 0x2000, 0x6cd8ce11 ) /* objects */ 658 ROM_LOAD( "gp2-12.64", 0x6000, 0x2000, 0x7316a1f1 ) /* objects */ 659 /* 0xa000-0xbfff empty space to decode sprite set #3 as 3 bits per pixel */ 660 661 ROM_REGION( 0x0800, REGION_PROMS ) 662 ROM_LOAD( "gp2-1p.bin", 0x0000, 0x0100, 0xa5091352 ) /* red palette ROM (4 bits) */ 663 ROM_LOAD( "gp2-1n.bin", 0x0100, 0x0100, 0x8bc8022a ) /* green palette ROM (4 bits) */ 664 ROM_LOAD( "gp2-2n.bin", 0x0200, 0x0100, 0x8dabc20b ) /* blue palette ROM (4 bits) */ 665 ROM_LOAD( "gp2-6s.bin", 0x0300, 0x0100, 0x2faa3e09 ) /* char color ROM */ 666 ROM_LOAD( "gp2-6p.bin", 0x0400, 0x0200, 0x6f99c2da ) /* sprite color ROM (lower 4 bits) */ 667 ROM_LOAD( "gp2-6n.bin", 0x0600, 0x0200, 0xc7d31657 ) /* sprite color ROM (upper 4 bits) */ 668 669 ROM_REGION( 0x0100, REGION_SOUND1 ) /* sound prom */ 670 ROM_LOAD( "gp2-3f.bin", 0x0000, 0x0100, 0x2d9fbdd8 ) 671 ROM_END 672 673 ROM_START( gaplusa ) 674 ROM_REGION( 0x10000, REGION_CPU1 ) /* 64k for the MAIN CPU */ 675 ROM_LOAD( "gp2-4.8d", 0xa000, 0x2000, 0xe525d75d ) 676 ROM_LOAD( "gp2-3b.8c", 0xc000, 0x2000, 0xd77840a4 ) 677 ROM_LOAD( "gp2-2b.8b", 0xe000, 0x2000, 0xb3cb90db ) 678 679 ROM_REGION( 0x10000, REGION_CPU2 ) /* 64k for the SUB CPU */ 680 ROM_LOAD( "gp2-8.11d", 0xa000, 0x2000, 0x42b9fd7c ) 681 ROM_LOAD( "gp2-7.64", 0xc000, 0x2000, 0x0621f7df ) 682 ROM_LOAD( "gp2-6.11b", 0xe000, 0x2000, 0x75b18652 ) 683 684 ROM_REGION( 0x10000, REGION_CPU3 ) /* 64k for the SOUND CPU */ 685 ROM_LOAD( "gp2-1.64", 0xe000, 0x2000, 0xed8aa206 ) 686 687 ROM_REGION( 0x2000, REGION_GFX1 | REGIONFLAG_DISPOSE ) 688 ROM_LOAD( "gp2-5.64", 0x0000, 0x2000, 0xf3d19987 ) /* characters */ 689 690 ROM_REGION( 0xa000, REGION_GFX2 | REGIONFLAG_DISPOSE ) 691 ROM_LOAD( "gp2-9.64", 0x0000, 0x2000, 0xe6a9ae67 ) /* objects */ 692 ROM_LOAD( "gp2-11.64", 0x2000, 0x2000, 0x57740ff9 ) /* objects */ 693 ROM_LOAD( "gp2-10.64", 0x4000, 0x2000, 0x6cd8ce11 ) /* objects */ 694 ROM_LOAD( "gp2-12.64", 0x6000, 0x2000, 0x7316a1f1 ) /* objects */ 695 /* 0xa000-0xbfff empty space to decode sprite set #3 as 3 bits per pixel */ 696 697 ROM_REGION( 0x0800, REGION_PROMS ) 698 ROM_LOAD( "gp2-1p.bin", 0x0000, 0x0100, 0xa5091352 ) /* red palette ROM (4 bits) */ 699 ROM_LOAD( "gp2-1n.bin", 0x0100, 0x0100, 0x8bc8022a ) /* green palette ROM (4 bits) */ 700 ROM_LOAD( "gp2-2n.bin", 0x0200, 0x0100, 0x8dabc20b ) /* blue palette ROM (4 bits) */ 701 ROM_LOAD( "gp2-6s.bin", 0x0300, 0x0100, 0x2faa3e09 ) /* char color ROM */ 702 ROM_LOAD( "gp2-6p.bin", 0x0400, 0x0200, 0x6f99c2da ) /* sprite color ROM (lower 4 bits) */ 703 ROM_LOAD( "gp2-6n.bin", 0x0600, 0x0200, 0xc7d31657 ) /* sprite color ROM (upper 4 bits) */ 704 705 ROM_REGION( 0x0100, REGION_SOUND1 ) /* sound prom */ 706 ROM_LOAD( "gp2-3f.bin", 0x0000, 0x0100, 0x2d9fbdd8 ) 707 ROM_END 708 709 ROM_START( galaga3 ) 710 ROM_REGION( 0x10000, REGION_CPU1 ) /* 64k for the MAIN CPU */ 711 ROM_LOAD( "gal3_9e.bin", 0xa000, 0x2000, 0xf4845e7f ) 712 ROM_LOAD( "gal3_9d.bin", 0xc000, 0x2000, 0x86fac687 ) 713 ROM_LOAD( "gal3_9c.bin", 0xe000, 0x2000, 0xf1b00073 ) 714 715 ROM_REGION( 0x10000, REGION_CPU2 ) /* 64k for the SUB CPU */ 716 ROM_LOAD( "gal3_6l.bin",0xa000, 0x2000, 0x9ec3dce5 ) 717 ROM_LOAD( "gp2-7.64", 0xc000, 0x2000, 0x0621f7df ) 718 ROM_LOAD( "gal3_6n.bin",0xe000, 0x2000, 0x6a2942c5 ) 719 720 ROM_REGION( 0x10000, REGION_CPU3 ) /* 64k for the SOUND CPU */ 721 ROM_LOAD( "gp2-1.64", 0xe000, 0x2000, 0xed8aa206 ) 722 723 ROM_REGION( 0x2000, REGION_GFX1 | REGIONFLAG_DISPOSE ) 724 ROM_LOAD( "gal3_9l.bin",0x0000, 0x2000, 0x8d4dcebf ) /* characters */ 725 726 ROM_REGION( 0xa000, REGION_GFX2 | REGIONFLAG_DISPOSE ) 727 ROM_LOAD( "gp2-9.64", 0x0000, 0x2000, 0xe6a9ae67 ) /* objects */ 728 ROM_LOAD( "gp2-11.64", 0x2000, 0x2000, 0x57740ff9 ) /* objects */ 729 ROM_LOAD( "gp2-10.64", 0x4000, 0x2000, 0x6cd8ce11 ) /* objects */ 730 ROM_LOAD( "gp2-12.64", 0x6000, 0x2000, 0x7316a1f1 ) /* objects */ 731 /* 0xa000-0xbfff empty space to decode sprite set #3 as 3 bits per pixel */ 732 733 ROM_REGION( 0x0800, REGION_PROMS ) 734 ROM_LOAD( "gp2-1p.bin", 0x0000, 0x0100, 0xa5091352 ) /* red palette ROM (4 bits) */ 735 ROM_LOAD( "gp2-1n.bin", 0x0100, 0x0100, 0x8bc8022a ) /* green palette ROM (4 bits) */ 736 ROM_LOAD( "gp2-2n.bin", 0x0200, 0x0100, 0x8dabc20b ) /* blue palette ROM (4 bits) */ 737 ROM_LOAD( "gp2-6s.bin", 0x0300, 0x0100, 0x2faa3e09 ) /* char color ROM */ 738 ROM_LOAD( "g3_3f.bin", 0x0400, 0x0200, 0xd48c0eef ) /* sprite color ROM (lower 4 bits) */ 739 ROM_LOAD( "g3_3e.bin", 0x0600, 0x0200, 0x417ba0dc ) /* sprite color ROM (upper 4 bits) */ 740 741 ROM_REGION( 0x0100, REGION_SOUND1 ) /* sound prom */ 742 ROM_LOAD( "gp2-3f.bin", 0x0000, 0x0100, 0x2d9fbdd8 ) 743 ROM_END 744 745 ROM_START( galaga3a ) 746 ROM_REGION( 0x10000, REGION_CPU1 ) /* 64k for the MAIN CPU */ 747 ROM_LOAD( "mi.9e", 0xa000, 0x2000, 0xe392704e ) 748 ROM_LOAD( "gal3_9d.bin", 0xc000, 0x2000, 0x86fac687 ) 749 ROM_LOAD( "gal3_9c.bin", 0xe000, 0x2000, 0xf1b00073 ) 750 751 ROM_REGION( 0x10000, REGION_CPU2 ) /* 64k for the SUB CPU */ 752 ROM_LOAD( "gal3_6l.bin",0xa000, 0x2000, 0x9ec3dce5 ) 753 ROM_LOAD( "gp2-7.64", 0xc000, 0x2000, 0x0621f7df ) 754 ROM_LOAD( "gal3_6n.bin",0xe000, 0x2000, 0x6a2942c5 ) 755 756 ROM_REGION( 0x10000, REGION_CPU3 ) /* 64k for the SOUND CPU */ 757 ROM_LOAD( "gp2-1.64", 0xe000, 0x2000, 0xed8aa206 ) 758 759 ROM_REGION( 0x2000, REGION_GFX1 | REGIONFLAG_DISPOSE ) 760 ROM_LOAD( "gal3_9l.bin",0x0000, 0x2000, 0x8d4dcebf ) /* characters */ 761 762 ROM_REGION( 0xa000, REGION_GFX2 | REGIONFLAG_DISPOSE ) 763 ROM_LOAD( "gp2-9.64", 0x0000, 0x2000, 0xe6a9ae67 ) /* objects */ 764 ROM_LOAD( "gp2-11.64", 0x2000, 0x2000, 0x57740ff9 ) /* objects */ 765 ROM_LOAD( "gp2-10.64", 0x4000, 0x2000, 0x6cd8ce11 ) /* objects */ 766 ROM_LOAD( "gp2-12.64", 0x6000, 0x2000, 0x7316a1f1 ) /* objects */ 767 /* 0xa000-0xbfff empty space to decode sprite set #3 as 3 bits per pixel */ 768 769 ROM_REGION( 0x0800, REGION_PROMS ) 770 ROM_LOAD( "gp2-1p.bin", 0x0000, 0x0100, 0xa5091352 ) /* red palette ROM (4 bits) */ 771 ROM_LOAD( "gp2-1n.bin", 0x0100, 0x0100, 0x8bc8022a ) /* green palette ROM (4 bits) */ 772 ROM_LOAD( "gp2-2n.bin", 0x0200, 0x0100, 0x8dabc20b ) /* blue palette ROM (4 bits) */ 773 ROM_LOAD( "gp2-6s.bin", 0x0300, 0x0100, 0x2faa3e09 ) /* char color ROM */ 774 ROM_LOAD( "g3_3f.bin", 0x0400, 0x0200, 0xd48c0eef ) /* sprite color ROM (lower 4 bits) */ 775 ROM_LOAD( "g3_3e.bin", 0x0600, 0x0200, 0x417ba0dc ) /* sprite color ROM (upper 4 bits) */ 776 777 ROM_REGION( 0x0100, REGION_SOUND1 ) /* sound prom */ 778 ROM_LOAD( "gp2-3f.bin", 0x0000, 0x0100, 0x2d9fbdd8 ) 779 ROM_END 780 781 782 783 GAME( 1984, gaplus, 0, gaplus, gaplus, 0, ROT90, "Namco", "Gaplus (set 1)" ) 784 GAME( 1984, gaplusa, gaplus, gaplusa, gaplus, 0, ROT90, "Namco", "Gaplus (set 2)" ) 785 GAME( 1984, galaga3, gaplus, galaga3, galaga3, 0, ROT90, "Namco", "Galaga 3 (set 1)" ) 786 GAME( 1984, galaga3a, gaplus, galaga3, galaga3a, 0, ROT90, "Namco", "Galaga 3 (set 2)" ) 787