1 #include "../vidhrdw/zerozone.c"
2 
3 /***************************************************************************
4 
5 Zero Zone memory map
6 
7 driver by Brad Oliver
8 
9 CPU 1 : 68000, uses irq 1
10 
11 0x000000 - 0x01ffff : ROM
12 0x080000 - 0x08000f : input ports and dipswitches
13 0x088000 - 0x0881ff : palette RAM, 256 total colors
14 0x09ce00 - 0x09d9ff : video ram, 48x32
15 0x0c0000 - 0x0cffff : RAM
16 0x0f8000 - 0x0f87ff : RAM (unused?)
17 
18 TODO:
19 	* adpcm samples don't seem to be playing at the proper tempo - too fast?
20 	* There are a lot of unknown dipswitches
21 
22 ***************************************************************************/
23 #include "driver.h"
24 #include "vidhrdw/generic.h"
25 
26 void zerozone_vh_screenrefresh(struct osd_bitmap *bitmap, int full_refresh);
27 int zerozone_vh_start(void);
28 void zerozone_vh_stop(void);
29 READ_HANDLER( zerozone_videoram_r );
30 WRITE_HANDLER( zerozone_videoram_w );
31 
32 extern unsigned char *zerozone_videoram;
33 static unsigned char *ram; /* for high score save */
34 
READ_HANDLER(zerozone_input_r)35 static READ_HANDLER( zerozone_input_r )
36 {
37 	switch (offset)
38 	{
39 		case 0x00:
40 			return readinputport(0); /* IN0 */
41 		case 0x02:
42 			return (readinputport(1) | (readinputport(2) << 8)); /* IN1 & IN2 */
43 		case 0x08:
44 			return (readinputport(4) << 8);
45 		case 0x0a:
46 			return readinputport(3);
47 	}
48 
49 //logerror("CPU #0 PC %06x: warning - read unmapped memory address %06x\n",cpu_get_pc(),0x800000+offset);
50 
51 	return 0x00;
52 }
53 
54 
WRITE_HANDLER(zerozone_sound_w)55 WRITE_HANDLER( zerozone_sound_w )
56 {
57 	soundlatch_w (offset, (data >> 8) & 0xff);
58 	cpu_cause_interrupt (1, 0xff);
59 }
60 
61 static struct MemoryReadAddress readmem[] =
62 {
63 	{ 0x000000, 0x01ffff, MRA_ROM },
64 	{ 0x080000, 0x08000f, zerozone_input_r },
65 	{ 0x088000, 0x0881ff, paletteram_word_r },
66 //	{ 0x098000, 0x098001, MRA_RAM }, /* watchdog? */
67 	{ 0x09ce00, 0x09d9ff, zerozone_videoram_r },
68 	{ 0x0c0000, 0x0cffff, MRA_BANK1 },
69 	{ 0x0f8000, 0x0f87ff, MRA_BANK2 },
70 	{ -1 }  /* end of table */
71 };
72 
73 static struct MemoryWriteAddress writemem[] =
74 {
75 	{ 0x000000, 0x01ffff, MWA_ROM },
76 	{ 0x084000, 0x084001, zerozone_sound_w },
77 	{ 0x088000, 0x0881ff, paletteram_BBBBGGGGRRRRxxxx_word_w, &paletteram },
78 	{ 0x09ce00, 0x09d9ff, zerozone_videoram_w, &zerozone_videoram, &videoram_size },
79 	{ 0x0c0000, 0x0cffff, MWA_BANK1, &ram }, /* RAM */
80 	{ 0x0f8000, 0x0f87ff, MWA_BANK2 },
81 	{ -1 }  /* end of table */
82 };
83 
84 
85 static struct MemoryReadAddress sound_readmem[] =
86 {
87 	{ 0x0000, 0x7fff, MRA_ROM },
88 	{ 0x8000, 0x87ff, MRA_RAM },
89 	{ 0x9800, 0x9800, OKIM6295_status_0_r },
90 	{ 0xa000, 0xa000, soundlatch_r },
91 	{ -1 }  /* end of table */
92 };
93 
94 static struct MemoryWriteAddress sound_writemem[] =
95 {
96 	{ 0x0000, 0x7fff, MWA_ROM },
97 	{ 0x8000, 0x87ff, MWA_RAM },
98 	{ 0x9800, 0x9800, OKIM6295_data_0_w },
99 	{ -1 }  /* end of table */
100 };
101 
102 INPUT_PORTS_START( zerozone )
103 	PORT_START      /* IN0 */
104 	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
105 	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
106 	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
107 	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
108 	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
109 	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
110 	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
111 	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
112 
113 	PORT_START      /* IN1 */
114 	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_4WAY )
115 	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_4WAY )
116 	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_4WAY )
117 	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_4WAY )
118 	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
119 	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
120 	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
121 	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
122 
123 	PORT_START      /* IN2 */
124 	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_4WAY | IPF_PLAYER2 )
125 	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_4WAY | IPF_PLAYER2 )
126 	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_4WAY | IPF_PLAYER2 )
127 	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_4WAY | IPF_PLAYER2 )
128 	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
129 	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
130 	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
131 	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
132 
133 	PORT_START /* DSW A */
134 	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
135 	PORT_DIPSETTING(    0x00, DEF_STR( 6C_1C ))
136 	PORT_DIPSETTING(    0x01, DEF_STR( 4C_1C ))
137 	PORT_DIPSETTING(    0x02, DEF_STR( 3C_1C ))
138 	PORT_DIPSETTING(    0x03, DEF_STR( 2C_1C ))
139 	PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ))
140 	PORT_DIPSETTING(    0x06, DEF_STR( 1C_2C ))
141 	PORT_DIPSETTING(    0x05, DEF_STR( 1C_3C ))
142 	PORT_DIPSETTING(    0x04, DEF_STR( 1C_4C ))
143 	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
144 	PORT_DIPSETTING(    0x08, DEF_STR( Off ))
145 	PORT_DIPSETTING(    0x00, DEF_STR( On ))
146 	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
147 	PORT_DIPSETTING(    0x10, DEF_STR( Off ))
148 	PORT_DIPSETTING(    0x00, DEF_STR( On ))
149 	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
150 	PORT_DIPSETTING(    0x20, DEF_STR( Off ))
151 	PORT_DIPSETTING(    0x00, DEF_STR( On ))
152 	PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Unknown ) )
153 	PORT_DIPSETTING(    0xc0, "1")
154 	PORT_DIPSETTING(    0x80, "2")
155 	PORT_DIPSETTING(    0x40, "3")
156 	PORT_DIPSETTING(    0x00, "4")
157 
158 	PORT_START /* DSW B */
159 	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
160 	PORT_DIPSETTING(    0x01, DEF_STR( Off ))
161 	PORT_DIPSETTING(    0x00, DEF_STR( On ))
162 	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
163 	PORT_DIPSETTING(    0x02, DEF_STR( Off ))
164 	PORT_DIPSETTING(    0x00, DEF_STR( On ))
165 	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Unknown ) )
166 	PORT_DIPSETTING(    0x0c, "1")
167 	PORT_DIPSETTING(    0x04, "2")
168 	PORT_DIPSETTING(    0x08, "3")
169 	PORT_DIPSETTING(    0x00, "4")
170 	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
171 	PORT_DIPSETTING(    0x10, DEF_STR( Off ))
172 	PORT_DIPSETTING(    0x00, DEF_STR( On ))
173 	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
174 	PORT_DIPSETTING(    0x20, DEF_STR( Off ))
175 	PORT_DIPSETTING(    0x00, DEF_STR( On ))
176 	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
177 	PORT_DIPSETTING(    0x40, DEF_STR( Off ))
178 	PORT_DIPSETTING(    0x00, DEF_STR( On ))
179 	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
180 INPUT_PORTS_END
181 
182 
183 static struct GfxLayout charlayout =
184 {
185 	8,8,	/* 8*8 characters */
186 	4096,	/* 4096 characters */
187 	4,	/* 4 bits per pixel */
188 	{ 0, 1, 2, 3 },
189 	{ 0, 4, 8+0, 8+4, 16+0, 16+4, 24+0, 24+4 },
190 	{ 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
191 	32*8	/* every sprite takes 32 consecutive bytes */
192 };
193 
194 
195 static struct GfxDecodeInfo gfxdecodeinfo[] =
196 {
197 	{ REGION_GFX1, 0, &charlayout, 0, 256 },         /* sprites & playfield */
198 	{ -1 } /* end of array */
199 };
200 
201 
202 static struct OKIM6295interface okim6295_interface =
203 {
204 	1,              /* 1 chip */
205 	{ 8000 },           /* 8000Hz ??? TODO: find out the real frequency */
206 	{ REGION_SOUND1 },	/* memory region 3 */
207 	{ 100 }
208 };
209 
210 static struct MachineDriver machine_driver_zerozone =
211 {
212 	{
213 		{
214 			CPU_M68000,
215 			10000000,	/* 10 MHz */
216 			readmem,writemem,0,0,
217 			m68_level1_irq,1
218 		},
219 		{
220 			CPU_Z80 | CPU_AUDIO_CPU,
221 			1000000,	/* 1 MHz ??? */
222 			sound_readmem, sound_writemem,0,0,
223 			ignore_interrupt,0	/* IRQs are triggered by the main cpu */
224 		}
225 	},
226 	60, DEFAULT_60HZ_VBLANK_DURATION,	/* frames per second, vblank duration */
227 	10,
228 	0,
229 
230 	/* video hardware */
231 	48*8, 32*8, { 1*8, 47*8-1, 2*8, 30*8-1 },
232 
233 	gfxdecodeinfo,
234 	256, 256,
235 	0,
236 
237 	VIDEO_TYPE_RASTER | VIDEO_SUPPORTS_DIRTY | VIDEO_MODIFIES_PALETTE,
238 	0,
239 	zerozone_vh_start,
240 	zerozone_vh_stop,
241 	zerozone_vh_screenrefresh,
242 
243 	/* sound hardware */
244 	0,0,0,0,
245 	{
246 		{
247 			SOUND_OKIM6295,
248 			&okim6295_interface
249 		}
250 	}
251 };
252 
253 
254 
255 /***************************************************************************
256 
257   Game driver(s)
258 
259 ***************************************************************************/
260 
261 ROM_START( zerozone )
262 	ROM_REGION( 0x20000, REGION_CPU1 )     /* 128k for 68000 code */
263 	ROM_LOAD_EVEN( "zz-4.rom", 0x0000, 0x10000, 0x83718b9b )
264 	ROM_LOAD_ODD ( "zz-5.rom", 0x0000, 0x10000, 0x18557f41 )
265 
266 	ROM_REGION( 0x10000, REGION_CPU2 )      /* sound cpu */
267 	ROM_LOAD( "zz-1.rom", 0x00000, 0x08000, 0x223ccce5 )
268 
269 	ROM_REGION( 0x080000, REGION_GFX1 | REGIONFLAG_DISPOSE )
270 	ROM_LOAD( "zz-6.rom", 0x00000, 0x80000, 0xc8b906b9 )
271 
272 	ROM_REGION( 0x40000, REGION_SOUND1 )      /* ADPCM samples */
273 	ROM_LOAD( "zz-2.rom", 0x00000, 0x20000, 0xc7551e81 )
274 	ROM_LOAD( "zz-3.rom", 0x20000, 0x20000, 0xe348ff5e )
275 ROM_END
276 
277 
278 
279 GAME( 1993, zerozone, 0, zerozone, zerozone, 0, ROT0, "Comad", "Zero Zone" )
280