1 #ifndef Z180_H 2 #define Z180_H 3 4 #include "cpuintrf.h" 5 #include "osd_cpu.h" 6 7 enum { 8 Z180_PC=1, 9 Z180_SP, 10 Z180_AF, 11 Z180_BC, 12 Z180_DE, 13 Z180_HL, 14 Z180_IX, 15 Z180_IY, 16 Z180_AF2, 17 Z180_BC2, 18 Z180_DE2, 19 Z180_HL2, 20 Z180_R, 21 Z180_I, 22 Z180_IM, 23 Z180_IFF1, 24 Z180_IFF2, 25 Z180_HALT, 26 Z180_NMI_STATE, 27 Z180_INT0_STATE, 28 Z180_INT1_STATE, 29 Z180_INT2_STATE, 30 Z180_DC0, 31 Z180_DC1, 32 Z180_DC2, 33 Z180_DC3, 34 Z180_CNTLA0, /* 00 ASCI control register A ch 0 */ 35 Z180_CNTLA1, /* 01 ASCI control register A ch 1 */ 36 Z180_CNTLB0, /* 02 ASCI control register B ch 0 */ 37 Z180_CNTLB1, /* 03 ASCI control register B ch 1 */ 38 Z180_STAT0, /* 04 ASCI status register 0 */ 39 Z180_STAT1, /* 05 ASCI status register 1 */ 40 Z180_TDR0, /* 06 ASCI transmit data register 0 */ 41 Z180_TDR1, /* 07 ASCI transmit data register 1 */ 42 Z180_RDR0, /* 08 ASCI receive data register 0 */ 43 Z180_RDR1, /* 09 ASCI receive data register 1 */ 44 Z180_CNTR, /* 0a CSI/O control/status register */ 45 Z180_TRDR, /* 0b CSI/O transmit/receive register */ 46 Z180_TMDR0L, /* 0c TIMER data register ch 0 L */ 47 Z180_TMDR0H, /* 0d TIMER data register ch 0 H */ 48 Z180_RLDR0L, /* 0e TIMER reload register ch 0 L */ 49 Z180_RLDR0H, /* 0f TIMER reload register ch 0 H */ 50 Z180_TCR, /* 10 TIMER control register */ 51 Z180_IO11, /* 11 reserved */ 52 Z180_ASEXT0, /* 12 (Z8S180/Z8L180) ASCI extension control register 0 */ 53 Z180_ASEXT1, /* 13 (Z8S180/Z8L180) ASCI extension control register 0 */ 54 Z180_TMDR1L, /* 14 TIMER data register ch 1 L */ 55 Z180_TMDR1H, /* 15 TIMER data register ch 1 H */ 56 Z180_RLDR1L, /* 16 TIMER reload register ch 1 L */ 57 Z180_RLDR1H, /* 17 TIMER reload register ch 1 H */ 58 Z180_FRC, /* 18 free running counter */ 59 Z180_IO19, /* 19 reserved */ 60 Z180_ASTC0L, /* 1a ASCI time constant ch 0 L */ 61 Z180_ASTC0H, /* 1b ASCI time constant ch 0 H */ 62 Z180_ASTC1L, /* 1c ASCI time constant ch 1 L */ 63 Z180_ASTC1H, /* 1d ASCI time constant ch 1 H */ 64 Z180_CMR, /* 1e clock multiplier */ 65 Z180_CCR, /* 1f chip control register */ 66 Z180_SAR0L, /* 20 DMA source address register ch 0 L */ 67 Z180_SAR0H, /* 21 DMA source address register ch 0 H */ 68 Z180_SAR0B, /* 22 DMA source address register ch 0 B */ 69 Z180_DAR0L, /* 23 DMA destination address register ch 0 L */ 70 Z180_DAR0H, /* 24 DMA destination address register ch 0 H */ 71 Z180_DAR0B, /* 25 DMA destination address register ch 0 B */ 72 Z180_BCR0L, /* 26 DMA byte count register ch 0 L */ 73 Z180_BCR0H, /* 27 DMA byte count register ch 0 H */ 74 Z180_MAR1L, /* 28 DMA memory address register ch 1 L */ 75 Z180_MAR1H, /* 29 DMA memory address register ch 1 H */ 76 Z180_MAR1B, /* 2a DMA memory address register ch 1 B */ 77 Z180_IAR1L, /* 2b DMA I/O address register ch 1 L */ 78 Z180_IAR1H, /* 2c DMA I/O address register ch 1 H */ 79 Z180_IAR1B, /* 2d (Z8S180/Z8L180) DMA I/O address register ch 1 B */ 80 Z180_BCR1L, /* 2e DMA byte count register ch 1 L */ 81 Z180_BCR1H, /* 2f DMA byte count register ch 1 H */ 82 Z180_DSTAT, /* 30 DMA status register */ 83 Z180_DMODE, /* 31 DMA mode register */ 84 Z180_DCNTL, /* 32 DMA/WAIT control register */ 85 Z180_IL, /* 33 INT vector low register */ 86 Z180_ITC, /* 34 INT/TRAP control register */ 87 Z180_IO35, /* 35 reserved */ 88 Z180_RCR, /* 36 refresh control register */ 89 Z180_IO37, /* 37 reserved */ 90 Z180_CBR, /* 38 MMU common base register */ 91 Z180_BBR, /* 39 MMU bank base register */ 92 Z180_CBAR, /* 3a MMU common/bank area register */ 93 Z180_IO3B, /* 3b reserved */ 94 Z180_IO3C, /* 3c reserved */ 95 Z180_IO3D, /* 3d reserved */ 96 Z180_OMCR, /* 3e operation mode control register */ 97 Z180_IOCR, /* 3f I/O control register */ 98 Z180_IOLINES /* read/write I/O lines */ 99 }; 100 101 enum { 102 Z180_TABLE_op, 103 Z180_TABLE_cb, 104 Z180_TABLE_ed, 105 Z180_TABLE_xy, 106 Z180_TABLE_xycb, 107 Z180_TABLE_ex /* cycles counts for taken jr/jp/call and interrupt latency (rst opcodes) */ 108 }; 109 110 extern int z180_icount; /* T-state count */ 111 #define z180_ICount z180_icount 112 113 #define Z180_INT0 0 /* Execute INT1 */ 114 #define Z180_INT1 1 /* Execute INT1 */ 115 #define Z180_INT2 2 /* Execute INT2 */ 116 #define Z180_INT_PRT0 3 /* Internal PRT channel 0 */ 117 #define Z180_INT_PRT1 4 /* Internal PRT channel 1 */ 118 #define Z180_INT_DMA0 5 /* Internal DMA channel 0 */ 119 #define Z180_INT_DMA1 6 /* Internal DMA channel 1 */ 120 #define Z180_INT_CSIO 7 /* Internal CSI/O */ 121 #define Z180_INT_ASCI0 8 /* Internal ASCI channel 0 */ 122 #define Z180_INT_ASCI1 9 /* Internal ASCI channel 1 */ 123 124 /* MMU mapped memory lookup */ 125 extern data8_t cpu_readmemz180(offs_t offset); 126 extern void cpu_writememz180(offs_t offset, data8_t data); 127 extern void cpu_setOPbasez180(int pc); 128 129 extern void z180_init(void); 130 extern void z180_reset (void *param); 131 extern void z180_exit (void); 132 extern int z180_execute(int cycles); 133 extern void z180_burn(int cycles); 134 extern unsigned z180_get_context (void *dst); 135 extern void z180_set_context (void *src); 136 extern const void *z180_get_cycle_table (int which); 137 extern void z180_set_cycle_table (int which, void *new_tbl); 138 extern unsigned z180_get_reg (int regnum); 139 extern READ_HANDLER( z180_internal_r ); 140 extern WRITE_HANDLER( z180_internal_w ); 141 extern void z180_set_reg (int regnum, unsigned val); 142 extern void z180_set_irq_line(int irqline, int state); 143 extern void z180_set_irq_callback(int (*irq_callback)(int)); 144 extern const char *z180_info(void *context, int regnum); 145 extern unsigned z180_dasm(char *buffer, unsigned pc); 146 147 #ifdef MAME_DEBUG 148 extern unsigned DasmZ180(char *buffer, unsigned pc); 149 #endif 150 151 #endif 152