1 /* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6 #ifndef ISA_INLINES_H
7 #define ISA_INLINES_H
8
9 #include "macros.h"
10
11 #include "arm.h"
12
13 #define ARM_COND_EQ (cpu->cpsr.z)
14 #define ARM_COND_NE (!cpu->cpsr.z)
15 #define ARM_COND_CS (cpu->cpsr.c)
16 #define ARM_COND_CC (!cpu->cpsr.c)
17 #define ARM_COND_MI (cpu->cpsr.n)
18 #define ARM_COND_PL (!cpu->cpsr.n)
19 #define ARM_COND_VS (cpu->cpsr.v)
20 #define ARM_COND_VC (!cpu->cpsr.v)
21 #define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
22 #define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
23 #define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
24 #define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
25 #define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
26 #define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
27 #define ARM_COND_AL 1
28
29 #define ARM_SIGN(I) ((I) >> 31)
30 #define ARM_SXT_8(I) (((int8_t) (I) << 24) >> 24)
31 #define ARM_SXT_16(I) (((int16_t) (I) << 16) >> 16)
32 #define ARM_UXT_64(I) (uint64_t)(uint32_t) (I)
33
34 #define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
35 #define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
36 #define ARM_BORROW_FROM_CARRY(M, N, D, C) (ARM_UXT_64(M) >= (ARM_UXT_64(N)) + (uint64_t) (C))
37 #define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
38 #define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
39
40 #define ARM_WAIT_MUL(R) \
41 { \
42 int32_t wait; \
43 if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
44 wait = 1; \
45 } else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
46 wait = 2; \
47 } else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
48 wait = 3; \
49 } else { \
50 wait = 4; \
51 } \
52 currentCycles += cpu->memory.stall(cpu, wait); \
53 }
54
55 #define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
56 #define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
57
ARMWritePC(struct ARMCore * cpu)58 static inline int32_t ARMWritePC(struct ARMCore* cpu) {
59 cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM);
60 cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);
61 LOAD_32(cpu->prefetch[0], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
62 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
63 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
64 return 2 + cpu->memory.activeNonseqCycles32 + cpu->memory.activeSeqCycles32;
65 }
66
ThumbWritePC(struct ARMCore * cpu)67 static inline int32_t ThumbWritePC(struct ARMCore* cpu) {
68 cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB);
69 cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);
70 LOAD_16(cpu->prefetch[0], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
71 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
72 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
73 return 2 + cpu->memory.activeNonseqCycles16 + cpu->memory.activeSeqCycles16;
74 }
75
_ARMModeHasSPSR(enum PrivilegeMode mode)76 static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
77 return mode != MODE_SYSTEM && mode != MODE_USER;
78 }
79
_ARMSetMode(struct ARMCore * cpu,enum ExecutionMode executionMode)80 static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
81 if (executionMode == cpu->executionMode) {
82 return;
83 }
84
85 cpu->executionMode = executionMode;
86 switch (executionMode) {
87 case MODE_ARM:
88 cpu->cpsr.t = 0;
89 break;
90 case MODE_THUMB:
91 cpu->cpsr.t = 1;
92 }
93 cpu->nextEvent = cpu->cycles;
94 }
95
_ARMReadCPSR(struct ARMCore * cpu)96 static inline void _ARMReadCPSR(struct ARMCore* cpu) {
97 _ARMSetMode(cpu, cpu->cpsr.t);
98 ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
99 cpu->irqh.readCPSR(cpu);
100 }
101
_ARMPCAddress(struct ARMCore * cpu)102 static inline uint32_t _ARMPCAddress(struct ARMCore* cpu) {
103 int instructionLength;
104 enum ExecutionMode mode = cpu->cpsr.t;
105 if (mode == MODE_ARM) {
106 instructionLength = WORD_SIZE_ARM;
107 } else {
108 instructionLength = WORD_SIZE_THUMB;
109 }
110 return cpu->gprs[ARM_PC] - instructionLength * 2;
111 }
112
113 #endif
114