1 /* 2 * Copyright © 2007-2019 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27 /** 28 ************************************************************************************************************************ 29 * @file addrlib2.h 30 * @brief Contains the Addr::V2::Lib class definition. 31 ************************************************************************************************************************ 32 */ 33 34 #ifndef __ADDR2_LIB2_H__ 35 #define __ADDR2_LIB2_H__ 36 37 #include "addrlib.h" 38 39 namespace Addr 40 { 41 namespace V2 42 { 43 44 /** 45 ************************************************************************************************************************ 46 * @brief Flags for SwizzleModeTable 47 ************************************************************************************************************************ 48 */ 49 union SwizzleModeFlags 50 { 51 struct 52 { 53 // Swizzle mode 54 UINT_32 isLinear : 1; // Linear 55 56 // Block size 57 UINT_32 is256b : 1; // Block size is 256B 58 UINT_32 is4kb : 1; // Block size is 4KB 59 UINT_32 is64kb : 1; // Block size is 64KB 60 UINT_32 isVar : 1; // Block size is variable 61 62 UINT_32 isZ : 1; // Z order swizzle mode 63 UINT_32 isStd : 1; // Standard swizzle mode 64 UINT_32 isDisp : 1; // Display swizzle mode 65 UINT_32 isRot : 1; // Rotate swizzle mode 66 67 // XOR mode 68 UINT_32 isXor : 1; // XOR after swizzle if set 69 70 UINT_32 isT : 1; // T mode 71 72 // GFX10 73 UINT_32 isRtOpt : 1; // mode opt for render target 74 75 UINT_32 reserved : 20; // Reserved bits 76 }; 77 78 UINT_32 u32All; 79 }; 80 81 struct Dim2d 82 { 83 UINT_32 w; 84 UINT_32 h; 85 }; 86 87 struct Dim3d 88 { 89 UINT_32 w; 90 UINT_32 h; 91 UINT_32 d; 92 }; 93 94 // Macro define resource block type 95 enum AddrBlockType 96 { 97 AddrBlockLinear = 0, // Resource uses linear swizzle mode 98 AddrBlockMicro = 1, // Resource uses 256B block 99 AddrBlockThin4KB = 2, // Resource uses thin 4KB block 100 AddrBlockThick4KB = 3, // Resource uses thick 4KB block 101 AddrBlockThin64KB = 4, // Resource uses thin 64KB block 102 AddrBlockThick64KB = 5, // Resource uses thick 64KB block 103 AddrBlockThinVar = 6, // Resource uses thin var block 104 AddrBlockThickVar = 7, // Resource uses thick var block 105 AddrBlockMaxTiledType, 106 107 }; 108 109 enum AddrSwSet 110 { 111 AddrSwSetZ = 1 << ADDR_SW_Z, 112 AddrSwSetS = 1 << ADDR_SW_S, 113 AddrSwSetD = 1 << ADDR_SW_D, 114 AddrSwSetR = 1 << ADDR_SW_R, 115 116 AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR, 117 }; 118 119 const UINT_32 Size256 = 256u; 120 const UINT_32 Size4K = 4096u; 121 const UINT_32 Size64K = 65536u; 122 123 const UINT_32 Log2Size256 = 8u; 124 const UINT_32 Log2Size4K = 12u; 125 const UINT_32 Log2Size64K = 16u; 126 127 /** 128 ************************************************************************************************************************ 129 * @brief Bit setting for swizzle pattern 130 ************************************************************************************************************************ 131 */ 132 union ADDR_BIT_SETTING 133 { 134 struct 135 { 136 UINT_16 x; 137 UINT_16 y; 138 UINT_16 z; 139 UINT_16 s; 140 }; 141 UINT_64 value; 142 }; 143 144 /** 145 ************************************************************************************************************************ 146 * @brief Swizzle pattern information 147 ************************************************************************************************************************ 148 */ 149 struct ADDR_SW_PATINFO 150 { 151 UINT_8 maxItemCount; 152 UINT_8 nibble01Idx; 153 UINT_16 nibble2Idx; 154 UINT_16 nibble3Idx; 155 UINT_8 nibble4Idx; 156 }; 157 158 /** 159 ************************************************************************************************************************ 160 * InitBit 161 * 162 * @brief 163 * Initialize bit setting value via a return value 164 ************************************************************************************************************************ 165 */ 166 #define InitBit(c, index) (1ull << ((c << 4) + index)) 167 168 const UINT_64 X0 = InitBit(0, 0); 169 const UINT_64 X1 = InitBit(0, 1); 170 const UINT_64 X2 = InitBit(0, 2); 171 const UINT_64 X3 = InitBit(0, 3); 172 const UINT_64 X4 = InitBit(0, 4); 173 const UINT_64 X5 = InitBit(0, 5); 174 const UINT_64 X6 = InitBit(0, 6); 175 const UINT_64 X7 = InitBit(0, 7); 176 const UINT_64 X8 = InitBit(0, 8); 177 const UINT_64 X9 = InitBit(0, 9); 178 const UINT_64 X10 = InitBit(0, 10); 179 const UINT_64 X11 = InitBit(0, 11); 180 181 const UINT_64 Y0 = InitBit(1, 0); 182 const UINT_64 Y1 = InitBit(1, 1); 183 const UINT_64 Y2 = InitBit(1, 2); 184 const UINT_64 Y3 = InitBit(1, 3); 185 const UINT_64 Y4 = InitBit(1, 4); 186 const UINT_64 Y5 = InitBit(1, 5); 187 const UINT_64 Y6 = InitBit(1, 6); 188 const UINT_64 Y7 = InitBit(1, 7); 189 const UINT_64 Y8 = InitBit(1, 8); 190 const UINT_64 Y9 = InitBit(1, 9); 191 const UINT_64 Y10 = InitBit(1, 10); 192 const UINT_64 Y11 = InitBit(1, 11); 193 194 const UINT_64 Z0 = InitBit(2, 0); 195 const UINT_64 Z1 = InitBit(2, 1); 196 const UINT_64 Z2 = InitBit(2, 2); 197 const UINT_64 Z3 = InitBit(2, 3); 198 const UINT_64 Z4 = InitBit(2, 4); 199 const UINT_64 Z5 = InitBit(2, 5); 200 const UINT_64 Z6 = InitBit(2, 6); 201 const UINT_64 Z7 = InitBit(2, 7); 202 const UINT_64 Z8 = InitBit(2, 8); 203 204 const UINT_64 S0 = InitBit(3, 0); 205 const UINT_64 S1 = InitBit(3, 1); 206 const UINT_64 S2 = InitBit(3, 2); 207 208 /** 209 ************************************************************************************************************************ 210 * @brief This class contains asic independent address lib functionalities 211 ************************************************************************************************************************ 212 */ 213 class Lib : public Addr::Lib 214 { 215 public: 216 virtual ~Lib(); 217 218 static Lib* GetLib( 219 ADDR_HANDLE hLib); 220 221 // 222 // Interface stubs 223 // 224 225 // For data surface 226 ADDR_E_RETURNCODE ComputeSurfaceInfo( 227 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 228 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 229 230 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord( 231 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 232 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 233 234 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr( 235 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 236 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 237 238 // For HTile 239 ADDR_E_RETURNCODE ComputeHtileInfo( 240 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 241 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 242 243 ADDR_E_RETURNCODE ComputeHtileAddrFromCoord( 244 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 245 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 246 247 ADDR_E_RETURNCODE ComputeHtileCoordFromAddr( 248 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 249 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 250 251 // For CMask 252 ADDR_E_RETURNCODE ComputeCmaskInfo( 253 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 254 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 255 256 ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord( 257 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 258 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 259 260 ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr( 261 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 262 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const; 263 264 // For FMask 265 ADDR_E_RETURNCODE ComputeFmaskInfo( 266 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 267 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 268 269 ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord( 270 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 271 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; 272 273 ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr( 274 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 275 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; 276 277 // For DCC key 278 ADDR_E_RETURNCODE ComputeDccInfo( 279 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 280 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 281 282 ADDR_E_RETURNCODE ComputeDccAddrFromCoord( 283 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 284 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 285 286 // Misc 287 ADDR_E_RETURNCODE ComputePipeBankXor( 288 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 289 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 290 291 ADDR_E_RETURNCODE ComputeSlicePipeBankXor( 292 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 293 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 294 295 ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern( 296 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 297 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 298 299 ADDR_E_RETURNCODE ComputeNonBlockCompressedView( 300 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 301 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 302 303 ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting( 304 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 305 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 306 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)307 virtual BOOL_32 IsValidDisplaySwizzleMode( 308 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 309 { 310 ADDR_NOT_IMPLEMENTED(); 311 return ADDR_NOTIMPLEMENTED; 312 } 313 314 protected: 315 Lib(); // Constructor is protected 316 Lib(const Client* pClient); 317 318 static const UINT_32 MaxNumOfBpp = 5; 319 static const UINT_32 MaxNumOfAA = 4; 320 321 static const Dim2d Block256_2d[MaxNumOfBpp]; 322 static const Dim3d Block1K_3d[MaxNumOfBpp]; 323 324 static const UINT_32 PrtAlignment = 64 * 1024; 325 static const UINT_32 MaxMacroBits = 20; 326 327 static const UINT_32 MaxMipLevels = 16; 328 IsValidSwMode(AddrSwizzleMode swizzleMode)329 BOOL_32 IsValidSwMode(AddrSwizzleMode swizzleMode) const 330 { 331 return (m_swizzleModeTable[swizzleMode].u32All != 0); 332 } 333 334 // Checking block size IsBlock256b(AddrSwizzleMode swizzleMode)335 BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const 336 { 337 return m_swizzleModeTable[swizzleMode].is256b; 338 } 339 IsBlock4kb(AddrSwizzleMode swizzleMode)340 BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const 341 { 342 return m_swizzleModeTable[swizzleMode].is4kb; 343 } 344 IsBlock64kb(AddrSwizzleMode swizzleMode)345 BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const 346 { 347 return m_swizzleModeTable[swizzleMode].is64kb; 348 } 349 IsBlockVariable(AddrSwizzleMode swizzleMode)350 BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const 351 { 352 return m_swizzleModeTable[swizzleMode].isVar; 353 } 354 355 // Checking swizzle mode IsLinear(AddrSwizzleMode swizzleMode)356 BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const 357 { 358 return m_swizzleModeTable[swizzleMode].isLinear; 359 } 360 IsRtOptSwizzle(AddrSwizzleMode swizzleMode)361 BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const 362 { 363 return m_swizzleModeTable[swizzleMode].isRtOpt; 364 } 365 IsZOrderSwizzle(AddrSwizzleMode swizzleMode)366 BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const 367 { 368 return m_swizzleModeTable[swizzleMode].isZ; 369 } 370 IsStandardSwizzle(AddrSwizzleMode swizzleMode)371 BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const 372 { 373 return m_swizzleModeTable[swizzleMode].isStd; 374 } 375 IsDisplaySwizzle(AddrSwizzleMode swizzleMode)376 BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const 377 { 378 return m_swizzleModeTable[swizzleMode].isDisp; 379 } 380 IsRotateSwizzle(AddrSwizzleMode swizzleMode)381 BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const 382 { 383 return m_swizzleModeTable[swizzleMode].isRot; 384 } 385 IsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)386 BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 387 { 388 return HwlIsStandardSwizzle(resourceType, swizzleMode); 389 } 390 IsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)391 BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 392 { 393 return HwlIsDisplaySwizzle(resourceType, swizzleMode); 394 } 395 IsXor(AddrSwizzleMode swizzleMode)396 BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const 397 { 398 return m_swizzleModeTable[swizzleMode].isXor; 399 } 400 IsPrt(AddrSwizzleMode swizzleMode)401 BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const 402 { 403 return m_swizzleModeTable[swizzleMode].isT; 404 } 405 IsNonPrtXor(AddrSwizzleMode swizzleMode)406 BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const 407 { 408 return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE)); 409 } 410 411 // Checking resource type IsTex1d(AddrResourceType resourceType)412 static BOOL_32 IsTex1d(AddrResourceType resourceType) 413 { 414 return (resourceType == ADDR_RSRC_TEX_1D); 415 } 416 IsTex2d(AddrResourceType resourceType)417 static BOOL_32 IsTex2d(AddrResourceType resourceType) 418 { 419 return (resourceType == ADDR_RSRC_TEX_2D); 420 } 421 IsTex3d(AddrResourceType resourceType)422 static BOOL_32 IsTex3d(AddrResourceType resourceType) 423 { 424 return (resourceType == ADDR_RSRC_TEX_3D); 425 } 426 IsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)427 BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 428 { 429 return HwlIsThick(resourceType, swizzleMode); 430 } 431 IsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)432 BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 433 { 434 return HwlIsThin(resourceType, swizzleMode); 435 } 436 GetBlockSizeLog2(AddrSwizzleMode swizzleMode)437 UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const 438 { 439 UINT_32 blockSizeLog2 = 0; 440 441 if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode)) 442 { 443 blockSizeLog2 = 8; 444 } 445 else if (IsBlock4kb(swizzleMode)) 446 { 447 blockSizeLog2 = 12; 448 } 449 else if (IsBlock64kb(swizzleMode)) 450 { 451 blockSizeLog2 = 16; 452 } 453 else if (IsBlockVariable(swizzleMode) && (m_blockVarSizeLog2 != 0)) 454 { 455 blockSizeLog2 = m_blockVarSizeLog2; 456 } 457 else 458 { 459 ADDR_ASSERT_ALWAYS(); 460 } 461 462 return blockSizeLog2; 463 } 464 GetBlockSize(AddrSwizzleMode swizzleMode)465 UINT_32 GetBlockSize(AddrSwizzleMode swizzleMode) const 466 { 467 return (1 << GetBlockSizeLog2(swizzleMode)); 468 } 469 GetFmaskBpp(UINT_32 sample,UINT_32 frag)470 static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag) 471 { 472 sample = (sample == 0) ? 1 : sample; 473 frag = (frag == 0) ? sample : frag; 474 475 UINT_32 fmaskBpp = QLog2(frag); 476 477 if (sample > frag) 478 { 479 fmaskBpp++; 480 } 481 482 if (fmaskBpp == 3) 483 { 484 fmaskBpp = 4; 485 } 486 487 fmaskBpp = Max(8u, fmaskBpp * sample); 488 489 return fmaskBpp; 490 } 491 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)492 virtual BOOL_32 HwlIsStandardSwizzle( 493 AddrResourceType resourceType, 494 AddrSwizzleMode swizzleMode) const 495 { 496 ADDR_NOT_IMPLEMENTED(); 497 return FALSE; 498 } 499 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)500 virtual BOOL_32 HwlIsDisplaySwizzle( 501 AddrResourceType resourceType, 502 AddrSwizzleMode swizzleMode) const 503 { 504 ADDR_NOT_IMPLEMENTED(); 505 return FALSE; 506 } 507 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)508 virtual BOOL_32 HwlIsThin( 509 AddrResourceType resourceType, 510 AddrSwizzleMode swizzleMode) const 511 { 512 ADDR_NOT_IMPLEMENTED(); 513 return FALSE; 514 } 515 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)516 virtual BOOL_32 HwlIsThick( 517 AddrResourceType resourceType, 518 AddrSwizzleMode swizzleMode) const 519 { 520 ADDR_NOT_IMPLEMENTED(); 521 return FALSE; 522 } 523 HwlComputeHtileInfo(const ADDR2_COMPUTE_HTILE_INFO_INPUT * pIn,ADDR2_COMPUTE_HTILE_INFO_OUTPUT * pOut)524 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 525 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 526 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const 527 { 528 ADDR_NOT_IMPLEMENTED(); 529 return ADDR_NOTSUPPORTED; 530 } 531 HwlComputeCmaskInfo(const ADDR2_COMPUTE_CMASK_INFO_INPUT * pIn,ADDR2_COMPUTE_CMASK_INFO_OUTPUT * pOut)532 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 533 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 534 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const 535 { 536 ADDR_NOT_IMPLEMENTED(); 537 return ADDR_NOTSUPPORTED; 538 } 539 HwlComputeDccInfo(const ADDR2_COMPUTE_DCCINFO_INPUT * pIn,ADDR2_COMPUTE_DCCINFO_OUTPUT * pOut)540 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 541 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 542 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const 543 { 544 ADDR_NOT_IMPLEMENTED(); 545 return ADDR_NOTSUPPORTED; 546 } 547 HwlSupportComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn)548 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 549 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn) 550 { 551 ADDR_NOT_IMPLEMENTED(); 552 return ADDR_NOTSUPPORTED; 553 } 554 HwlComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT * pOut)555 virtual VOID HwlComputeDccAddrFromCoord( 556 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 557 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) 558 { 559 ADDR_NOT_IMPLEMENTED(); 560 } 561 HwlComputeCmaskAddrFromCoord(const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT * pOut)562 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 563 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 564 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) 565 { 566 ADDR_NOT_IMPLEMENTED(); 567 return ADDR_NOTSUPPORTED; 568 } 569 HwlComputeHtileAddrFromCoord(const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT * pOut)570 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 571 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 572 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) 573 { 574 ADDR_NOT_IMPLEMENTED(); 575 return ADDR_NOTSUPPORTED; 576 } 577 HwlComputeHtileCoordFromAddr(const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT * pIn,ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT * pOut)578 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 579 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 580 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) 581 { 582 ADDR_NOT_IMPLEMENTED(); 583 return ADDR_NOTSUPPORTED; 584 } 585 HwlComputeBlock256Equation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)586 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 587 AddrResourceType rsrcType, 588 AddrSwizzleMode swMode, 589 UINT_32 elementBytesLog2, 590 ADDR_EQUATION* pEquation) const 591 { 592 ADDR_NOT_IMPLEMENTED(); 593 return ADDR_NOTSUPPORTED; 594 } 595 HwlComputeThinEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)596 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 597 AddrResourceType rsrcType, 598 AddrSwizzleMode swMode, 599 UINT_32 elementBytesLog2, 600 ADDR_EQUATION* pEquation) const 601 { 602 ADDR_NOT_IMPLEMENTED(); 603 return ADDR_NOTSUPPORTED; 604 } 605 HwlComputeThickEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)606 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 607 AddrResourceType rsrcType, 608 AddrSwizzleMode swMode, 609 UINT_32 elementBytesLog2, 610 ADDR_EQUATION* pEquation) const 611 { 612 ADDR_NOT_IMPLEMENTED(); 613 return ADDR_NOTSUPPORTED; 614 } 615 HwlGetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)616 virtual UINT_32 HwlGetEquationIndex( 617 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 618 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 619 { 620 ADDR_NOT_IMPLEMENTED(); 621 return ADDR_INVALID_EQUATION_INDEX; 622 } 623 GetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)624 UINT_32 GetEquationIndex( 625 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 626 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 627 { 628 return HwlGetEquationIndex(pIn, pOut); 629 } 630 HwlComputePipeBankXor(const ADDR2_COMPUTE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT * pOut)631 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 632 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 633 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const 634 { 635 ADDR_NOT_IMPLEMENTED(); 636 return ADDR_NOTSUPPORTED; 637 } 638 HwlComputeSlicePipeBankXor(const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT * pOut)639 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 640 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 641 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const 642 { 643 ADDR_NOT_IMPLEMENTED(); 644 return ADDR_NOTSUPPORTED; 645 } 646 HwlComputeSubResourceOffsetForSwizzlePattern(const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT * pIn,ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT * pOut)647 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 648 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 649 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const 650 { 651 ADDR_NOT_IMPLEMENTED(); 652 return ADDR_NOTSUPPORTED; 653 } 654 HwlComputeNonBlockCompressedView(const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT * pIn,ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT * pOut)655 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 656 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 657 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const 658 { 659 ADDR_NOT_IMPLEMENTED(); 660 return ADDR_NOTSUPPORTED; 661 } 662 HwlGetPreferredSurfaceSetting(const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT * pIn,ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT * pOut)663 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 664 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 665 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const 666 { 667 ADDR_NOT_IMPLEMENTED(); 668 return ADDR_NOTSUPPORTED; 669 } 670 HwlComputeSurfaceInfoSanityCheck(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)671 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 672 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 673 { 674 ADDR_NOT_IMPLEMENTED(); 675 return ADDR_NOTSUPPORTED; 676 } 677 HwlComputeSurfaceInfoTiled(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)678 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 679 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 680 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 681 { 682 ADDR_NOT_IMPLEMENTED(); 683 return ADDR_NOTIMPLEMENTED; 684 } 685 HwlComputeSurfaceInfoLinear(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)686 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 687 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 688 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 689 { 690 ADDR_NOT_IMPLEMENTED(); 691 return ADDR_NOTIMPLEMENTED; 692 } 693 HwlComputeSurfaceAddrFromCoordTiled(const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT * pOut)694 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 695 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 696 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const 697 { 698 ADDR_NOT_IMPLEMENTED(); 699 return ADDR_NOTIMPLEMENTED; 700 } 701 702 ADDR_E_RETURNCODE ComputeBlock256Equation( 703 AddrResourceType rsrcType, 704 AddrSwizzleMode swMode, 705 UINT_32 elementBytesLog2, 706 ADDR_EQUATION* pEquation) const; 707 708 ADDR_E_RETURNCODE ComputeThinEquation( 709 AddrResourceType rsrcType, 710 AddrSwizzleMode swMode, 711 UINT_32 elementBytesLog2, 712 ADDR_EQUATION* pEquation) const; 713 714 ADDR_E_RETURNCODE ComputeThickEquation( 715 AddrResourceType rsrcType, 716 AddrSwizzleMode swMode, 717 UINT_32 elementBytesLog2, 718 ADDR_EQUATION* pEquation) const; 719 720 ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck( 721 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 722 723 ADDR_E_RETURNCODE ComputeSurfaceInfoLinear( 724 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 725 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 726 727 ADDR_E_RETURNCODE ComputeSurfaceInfoTiled( 728 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 729 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 730 731 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear( 732 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 733 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 734 735 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled( 736 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 737 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 738 739 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrLinear( 740 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 741 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 742 743 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrTiled( 744 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 745 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 746 747 UINT_32 ComputeSurface2DMicroBlockOffset( 748 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 749 750 UINT_32 ComputeSurface3DMicroBlockOffset( 751 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 752 753 // Misc 754 ADDR_E_RETURNCODE ComputeBlockDimensionForSurf( 755 UINT_32* pWidth, 756 UINT_32* pHeight, 757 UINT_32* pDepth, 758 UINT_32 bpp, 759 UINT_32 numSamples, 760 AddrResourceType resourceType, 761 AddrSwizzleMode swizzleMode) const; 762 763 ADDR_E_RETURNCODE ComputeBlockDimension( 764 UINT_32* pWidth, 765 UINT_32* pHeight, 766 UINT_32* pDepth, 767 UINT_32 bpp, 768 AddrResourceType resourceType, 769 AddrSwizzleMode swizzleMode) const; 770 771 virtual VOID ComputeThinBlockDimension( 772 UINT_32* pWidth, 773 UINT_32* pHeight, 774 UINT_32* pDepth, 775 UINT_32 bpp, 776 UINT_32 numSamples, 777 AddrResourceType resourceType, 778 AddrSwizzleMode swizzleMode) const; 779 780 VOID ComputeThickBlockDimension( 781 UINT_32* pWidth, 782 UINT_32* pHeight, 783 UINT_32* pDepth, 784 UINT_32 bpp, 785 AddrResourceType resourceType, 786 AddrSwizzleMode swizzleMode) const; 787 ComputePadSize(const Dim3d * pBlkDim,UINT_32 width,UINT_32 height,UINT_32 numSlices,Dim3d * pPadDim)788 static UINT_64 ComputePadSize( 789 const Dim3d* pBlkDim, 790 UINT_32 width, 791 UINT_32 height, 792 UINT_32 numSlices, 793 Dim3d* pPadDim) 794 { 795 pPadDim->w = PowTwoAlign(width ,pBlkDim->w); 796 pPadDim->h = PowTwoAlign(height ,pBlkDim->h); 797 pPadDim->d = PowTwoAlign(numSlices, pBlkDim->d); 798 return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d; 799 } 800 801 static ADDR_E_RETURNCODE ExtractPipeBankXor( 802 UINT_32 pipeBankXor, 803 UINT_32 bankBits, 804 UINT_32 pipeBits, 805 UINT_32* pBankX, 806 UINT_32* pPipeX); 807 Valid3DMipSliceIdConstraint(UINT_32 numSlices,UINT_32 mipId,UINT_32 slice)808 static BOOL_32 Valid3DMipSliceIdConstraint( 809 UINT_32 numSlices, 810 UINT_32 mipId, 811 UINT_32 slice) 812 { 813 return (Max((numSlices >> mipId), 1u) > slice); 814 } 815 816 Dim3d GetMipTailDim( 817 AddrResourceType resourceType, 818 AddrSwizzleMode swizzleMode, 819 UINT_32 blockWidth, 820 UINT_32 blockHeight, 821 UINT_32 blockDepth) const; 822 IsLocalHeap(AddrResrouceLocation resourceType)823 static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType) 824 { 825 return ((resourceType == ADDR_RSRC_LOC_LOCAL) || 826 (resourceType == ADDR_RSRC_LOC_INVIS)); 827 } 828 IsInvisibleHeap(AddrResrouceLocation resourceType)829 static BOOL_32 IsInvisibleHeap(AddrResrouceLocation resourceType) 830 { 831 return (resourceType == ADDR_RSRC_LOC_INVIS); 832 } 833 IsNonlocalHeap(AddrResrouceLocation resourceType)834 static BOOL_32 IsNonlocalHeap(AddrResrouceLocation resourceType) 835 { 836 return ((resourceType == ADDR_RSRC_LOC_USWC) || 837 (resourceType == ADDR_RSRC_LOC_CACHED)); 838 } 839 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)840 UINT_32 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 841 { 842 UINT_32 numPipeLog2 = pipeAligned ? Min(m_pipesLog2 + m_seLog2, 5u) : 0; 843 844 if (IsXor(swizzleMode)) 845 { 846 UINT_32 maxPipeLog2 = GetBlockSizeLog2(swizzleMode) - m_pipeInterleaveLog2; 847 848 numPipeLog2 = Min(numPipeLog2, maxPipeLog2); 849 } 850 851 return numPipeLog2; 852 } 853 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)854 UINT_32 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 855 { 856 return (1 << GetPipeLog2ForMetaAddressing(pipeAligned, swizzleMode)); 857 } 858 VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)859 VOID VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 860 { 861 #if DEBUG 862 if (pIn->numMipLevels > 1) 863 { 864 UINT_32 actualMipLevels = 1; 865 switch (pIn->resourceType) 866 { 867 case ADDR_RSRC_TEX_3D: 868 // Fall through to share 2D case 869 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->numSlices) + 1); 870 case ADDR_RSRC_TEX_2D: 871 // Fall through to share 1D case 872 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->height) + 1); 873 case ADDR_RSRC_TEX_1D: 874 // Base 1D case 875 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->width) + 1); 876 break; 877 default: 878 ADDR_ASSERT_ALWAYS(); 879 break; 880 } 881 // Client pass wrong number of MipLevels to addrlib and result will be bad. 882 // Not sure if we should fail this calling instead of putting an assertion here. 883 ADDR_ASSERT(actualMipLevels >= pIn->numMipLevels); 884 } 885 #endif 886 } 887 ApplyCustomerPipeBankXor(AddrSwizzleMode swizzleMode,UINT_32 pipeBankXor,UINT_32 bankBits,UINT_32 pipeBits,UINT_32 * pBlockOffset)888 ADDR_E_RETURNCODE ApplyCustomerPipeBankXor( 889 AddrSwizzleMode swizzleMode, 890 UINT_32 pipeBankXor, 891 UINT_32 bankBits, 892 UINT_32 pipeBits, 893 UINT_32* pBlockOffset) const 894 { 895 ADDR_E_RETURNCODE returnCode = ADDR_OK; 896 897 if (IsXor(swizzleMode)) 898 { 899 // Apply driver set bankPipeXor 900 UINT_32 bankX = 0; 901 UINT_32 pipeX = 0; 902 returnCode = ExtractPipeBankXor(pipeBankXor, bankBits, pipeBits, &bankX, &pipeX); 903 *pBlockOffset ^= (pipeX << m_pipeInterleaveLog2); 904 *pBlockOffset ^= (bankX << (m_pipeInterleaveLog2 + pipeBits)); 905 } 906 907 return returnCode; 908 } 909 910 UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const; 911 912 ADDR_E_RETURNCODE ApplyCustomizedPitchHeight( 913 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 914 UINT_32 elementBytes, 915 UINT_32 pitchAlignInElement, 916 UINT_32* pPitch, 917 UINT_32* pHeight) const; 918 919 VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 920 921 VOID FilterInvalidEqSwizzleMode( 922 ADDR2_SWMODE_SET& allowedSwModeSet, 923 AddrResourceType resourceType, 924 UINT_32 elemLog2) const; 925 926 static BOOL_32 IsBlockTypeAvaiable(ADDR2_BLOCK_SET blockSet, AddrBlockType blockType); 927 928 static BOOL_32 BlockTypeWithinMemoryBudget( 929 UINT_64 minSize, 930 UINT_64 newBlockTypeSize, 931 UINT_32 ratioLow, 932 UINT_32 ratioHi, 933 DOUBLE memoryBudget = 0.0f, 934 BOOL_32 newBlockTypeBigger = TRUE); 935 936 #if DEBUG 937 VOID ValidateStereoInfo( 938 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 939 const ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 940 #endif 941 942 UINT_32 m_se; ///< Number of shader engine 943 UINT_32 m_rbPerSe; ///< Number of render backend per shader engine 944 UINT_32 m_maxCompFrag; ///< Number of max compressed fragment 945 946 UINT_32 m_banksLog2; ///< Number of bank Log2 947 UINT_32 m_pipesLog2; ///< Number of pipe per shader engine Log2 948 UINT_32 m_seLog2; ///< Number of shader engine Log2 949 UINT_32 m_rbPerSeLog2; ///< Number of render backend per shader engine Log2 950 UINT_32 m_maxCompFragLog2; ///< Number of max compressed fragment Log2 951 952 UINT_32 m_pipeInterleaveLog2; ///< Log2 of pipe interleave bytes 953 954 UINT_32 m_blockVarSizeLog2; ///< Log2 of block var size 955 956 SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE]; ///< Swizzle mode table 957 958 // Max number of swizzle mode supported for equation 959 static const UINT_32 MaxSwModeType = 32; 960 // Max number of resource type (2D/3D) supported for equation 961 static const UINT_32 MaxRsrcType = 2; 962 // Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp) 963 static const UINT_32 MaxElementBytesLog2 = 5; 964 // Almost all swizzle mode + resource type support equation 965 static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwModeType * MaxRsrcType; 966 // Equation table 967 ADDR_EQUATION m_equationTable[EquationTableSize]; 968 969 // Number of equation entries in the table 970 UINT_32 m_numEquations; 971 // Equation lookup table according to bpp and tile index 972 UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwModeType][MaxElementBytesLog2]; 973 974 private: 975 // Disallow the copy constructor 976 Lib(const Lib& a); 977 978 // Disallow the assignment operator 979 Lib& operator=(const Lib& a); 980 }; 981 982 } // V2 983 } // Addr 984 985 #endif 986 987