1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16_sh0(<8 x i16> %a) { 5; CHECK-LABEL: test_vbicq_n_u16_sh0: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vbic.i16 q0, #0x64 8; CHECK-NEXT: bx lr 9entry: 10 %0 = and <8 x i16> %a, <i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101> 11 ret <8 x i16> %0 12} 13 14define arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16_sh8(<8 x i16> %a) { 15; CHECK-LABEL: test_vbicq_n_u16_sh8: 16; CHECK: @ %bb.0: @ %entry 17; CHECK-NEXT: vbic.i16 q0, #0x6400 18; CHECK-NEXT: bx lr 19entry: 20 %0 = and <8 x i16> %a, <i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601> 21 ret <8 x i16> %0 22} 23 24define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh0(<4 x i32> %a) { 25; CHECK-LABEL: test_vbicq_n_u32_sh0: 26; CHECK: @ %bb.0: @ %entry 27; CHECK-NEXT: vbic.i32 q0, #0x64 28; CHECK-NEXT: bx lr 29entry: 30 %0 = and <4 x i32> %a, <i32 -101, i32 -101, i32 -101, i32 -101> 31 ret <4 x i32> %0 32} 33 34define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh8(<4 x i32> %a) { 35; CHECK-LABEL: test_vbicq_n_u32_sh8: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: vbic.i32 q0, #0x6400 38; CHECK-NEXT: bx lr 39entry: 40 %0 = and <4 x i32> %a, <i32 -25601, i32 -25601, i32 -25601, i32 -25601> 41 ret <4 x i32> %0 42} 43 44define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh16(<4 x i32> %a) { 45; CHECK-LABEL: test_vbicq_n_u32_sh16: 46; CHECK: @ %bb.0: @ %entry 47; CHECK-NEXT: vbic.i32 q0, #0x640000 48; CHECK-NEXT: bx lr 49entry: 50 %0 = and <4 x i32> %a, <i32 -6553601, i32 -6553601, i32 -6553601, i32 -6553601> 51 ret <4 x i32> %0 52} 53 54define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_sh24(<4 x i32> %a) { 55; CHECK-LABEL: test_vbicq_n_u32_sh24: 56; CHECK: @ %bb.0: @ %entry 57; CHECK-NEXT: vbic.i32 q0, #0x64000000 58; CHECK-NEXT: bx lr 59entry: 60 %0 = and <4 x i32> %a, <i32 -1677721601, i32 -1677721601, i32 -1677721601, i32 -1677721601> 61 ret <4 x i32> %0 62} 63 64; The immediate in this case is legal for a VMVN but not for a VBIC, 65; so in this case we expect to see the constant being prepared in 66; another register. 67define arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32_illegal(<4 x i32> %a) { 68; CHECK-LABEL: test_vbicq_n_u32_illegal: 69; CHECK: @ %bb.0: @ %entry 70; CHECK-NEXT: vmvn.i32 q1, #0x54ff 71; CHECK-NEXT: vand q0, q0, q1 72; CHECK-NEXT: bx lr 73entry: 74 %0 = and <4 x i32> %a, <i32 -21760, i32 -21760, i32 -21760, i32 -21760> 75 ret <4 x i32> %0 76} 77 78define arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16_sh0(<8 x i16> %a) { 79; CHECK-LABEL: test_vorrq_n_u16_sh0: 80; CHECK: @ %bb.0: @ %entry 81; CHECK-NEXT: vorr.i16 q0, #0x64 82; CHECK-NEXT: bx lr 83entry: 84 %0 = or <8 x i16> %a, <i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100> 85 ret <8 x i16> %0 86} 87 88define arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16_sh8(<8 x i16> %a) { 89; CHECK-LABEL: test_vorrq_n_u16_sh8: 90; CHECK: @ %bb.0: @ %entry 91; CHECK-NEXT: vorr.i16 q0, #0x6400 92; CHECK-NEXT: bx lr 93entry: 94 %0 = or <8 x i16> %a, <i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600> 95 ret <8 x i16> %0 96} 97 98define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh0(<4 x i32> %a) { 99; CHECK-LABEL: test_vorrq_n_u32_sh0: 100; CHECK: @ %bb.0: @ %entry 101; CHECK-NEXT: vorr.i32 q0, #0x64 102; CHECK-NEXT: bx lr 103entry: 104 %0 = or <4 x i32> %a, <i32 100, i32 100, i32 100, i32 100> 105 ret <4 x i32> %0 106} 107 108define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh8(<4 x i32> %a) { 109; CHECK-LABEL: test_vorrq_n_u32_sh8: 110; CHECK: @ %bb.0: @ %entry 111; CHECK-NEXT: vorr.i32 q0, #0x6400 112; CHECK-NEXT: bx lr 113entry: 114 %0 = or <4 x i32> %a, <i32 25600, i32 25600, i32 25600, i32 25600> 115 ret <4 x i32> %0 116} 117 118define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh16(<4 x i32> %a) { 119; CHECK-LABEL: test_vorrq_n_u32_sh16: 120; CHECK: @ %bb.0: @ %entry 121; CHECK-NEXT: vorr.i32 q0, #0x640000 122; CHECK-NEXT: bx lr 123entry: 124 %0 = or <4 x i32> %a, <i32 6553600, i32 6553600, i32 6553600, i32 6553600> 125 ret <4 x i32> %0 126} 127 128define arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32_sh24(<4 x i32> %a) { 129; CHECK-LABEL: test_vorrq_n_u32_sh24: 130; CHECK: @ %bb.0: @ %entry 131; CHECK-NEXT: vorr.i32 q0, #0x64000000 132; CHECK-NEXT: bx lr 133entry: 134 %0 = or <4 x i32> %a, <i32 1677721600, i32 1677721600, i32 1677721600, i32 1677721600> 135 ret <4 x i32> %0 136} 137 138define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16_sh0(<8 x i16> %a, i16 zeroext %p) { 139; CHECK-LABEL: test_vbicq_m_n_u16_sh0: 140; CHECK: @ %bb.0: @ %entry 141; CHECK-NEXT: vmsr p0, r0 142; CHECK-NEXT: vpst 143; CHECK-NEXT: vbict.i16 q0, #0x64 144; CHECK-NEXT: bx lr 145entry: 146 %0 = zext i16 %p to i32 147 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 148 %2 = and <8 x i16> %a, <i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101, i16 -101> 149 %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %a 150 ret <8 x i16> %3 151} 152 153define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16_sh8(<8 x i16> %a, i16 zeroext %p) { 154; CHECK-LABEL: test_vbicq_m_n_u16_sh8: 155; CHECK: @ %bb.0: @ %entry 156; CHECK-NEXT: vmsr p0, r0 157; CHECK-NEXT: vpst 158; CHECK-NEXT: vbict.i16 q0, #0x6400 159; CHECK-NEXT: bx lr 160entry: 161 %0 = zext i16 %p to i32 162 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 163 %2 = and <8 x i16> %a, <i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601, i16 -25601> 164 %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %a 165 ret <8 x i16> %3 166} 167 168define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh0(<4 x i32> %a, i16 zeroext %p) { 169; CHECK-LABEL: test_vbicq_m_n_u32_sh0: 170; CHECK: @ %bb.0: @ %entry 171; CHECK-NEXT: vmsr p0, r0 172; CHECK-NEXT: vpst 173; CHECK-NEXT: vbict.i32 q0, #0x64 174; CHECK-NEXT: bx lr 175entry: 176 %0 = zext i16 %p to i32 177 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 178 %2 = and <4 x i32> %a, <i32 -101, i32 -101, i32 -101, i32 -101> 179 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a 180 ret <4 x i32> %3 181} 182 183define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh8(<4 x i32> %a, i16 zeroext %p) { 184; CHECK-LABEL: test_vbicq_m_n_u32_sh8: 185; CHECK: @ %bb.0: @ %entry 186; CHECK-NEXT: vmsr p0, r0 187; CHECK-NEXT: vpst 188; CHECK-NEXT: vbict.i32 q0, #0x6400 189; CHECK-NEXT: bx lr 190entry: 191 %0 = zext i16 %p to i32 192 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 193 %2 = and <4 x i32> %a, <i32 -25601, i32 -25601, i32 -25601, i32 -25601> 194 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a 195 ret <4 x i32> %3 196} 197 198define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh16(<4 x i32> %a, i16 zeroext %p) { 199; CHECK-LABEL: test_vbicq_m_n_u32_sh16: 200; CHECK: @ %bb.0: @ %entry 201; CHECK-NEXT: vmsr p0, r0 202; CHECK-NEXT: vpst 203; CHECK-NEXT: vbict.i32 q0, #0x640000 204; CHECK-NEXT: bx lr 205entry: 206 %0 = zext i16 %p to i32 207 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 208 %2 = and <4 x i32> %a, <i32 -6553601, i32 -6553601, i32 -6553601, i32 -6553601> 209 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a 210 ret <4 x i32> %3 211} 212 213define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32_sh24(<4 x i32> %a, i16 zeroext %p) { 214; CHECK-LABEL: test_vbicq_m_n_u32_sh24: 215; CHECK: @ %bb.0: @ %entry 216; CHECK-NEXT: vmsr p0, r0 217; CHECK-NEXT: vpst 218; CHECK-NEXT: vbict.i32 q0, #0x64000000 219; CHECK-NEXT: bx lr 220entry: 221 %0 = zext i16 %p to i32 222 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 223 %2 = and <4 x i32> %a, <i32 -1677721601, i32 -1677721601, i32 -1677721601, i32 -1677721601> 224 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a 225 ret <4 x i32> %3 226} 227 228define arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16_sh0(<8 x i16> %a, i16 zeroext %p) { 229; CHECK-LABEL: test_vorrq_m_n_u16_sh0: 230; CHECK: @ %bb.0: @ %entry 231; CHECK-NEXT: vmsr p0, r0 232; CHECK-NEXT: vpst 233; CHECK-NEXT: vorrt.i16 q0, #0x64 234; CHECK-NEXT: bx lr 235entry: 236 %0 = zext i16 %p to i32 237 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 238 %2 = or <8 x i16> %a, <i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100, i16 100> 239 %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %a 240 ret <8 x i16> %3 241} 242 243define arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16_sh8(<8 x i16> %a, i16 zeroext %p) { 244; CHECK-LABEL: test_vorrq_m_n_u16_sh8: 245; CHECK: @ %bb.0: @ %entry 246; CHECK-NEXT: vmsr p0, r0 247; CHECK-NEXT: vpst 248; CHECK-NEXT: vorrt.i16 q0, #0x6400 249; CHECK-NEXT: bx lr 250entry: 251 %0 = zext i16 %p to i32 252 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 253 %2 = or <8 x i16> %a, <i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600, i16 25600> 254 %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %a 255 ret <8 x i16> %3 256} 257 258define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh0(<4 x i32> %a, i16 zeroext %p) { 259; CHECK-LABEL: test_vorrq_m_n_u32_sh0: 260; CHECK: @ %bb.0: @ %entry 261; CHECK-NEXT: vmsr p0, r0 262; CHECK-NEXT: vpst 263; CHECK-NEXT: vorrt.i32 q0, #0x64 264; CHECK-NEXT: bx lr 265entry: 266 %0 = zext i16 %p to i32 267 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 268 %2 = or <4 x i32> %a, <i32 100, i32 100, i32 100, i32 100> 269 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a 270 ret <4 x i32> %3 271} 272 273define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh8(<4 x i32> %a, i16 zeroext %p) { 274; CHECK-LABEL: test_vorrq_m_n_u32_sh8: 275; CHECK: @ %bb.0: @ %entry 276; CHECK-NEXT: vmsr p0, r0 277; CHECK-NEXT: vpst 278; CHECK-NEXT: vorrt.i32 q0, #0x6400 279; CHECK-NEXT: bx lr 280entry: 281 %0 = zext i16 %p to i32 282 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 283 %2 = or <4 x i32> %a, <i32 25600, i32 25600, i32 25600, i32 25600> 284 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a 285 ret <4 x i32> %3 286} 287 288define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh16(<4 x i32> %a, i16 zeroext %p) { 289; CHECK-LABEL: test_vorrq_m_n_u32_sh16: 290; CHECK: @ %bb.0: @ %entry 291; CHECK-NEXT: vmsr p0, r0 292; CHECK-NEXT: vpst 293; CHECK-NEXT: vorrt.i32 q0, #0x640000 294; CHECK-NEXT: bx lr 295entry: 296 %0 = zext i16 %p to i32 297 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 298 %2 = or <4 x i32> %a, <i32 6553600, i32 6553600, i32 6553600, i32 6553600> 299 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a 300 ret <4 x i32> %3 301} 302 303define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32_sh24(<4 x i32> %a, i16 zeroext %p) { 304; CHECK-LABEL: test_vorrq_m_n_u32_sh24: 305; CHECK: @ %bb.0: @ %entry 306; CHECK-NEXT: vmsr p0, r0 307; CHECK-NEXT: vpst 308; CHECK-NEXT: vorrt.i32 q0, #0x64000000 309; CHECK-NEXT: bx lr 310entry: 311 %0 = zext i16 %p to i32 312 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 313 %2 = or <4 x i32> %a, <i32 1677721600, i32 1677721600, i32 1677721600, i32 1677721600> 314 %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %a 315 ret <4 x i32> %3 316} 317 318define arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() { 319; CHECK-LABEL: test_vmvnq_n_u16: 320; CHECK: @ %bb.0: @ %entry 321; CHECK-NEXT: vmvn.i16 q0, #0xaa00 322; CHECK-NEXT: bx lr 323entry: 324 ret <8 x i16> <i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521> 325} 326 327define arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() { 328; CHECK-LABEL: test_vmvnq_n_u32: 329; CHECK: @ %bb.0: @ %entry 330; CHECK-NEXT: vmvn.i32 q0, #0xaa00 331; CHECK-NEXT: bx lr 332entry: 333 ret <4 x i32> <i32 -43521, i32 -43521, i32 -43521, i32 -43521> 334} 335 336define arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> %inactive, i16 zeroext %p) { 337; CHECK-LABEL: test_vmvnq_m_n_u16: 338; CHECK: @ %bb.0: @ %entry 339; CHECK-NEXT: vmsr p0, r0 340; CHECK-NEXT: vpst 341; CHECK-NEXT: vmvnt.i16 q0, #0xaa00 342; CHECK-NEXT: bx lr 343entry: 344 %0 = zext i16 %p to i32 345 %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) 346 %2 = select <8 x i1> %1, <8 x i16> <i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521, i16 -43521>, <8 x i16> %inactive 347 ret <8 x i16> %2 348} 349 350define arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_u32(<4 x i32> %inactive, i16 zeroext %p) { 351; CHECK-LABEL: test_vmvnq_m_n_u32: 352; CHECK: @ %bb.0: @ %entry 353; CHECK-NEXT: vmsr p0, r0 354; CHECK-NEXT: vpst 355; CHECK-NEXT: vmvnt.i32 q0, #0xaa00 356; CHECK-NEXT: bx lr 357entry: 358 %0 = zext i16 %p to i32 359 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) 360 %2 = select <4 x i1> %1, <4 x i32> <i32 -43521, i32 -43521, i32 -43521, i32 -43521>, <4 x i32> %inactive 361 ret <4 x i32> %2 362} 363 364declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) 365declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) 366