1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "ac_shader_util.h"
28 #include "ac_debug.h"
29
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "sid.h"
32 #include "util/macros.h"
33 #include "util/u_cpu_detect.h"
34 #include "util/u_math.h"
35 #include "util/os_misc.h"
36 #include "util/bitset.h"
37
38 #include <stdio.h>
39 #include <ctype.h>
40
41 #ifdef _WIN32
42 #define DRM_CAP_ADDFB2_MODIFIERS 0x10
43 #define DRM_CAP_SYNCOBJ 0x13
44 #define DRM_CAP_SYNCOBJ_TIMELINE 0x14
45 #define AMDGPU_GEM_DOMAIN_GTT 0x2
46 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
47 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
48 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
49 #define AMDGPU_HW_IP_GFX 0
50 #define AMDGPU_HW_IP_COMPUTE 1
51 #define AMDGPU_HW_IP_DMA 2
52 #define AMDGPU_HW_IP_UVD 3
53 #define AMDGPU_HW_IP_VCE 4
54 #define AMDGPU_HW_IP_UVD_ENC 5
55 #define AMDGPU_HW_IP_VCN_DEC 6
56 #define AMDGPU_HW_IP_VCN_ENC 7
57 #define AMDGPU_HW_IP_VCN_JPEG 8
58 #define AMDGPU_IDS_FLAGS_FUSION 0x1
59 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
60 #define AMDGPU_IDS_FLAGS_TMZ 0x4
61 #define AMDGPU_INFO_FW_VCE 0x1
62 #define AMDGPU_INFO_FW_UVD 0x2
63 #define AMDGPU_INFO_FW_GFX_ME 0x04
64 #define AMDGPU_INFO_FW_GFX_PFP 0x05
65 #define AMDGPU_INFO_FW_GFX_CE 0x06
66 #define AMDGPU_INFO_DEV_INFO 0x16
67 #define AMDGPU_INFO_MEMORY 0x19
68 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
69 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
70 #define AMDGPU_INFO_FW_GFX_MEC 0x08
71 struct drm_amdgpu_heap_info {
72 uint64_t total_heap_size;
73 };
74 struct drm_amdgpu_memory_info {
75 struct drm_amdgpu_heap_info vram;
76 struct drm_amdgpu_heap_info cpu_accessible_vram;
77 struct drm_amdgpu_heap_info gtt;
78 };
79 struct drm_amdgpu_info_device {
80 uint32_t num_tcc_blocks;
81 uint32_t pa_sc_tile_steering_override;
82 uint64_t tcc_disabled_mask;
83 };
84 struct drm_amdgpu_info_hw_ip {
85 uint32_t ib_start_alignment;
86 uint32_t ib_size_alignment;
87 uint32_t available_rings;
88 };
89 typedef struct _drmPciBusInfo {
90 uint16_t domain;
91 uint8_t bus;
92 uint8_t dev;
93 uint8_t func;
94 } drmPciBusInfo, *drmPciBusInfoPtr;
95 typedef struct _drmDevice {
96 union {
97 drmPciBusInfoPtr pci;
98 } businfo;
99 } drmDevice, *drmDevicePtr;
100 enum amdgpu_sw_info {
101 amdgpu_sw_info_address32_hi = 0,
102 };
103 typedef struct amdgpu_device *amdgpu_device_handle;
104 typedef struct amdgpu_bo *amdgpu_bo_handle;
105 struct amdgpu_bo_alloc_request {
106 uint64_t alloc_size;
107 uint64_t phys_alignment;
108 uint32_t preferred_heap;
109 uint64_t flags;
110 };
111 struct amdgpu_gds_resource_info {
112 uint32_t gds_gfx_partition_size;
113 uint32_t gds_total_size;
114 };
115 struct amdgpu_buffer_size_alignments {
116 uint64_t size_local;
117 uint64_t size_remote;
118 };
119 struct amdgpu_heap_info {
120 uint64_t heap_size;
121 };
122 struct amdgpu_gpu_info {
123 uint32_t asic_id;
124 uint32_t chip_external_rev;
125 uint32_t family_id;
126 uint64_t ids_flags;
127 uint64_t max_engine_clk;
128 uint64_t max_memory_clk;
129 uint32_t num_shader_engines;
130 uint32_t num_shader_arrays_per_engine;
131 uint32_t rb_pipes;
132 uint32_t enabled_rb_pipes_mask;
133 uint32_t gpu_counter_freq;
134 uint32_t mc_arb_ramcfg;
135 uint32_t gb_addr_cfg;
136 uint32_t gb_tile_mode[32];
137 uint32_t gb_macro_tile_mode[16];
138 uint32_t cu_bitmap[4][4];
139 uint32_t vram_type;
140 uint32_t vram_bit_width;
141 uint32_t ce_ram_size;
142 uint32_t vce_harvest_config;
143 uint32_t pci_rev_id;
144 };
drmGetCap(int fd,uint64_t capability,uint64_t * value)145 static int drmGetCap(int fd, uint64_t capability, uint64_t *value)
146 {
147 return -EINVAL;
148 }
drmFreeDevice(drmDevicePtr * device)149 static void drmFreeDevice(drmDevicePtr *device)
150 {
151 }
drmGetDevice2(int fd,uint32_t flags,drmDevicePtr * device)152 static int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device)
153 {
154 return -ENODEV;
155 }
amdgpu_bo_alloc(amdgpu_device_handle dev,struct amdgpu_bo_alloc_request * alloc_buffer,amdgpu_bo_handle * buf_handle)156 static int amdgpu_bo_alloc(amdgpu_device_handle dev,
157 struct amdgpu_bo_alloc_request *alloc_buffer,
158 amdgpu_bo_handle *buf_handle)
159 {
160 return -EINVAL;
161 }
amdgpu_bo_free(amdgpu_bo_handle buf_handle)162 static int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
163 {
164 return -EINVAL;
165 }
amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,struct amdgpu_buffer_size_alignments * info)166 static int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
167 struct amdgpu_buffer_size_alignments
168 *info)
169 {
170 return -EINVAL;
171 }
amdgpu_query_firmware_version(amdgpu_device_handle dev,unsigned fw_type,unsigned ip_instance,unsigned index,uint32_t * version,uint32_t * feature)172 static int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
173 unsigned ip_instance, unsigned index,
174 uint32_t *version, uint32_t *feature)
175 {
176 return -EINVAL;
177 }
amdgpu_query_hw_ip_info(amdgpu_device_handle dev,unsigned type,unsigned ip_instance,struct drm_amdgpu_info_hw_ip * info)178 static int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
179 unsigned ip_instance,
180 struct drm_amdgpu_info_hw_ip *info)
181 {
182 return -EINVAL;
183 }
amdgpu_query_heap_info(amdgpu_device_handle dev,uint32_t heap,uint32_t flags,struct amdgpu_heap_info * info)184 static int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
185 uint32_t flags, struct amdgpu_heap_info *info)
186 {
187 return -EINVAL;
188 }
amdgpu_query_gpu_info(amdgpu_device_handle dev,struct amdgpu_gpu_info * info)189 static int amdgpu_query_gpu_info(amdgpu_device_handle dev,
190 struct amdgpu_gpu_info *info)
191 {
192 return -EINVAL;
193 }
amdgpu_query_info(amdgpu_device_handle dev,unsigned info_id,unsigned size,void * value)194 static int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
195 unsigned size, void *value)
196 {
197 return -EINVAL;
198 }
amdgpu_query_sw_info(amdgpu_device_handle dev,enum amdgpu_sw_info info,void * value)199 static int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
200 void *value)
201 {
202 return -EINVAL;
203 }
amdgpu_query_gds_info(amdgpu_device_handle dev,struct amdgpu_gds_resource_info * gds_info)204 static int amdgpu_query_gds_info(amdgpu_device_handle dev,
205 struct amdgpu_gds_resource_info *gds_info)
206 {
207 return -EINVAL;
208 }
amdgpu_query_video_caps_info(amdgpu_device_handle dev,unsigned cap_type,unsigned size,void * value)209 static int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type,
210 unsigned size, void *value)
211 {
212 return -EINVAL;
213 }
amdgpu_get_marketing_name(amdgpu_device_handle dev)214 static const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
215 {
216 return NULL;
217 }
218 #else
219 #include "drm-uapi/amdgpu_drm.h"
220 #include <amdgpu.h>
221 #include <xf86drm.h>
222 #endif
223
224 #define CIK_TILE_MODE_COLOR_2D 14
225
226 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
227 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
228 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
229 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
230 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
231 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
232 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
233 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
234 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
235 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
236 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
237 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
238 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
239 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
240 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
241
cik_get_num_tile_pipes(struct amdgpu_gpu_info * info)242 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
243 {
244 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
245
246 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
247 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
248 return 2;
249 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
250 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
251 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
252 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
253 return 4;
254 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
255 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
256 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
257 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
258 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
259 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
260 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
261 return 8;
262 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
263 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
264 return 16;
265 default:
266 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
267 assert(!"this should never occur");
268 return 2;
269 }
270 }
271
has_syncobj(int fd)272 static bool has_syncobj(int fd)
273 {
274 uint64_t value;
275 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
276 return false;
277 return value ? true : false;
278 }
279
has_timeline_syncobj(int fd)280 static bool has_timeline_syncobj(int fd)
281 {
282 uint64_t value;
283 if (drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &value))
284 return false;
285 return value ? true : false;
286 }
287
has_modifiers(int fd)288 static bool has_modifiers(int fd)
289 {
290 uint64_t value;
291 if (drmGetCap(fd, DRM_CAP_ADDFB2_MODIFIERS, &value))
292 return false;
293 return value ? true : false;
294 }
295
fix_vram_size(uint64_t size)296 static uint64_t fix_vram_size(uint64_t size)
297 {
298 /* The VRAM size is underreported, so we need to fix it, because
299 * it's used to compute the number of memory modules for harvesting.
300 */
301 return align64(size, 256 * 1024 * 1024);
302 }
303
304 static bool
has_tmz_support(amdgpu_device_handle dev,struct radeon_info * info,struct amdgpu_gpu_info * amdinfo)305 has_tmz_support(amdgpu_device_handle dev,
306 struct radeon_info *info,
307 struct amdgpu_gpu_info *amdinfo)
308 {
309 struct amdgpu_bo_alloc_request request = {0};
310 int r;
311 amdgpu_bo_handle bo;
312
313 if (amdinfo->ids_flags & AMDGPU_IDS_FLAGS_TMZ)
314 return true;
315
316 /* AMDGPU_IDS_FLAGS_TMZ is supported starting from drm_minor 40 */
317 if (info->drm_minor >= 40)
318 return false;
319
320 /* Find out ourselves if TMZ is enabled */
321 if (info->chip_class < GFX9)
322 return false;
323
324 if (info->drm_minor < 36)
325 return false;
326
327 request.alloc_size = 256;
328 request.phys_alignment = 1024;
329 request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
330 request.flags = AMDGPU_GEM_CREATE_ENCRYPTED;
331 r = amdgpu_bo_alloc(dev, &request, &bo);
332 if (r)
333 return false;
334 amdgpu_bo_free(bo);
335 return true;
336 }
337
set_custom_cu_en_mask(struct radeon_info * info)338 static void set_custom_cu_en_mask(struct radeon_info *info)
339 {
340 info->spi_cu_en = ~0;
341
342 const char *cu_env_var = os_get_option("AMD_CU_MASK");
343 if (!cu_env_var)
344 return;
345
346 int size = strlen(cu_env_var);
347 char *str = alloca(size + 1);
348 memset(str, 0, size + 1);
349
350 size = 0;
351
352 /* Strip whitespace. */
353 for (unsigned src = 0; cu_env_var[src]; src++) {
354 if (cu_env_var[src] != ' ' && cu_env_var[src] != '\t' &&
355 cu_env_var[src] != '\n' && cu_env_var[src] != '\r') {
356 str[size++] = cu_env_var[src];
357 }
358 }
359
360 /* The following syntax is used, all whitespace is ignored:
361 * ID = [0-9][0-9]* ex. base 10 numbers
362 * ID_list = (ID | ID-ID)[, (ID | ID-ID)]* ex. 0,2-4,7
363 * CU_list = 0x[0-F]* | ID_list ex. 0x337F OR 0,2-4,7
364 * AMD_CU_MASK = CU_list
365 *
366 * It's a CU mask within a shader array. It's applied to all shader arrays.
367 */
368 bool is_good_form = true;
369 uint32_t spi_cu_en = 0;
370
371 if (size > 2 && str[0] == '0' && (str[1] == 'x' || str[1] == 'X')) {
372 str += 2;
373 size -= 2;
374
375 for (unsigned i = 0; i < size; i++)
376 is_good_form &= isxdigit(str[i]) != 0;
377
378 if (!is_good_form) {
379 fprintf(stderr, "amd: invalid AMD_CU_MASK: ill-formed hex value\n");
380 } else {
381 spi_cu_en = strtol(str, NULL, 16);
382 }
383 } else {
384 /* Parse ID_list. */
385 long first = 0, last = -1;
386
387 if (!isdigit(*str)) {
388 is_good_form = false;
389 } else {
390 while (*str) {
391 bool comma = false;
392
393 if (isdigit(*str)) {
394 first = last = strtol(str, &str, 10);
395 } else if (*str == '-') {
396 str++;
397 /* Parse a digit after a dash. */
398 if (isdigit(*str)) {
399 last = strtol(str, &str, 10);
400 } else {
401 fprintf(stderr, "amd: invalid AMD_CU_MASK: expected a digit after -\n");
402 is_good_form = false;
403 break;
404 }
405 } else if (*str == ',') {
406 comma = true;
407 str++;
408 if (!isdigit(*str)) {
409 fprintf(stderr, "amd: invalid AMD_CU_MASK: expected a digit after ,\n");
410 is_good_form = false;
411 break;
412 }
413 }
414
415 if (comma || !*str) {
416 if (first > last) {
417 fprintf(stderr, "amd: invalid AMD_CU_MASK: range not increasing (%li, %li)\n", first, last);
418 is_good_form = false;
419 break;
420 }
421 if (last > 31) {
422 fprintf(stderr, "amd: invalid AMD_CU_MASK: index too large (%li)\n", last);
423 is_good_form = false;
424 break;
425 }
426
427 spi_cu_en |= BITFIELD_RANGE(first, last - first + 1);
428 last = -1;
429 }
430 }
431 }
432 }
433
434 /* The mask is parsed. Now assign bits to CUs. */
435 if (is_good_form) {
436 bool error = false;
437
438 /* Clear bits that have no effect. */
439 spi_cu_en &= BITFIELD_MASK(info->max_good_cu_per_sa);
440
441 if (!spi_cu_en) {
442 fprintf(stderr, "amd: invalid AMD_CU_MASK: at least 1 CU in each SA must be enabled\n");
443 error = true;
444 }
445
446 if (info->has_graphics) {
447 uint32_t min_full_cu_mask = BITFIELD_MASK(info->min_good_cu_per_sa);
448
449 /* The hw ignores all non-compute CU masks if any of them is 0. Disallow that. */
450 if ((spi_cu_en & min_full_cu_mask) == 0) {
451 fprintf(stderr, "amd: invalid AMD_CU_MASK: at least 1 CU from 0x%x per SA must be "
452 "enabled (SPI limitation)\n", min_full_cu_mask);
453 error = true;
454 }
455
456 /* We usually disable 1 or 2 CUs for VS and GS, which means at last 1 other CU
457 * must be enabled.
458 */
459 uint32_t cu_mask_ge, unused;
460 ac_compute_late_alloc(info, false, false, false, &unused, &cu_mask_ge);
461 cu_mask_ge &= min_full_cu_mask;
462
463 if ((spi_cu_en & cu_mask_ge) == 0) {
464 fprintf(stderr, "amd: invalid AMD_CU_MASK: at least 1 CU from 0x%x per SA must be "
465 "enabled (late alloc constraint for GE)\n", cu_mask_ge);
466 error = true;
467 }
468
469 if ((min_full_cu_mask & spi_cu_en & ~cu_mask_ge) == 0) {
470 fprintf(stderr, "amd: invalid AMD_CU_MASK: at least 1 CU from 0x%x per SA must be "
471 "enabled (late alloc constraint for PS)\n",
472 min_full_cu_mask & ~cu_mask_ge);
473 error = true;
474 }
475 }
476
477 if (!error) {
478 info->spi_cu_en = spi_cu_en;
479 info->spi_cu_en_has_effect = spi_cu_en & BITFIELD_MASK(info->max_good_cu_per_sa);
480 }
481 }
482 }
483
ac_query_gpu_info(int fd,void * dev_p,struct radeon_info * info,struct amdgpu_gpu_info * amdinfo)484 bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
485 struct amdgpu_gpu_info *amdinfo)
486 {
487 struct drm_amdgpu_info_device device_info = {0};
488 struct amdgpu_buffer_size_alignments alignment_info = {0};
489 struct drm_amdgpu_info_hw_ip dma = {0}, compute = {0}, uvd = {0};
490 struct drm_amdgpu_info_hw_ip uvd_enc = {0}, vce = {0}, vcn_dec = {0}, vcn_jpeg = {0};
491 struct drm_amdgpu_info_hw_ip vcn_enc = {0}, gfx = {0};
492 struct amdgpu_gds_resource_info gds = {0};
493 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
494 int r, i, j;
495 amdgpu_device_handle dev = dev_p;
496 drmDevicePtr devinfo;
497
498 /* Get PCI info. */
499 r = drmGetDevice2(fd, 0, &devinfo);
500 if (r) {
501 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
502 return false;
503 }
504 info->pci_domain = devinfo->businfo.pci->domain;
505 info->pci_bus = devinfo->businfo.pci->bus;
506 info->pci_dev = devinfo->businfo.pci->dev;
507 info->pci_func = devinfo->businfo.pci->func;
508 drmFreeDevice(&devinfo);
509
510 assert(info->drm_major == 3);
511 info->is_amdgpu = true;
512
513 /* Query hardware and driver information. */
514 r = amdgpu_query_gpu_info(dev, amdinfo);
515 if (r) {
516 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
517 return false;
518 }
519
520 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info), &device_info);
521 if (r) {
522 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
523 return false;
524 }
525
526 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
527 if (r) {
528 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
529 return false;
530 }
531
532 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
533 if (r) {
534 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
535 return false;
536 }
537
538 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
539 if (r) {
540 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
541 return false;
542 }
543
544 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
545 if (r) {
546 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
547 return false;
548 }
549
550 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
551 if (r) {
552 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
553 return false;
554 }
555
556 if (info->drm_minor >= 17) {
557 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
558 if (r) {
559 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
560 return false;
561 }
562 }
563
564 if (info->drm_minor >= 17) {
565 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
566 if (r) {
567 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
568 return false;
569 }
570 }
571
572 if (info->drm_minor >= 17) {
573 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
574 if (r) {
575 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
576 return false;
577 }
578 }
579
580 if (info->drm_minor >= 27) {
581 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
582 if (r) {
583 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
584 return false;
585 }
586 }
587
588 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, &info->me_fw_version,
589 &info->me_fw_feature);
590 if (r) {
591 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
592 return false;
593 }
594
595 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_MEC, 0, 0, &info->mec_fw_version,
596 &info->mec_fw_feature);
597 if (r) {
598 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(mec) failed.\n");
599 return false;
600 }
601
602 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0, &info->pfp_fw_version,
603 &info->pfp_fw_feature);
604 if (r) {
605 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
606 return false;
607 }
608
609 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0, &info->ce_fw_version,
610 &info->ce_fw_feature);
611 if (r) {
612 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
613 return false;
614 }
615
616 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0, &uvd_version, &uvd_feature);
617 if (r) {
618 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
619 return false;
620 }
621
622 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
623 if (r) {
624 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
625 return false;
626 }
627
628 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0, &vce_version, &vce_feature);
629 if (r) {
630 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
631 return false;
632 }
633
634 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
635 if (r) {
636 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
637 return false;
638 }
639
640 r = amdgpu_query_gds_info(dev, &gds);
641 if (r) {
642 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
643 return false;
644 }
645
646 if (info->drm_minor >= 9) {
647 struct drm_amdgpu_memory_info meminfo = {0};
648
649 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
650 if (r) {
651 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
652 return false;
653 }
654
655 /* Note: usable_heap_size values can be random and can't be relied on. */
656 info->gart_size = meminfo.gtt.total_heap_size;
657 info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
658 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
659 } else {
660 /* This is a deprecated interface, which reports usable sizes
661 * (total minus pinned), but the pinned size computation is
662 * buggy, so the values returned from these functions can be
663 * random.
664 */
665 struct amdgpu_heap_info vram, vram_vis, gtt;
666
667 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
668 if (r) {
669 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
670 return false;
671 }
672
673 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
674 &vram_vis);
675 if (r) {
676 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
677 return false;
678 }
679
680 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
681 if (r) {
682 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
683 return false;
684 }
685
686 info->gart_size = gtt.heap_size;
687 info->vram_size = fix_vram_size(vram.heap_size);
688 info->vram_vis_size = vram_vis.heap_size;
689 }
690
691 info->gart_size_kb = DIV_ROUND_UP(info->gart_size, 1024);
692 info->vram_size_kb = DIV_ROUND_UP(info->vram_size, 1024);
693
694 if (info->drm_minor >= 41) {
695 amdgpu_query_video_caps_info(dev, AMDGPU_INFO_VIDEO_CAPS_DECODE,
696 sizeof(info->dec_caps), &(info->dec_caps));
697 amdgpu_query_video_caps_info(dev, AMDGPU_INFO_VIDEO_CAPS_ENCODE,
698 sizeof(info->enc_caps), &(info->enc_caps));
699 }
700
701 /* Add some margin of error, though this shouldn't be needed in theory. */
702 info->all_vram_visible = info->vram_size * 0.9 < info->vram_vis_size;
703
704 util_cpu_detect();
705
706 /* Set chip identification. */
707 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
708 info->pci_rev_id = amdinfo->pci_rev_id;
709 info->vce_harvest_config = amdinfo->vce_harvest_config;
710
711 #define identify_chip2(asic, chipname) \
712 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
713 info->family = CHIP_##chipname; \
714 info->name = #chipname; \
715 }
716 #define identify_chip(chipname) identify_chip2(chipname, chipname)
717
718 switch (amdinfo->family_id) {
719 case FAMILY_SI:
720 identify_chip(TAHITI);
721 identify_chip(PITCAIRN);
722 identify_chip2(CAPEVERDE, VERDE);
723 identify_chip(OLAND);
724 identify_chip(HAINAN);
725 break;
726 case FAMILY_CI:
727 identify_chip(BONAIRE);
728 identify_chip(HAWAII);
729 break;
730 case FAMILY_KV:
731 identify_chip2(SPECTRE, KAVERI);
732 identify_chip2(SPOOKY, KAVERI);
733 identify_chip2(KALINDI, KABINI);
734 identify_chip2(GODAVARI, KABINI);
735 break;
736 case FAMILY_VI:
737 identify_chip(ICELAND);
738 identify_chip(TONGA);
739 identify_chip(FIJI);
740 identify_chip(POLARIS10);
741 identify_chip(POLARIS11);
742 identify_chip(POLARIS12);
743 identify_chip(VEGAM);
744 break;
745 case FAMILY_CZ:
746 identify_chip(CARRIZO);
747 identify_chip(STONEY);
748 break;
749 case FAMILY_AI:
750 identify_chip(VEGA10);
751 identify_chip(VEGA12);
752 identify_chip(VEGA20);
753 identify_chip(ARCTURUS);
754 identify_chip(ALDEBARAN);
755 break;
756 case FAMILY_RV:
757 identify_chip(RAVEN);
758 identify_chip(RAVEN2);
759 identify_chip(RENOIR);
760 break;
761 case FAMILY_NV:
762 identify_chip(NAVI10);
763 identify_chip(NAVI12);
764 identify_chip(NAVI14);
765 identify_chip(SIENNA_CICHLID);
766 identify_chip(NAVY_FLOUNDER);
767 identify_chip(DIMGREY_CAVEFISH);
768 identify_chip(BEIGE_GOBY);
769 break;
770 case FAMILY_VGH:
771 identify_chip(VANGOGH);
772 break;
773 case FAMILY_YC:
774 identify_chip(YELLOW_CARP);
775 break;
776 case FAMILY_GC_10_3_6:
777 identify_chip(GFX1036);
778 break;
779 case FAMILY_GC_10_3_7:
780 identify_chip2(GFX1037, GFX1036);
781 break;
782 }
783
784 if (!info->name) {
785 fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
786 amdinfo->family_id, amdinfo->chip_external_rev);
787 return false;
788 }
789
790 memset(info->lowercase_name, 0, sizeof(info->lowercase_name));
791 for (unsigned i = 0; info->name[i] && i < ARRAY_SIZE(info->lowercase_name) - 1; i++)
792 info->lowercase_name[i] = tolower(info->name[i]);
793
794 if (info->family >= CHIP_SIENNA_CICHLID)
795 info->chip_class = GFX10_3;
796 else if (info->family >= CHIP_NAVI10)
797 info->chip_class = GFX10;
798 else if (info->family >= CHIP_VEGA10)
799 info->chip_class = GFX9;
800 else if (info->family >= CHIP_TONGA)
801 info->chip_class = GFX8;
802 else if (info->family >= CHIP_BONAIRE)
803 info->chip_class = GFX7;
804 else if (info->family >= CHIP_TAHITI)
805 info->chip_class = GFX6;
806 else {
807 fprintf(stderr, "amdgpu: Unknown family.\n");
808 return false;
809 }
810
811 info->smart_access_memory = info->all_vram_visible &&
812 info->chip_class >= GFX10_3 &&
813 util_get_cpu_caps()->family >= CPU_AMD_ZEN3 &&
814 util_get_cpu_caps()->family < CPU_AMD_LAST;
815
816 info->family_id = amdinfo->family_id;
817 info->chip_external_rev = amdinfo->chip_external_rev;
818 info->marketing_name = amdgpu_get_marketing_name(dev);
819 info->is_pro_graphics = info->marketing_name && (strstr(info->marketing_name, "Pro") ||
820 strstr(info->marketing_name, "PRO") ||
821 strstr(info->marketing_name, "Frontier"));
822
823 /* Set which chips have dedicated VRAM. */
824 info->has_dedicated_vram = !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
825
826 /* The kernel can split large buffers in VRAM but not in GTT, so large
827 * allocations can fail or cause buffer movement failures in the kernel.
828 */
829 if (info->has_dedicated_vram)
830 info->max_alloc_size = info->vram_size * 0.8;
831 else
832 info->max_alloc_size = info->gart_size * 0.7;
833
834 info->vram_type = amdinfo->vram_type;
835 info->vram_bit_width = amdinfo->vram_bit_width;
836 info->ce_ram_size = amdinfo->ce_ram_size;
837
838 /* Set which chips have uncached device memory. */
839 info->has_l2_uncached = info->chip_class >= GFX9;
840
841 /* Set hardware information. */
842 info->gds_size = gds.gds_total_size;
843 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
844 /* convert the shader/memory clocks from KHz to MHz */
845 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
846 info->max_memory_clock = amdinfo->max_memory_clk / 1000;
847 info->max_tcc_blocks = device_info.num_tcc_blocks;
848 info->max_se = amdinfo->num_shader_engines;
849 info->max_sa_per_se = amdinfo->num_shader_arrays_per_engine;
850 info->uvd_fw_version = uvd.available_rings ? uvd_version : 0;
851 info->vce_fw_version = vce.available_rings ? vce_version : 0;
852 info->has_video_hw.uvd_decode = uvd.available_rings != 0;
853 info->has_video_hw.vcn_decode = vcn_dec.available_rings != 0;
854 info->has_video_hw.jpeg_decode = vcn_jpeg.available_rings != 0;
855 info->has_video_hw.vce_encode = vce.available_rings != 0;
856 info->has_video_hw.uvd_encode = uvd_enc.available_rings != 0;
857 info->has_video_hw.vcn_encode = vcn_enc.available_rings != 0;
858 info->has_userptr = true;
859 info->has_syncobj = has_syncobj(fd);
860 info->has_timeline_syncobj = has_timeline_syncobj(fd);
861 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
862 info->has_local_buffers = info->drm_minor >= 20;
863 info->kernel_flushes_hdp_before_ib = true;
864 info->htile_cmask_support_1d_tiling = true;
865 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
866 info->has_bo_metadata = true;
867 info->has_gpu_reset_status_query = true;
868 info->has_eqaa_surface_allocator = true;
869 info->has_format_bc1_through_bc7 = true;
870 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
871 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 || info->drm_minor >= 2;
872 info->has_indirect_compute_dispatch = true;
873 /* GFX6 doesn't support unaligned loads. */
874 info->has_unaligned_shader_loads = info->chip_class != GFX6;
875 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
876 * these faults are mitigated in software.
877 */
878 info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13;
879 info->has_2d_tiling = true;
880 info->has_read_registers_query = true;
881 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
882 info->mid_command_buffer_preemption_enabled = amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
883 info->has_tmz_support = has_tmz_support(dev, info, amdinfo);
884 info->kernel_has_modifiers = has_modifiers(fd);
885 info->has_graphics = gfx.available_rings > 0;
886
887 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
888 info->max_render_backends = amdinfo->rb_pipes;
889 /* The value returned by the kernel driver was wrong. */
890 if (info->family == CHIP_KAVERI)
891 info->max_render_backends = 2;
892
893 /* Guess the number of enabled SEs because the kernel doesn't tell us. */
894 if (info->chip_class >= GFX10_3 && info->max_se > 1) {
895 unsigned num_rbs_per_se = info->max_render_backends / info->max_se;
896 info->num_se = util_bitcount(amdinfo->enabled_rb_pipes_mask) / num_rbs_per_se;
897 } else {
898 info->num_se = info->max_se;
899 }
900
901 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
902 if (!info->clock_crystal_freq) {
903 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
904 info->clock_crystal_freq = 1;
905 }
906 if (info->chip_class >= GFX10) {
907 info->tcc_cache_line_size = 128;
908
909 if (info->drm_minor >= 35) {
910 info->num_tcc_blocks = info->max_tcc_blocks - util_bitcount64(device_info.tcc_disabled_mask);
911 } else {
912 /* This is a hack, but it's all we can do without a kernel upgrade. */
913 info->num_tcc_blocks = info->vram_size / (512 * 1024 * 1024);
914 if (info->num_tcc_blocks > info->max_tcc_blocks)
915 info->num_tcc_blocks /= 2;
916 }
917 } else {
918 if (!info->has_graphics && info->family >= CHIP_ALDEBARAN)
919 info->tcc_cache_line_size = 128;
920 else
921 info->tcc_cache_line_size = 64;
922
923 info->num_tcc_blocks = info->max_tcc_blocks;
924 }
925
926 info->tcc_rb_non_coherent = !util_is_power_of_two_or_zero(info->num_tcc_blocks);
927
928 switch (info->family) {
929 case CHIP_TAHITI:
930 case CHIP_PITCAIRN:
931 case CHIP_OLAND:
932 case CHIP_HAWAII:
933 case CHIP_KABINI:
934 case CHIP_TONGA:
935 case CHIP_STONEY:
936 case CHIP_RAVEN2:
937 info->l2_cache_size = info->num_tcc_blocks * 64 * 1024;
938 break;
939 case CHIP_VERDE:
940 case CHIP_HAINAN:
941 case CHIP_BONAIRE:
942 case CHIP_KAVERI:
943 case CHIP_ICELAND:
944 case CHIP_CARRIZO:
945 case CHIP_FIJI:
946 case CHIP_POLARIS12:
947 case CHIP_VEGAM:
948 info->l2_cache_size = info->num_tcc_blocks * 128 * 1024;
949 break;
950 default:
951 info->l2_cache_size = info->num_tcc_blocks * 256 * 1024;
952 break;
953 case CHIP_YELLOW_CARP:
954 info->l2_cache_size = info->num_tcc_blocks * 512 * 1024;
955 break;
956 }
957
958 info->l1_cache_size = 16384;
959
960 info->mc_arb_ramcfg = amdinfo->mc_arb_ramcfg;
961 info->gb_addr_config = amdinfo->gb_addr_cfg;
962 if (info->chip_class >= GFX9) {
963 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
964 info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
965 } else {
966 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
967 info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
968 }
969 info->r600_has_virtual_memory = true;
970
971 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
972 * 16KB makes some SIMDs unoccupied).
973 *
974 * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used.
975 */
976 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
977 /* lds_encode_granularity is the block size used for encoding registers.
978 * lds_alloc_granularity is what the hardware will align the LDS size to.
979 */
980 info->lds_encode_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4;
981 info->lds_alloc_granularity = info->chip_class >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity;
982
983 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
984 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
985
986 info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
987 info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
988 info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
989 info->num_rings[RING_UVD] = util_bitcount(uvd.available_rings);
990 info->num_rings[RING_VCE] = util_bitcount(vce.available_rings);
991 info->num_rings[RING_UVD_ENC] = util_bitcount(uvd_enc.available_rings);
992 info->num_rings[RING_VCN_DEC] = util_bitcount(vcn_dec.available_rings);
993 info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
994 info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
995
996 /* This is "align_mask" copied from the kernel, maximums of all IP versions. */
997 info->ib_pad_dw_mask[RING_GFX] = 0xff;
998 info->ib_pad_dw_mask[RING_COMPUTE] = 0xff;
999 info->ib_pad_dw_mask[RING_DMA] = 0xf;
1000 info->ib_pad_dw_mask[RING_UVD] = 0xf;
1001 info->ib_pad_dw_mask[RING_VCE] = 0x3f;
1002 info->ib_pad_dw_mask[RING_UVD_ENC] = 0x3f;
1003 info->ib_pad_dw_mask[RING_VCN_DEC] = 0xf;
1004 info->ib_pad_dw_mask[RING_VCN_ENC] = 0x3f;
1005 info->ib_pad_dw_mask[RING_VCN_JPEG] = 0xf;
1006
1007 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
1008 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1009 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
1010 */
1011 info->has_clear_state = info->chip_class >= GFX7;
1012
1013 info->has_distributed_tess =
1014 info->chip_class >= GFX10 || (info->chip_class >= GFX8 && info->max_se >= 2);
1015
1016 info->has_dcc_constant_encode =
1017 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10;
1018
1019 info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9;
1020
1021 /* Some chips have RB+ registers, but don't support RB+. Those must
1022 * always disable it.
1023 */
1024 info->rbplus_allowed =
1025 info->has_rbplus &&
1026 (info->family == CHIP_STONEY || info->family == CHIP_VEGA12 || info->family == CHIP_RAVEN ||
1027 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10_3);
1028
1029 info->has_out_of_order_rast =
1030 info->chip_class >= GFX8 && info->chip_class <= GFX9 && info->max_se >= 2;
1031
1032 /* Whether chips support double rate packed math instructions. */
1033 info->has_packed_math_16bit = info->chip_class >= GFX9;
1034
1035 /* Whether chips support dot product instructions. A subset of these support a smaller
1036 * instruction encoding which accumulates with the destination.
1037 */
1038 info->has_accelerated_dot_product =
1039 info->family == CHIP_ARCTURUS || info->family == CHIP_ALDEBARAN ||
1040 info->family == CHIP_VEGA20 || info->family >= CHIP_NAVI12;
1041
1042 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
1043 info->has_load_ctx_reg_pkt =
1044 info->chip_class >= GFX9 || (info->chip_class >= GFX8 && info->me_fw_feature >= 41);
1045
1046 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
1047
1048 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
1049
1050 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 && info->chip_class <= GFX9;
1051
1052 info->has_msaa_sample_loc_bug =
1053 (info->family >= CHIP_POLARIS10 && info->family <= CHIP_POLARIS12) ||
1054 info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
1055
1056 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
1057
1058 /* Drawing from 0-sized index buffers causes hangs on gfx10. */
1059 info->has_zero_index_buffer_bug = info->chip_class == GFX10;
1060
1061 /* Whether chips are affected by the image load/sample/gather hw bug when
1062 * DCC is enabled (ie. WRITE_COMPRESS_ENABLE should be 0).
1063 */
1064 info->has_image_load_dcc_bug = info->family == CHIP_DIMGREY_CAVEFISH ||
1065 info->family == CHIP_VANGOGH ||
1066 info->family == CHIP_YELLOW_CARP;
1067
1068 /* DB has a bug when ITERATE_256 is set to 1 that can cause a hang. The
1069 * workaround is to set DECOMPRESS_ON_Z_PLANES to 2 for 4X MSAA D/S images.
1070 */
1071 info->has_two_planes_iterate256_bug = info->chip_class == GFX10;
1072
1073 /* GFX10+Sienna: NGG->legacy transitions require VGT_FLUSH. */
1074 info->has_vgt_flush_ngg_legacy_bug = info->chip_class == GFX10 ||
1075 info->family == CHIP_SIENNA_CICHLID;
1076
1077 /* HW bug workaround when CS threadgroups > 256 threads and async compute
1078 * isn't used, i.e. only one compute job can run at a time. If async
1079 * compute is possible, the threadgroup size must be limited to 256 threads
1080 * on all queues to avoid the bug.
1081 * Only GFX6 and certain GFX7 chips are affected.
1082 *
1083 * FIXME: RADV doesn't limit the number of threads for async compute.
1084 */
1085 info->has_cs_regalloc_hang_bug = info->chip_class == GFX6 ||
1086 info->family == CHIP_BONAIRE ||
1087 info->family == CHIP_KABINI;
1088
1089 /* Support for GFX10.3 was added with F32_ME_FEATURE_VERSION_31 but the
1090 * feature version wasn't bumped.
1091 */
1092 info->has_32bit_predication = (info->chip_class >= GFX10 &&
1093 info->me_fw_feature >= 32) ||
1094 (info->chip_class == GFX9 &&
1095 info->me_fw_feature >= 52);
1096
1097 /* Get the number of good compute units. */
1098 info->num_good_compute_units = 0;
1099 for (i = 0; i < info->max_se; i++) {
1100 for (j = 0; j < info->max_sa_per_se; j++) {
1101 if (info->family == CHIP_ARCTURUS) {
1102 /* The CU bitmap in amd gpu info structure is
1103 * 4x4 size array, and it's usually suitable for Vega
1104 * ASICs which has 4*2 SE/SA layout.
1105 * But for Arcturus, SE/SA layout is changed to 8*1.
1106 * To mostly reduce the impact, we make it compatible
1107 * with current bitmap array as below:
1108 * SE4 --> cu_bitmap[0][1]
1109 * SE5 --> cu_bitmap[1][1]
1110 * SE6 --> cu_bitmap[2][1]
1111 * SE7 --> cu_bitmap[3][1]
1112 */
1113 assert(info->max_sa_per_se == 1);
1114 info->cu_mask[i][0] = amdinfo->cu_bitmap[i % 4][i / 4];
1115 } else {
1116 info->cu_mask[i][j] = amdinfo->cu_bitmap[i][j];
1117 }
1118 info->num_good_compute_units += util_bitcount(info->cu_mask[i][j]);
1119 }
1120 }
1121
1122 /* On GFX10, only whole WGPs (in units of 2 CUs) can be disabled,
1123 * and max - min <= 2.
1124 */
1125 unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1;
1126 info->max_good_cu_per_sa =
1127 DIV_ROUND_UP(info->num_good_compute_units, (info->num_se * info->max_sa_per_se * cu_group)) *
1128 cu_group;
1129 info->min_good_cu_per_sa =
1130 (info->num_good_compute_units / (info->num_se * info->max_sa_per_se * cu_group)) * cu_group;
1131
1132 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode, sizeof(amdinfo->gb_tile_mode));
1133 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
1134
1135 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
1136 sizeof(amdinfo->gb_macro_tile_mode));
1137
1138 info->pte_fragment_size = alignment_info.size_local;
1139 info->gart_page_size = alignment_info.size_remote;
1140
1141 if (info->chip_class == GFX6)
1142 info->gfx_ib_pad_with_type2 = true;
1143
1144 unsigned ib_align = 0;
1145 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
1146 ib_align = MAX2(ib_align, gfx.ib_size_alignment);
1147 ib_align = MAX2(ib_align, compute.ib_start_alignment);
1148 ib_align = MAX2(ib_align, compute.ib_size_alignment);
1149 ib_align = MAX2(ib_align, dma.ib_start_alignment);
1150 ib_align = MAX2(ib_align, dma.ib_size_alignment);
1151 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
1152 ib_align = MAX2(ib_align, uvd.ib_size_alignment);
1153 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
1154 ib_align = MAX2(ib_align, uvd_enc.ib_size_alignment);
1155 ib_align = MAX2(ib_align, vce.ib_start_alignment);
1156 ib_align = MAX2(ib_align, vce.ib_size_alignment);
1157 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
1158 ib_align = MAX2(ib_align, vcn_dec.ib_size_alignment);
1159 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
1160 ib_align = MAX2(ib_align, vcn_enc.ib_size_alignment);
1161 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
1162 ib_align = MAX2(ib_align, vcn_jpeg.ib_size_alignment);
1163 /* GFX10 and maybe GFX9 need this alignment for cache coherency. */
1164 if (info->chip_class >= GFX9)
1165 ib_align = MAX2(ib_align, info->tcc_cache_line_size);
1166 /* The kernel pads gfx and compute IBs to 256 dwords since:
1167 * 66f3b2d527154bd258a57c8815004b5964aa1cf5
1168 * Do the same.
1169 */
1170 ib_align = MAX2(ib_align, 1024);
1171 info->ib_alignment = ib_align;
1172
1173 if ((info->drm_minor >= 31 && (info->family == CHIP_RAVEN || info->family == CHIP_RAVEN2 ||
1174 info->family == CHIP_RENOIR)) ||
1175 (info->drm_minor >= 34 && (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14)) ||
1176 info->chip_class >= GFX10_3) {
1177 if (info->max_render_backends == 1)
1178 info->use_display_dcc_unaligned = true;
1179 else
1180 info->use_display_dcc_with_retile_blit = true;
1181 }
1182
1183 info->has_gds_ordered_append = info->chip_class >= GFX7 && info->drm_minor >= 29;
1184
1185 info->has_stable_pstate = info->drm_minor >= 45;
1186
1187 if (info->chip_class >= GFX9 && info->has_graphics) {
1188 unsigned pc_lines = 0;
1189
1190 switch (info->family) {
1191 case CHIP_VEGA10:
1192 case CHIP_VEGA12:
1193 case CHIP_VEGA20:
1194 pc_lines = 2048;
1195 break;
1196 case CHIP_RAVEN:
1197 case CHIP_RAVEN2:
1198 case CHIP_RENOIR:
1199 case CHIP_NAVI10:
1200 case CHIP_NAVI12:
1201 case CHIP_SIENNA_CICHLID:
1202 case CHIP_NAVY_FLOUNDER:
1203 case CHIP_DIMGREY_CAVEFISH:
1204 pc_lines = 1024;
1205 break;
1206 case CHIP_NAVI14:
1207 case CHIP_BEIGE_GOBY:
1208 pc_lines = 512;
1209 break;
1210 case CHIP_VANGOGH:
1211 case CHIP_YELLOW_CARP:
1212 case CHIP_GFX1036:
1213 pc_lines = 256;
1214 break;
1215 default:
1216 assert(0);
1217 }
1218
1219 info->pc_lines = pc_lines;
1220
1221 if (info->chip_class >= GFX10) {
1222 info->pbb_max_alloc_count = pc_lines / 3;
1223 } else {
1224 info->pbb_max_alloc_count = MIN2(128, pc_lines / (4 * info->max_se));
1225 }
1226 }
1227
1228 if (info->chip_class >= GFX10_3)
1229 info->max_wave64_per_simd = 16;
1230 else if (info->chip_class == GFX10)
1231 info->max_wave64_per_simd = 20;
1232 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
1233 info->max_wave64_per_simd = 8;
1234 else
1235 info->max_wave64_per_simd = 10;
1236
1237 if (info->chip_class >= GFX10) {
1238 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd;
1239 info->min_sgpr_alloc = 128;
1240 info->sgpr_alloc_granularity = 128;
1241 } else if (info->chip_class >= GFX8) {
1242 info->num_physical_sgprs_per_simd = 800;
1243 info->min_sgpr_alloc = 16;
1244 info->sgpr_alloc_granularity = 16;
1245 } else {
1246 info->num_physical_sgprs_per_simd = 512;
1247 info->min_sgpr_alloc = 8;
1248 info->sgpr_alloc_granularity = 8;
1249 }
1250
1251 info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_ARCTURUS;
1252 info->never_stop_sq_perf_counters = info->chip_class == GFX10 ||
1253 info->chip_class == GFX10_3;
1254 info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104;
1255
1256 if (!info->has_graphics && info->family >= CHIP_ALDEBARAN) {
1257 info->min_wave64_vgpr_alloc = 8;
1258 info->max_vgpr_alloc = 512;
1259 info->wave64_vgpr_alloc_granularity = 8;
1260 } else {
1261 info->min_wave64_vgpr_alloc = 4;
1262 info->max_vgpr_alloc = 256;
1263 info->wave64_vgpr_alloc_granularity = 4;
1264 }
1265
1266 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
1267 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
1268
1269 set_custom_cu_en_mask(info);
1270
1271 const char *ib_filename = debug_get_option("AMD_PARSE_IB", NULL);
1272 if (ib_filename) {
1273 FILE *f = fopen(ib_filename, "r");
1274 if (f) {
1275 fseek(f, 0, SEEK_END);
1276 size_t size = ftell(f);
1277 uint32_t *ib = (uint32_t *)malloc(size);
1278 fseek(f, 0, SEEK_SET);
1279 size_t n_read = fread(ib, 1, size, f);
1280 fclose(f);
1281
1282 if (n_read != size) {
1283 fprintf(stderr, "failed to read %zu bytes from '%s'\n", size, ib_filename);
1284 exit(1);
1285 }
1286
1287 ac_parse_ib(stdout, ib, size / 4, NULL, 0, "IB", info->chip_class, NULL, NULL);
1288 free(ib);
1289 exit(0);
1290 }
1291 }
1292 return true;
1293 }
1294
ac_compute_driver_uuid(char * uuid,size_t size)1295 void ac_compute_driver_uuid(char *uuid, size_t size)
1296 {
1297 char amd_uuid[] = "AMD-MESA-DRV";
1298
1299 assert(size >= sizeof(amd_uuid));
1300
1301 memset(uuid, 0, size);
1302 strncpy(uuid, amd_uuid, size);
1303 }
1304
ac_compute_device_uuid(struct radeon_info * info,char * uuid,size_t size)1305 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
1306 {
1307 uint32_t *uint_uuid = (uint32_t *)uuid;
1308
1309 assert(size >= sizeof(uint32_t) * 4);
1310
1311 /**
1312 * Use the device info directly instead of using a sha1. GL/VK UUIDs
1313 * are 16 byte vs 20 byte for sha1, and the truncation that would be
1314 * required would get rid of part of the little entropy we have.
1315 * */
1316 memset(uuid, 0, size);
1317 uint_uuid[0] = info->pci_domain;
1318 uint_uuid[1] = info->pci_bus;
1319 uint_uuid[2] = info->pci_dev;
1320 uint_uuid[3] = info->pci_func;
1321 }
1322
ac_print_gpu_info(struct radeon_info * info,FILE * f)1323 void ac_print_gpu_info(struct radeon_info *info, FILE *f)
1324 {
1325 fprintf(f, "Device info:\n");
1326 fprintf(f, " pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n", info->pci_domain, info->pci_bus,
1327 info->pci_dev, info->pci_func);
1328
1329 fprintf(f, " name = %s\n", info->name);
1330 fprintf(f, " lowercase_name = %s\n", info->lowercase_name);
1331 fprintf(f, " marketing_name = %s\n", info->marketing_name);
1332 fprintf(f, " is_pro_graphics = %u\n", info->is_pro_graphics);
1333 fprintf(f, " pci_id = 0x%x\n", info->pci_id);
1334 fprintf(f, " pci_rev_id = 0x%x\n", info->pci_rev_id);
1335 fprintf(f, " family = %i\n", info->family);
1336 fprintf(f, " chip_class = %i\n", info->chip_class);
1337 fprintf(f, " family_id = %i\n", info->family_id);
1338 fprintf(f, " chip_external_rev = %i\n", info->chip_external_rev);
1339 fprintf(f, " clock_crystal_freq = %i KHz\n", info->clock_crystal_freq);
1340
1341 fprintf(f, "Features:\n");
1342 fprintf(f, " has_graphics = %i\n", info->has_graphics);
1343 fprintf(f, " num_rings[RING_GFX] = %i\n", info->num_rings[RING_GFX]);
1344 fprintf(f, " num_rings[RING_DMA] = %i\n", info->num_rings[RING_DMA]);
1345 fprintf(f, " num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
1346 fprintf(f, " num_rings[RING_UVD] = %i\n", info->num_rings[RING_UVD]);
1347 fprintf(f, " num_rings[RING_VCE] = %i\n", info->num_rings[RING_VCE]);
1348 fprintf(f, " num_rings[RING_UVD_ENC] = %i\n", info->num_rings[RING_UVD_ENC]);
1349 fprintf(f, " num_rings[RING_VCN_DEC] = %i\n", info->num_rings[RING_VCN_DEC]);
1350 fprintf(f, " num_rings[RING_VCN_ENC] = %i\n", info->num_rings[RING_VCN_ENC]);
1351 fprintf(f, " num_rings[RING_VCN_JPEG] = %i\n", info->num_rings[RING_VCN_JPEG]);
1352 fprintf(f, " has_clear_state = %u\n", info->has_clear_state);
1353 fprintf(f, " has_distributed_tess = %u\n", info->has_distributed_tess);
1354 fprintf(f, " has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
1355 fprintf(f, " has_rbplus = %u\n", info->has_rbplus);
1356 fprintf(f, " rbplus_allowed = %u\n", info->rbplus_allowed);
1357 fprintf(f, " has_load_ctx_reg_pkt = %u\n", info->has_load_ctx_reg_pkt);
1358 fprintf(f, " has_out_of_order_rast = %u\n", info->has_out_of_order_rast);
1359 fprintf(f, " cpdma_prefetch_writes_memory = %u\n", info->cpdma_prefetch_writes_memory);
1360 fprintf(f, " has_gfx9_scissor_bug = %i\n", info->has_gfx9_scissor_bug);
1361 fprintf(f, " has_tc_compat_zrange_bug = %i\n", info->has_tc_compat_zrange_bug);
1362 fprintf(f, " has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug);
1363 fprintf(f, " has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
1364 fprintf(f, " has_32bit_predication = %i\n", info->has_32bit_predication);
1365 fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap);
1366 fprintf(f, " never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters);
1367
1368 fprintf(f, "Display features:\n");
1369 fprintf(f, " use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
1370 fprintf(f, " use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
1371
1372 fprintf(f, "Memory info:\n");
1373 fprintf(f, " pte_fragment_size = %u\n", info->pte_fragment_size);
1374 fprintf(f, " gart_page_size = %u\n", info->gart_page_size);
1375 fprintf(f, " gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024 * 1024));
1376 fprintf(f, " vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024 * 1024));
1377 fprintf(f, " vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024 * 1024));
1378 fprintf(f, " vram_type = %i\n", info->vram_type);
1379 fprintf(f, " vram_bit_width = %i\n", info->vram_bit_width);
1380 fprintf(f, " gds_size = %u kB\n", info->gds_size / 1024);
1381 fprintf(f, " gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
1382 fprintf(f, " max_alloc_size = %i MB\n", (int)DIV_ROUND_UP(info->max_alloc_size, 1024 * 1024));
1383 fprintf(f, " min_alloc_size = %u\n", info->min_alloc_size);
1384 fprintf(f, " address32_hi = 0x%x\n", info->address32_hi);
1385 fprintf(f, " has_dedicated_vram = %u\n", info->has_dedicated_vram);
1386 fprintf(f, " all_vram_visible = %u\n", info->all_vram_visible);
1387 fprintf(f, " smart_access_memory = %u\n", info->smart_access_memory);
1388 fprintf(f, " max_tcc_blocks = %i\n", info->max_tcc_blocks);
1389 fprintf(f, " num_tcc_blocks = %i\n", info->num_tcc_blocks);
1390 fprintf(f, " tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
1391 fprintf(f, " tcc_rb_non_coherent = %u\n", info->tcc_rb_non_coherent);
1392 fprintf(f, " pc_lines = %u\n", info->pc_lines);
1393 fprintf(f, " lds_size_per_workgroup = %u\n", info->lds_size_per_workgroup);
1394 fprintf(f, " lds_alloc_granularity = %i\n", info->lds_alloc_granularity);
1395 fprintf(f, " lds_encode_granularity = %i\n", info->lds_encode_granularity);
1396 fprintf(f, " max_memory_clock = %i MHz\n", info->max_memory_clock);
1397 fprintf(f, " ce_ram_size = %i\n", info->ce_ram_size);
1398 fprintf(f, " l1_cache_size = %i\n", info->l1_cache_size);
1399 fprintf(f, " l2_cache_size = %i\n", info->l2_cache_size);
1400
1401 fprintf(f, "CP info:\n");
1402 fprintf(f, " gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
1403 fprintf(f, " ib_alignment = %u\n", info->ib_alignment);
1404 fprintf(f, " me_fw_version = %i\n", info->me_fw_version);
1405 fprintf(f, " me_fw_feature = %i\n", info->me_fw_feature);
1406 fprintf(f, " mec_fw_version = %i\n", info->mec_fw_version);
1407 fprintf(f, " mec_fw_feature = %i\n", info->mec_fw_feature);
1408 fprintf(f, " pfp_fw_version = %i\n", info->pfp_fw_version);
1409 fprintf(f, " pfp_fw_feature = %i\n", info->pfp_fw_feature);
1410 fprintf(f, " ce_fw_version = %i\n", info->ce_fw_version);
1411 fprintf(f, " ce_fw_feature = %i\n", info->ce_fw_feature);
1412
1413 fprintf(f, "Multimedia info:\n");
1414 fprintf(f, " uvd_decode = %u\n", info->has_video_hw.uvd_decode);
1415 fprintf(f, " vcn_decode = %u\n", info->has_video_hw.vcn_decode);
1416 fprintf(f, " jpeg_decode = %u\n", info->has_video_hw.jpeg_decode);
1417 fprintf(f, " vce_encode = %u\n", info->has_video_hw.vce_encode);
1418 fprintf(f, " uvd_encode = %u\n", info->has_video_hw.uvd_encode);
1419 fprintf(f, " vcn_encode = %u\n", info->has_video_hw.vcn_encode);
1420 fprintf(f, " uvd_fw_version = %u\n", info->uvd_fw_version);
1421 fprintf(f, " vce_fw_version = %u\n", info->vce_fw_version);
1422 fprintf(f, " vce_harvest_config = %i\n", info->vce_harvest_config);
1423
1424 fprintf(f, "Kernel & winsys capabilities:\n");
1425 fprintf(f, " drm = %i.%i.%i\n", info->drm_major, info->drm_minor, info->drm_patchlevel);
1426 fprintf(f, " has_userptr = %i\n", info->has_userptr);
1427 fprintf(f, " has_syncobj = %u\n", info->has_syncobj);
1428 fprintf(f, " has_timeline_syncobj = %u\n", info->has_timeline_syncobj);
1429 fprintf(f, " has_fence_to_handle = %u\n", info->has_fence_to_handle);
1430 fprintf(f, " has_local_buffers = %u\n", info->has_local_buffers);
1431 fprintf(f, " kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
1432 fprintf(f, " htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
1433 fprintf(f, " si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
1434 fprintf(f, " has_bo_metadata = %u\n", info->has_bo_metadata);
1435 fprintf(f, " has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
1436 fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
1437 fprintf(f, " has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
1438 fprintf(f, " kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
1439 fprintf(f, " has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
1440 fprintf(f, " has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
1441 fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
1442 fprintf(f, " has_2d_tiling = %u\n", info->has_2d_tiling);
1443 fprintf(f, " has_read_registers_query = %u\n", info->has_read_registers_query);
1444 fprintf(f, " has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
1445 fprintf(f, " has_stable_pstate = %u\n", info->has_stable_pstate);
1446 fprintf(f, " has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
1447 fprintf(f, " mid_command_buffer_preemption_enabled = %u\n",
1448 info->mid_command_buffer_preemption_enabled);
1449 fprintf(f, " has_tmz_support = %u\n", info->has_tmz_support);
1450
1451 fprintf(f, "Shader core info:\n");
1452 for (unsigned i = 0; i < info->max_se; i++) {
1453 for (unsigned j = 0; j < info->max_sa_per_se; j++) {
1454 fprintf(f, " cu_mask[SE%u][SA%u] = 0x%x \t(%u)\tCU_EN = 0x%x\n", i, j,
1455 info->cu_mask[i][j], util_bitcount(info->cu_mask[i][j]),
1456 info->spi_cu_en & BITFIELD_MASK(util_bitcount(info->cu_mask[i][j])));
1457 }
1458 }
1459 fprintf(f, " spi_cu_en_has_effect = %i\n", info->spi_cu_en_has_effect);
1460 fprintf(f, " max_shader_clock = %i MHz\n", info->max_shader_clock);
1461 fprintf(f, " num_good_compute_units = %i\n", info->num_good_compute_units);
1462 fprintf(f, " max_good_cu_per_sa = %i\n", info->max_good_cu_per_sa);
1463 fprintf(f, " min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa);
1464 fprintf(f, " max_se = %i\n", info->max_se);
1465 fprintf(f, " num_se = %i\n", info->num_se);
1466 fprintf(f, " max_sa_per_se = %i\n", info->max_sa_per_se);
1467 fprintf(f, " max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
1468 fprintf(f, " num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd);
1469 fprintf(f, " num_physical_wave64_vgprs_per_simd = %i\n",
1470 info->num_physical_wave64_vgprs_per_simd);
1471 fprintf(f, " num_simd_per_compute_unit = %i\n", info->num_simd_per_compute_unit);
1472 fprintf(f, " min_sgpr_alloc = %i\n", info->min_sgpr_alloc);
1473 fprintf(f, " max_sgpr_alloc = %i\n", info->max_sgpr_alloc);
1474 fprintf(f, " sgpr_alloc_granularity = %i\n", info->sgpr_alloc_granularity);
1475 fprintf(f, " min_wave64_vgpr_alloc = %i\n", info->min_wave64_vgpr_alloc);
1476 fprintf(f, " max_vgpr_alloc = %i\n", info->max_vgpr_alloc);
1477 fprintf(f, " wave64_vgpr_alloc_granularity = %i\n", info->wave64_vgpr_alloc_granularity);
1478
1479 fprintf(f, "Render backend info:\n");
1480 fprintf(f, " pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
1481 fprintf(f, " max_render_backends = %i\n", info->max_render_backends);
1482 fprintf(f, " num_tile_pipes = %i\n", info->num_tile_pipes);
1483 fprintf(f, " pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
1484 fprintf(f, " enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
1485 fprintf(f, " max_alignment = %u\n", (unsigned)info->max_alignment);
1486 fprintf(f, " pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count);
1487
1488 fprintf(f, "GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config);
1489 if (info->chip_class >= GFX10) {
1490 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1491 fprintf(f, " pipe_interleave_size = %u\n",
1492 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
1493 fprintf(f, " max_compressed_frags = %u\n",
1494 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
1495 if (info->chip_class >= GFX10_3)
1496 fprintf(f, " num_pkrs = %u\n", 1 << G_0098F8_NUM_PKRS(info->gb_addr_config));
1497 } else if (info->chip_class == GFX9) {
1498 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1499 fprintf(f, " pipe_interleave_size = %u\n",
1500 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
1501 fprintf(f, " max_compressed_frags = %u\n",
1502 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
1503 fprintf(f, " bank_interleave_size = %u\n",
1504 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1505 fprintf(f, " num_banks = %u\n", 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
1506 fprintf(f, " shader_engine_tile_size = %u\n",
1507 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1508 fprintf(f, " num_shader_engines = %u\n",
1509 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
1510 fprintf(f, " num_gpus = %u (raw)\n", G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
1511 fprintf(f, " multi_gpu_tile_size = %u (raw)\n",
1512 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1513 fprintf(f, " num_rb_per_se = %u\n", 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
1514 fprintf(f, " row_size = %u\n", 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1515 fprintf(f, " num_lower_pipes = %u (raw)\n", G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1516 fprintf(f, " se_enable = %u (raw)\n", G_0098F8_SE_ENABLE(info->gb_addr_config));
1517 } else {
1518 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1519 fprintf(f, " pipe_interleave_size = %u\n",
1520 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
1521 fprintf(f, " bank_interleave_size = %u\n",
1522 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1523 fprintf(f, " num_shader_engines = %u\n",
1524 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
1525 fprintf(f, " shader_engine_tile_size = %u\n",
1526 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1527 fprintf(f, " num_gpus = %u (raw)\n", G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
1528 fprintf(f, " multi_gpu_tile_size = %u (raw)\n",
1529 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1530 fprintf(f, " row_size = %u\n", 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1531 fprintf(f, " num_lower_pipes = %u (raw)\n", G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1532 }
1533 }
1534
ac_get_gs_table_depth(enum chip_class chip_class,enum radeon_family family)1535 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
1536 {
1537 if (chip_class >= GFX9)
1538 return -1;
1539
1540 switch (family) {
1541 case CHIP_OLAND:
1542 case CHIP_HAINAN:
1543 case CHIP_KAVERI:
1544 case CHIP_KABINI:
1545 case CHIP_ICELAND:
1546 case CHIP_CARRIZO:
1547 case CHIP_STONEY:
1548 return 16;
1549 case CHIP_TAHITI:
1550 case CHIP_PITCAIRN:
1551 case CHIP_VERDE:
1552 case CHIP_BONAIRE:
1553 case CHIP_HAWAII:
1554 case CHIP_TONGA:
1555 case CHIP_FIJI:
1556 case CHIP_POLARIS10:
1557 case CHIP_POLARIS11:
1558 case CHIP_POLARIS12:
1559 case CHIP_VEGAM:
1560 return 32;
1561 default:
1562 unreachable("Unknown GPU");
1563 }
1564 }
1565
ac_get_raster_config(struct radeon_info * info,uint32_t * raster_config_p,uint32_t * raster_config_1_p,uint32_t * se_tile_repeat_p)1566 void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p,
1567 uint32_t *raster_config_1_p, uint32_t *se_tile_repeat_p)
1568 {
1569 unsigned raster_config, raster_config_1, se_tile_repeat;
1570
1571 switch (info->family) {
1572 /* 1 SE / 1 RB */
1573 case CHIP_HAINAN:
1574 case CHIP_KABINI:
1575 case CHIP_STONEY:
1576 raster_config = 0x00000000;
1577 raster_config_1 = 0x00000000;
1578 break;
1579 /* 1 SE / 4 RBs */
1580 case CHIP_VERDE:
1581 raster_config = 0x0000124a;
1582 raster_config_1 = 0x00000000;
1583 break;
1584 /* 1 SE / 2 RBs (Oland is special) */
1585 case CHIP_OLAND:
1586 raster_config = 0x00000082;
1587 raster_config_1 = 0x00000000;
1588 break;
1589 /* 1 SE / 2 RBs */
1590 case CHIP_KAVERI:
1591 case CHIP_ICELAND:
1592 case CHIP_CARRIZO:
1593 raster_config = 0x00000002;
1594 raster_config_1 = 0x00000000;
1595 break;
1596 /* 2 SEs / 4 RBs */
1597 case CHIP_BONAIRE:
1598 case CHIP_POLARIS11:
1599 case CHIP_POLARIS12:
1600 raster_config = 0x16000012;
1601 raster_config_1 = 0x00000000;
1602 break;
1603 /* 2 SEs / 8 RBs */
1604 case CHIP_TAHITI:
1605 case CHIP_PITCAIRN:
1606 raster_config = 0x2a00126a;
1607 raster_config_1 = 0x00000000;
1608 break;
1609 /* 4 SEs / 8 RBs */
1610 case CHIP_TONGA:
1611 case CHIP_POLARIS10:
1612 raster_config = 0x16000012;
1613 raster_config_1 = 0x0000002a;
1614 break;
1615 /* 4 SEs / 16 RBs */
1616 case CHIP_HAWAII:
1617 case CHIP_FIJI:
1618 case CHIP_VEGAM:
1619 raster_config = 0x3a00161a;
1620 raster_config_1 = 0x0000002e;
1621 break;
1622 default:
1623 fprintf(stderr, "ac: Unknown GPU, using 0 for raster_config\n");
1624 raster_config = 0x00000000;
1625 raster_config_1 = 0x00000000;
1626 break;
1627 }
1628
1629 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
1630 * This decreases performance by up to 50% when the RB is the bottleneck.
1631 */
1632 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
1633 raster_config = 0x00000000;
1634
1635 /* Fiji: Old kernels have incorrect tiling config. This decreases
1636 * RB performance by 25%. (it disables 1 RB in the second packer)
1637 */
1638 if (info->family == CHIP_FIJI && info->cik_macrotile_mode_array[0] == 0x000000e8) {
1639 raster_config = 0x16000012;
1640 raster_config_1 = 0x0000002a;
1641 }
1642
1643 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
1644 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
1645
1646 /* I don't know how to calculate this, though this is probably a good guess. */
1647 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
1648
1649 *raster_config_p = raster_config;
1650 *raster_config_1_p = raster_config_1;
1651 if (se_tile_repeat_p)
1652 *se_tile_repeat_p = se_tile_repeat;
1653 }
1654
ac_get_harvested_configs(struct radeon_info * info,unsigned raster_config,unsigned * cik_raster_config_1_p,unsigned * raster_config_se)1655 void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config,
1656 unsigned *cik_raster_config_1_p, unsigned *raster_config_se)
1657 {
1658 unsigned sh_per_se = MAX2(info->max_sa_per_se, 1);
1659 unsigned num_se = MAX2(info->max_se, 1);
1660 unsigned rb_mask = info->enabled_rb_mask;
1661 unsigned num_rb = MIN2(info->max_render_backends, 16);
1662 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
1663 unsigned rb_per_se = num_rb / num_se;
1664 unsigned se_mask[4];
1665 unsigned se;
1666
1667 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1668 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1669 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1670 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1671
1672 assert(num_se == 1 || num_se == 2 || num_se == 4);
1673 assert(sh_per_se == 1 || sh_per_se == 2);
1674 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
1675
1676 if (info->chip_class >= GFX7) {
1677 unsigned raster_config_1 = *cik_raster_config_1_p;
1678 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || (!se_mask[2] && !se_mask[3]))) {
1679 raster_config_1 &= C_028354_SE_PAIR_MAP;
1680
1681 if (!se_mask[0] && !se_mask[1]) {
1682 raster_config_1 |= S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
1683 } else {
1684 raster_config_1 |= S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
1685 }
1686 *cik_raster_config_1_p = raster_config_1;
1687 }
1688 }
1689
1690 for (se = 0; se < num_se; se++) {
1691 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1692 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1693 int idx = (se / 2) * 2;
1694
1695 raster_config_se[se] = raster_config;
1696 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1697 raster_config_se[se] &= C_028350_SE_MAP;
1698
1699 if (!se_mask[idx]) {
1700 raster_config_se[se] |= S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
1701 } else {
1702 raster_config_se[se] |= S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
1703 }
1704 }
1705
1706 pkr0_mask &= rb_mask;
1707 pkr1_mask &= rb_mask;
1708 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1709 raster_config_se[se] &= C_028350_PKR_MAP;
1710
1711 if (!pkr0_mask) {
1712 raster_config_se[se] |= S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
1713 } else {
1714 raster_config_se[se] |= S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
1715 }
1716 }
1717
1718 if (rb_per_se >= 2) {
1719 unsigned rb0_mask = 1 << (se * rb_per_se);
1720 unsigned rb1_mask = rb0_mask << 1;
1721
1722 rb0_mask &= rb_mask;
1723 rb1_mask &= rb_mask;
1724 if (!rb0_mask || !rb1_mask) {
1725 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
1726
1727 if (!rb0_mask) {
1728 raster_config_se[se] |= S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
1729 } else {
1730 raster_config_se[se] |= S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
1731 }
1732 }
1733
1734 if (rb_per_se > 2) {
1735 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1736 rb1_mask = rb0_mask << 1;
1737 rb0_mask &= rb_mask;
1738 rb1_mask &= rb_mask;
1739 if (!rb0_mask || !rb1_mask) {
1740 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
1741
1742 if (!rb0_mask) {
1743 raster_config_se[se] |= S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
1744 } else {
1745 raster_config_se[se] |= S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
1746 }
1747 }
1748 }
1749 }
1750 }
1751 }
1752
ac_get_compute_resource_limits(struct radeon_info * info,unsigned waves_per_threadgroup,unsigned max_waves_per_sh,unsigned threadgroups_per_cu)1753 unsigned ac_get_compute_resource_limits(struct radeon_info *info, unsigned waves_per_threadgroup,
1754 unsigned max_waves_per_sh, unsigned threadgroups_per_cu)
1755 {
1756 unsigned compute_resource_limits = S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
1757
1758 if (info->chip_class >= GFX7) {
1759 unsigned num_cu_per_se = info->num_good_compute_units / info->num_se;
1760
1761 /* Gfx9 should set the limit to max instead of 0 to fix high priority compute. */
1762 if (info->chip_class == GFX9 && !max_waves_per_sh) {
1763 max_waves_per_sh = info->max_good_cu_per_sa * info->num_simd_per_compute_unit *
1764 info->max_wave64_per_simd;
1765 }
1766
1767 /* Force even distribution on all SIMDs in CU if the workgroup
1768 * size is 64. This has shown some good improvements if # of CUs
1769 * per SE is not a multiple of 4.
1770 */
1771 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
1772 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
1773
1774 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
1775 compute_resource_limits |=
1776 S_00B854_WAVES_PER_SH(max_waves_per_sh) | S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
1777 } else {
1778 /* GFX6 */
1779 if (max_waves_per_sh) {
1780 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
1781 compute_resource_limits |= S_00B854_WAVES_PER_SH_GFX6(limit_div16);
1782 }
1783 }
1784 return compute_resource_limits;
1785 }
1786