1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_blitter.h"
40 #include "fd5_context.h"
41 #include "fd5_image.h"
42 #include "fd5_program.h"
43 #include "fd5_rasterizer.h"
44 #include "fd5_texture.h"
45 #include "fd5_screen.h"
46 #include "fd5_format.h"
47 #include "fd5_zsa.h"
48
49 #define emit_const_user fd5_emit_const_user
50 #define emit_const_bo fd5_emit_const_bo
51 #include "ir3_const.h"
52
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
56 */
57 static void
fd5_emit_const_user(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords,const uint32_t * dwords)58 fd5_emit_const_user(struct fd_ringbuffer *ring,
59 const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords,
60 const uint32_t *dwords)
61 {
62 emit_const_asserts(ring, v, regid, sizedwords);
63
64 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sizedwords);
65 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
66 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
67 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
68 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
69 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
70 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
71 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
72 for (int i = 0; i < sizedwords; i++)
73 OUT_RING(ring, ((uint32_t *)dwords)[i]);
74 }
75
76 static void
fd5_emit_const_bo(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t sizedwords,struct fd_bo * bo)77 fd5_emit_const_bo(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
78 uint32_t regid, uint32_t offset, uint32_t sizedwords, struct fd_bo *bo)
79 {
80 uint32_t dst_off = regid / 4;
81 assert(dst_off % 4 == 0);
82 uint32_t num_unit = sizedwords / 4;
83 assert(num_unit % 4 == 0);
84
85 emit_const_asserts(ring, v, regid, sizedwords);
86
87 OUT_PKT7(ring, CP_LOAD_STATE4, 3);
88 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(dst_off) |
89 CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT) |
90 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
91 CP_LOAD_STATE4_0_NUM_UNIT(num_unit));
92 OUT_RELOC(ring, bo, offset,
93 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
94 }
95
96 static void
fd5_emit_const_ptrs(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t num,struct pipe_resource ** prscs,uint32_t * offsets)97 fd5_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type,
98 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
99 {
100 uint32_t anum = align(num, 2);
101 uint32_t i;
102
103 debug_assert((regid % 4) == 0);
104
105 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
106 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
107 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
108 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
109 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
110 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
111 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
112 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
113
114 for (i = 0; i < num; i++) {
115 if (prscs[i]) {
116 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 OUT_RING(ring, 0xbad00000 | (i << 16));
120 }
121 }
122
123 for (; i < anum; i++) {
124 OUT_RING(ring, 0xffffffff);
125 OUT_RING(ring, 0xffffffff);
126 }
127 }
128
129 static bool
is_stateobj(struct fd_ringbuffer * ring)130 is_stateobj(struct fd_ringbuffer *ring)
131 {
132 return false;
133 }
134
135 static void
emit_const_ptrs(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t dst_offset,uint32_t num,struct pipe_resource ** prscs,uint32_t * offsets)136 emit_const_ptrs(struct fd_ringbuffer *ring,
137 const struct ir3_shader_variant *v, uint32_t dst_offset,
138 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
139 {
140 /* TODO inline this */
141 assert(dst_offset + num <= v->constlen * 4);
142 fd5_emit_const_ptrs(ring, v->type, dst_offset, num, prscs, offsets);
143 }
144
145 void
fd5_emit_cs_consts(const struct ir3_shader_variant * v,struct fd_ringbuffer * ring,struct fd_context * ctx,const struct pipe_grid_info * info)146 fd5_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
147 struct fd_context *ctx, const struct pipe_grid_info *info)
148 {
149 ir3_emit_cs_consts(v, ring, ctx, info);
150 }
151
152 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
153 * the same as a6xx then move this somewhere common ;-)
154 *
155 * Entry layout looks like (total size, 0x60 bytes):
156 */
157
158 struct PACKED bcolor_entry {
159 uint32_t fp32[4];
160 uint16_t ui16[4];
161 int16_t si16[4];
162
163 uint16_t fp16[4];
164 uint16_t rgb565;
165 uint16_t rgb5a1;
166 uint16_t rgba4;
167 uint8_t __pad0[2];
168 uint8_t ui8[4];
169 int8_t si8[4];
170 uint32_t rgb10a2;
171 uint32_t z24; /* also s8? */
172
173 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
174 uint8_t __pad1[24];
175 };
176
177 #define FD5_BORDER_COLOR_SIZE 0x60
178 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
179
180 static void
setup_border_colors(struct fd_texture_stateobj * tex,struct bcolor_entry * entries)181 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
182 {
183 unsigned i, j;
184 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
185
186 for (i = 0; i < tex->num_samplers; i++) {
187 struct bcolor_entry *e = &entries[i];
188 struct pipe_sampler_state *sampler = tex->samplers[i];
189 union pipe_color_union *bc;
190
191 if (!sampler)
192 continue;
193
194 bc = &sampler->border_color;
195
196 /*
197 * XXX HACK ALERT XXX
198 *
199 * The border colors need to be swizzled in a particular
200 * format-dependent order. Even though samplers don't know about
201 * formats, we can assume that with a GL state tracker, there's a
202 * 1:1 correspondence between sampler and texture. Take advantage
203 * of that knowledge.
204 */
205 if ((i >= tex->num_textures) || !tex->textures[i])
206 continue;
207
208 enum pipe_format format = tex->textures[i]->format;
209 const struct util_format_description *desc =
210 util_format_description(format);
211
212 e->rgb565 = 0;
213 e->rgb5a1 = 0;
214 e->rgba4 = 0;
215 e->rgb10a2 = 0;
216 e->z24 = 0;
217
218 for (j = 0; j < 4; j++) {
219 int c = desc->swizzle[j];
220 int cd = c;
221
222 /*
223 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
224 * stencil border color value in bc->ui[0] but according
225 * to desc->swizzle and desc->channel, the .x component
226 * is NONE and the stencil value is in the y component.
227 * Meanwhile the hardware wants this in the .x componetn.
228 */
229 if ((format == PIPE_FORMAT_X24S8_UINT) ||
230 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
231 if (j == 0) {
232 c = 1;
233 cd = 0;
234 } else {
235 continue;
236 }
237 }
238
239 if (c >= 4)
240 continue;
241
242 if (desc->channel[c].pure_integer) {
243 uint16_t clamped;
244 switch (desc->channel[c].size) {
245 case 2:
246 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
247 clamped = CLAMP(bc->ui[j], 0, 0x3);
248 break;
249 case 8:
250 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
251 clamped = CLAMP(bc->i[j], -128, 127);
252 else
253 clamped = CLAMP(bc->ui[j], 0, 255);
254 break;
255 case 10:
256 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
257 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
258 break;
259 case 16:
260 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
261 clamped = CLAMP(bc->i[j], -32768, 32767);
262 else
263 clamped = CLAMP(bc->ui[j], 0, 65535);
264 break;
265 default:
266 assert(!"Unexpected bit size");
267 case 32:
268 clamped = 0;
269 break;
270 }
271 e->fp32[cd] = bc->ui[j];
272 e->fp16[cd] = clamped;
273 } else {
274 float f = bc->f[j];
275 float f_u = CLAMP(f, 0, 1);
276 float f_s = CLAMP(f, -1, 1);
277
278 e->fp32[c] = fui(f);
279 e->fp16[c] = util_float_to_half(f);
280 e->srgb[c] = util_float_to_half(f_u);
281 e->ui16[c] = f_u * 0xffff;
282 e->si16[c] = f_s * 0x7fff;
283 e->ui8[c] = f_u * 0xff;
284 e->si8[c] = f_s * 0x7f;
285 if (c == 1)
286 e->rgb565 |= (int)(f_u * 0x3f) << 5;
287 else if (c < 3)
288 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
289 if (c == 3)
290 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
291 else
292 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
293 if (c == 3)
294 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
295 else
296 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
297 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
298 if (c == 0)
299 e->z24 = f_u * 0xffffff;
300 }
301 }
302
303 #ifdef DEBUG
304 memset(&e->__pad0, 0, sizeof(e->__pad0));
305 memset(&e->__pad1, 0, sizeof(e->__pad1));
306 #endif
307 }
308 }
309
310 static void
emit_border_color(struct fd_context * ctx,struct fd_ringbuffer * ring)311 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
312 {
313 struct fd5_context *fd5_ctx = fd5_context(ctx);
314 struct bcolor_entry *entries;
315 unsigned off;
316 void *ptr;
317
318 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
319
320 u_upload_alloc(fd5_ctx->border_color_uploader,
321 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
322 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
323 &fd5_ctx->border_color_buf,
324 &ptr);
325
326 entries = ptr;
327
328 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
329 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
330 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
331
332 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
333 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
334
335 u_upload_unmap(fd5_ctx->border_color_uploader);
336 }
337
338 static bool
emit_textures(struct fd_context * ctx,struct fd_ringbuffer * ring,enum a4xx_state_block sb,struct fd_texture_stateobj * tex)339 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
340 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
341 {
342 bool needs_border = false;
343 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
344 unsigned i;
345
346 if (tex->num_samplers > 0) {
347 /* output sampler state: */
348 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
349 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
350 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
351 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
352 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
353 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
354 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
355 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
356 for (i = 0; i < tex->num_samplers; i++) {
357 static const struct fd5_sampler_stateobj dummy_sampler = {};
358 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
359 fd5_sampler_stateobj(tex->samplers[i]) :
360 &dummy_sampler;
361 OUT_RING(ring, sampler->texsamp0);
362 OUT_RING(ring, sampler->texsamp1);
363 OUT_RING(ring, sampler->texsamp2 |
364 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
365 OUT_RING(ring, sampler->texsamp3);
366
367 needs_border |= sampler->needs_border;
368 }
369 }
370
371 if (tex->num_textures > 0) {
372 unsigned num_textures = tex->num_textures;
373
374 /* emit texture state: */
375 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
376 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
377 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
378 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
379 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
380 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
381 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
382 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
383 for (i = 0; i < tex->num_textures; i++) {
384 static const struct fd5_pipe_sampler_view dummy_view = {};
385 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
386 fd5_pipe_sampler_view(tex->textures[i]) :
387 &dummy_view;
388 enum a5xx_tile_mode tile_mode = TILE5_LINEAR;
389
390 if (view->base.texture)
391 tile_mode = fd_resource(view->base.texture)->layout.tile_mode;
392
393 OUT_RING(ring, view->texconst0 |
394 A5XX_TEX_CONST_0_TILE_MODE(tile_mode));
395 OUT_RING(ring, view->texconst1);
396 OUT_RING(ring, view->texconst2);
397 OUT_RING(ring, view->texconst3);
398 if (view->base.texture) {
399 struct fd_resource *rsc = fd_resource(view->base.texture);
400 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
401 rsc = rsc->stencil;
402 OUT_RELOC(ring, rsc->bo, view->offset,
403 (uint64_t)view->texconst5 << 32, 0);
404 } else {
405 OUT_RING(ring, 0x00000000);
406 OUT_RING(ring, view->texconst5);
407 }
408 OUT_RING(ring, view->texconst6);
409 OUT_RING(ring, view->texconst7);
410 OUT_RING(ring, view->texconst8);
411 OUT_RING(ring, view->texconst9);
412 OUT_RING(ring, view->texconst10);
413 OUT_RING(ring, view->texconst11);
414 }
415 }
416
417 return needs_border;
418 }
419
420 static void
emit_ssbos(struct fd_context * ctx,struct fd_ringbuffer * ring,enum a4xx_state_block sb,struct fd_shaderbuf_stateobj * so,const struct ir3_shader_variant * v)421 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
422 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so,
423 const struct ir3_shader_variant *v)
424 {
425 unsigned count = util_last_bit(so->enabled_mask);
426
427 for (unsigned i = 0; i < count; i++) {
428 OUT_PKT7(ring, CP_LOAD_STATE4, 5);
429 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(i) |
430 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
431 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
432 CP_LOAD_STATE4_0_NUM_UNIT(1));
433 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
434 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
435 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
436
437 struct pipe_shader_buffer *buf = &so->sb[i];
438 unsigned sz = buf->buffer_size;
439
440 /* width is in dwords, overflows into height: */
441 sz /= 4;
442
443 OUT_RING(ring, A5XX_SSBO_1_0_WIDTH(sz));
444 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(sz >> 16));
445
446 OUT_PKT7(ring, CP_LOAD_STATE4, 5);
447 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(i) |
448 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
449 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
450 CP_LOAD_STATE4_0_NUM_UNIT(1));
451 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
452 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
453 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
454
455 if (buf->buffer) {
456 struct fd_resource *rsc = fd_resource(buf->buffer);
457 OUT_RELOC(ring, rsc->bo, buf->buffer_offset, 0, 0);
458 } else {
459 OUT_RING(ring, 0x00000000);
460 OUT_RING(ring, 0x00000000);
461 }
462 }
463 }
464
465 void
fd5_emit_vertex_bufs(struct fd_ringbuffer * ring,struct fd5_emit * emit)466 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
467 {
468 int32_t i, j;
469 const struct fd_vertex_state *vtx = emit->vtx;
470 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
471
472 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
473 if (vp->inputs[i].sysval)
474 continue;
475 if (vp->inputs[i].compmask) {
476 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
477 const struct pipe_vertex_buffer *vb =
478 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
479 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
480 enum pipe_format pfmt = elem->src_format;
481 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
482 bool isint = util_format_is_pure_integer(pfmt);
483 uint32_t off = vb->buffer_offset + elem->src_offset;
484 uint32_t size = fd_bo_size(rsc->bo) - off;
485 debug_assert(fmt != VFMT5_NONE);
486
487 #ifdef DEBUG
488 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
489 */
490 if (off > fd_bo_size(rsc->bo))
491 continue;
492 #endif
493
494 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
495 OUT_RELOC(ring, rsc->bo, off, 0, 0);
496 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
497 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
498
499 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
500 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
501 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
502 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
503 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) |
504 A5XX_VFD_DECODE_INSTR_UNK30 |
505 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
506 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
507
508 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
509 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
510 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
511
512 j++;
513 }
514 }
515
516 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
517 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
518 }
519
520 void
fd5_emit_state(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit)521 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
522 struct fd5_emit *emit)
523 {
524 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
525 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
526 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
527 const enum fd_dirty_3d_state dirty = emit->dirty;
528 bool needs_border = false;
529
530 emit_marker5(ring, 5);
531
532 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
533 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
534
535 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
536 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
537 }
538
539 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
540 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
541 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
542 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
543 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
544 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
545 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
546 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
547 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
548 }
549
550 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
551 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
552 uint32_t rb_alpha_control = zsa->rb_alpha_control;
553
554 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
555 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
556
557 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
558 OUT_RING(ring, rb_alpha_control);
559
560 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
561 OUT_RING(ring, zsa->rb_stencil_control);
562 }
563
564 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
565 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
566 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
567
568 if (pfb->zsbuf) {
569 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
570 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
571
572 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
573 gras_lrz_cntl = 0;
574 else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write)
575 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
576
577 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
578 OUT_RING(ring, gras_lrz_cntl);
579 }
580 }
581
582 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
583 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
584 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
585
586 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);
587 OUT_RING(ring, zsa->rb_stencilrefmask |
588 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
589 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
590 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
591 }
592
593 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
594 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
595 bool fragz = fp->no_earlyz || fp->has_kill || fp->writes_pos;
596
597 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
598 OUT_RING(ring, zsa->rb_depth_cntl);
599
600 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
601 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
602 COND(fragz && fp->fragcoord_compmask != 0,
603 A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
604
605 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
606 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
607 COND(fragz && fp->fragcoord_compmask != 0,
608 A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
609 }
610
611 /* NOTE: scissor enabled bit is part of rasterizer state: */
612 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
613 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
614
615 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
616 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
617 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
618 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
619 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
620
621 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
622 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
623 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
624 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
625 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
626
627 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
628 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
629 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
630 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
631 }
632
633 if (dirty & FD_DIRTY_VIEWPORT) {
634 fd_wfi(ctx->batch, ring);
635 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
636 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
637 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
638 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
639 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
640 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
641 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
642 }
643
644 if (dirty & FD_DIRTY_PROG)
645 fd5_program_emit(ctx, ring, emit);
646
647 if (dirty & FD_DIRTY_RASTERIZER) {
648 struct fd5_rasterizer_stateobj *rasterizer =
649 fd5_rasterizer_stateobj(ctx->rasterizer);
650
651 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
652 OUT_RING(ring, rasterizer->gras_su_cntl |
653 COND(pfb->samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
654
655 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
656 OUT_RING(ring, rasterizer->gras_su_point_minmax);
657 OUT_RING(ring, rasterizer->gras_su_point_size);
658
659 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
660 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
661 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
662 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
663
664 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
665 OUT_RING(ring, rasterizer->pc_raster_cntl);
666
667 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
668 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
669 }
670
671 /* note: must come after program emit.. because there is some overlap
672 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
673 * values from fd5_program_emit() to avoid having to re-emit the prog
674 * every time rast state changes.
675 *
676 * Since the primitive restart state is not part of a tracked object, we
677 * re-emit this register every time.
678 */
679 if (emit->info && ctx->rasterizer) {
680 struct fd5_rasterizer_stateobj *rasterizer =
681 fd5_rasterizer_stateobj(ctx->rasterizer);
682 unsigned max_loc = fd5_context(ctx)->max_loc;
683
684 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
685 OUT_RING(ring, rasterizer->pc_primitive_cntl |
686 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) |
687 COND(emit->info->primitive_restart && emit->info->index_size,
688 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
689 }
690
691 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
692 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
693 unsigned nr = pfb->nr_cbufs;
694
695 if (emit->binning_pass)
696 nr = 0;
697 else if (ctx->rasterizer->rasterizer_discard)
698 nr = 0;
699
700 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
701 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
702 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
703
704 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
705 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
706 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
707 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
708 }
709
710 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
711 if (!emit->binning_pass)
712 ir3_emit_fs_consts(fp, ring, ctx);
713
714 struct ir3_stream_output_info *info = &vp->shader->stream_output;
715 if (info->num_outputs) {
716 struct fd_streamout_stateobj *so = &ctx->streamout;
717
718 for (unsigned i = 0; i < so->num_targets; i++) {
719 struct pipe_stream_output_target *target = so->targets[i];
720
721 if (!target)
722 continue;
723
724 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
725 target->buffer_offset;
726
727 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
728 /* VPC_SO[i].BUFFER_BASE_LO: */
729 OUT_RELOC(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
730 OUT_RING(ring, target->buffer_size + offset);
731
732 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
733 OUT_RING(ring, offset);
734 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
735 // TODO just give hw a dummy addr for now.. we should
736 // be using this an then CP_MEM_TO_REG to set the
737 // VPC_SO[i].BUFFER_OFFSET for the next draw..
738 OUT_RELOC(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
739
740 emit->streamout_mask |= (1 << i);
741 }
742 }
743
744 if (dirty & FD_DIRTY_BLEND) {
745 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
746 uint32_t i;
747
748 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
749 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
750 bool is_int = util_format_is_pure_integer(format);
751 bool has_alpha = util_format_has_alpha(format);
752 uint32_t control = blend->rb_mrt[i].control;
753
754 if (is_int) {
755 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
756 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
757 }
758
759 if (!has_alpha) {
760 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
761 }
762
763 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
764 OUT_RING(ring, control);
765
766 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
767 OUT_RING(ring, blend->rb_mrt[i].blend_control);
768 }
769
770 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
771 OUT_RING(ring, blend->sp_blend_cntl);
772 }
773
774 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
775 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
776
777 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
778 OUT_RING(ring, blend->rb_blend_cntl |
779 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
780 }
781
782 if (dirty & FD_DIRTY_BLEND_COLOR) {
783 struct pipe_blend_color *bcolor = &ctx->blend_color;
784
785 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
786 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
787 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
788 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
789 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
790 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
791 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
792 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
793 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
794 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
795 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
796 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
797 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
798 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
799 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
800 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
801 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
802 }
803
804 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
805 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
806 &ctx->tex[PIPE_SHADER_VERTEX]);
807 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
808 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
809 }
810
811 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
812 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
813 &ctx->tex[PIPE_SHADER_FRAGMENT]);
814 }
815
816 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
817 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask ?
818 ~0 : ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
819
820 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
821 OUT_RING(ring, 0);
822
823 if (needs_border)
824 emit_border_color(ctx, ring);
825
826 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
827 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT], fp);
828
829 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
830 fd5_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT, fp);
831 }
832
833 void
fd5_emit_cs_state(struct fd_context * ctx,struct fd_ringbuffer * ring,struct ir3_shader_variant * cp)834 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
835 struct ir3_shader_variant *cp)
836 {
837 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
838
839 if (dirty & FD_DIRTY_SHADER_TEX) {
840 bool needs_border = false;
841 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
842 &ctx->tex[PIPE_SHADER_COMPUTE]);
843
844 if (needs_border)
845 emit_border_color(ctx, ring);
846
847 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
848 OUT_RING(ring, 0);
849
850 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
851 OUT_RING(ring, 0);
852
853 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
854 OUT_RING(ring, 0);
855
856 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
857 OUT_RING(ring, 0);
858
859 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
860 OUT_RING(ring, 0);
861 }
862
863 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
864 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ?
865 ~0 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
866
867 if (dirty & FD_DIRTY_SHADER_SSBO)
868 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE], cp);
869
870 if (dirty & FD_DIRTY_SHADER_IMAGE)
871 fd5_emit_images(ctx, ring, PIPE_SHADER_COMPUTE, cp);
872 }
873
874 /* emit setup at begin of new cmdstream buffer (don't rely on previous
875 * state, there could have been a context switch between ioctls):
876 */
877 void
fd5_emit_restore(struct fd_batch * batch,struct fd_ringbuffer * ring)878 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
879 {
880 struct fd_context *ctx = batch->ctx;
881
882 fd5_set_render_mode(ctx, ring, BYPASS);
883 fd5_cache_flush(batch, ring);
884
885 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
886 OUT_RING(ring, 0xfffff);
887
888 /*
889 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
890 0000000500024048: 70d08003 00000000 001c5000 00000005
891 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
892 0000000500024058: 70d08003 00000010 001c7000 00000005
893
894 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
895 0000000500024068: 70268000
896 */
897
898 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
899 OUT_RING(ring, 0xffffffff);
900
901 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
902 OUT_RING(ring, 0x00000012);
903
904 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
905 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
906 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
907 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
908
909 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
910 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
911
912 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
913 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
914
915 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
916 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
917
918 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
919 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
920
921 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
922 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
923 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
924
925 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
926 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
927
928 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
929 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
930
931 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
932 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
933
934 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
935 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
936
937 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
938 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
939
940 if (ctx->screen->gpu_id == 540) {
941 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
942 OUT_RING(ring, 0x800); /* SP_DBG_ECO_CNTL */
943
944 OUT_PKT4(ring, REG_A5XX_HLSQ_DBG_ECO_CNTL, 1);
945 OUT_RING(ring, 0x0);
946
947 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
948 OUT_RING(ring, 0x800400);
949 } else {
950 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
951 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
952 }
953
954 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
955 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
956
957 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
958 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
959 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
960
961 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
962 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
963
964 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
965 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
966
967 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
968 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
969
970 /* we don't use this yet.. probably best to disable.. */
971 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
972 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
973 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
974 CP_SET_DRAW_STATE__0_GROUP_ID(0));
975 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
976 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
977
978 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
979 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
980
981 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
982 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
983
984 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
985 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
986
987 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
988 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
989
990 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
991 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
992
993 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
994 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
995 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
996 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
997
998 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
999 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1000 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1001
1002 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
1003 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
1004
1005 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
1006 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
1007
1008 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
1009 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
1010
1011 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
1012 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
1013
1014 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
1015 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
1016
1017 OUT_PKT4(ring, REG_A5XX_GRAS_SU_LAYERED, 1);
1018 OUT_RING(ring, 0x00000000); /* GRAS_SU_LAYERED */
1019
1020 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
1021 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
1022
1023 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
1024 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1025
1026 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
1027 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
1028
1029 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
1030 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
1031
1032 OUT_PKT4(ring, REG_A5XX_PC_GS_LAYERED, 1);
1033 OUT_RING(ring, 0x00000000); /* PC_GS_LAYERED */
1034
1035 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
1036 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
1037
1038 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
1039 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
1040
1041 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1042 OUT_RING(ring, 0x00000000);
1043 OUT_RING(ring, 0x00000000);
1044 OUT_RING(ring, 0x00000000);
1045
1046 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
1047 OUT_RING(ring, 0x00000000);
1048 OUT_RING(ring, 0x00000000);
1049 OUT_RING(ring, 0x00000000);
1050 OUT_RING(ring, 0x00000000);
1051 OUT_RING(ring, 0x00000000);
1052 OUT_RING(ring, 0x00000000);
1053
1054 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
1055 OUT_RING(ring, 0x00000000);
1056 OUT_RING(ring, 0x00000000);
1057 OUT_RING(ring, 0x00000000);
1058 OUT_RING(ring, 0x00000000);
1059 OUT_RING(ring, 0x00000000);
1060 OUT_RING(ring, 0x00000000);
1061
1062 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
1063 OUT_RING(ring, 0x00000000);
1064 OUT_RING(ring, 0x00000000);
1065 OUT_RING(ring, 0x00000000);
1066
1067 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
1068 OUT_RING(ring, 0x00000000);
1069
1070 OUT_PKT4(ring, REG_A5XX_SP_HS_CTRL_REG0, 1);
1071 OUT_RING(ring, 0x00000000);
1072
1073 OUT_PKT4(ring, REG_A5XX_SP_GS_CTRL_REG0, 1);
1074 OUT_RING(ring, 0x00000000);
1075
1076 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
1077 OUT_RING(ring, 0x00000000);
1078 OUT_RING(ring, 0x00000000);
1079 OUT_RING(ring, 0x00000000);
1080 OUT_RING(ring, 0x00000000);
1081
1082 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
1083 OUT_RING(ring, 0x00000000);
1084 OUT_RING(ring, 0x00000000);
1085
1086 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
1087 OUT_RING(ring, 0x00000000);
1088 OUT_RING(ring, 0x00000000);
1089 OUT_RING(ring, 0x00000000);
1090
1091 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
1092 OUT_RING(ring, 0x00000000);
1093 OUT_RING(ring, 0x00000000);
1094 OUT_RING(ring, 0x00000000);
1095
1096 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
1097 OUT_RING(ring, 0x00000000);
1098 OUT_RING(ring, 0x00000000);
1099 OUT_RING(ring, 0x00000000);
1100
1101 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1102 OUT_RING(ring, 0x00000000);
1103 OUT_RING(ring, 0x00000000);
1104 OUT_RING(ring, 0x00000000);
1105
1106 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1107 OUT_RING(ring, 0x00000000);
1108 OUT_RING(ring, 0x00000000);
1109 OUT_RING(ring, 0x00000000);
1110
1111 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1112 OUT_RING(ring, 0x00000000);
1113 OUT_RING(ring, 0x00000000);
1114 OUT_RING(ring, 0x00000000);
1115
1116 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
1117 OUT_RING(ring, 0x00000000);
1118 }
1119
1120 static void
fd5_mem_to_mem(struct fd_ringbuffer * ring,struct pipe_resource * dst,unsigned dst_off,struct pipe_resource * src,unsigned src_off,unsigned sizedwords)1121 fd5_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1122 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1123 unsigned sizedwords)
1124 {
1125 struct fd_bo *src_bo = fd_resource(src)->bo;
1126 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1127 unsigned i;
1128
1129 for (i = 0; i < sizedwords; i++) {
1130 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1131 OUT_RING(ring, 0x00000000);
1132 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
1133 OUT_RELOC(ring, src_bo, src_off, 0, 0);
1134
1135 dst_off += 4;
1136 src_off += 4;
1137 }
1138 }
1139
1140 void
fd5_emit_init_screen(struct pipe_screen * pscreen)1141 fd5_emit_init_screen(struct pipe_screen *pscreen)
1142 {
1143 struct fd_screen *screen = fd_screen(pscreen);
1144 screen->emit_ib = fd5_emit_ib;
1145 screen->mem_to_mem = fd5_mem_to_mem;
1146 }
1147
1148 void
fd5_emit_init(struct pipe_context * pctx)1149 fd5_emit_init(struct pipe_context *pctx)
1150 {
1151 }
1152