1 /*
2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
6 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * SOFTWARE.
26 *
27 */
28
29 #include "util/u_debug.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
32 #include "util/format/u_format_s3tc.h"
33 #include "util/u_video.h"
34 #include "util/u_screen.h"
35 #include "util/os_time.h"
36 #include "util/u_process.h"
37 #include "pipe/p_defines.h"
38 #include "pipe/p_screen.h"
39 #include "draw/draw_context.h"
40
41 #include <fcntl.h>
42
43 #include "drm-uapi/drm_fourcc.h"
44 #include "drm-uapi/panfrost_drm.h"
45
46 #include "pan_bo.h"
47 #include "pan_screen.h"
48 #include "pan_resource.h"
49 #include "pan_public.h"
50 #include "pan_util.h"
51 #include "pandecode/decode.h"
52
53 #include "pan_context.h"
54 #include "midgard/midgard_compile.h"
55 #include "bifrost/bifrost_compile.h"
56 #include "panfrost-quirks.h"
57
58 static const struct debug_named_value debug_options[] = {
59 {"msgs", PAN_DBG_MSGS, "Print debug messages"},
60 {"trace", PAN_DBG_TRACE, "Trace the command stream"},
61 {"deqp", PAN_DBG_DEQP, "Hacks for dEQP"},
62 {"afbc", PAN_DBG_AFBC, "Enable non-conformant AFBC impl"},
63 {"sync", PAN_DBG_SYNC, "Wait for each job's completion and check for any GPU fault"},
64 {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
65 {"nofp16", PAN_DBG_NOFP16, "Disable 16-bit support"},
66 {"bifrost", PAN_DBG_BIFROST, "Enable experimental Mali G31 and G52 support"},
67 {"gl3", PAN_DBG_GL3, "Enable experimental GL 3.x implementation, up to 3.3"},
68 DEBUG_NAMED_VALUE_END
69 };
70
71 static const char *
panfrost_get_name(struct pipe_screen * screen)72 panfrost_get_name(struct pipe_screen *screen)
73 {
74 return panfrost_model_name(pan_device(screen)->gpu_id);
75 }
76
77 static const char *
panfrost_get_vendor(struct pipe_screen * screen)78 panfrost_get_vendor(struct pipe_screen *screen)
79 {
80 return "Panfrost";
81 }
82
83 static const char *
panfrost_get_device_vendor(struct pipe_screen * screen)84 panfrost_get_device_vendor(struct pipe_screen *screen)
85 {
86 return "Arm";
87 }
88
89 static int
panfrost_get_param(struct pipe_screen * screen,enum pipe_cap param)90 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
91 {
92 /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
93 struct panfrost_device *dev = pan_device(screen);
94 bool is_deqp = dev->debug & PAN_DBG_DEQP;
95
96 /* Our GL 3.x implementation is WIP */
97 bool is_gl3 = dev->debug & PAN_DBG_GL3;
98 is_gl3 |= is_deqp;
99
100 /* Don't expose MRT related CAPs on GPUs that don't implement them */
101 bool has_mrt = !(dev->quirks & MIDGARD_SFBD);
102
103 /* Bifrost is WIP. No MRT support yet. */
104 bool is_bifrost = (dev->quirks & IS_BIFROST);
105 has_mrt &= !is_bifrost;
106
107 switch (param) {
108 case PIPE_CAP_NPOT_TEXTURES:
109 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
110 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
111 case PIPE_CAP_VERTEX_SHADER_SATURATE:
112 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
113 case PIPE_CAP_POINT_SPRITE:
114 case PIPE_CAP_DEPTH_CLIP_DISABLE:
115 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
116 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
117 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
118 return 1;
119
120 case PIPE_CAP_MAX_RENDER_TARGETS:
121 case PIPE_CAP_FBFETCH:
122 case PIPE_CAP_FBFETCH_COHERENT:
123 return has_mrt ? 8 : 1;
124
125 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
126 return 1;
127
128 case PIPE_CAP_SAMPLE_SHADING:
129 /* WIP */
130 return is_gl3 ? 1 : 0;
131
132
133 /* ES3 features unsupported on Bifrost */
134 case PIPE_CAP_OCCLUSION_QUERY:
135 case PIPE_CAP_TGSI_INSTANCEID:
136 case PIPE_CAP_TEXTURE_MULTISAMPLE:
137 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
138 case PIPE_CAP_PRIMITIVE_RESTART:
139 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
140 return !is_bifrost;
141
142 case PIPE_CAP_SAMPLER_VIEW_TARGET:
143 case PIPE_CAP_TEXTURE_SWIZZLE:
144 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
145 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
146 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
147 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
148 case PIPE_CAP_INDEP_BLEND_ENABLE:
149 case PIPE_CAP_INDEP_BLEND_FUNC:
150 case PIPE_CAP_GENERATE_MIPMAP:
151 case PIPE_CAP_ACCELERATED:
152 case PIPE_CAP_UMA:
153 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
154 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
155 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
156 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
157 return 1;
158
159 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
160 return is_bifrost ? 0 : 4;
161 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
162 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
163 return is_bifrost ? 0 : 64;
164 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
165 return is_bifrost ? 0 : 1;
166
167 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
168 return is_bifrost ? 0 : 256;
169
170 case PIPE_CAP_GLSL_FEATURE_LEVEL:
171 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
172 return is_gl3 ? 330 : (is_bifrost ? 120 : 140);
173 case PIPE_CAP_ESSL_FEATURE_LEVEL:
174 return is_bifrost ? 120 : 300;
175
176 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
177 return 16;
178
179 /* For faking GLES 3.1 for dEQP-GLES31 */
180 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
181 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
182 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
183 case PIPE_CAP_CUBE_MAP_ARRAY:
184 case PIPE_CAP_COMPUTE:
185 return is_deqp;
186 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
187 return is_deqp ? 65536 : 0;
188
189 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
190 case PIPE_CAP_QUERY_TIMESTAMP:
191 case PIPE_CAP_CONDITIONAL_RENDER:
192 return is_gl3;
193
194 /* TODO: Where does this req come from in practice? */
195 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
196 return 1;
197
198 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
199 return 4096;
200 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
201 return is_bifrost ? 0 : 13;
202 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
203 return 13;
204
205 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
206 /* Hardware is natively upper left */
207 return 0;
208
209 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
210 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
211 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
212 case PIPE_CAP_TGSI_TEXCOORD:
213 return 1;
214
215 /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
216 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
217 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
218 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
219 return is_bifrost;
220
221 case PIPE_CAP_SEAMLESS_CUBE_MAP:
222 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
223 return !is_bifrost;
224
225 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
226 return 0xffff;
227
228 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
229 return 0;
230
231 case PIPE_CAP_ENDIANNESS:
232 return PIPE_ENDIAN_NATIVE;
233
234 return 1;
235
236 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
237 return -8;
238
239 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
240 return 7;
241
242 case PIPE_CAP_VIDEO_MEMORY: {
243 uint64_t system_memory;
244
245 if (!os_get_total_physical_memory(&system_memory))
246 return 0;
247
248 return (int)(system_memory >> 20);
249 }
250
251 case PIPE_CAP_SHADER_STENCIL_EXPORT:
252 return !is_bifrost;
253
254 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
255 return 4;
256
257 case PIPE_CAP_MAX_VARYINGS:
258 return 16;
259
260 case PIPE_CAP_ALPHA_TEST:
261 case PIPE_CAP_FLATSHADE:
262 case PIPE_CAP_TWO_SIDED_COLOR:
263 case PIPE_CAP_CLIP_PLANES:
264 return 0;
265
266 case PIPE_CAP_PACKED_STREAM_OUTPUT:
267 return 0;
268
269 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
270 case PIPE_CAP_PSIZ_CLAMPED:
271 return 1;
272
273 default:
274 return u_pipe_screen_get_param_defaults(screen, param);
275 }
276 }
277
278 static int
panfrost_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)279 panfrost_get_shader_param(struct pipe_screen *screen,
280 enum pipe_shader_type shader,
281 enum pipe_shader_cap param)
282 {
283 struct panfrost_device *dev = pan_device(screen);
284 bool is_deqp = dev->debug & PAN_DBG_DEQP;
285 bool is_nofp16 = dev->debug & PAN_DBG_NOFP16;
286 bool is_bifrost = dev->quirks & IS_BIFROST;
287
288 if (shader != PIPE_SHADER_VERTEX &&
289 shader != PIPE_SHADER_FRAGMENT &&
290 !(shader == PIPE_SHADER_COMPUTE && is_deqp))
291 return 0;
292
293 /* this is probably not totally correct.. but it's a start: */
294 switch (param) {
295 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
296 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
297 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
298 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
299 return 16384;
300
301 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
302 return 1024;
303
304 case PIPE_SHADER_CAP_MAX_INPUTS:
305 return 16;
306
307 case PIPE_SHADER_CAP_MAX_OUTPUTS:
308 return shader == PIPE_SHADER_FRAGMENT ? 8 : 16;
309
310 case PIPE_SHADER_CAP_MAX_TEMPS:
311 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
312
313 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
314 return 16 * 1024 * sizeof(float);
315
316 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
317 return PAN_MAX_CONST_BUFFERS;
318
319 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
320 return 0;
321
322 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
323 return is_bifrost ? 0 : 1;
324 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
325 return 0;
326
327 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
328 return 0;
329
330 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
331 return is_bifrost ? 0 : 1;
332
333 case PIPE_SHADER_CAP_SUBROUTINES:
334 return 0;
335
336 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
337 return 0;
338
339 case PIPE_SHADER_CAP_INTEGERS:
340 return 1;
341
342 case PIPE_SHADER_CAP_FP16:
343 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
344 return !is_nofp16;
345
346 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
347 case PIPE_SHADER_CAP_INT16:
348 case PIPE_SHADER_CAP_INT64_ATOMICS:
349 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
350 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
351 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
352 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
353 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
354 return 0;
355
356 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
357 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
358 return 16; /* XXX: How many? */
359
360 case PIPE_SHADER_CAP_PREFERRED_IR:
361 return PIPE_SHADER_IR_NIR;
362
363 case PIPE_SHADER_CAP_SUPPORTED_IRS:
364 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
365
366 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
367 return 32;
368
369 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
370 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
371 return is_deqp ? 8 : 0;
372 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
373 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
374 return 0;
375
376 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
377 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
378 return 0;
379
380 default:
381 /* Other params are unknown */
382 return 0;
383 }
384
385 return 0;
386 }
387
388 static float
panfrost_get_paramf(struct pipe_screen * screen,enum pipe_capf param)389 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
390 {
391 switch (param) {
392 case PIPE_CAPF_MAX_LINE_WIDTH:
393
394 /* fall-through */
395 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
396 return 255.0; /* arbitrary */
397
398 case PIPE_CAPF_MAX_POINT_WIDTH:
399
400 /* fall-through */
401 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
402 return 1024.0;
403
404 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
405 return 16.0;
406
407 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
408 return 16.0; /* arbitrary */
409
410 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
411 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
412 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
413 return 0.0f;
414
415 default:
416 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
417 return 0.0;
418 }
419 }
420
421 /**
422 * Query format support for creating a texture, drawing surface, etc.
423 * \param format the format to test
424 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
425 */
426 static bool
panfrost_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bind)427 panfrost_is_format_supported( struct pipe_screen *screen,
428 enum pipe_format format,
429 enum pipe_texture_target target,
430 unsigned sample_count,
431 unsigned storage_sample_count,
432 unsigned bind)
433 {
434 struct panfrost_device *dev = pan_device(screen);
435 const struct util_format_description *format_desc;
436
437 assert(target == PIPE_BUFFER ||
438 target == PIPE_TEXTURE_1D ||
439 target == PIPE_TEXTURE_1D_ARRAY ||
440 target == PIPE_TEXTURE_2D ||
441 target == PIPE_TEXTURE_2D_ARRAY ||
442 target == PIPE_TEXTURE_RECT ||
443 target == PIPE_TEXTURE_3D ||
444 target == PIPE_TEXTURE_CUBE ||
445 target == PIPE_TEXTURE_CUBE_ARRAY);
446
447 format_desc = util_format_description(format);
448
449 if (!format_desc)
450 return false;
451
452 /* MSAA 4x supported, but no more. Technically some revisions of the
453 * hardware can go up to 16x but we don't support higher modes yet.
454 * MSAA 2x is notably not supported and gets rounded up to MSAA 4x. */
455
456 if (!(sample_count == 0 || sample_count == 1 || sample_count == 4))
457 return false;
458
459 if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
460 return false;
461
462 /* Don't confuse poorly written apps (workaround dEQP bug) that expect
463 * more alpha than they ask for */
464
465 bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
466 bool renderable = bind & PIPE_BIND_RENDER_TARGET;
467
468 if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
469 return false;
470
471 /* Check we support the format with the given bind */
472
473 unsigned relevant_bind = bind &
474 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
475 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
476
477 struct panfrost_format fmt = panfrost_pipe_format_table[format];
478
479 /* Also check that compressed texture formats are supported on this
480 * particular chip. They may not be depending on system integration
481 * differences. RGTC can be emulated so is always supported. */
482
483 bool is_rgtc = format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC;
484 bool supported = panfrost_supports_compressed_format(dev, fmt.hw);
485
486 if (!is_rgtc && !supported)
487 return false;
488
489 return fmt.hw && ((relevant_bind & ~fmt.bind) == 0);
490 }
491
492 static int
panfrost_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)493 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
494 enum pipe_compute_cap param, void *ret)
495 {
496 struct panfrost_device *dev = pan_device(pscreen);
497 const char * const ir = "panfrost";
498
499 if (!(dev->debug & PAN_DBG_DEQP))
500 return 0;
501
502 #define RET(x) do { \
503 if (ret) \
504 memcpy(ret, x, sizeof(x)); \
505 return sizeof(x); \
506 } while (0)
507
508 switch (param) {
509 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
510 RET((uint32_t []){ 64 });
511
512 case PIPE_COMPUTE_CAP_IR_TARGET:
513 if (ret)
514 sprintf(ret, "%s", ir);
515 return strlen(ir) * sizeof(char);
516
517 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
518 RET((uint64_t []) { 3 });
519
520 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
521 RET(((uint64_t []) { 65535, 65535, 65535 }));
522
523 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
524 RET(((uint64_t []) { 1024, 1024, 64 }));
525
526 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
527 RET((uint64_t []) { 1024 });
528
529 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
530 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
531
532 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
533 RET((uint64_t []) { 32768 });
534
535 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
536 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
537 RET((uint64_t []) { 4096 });
538
539 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
540 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
541
542 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
543 RET((uint32_t []) { 800 /* MHz -- TODO */ });
544
545 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
546 RET((uint32_t []) { 9999 }); // TODO
547
548 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
549 RET((uint32_t []) { 1 }); // TODO
550
551 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
552 RET((uint32_t []) { 32 }); // TODO
553
554 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
555 RET((uint64_t []) { 1024 }); // TODO
556 }
557
558 return 0;
559 }
560
561 static void
panfrost_destroy_screen(struct pipe_screen * pscreen)562 panfrost_destroy_screen(struct pipe_screen *pscreen)
563 {
564 panfrost_close_device(pan_device(pscreen));
565 ralloc_free(pscreen);
566 }
567
568 static uint64_t
panfrost_get_timestamp(struct pipe_screen * _screen)569 panfrost_get_timestamp(struct pipe_screen *_screen)
570 {
571 return os_time_get_nano();
572 }
573
574 static void
panfrost_fence_reference(struct pipe_screen * pscreen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)575 panfrost_fence_reference(struct pipe_screen *pscreen,
576 struct pipe_fence_handle **ptr,
577 struct pipe_fence_handle *fence)
578 {
579 struct panfrost_device *dev = pan_device(pscreen);
580 struct panfrost_fence **p = (struct panfrost_fence **)ptr;
581 struct panfrost_fence *f = (struct panfrost_fence *)fence;
582 struct panfrost_fence *old = *p;
583
584 if (pipe_reference(&(*p)->reference, &f->reference)) {
585 drmSyncobjDestroy(dev->fd, old->syncobj);
586 free(old);
587 }
588 *p = f;
589 }
590
591 static bool
panfrost_fence_finish(struct pipe_screen * pscreen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)592 panfrost_fence_finish(struct pipe_screen *pscreen,
593 struct pipe_context *ctx,
594 struct pipe_fence_handle *fence,
595 uint64_t timeout)
596 {
597 struct panfrost_device *dev = pan_device(pscreen);
598 struct panfrost_fence *f = (struct panfrost_fence *)fence;
599 int ret;
600
601 if (f->signaled)
602 return true;
603
604 uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
605 if (abs_timeout == OS_TIMEOUT_INFINITE)
606 abs_timeout = INT64_MAX;
607
608 ret = drmSyncobjWait(dev->fd, &f->syncobj,
609 1,
610 abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
611 NULL);
612
613 f->signaled = (ret >= 0);
614 return f->signaled;
615 }
616
617 struct panfrost_fence *
panfrost_fence_create(struct panfrost_context * ctx,uint32_t syncobj)618 panfrost_fence_create(struct panfrost_context *ctx,
619 uint32_t syncobj)
620 {
621 struct panfrost_fence *f = calloc(1, sizeof(*f));
622 if (!f)
623 return NULL;
624
625 pipe_reference_init(&f->reference, 1);
626 f->syncobj = syncobj;
627
628 return f;
629 }
630
631 static const void *
panfrost_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)632 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
633 enum pipe_shader_ir ir,
634 enum pipe_shader_type shader)
635 {
636 if (pan_device(pscreen)->quirks & IS_BIFROST)
637 return &bifrost_nir_options;
638 else
639 return &midgard_nir_options;
640 }
641
642 struct pipe_screen *
panfrost_create_screen(int fd,struct renderonly * ro)643 panfrost_create_screen(int fd, struct renderonly *ro)
644 {
645 /* Create the screen */
646 struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
647
648 if (!screen)
649 return NULL;
650
651 struct panfrost_device *dev = pan_device(&screen->base);
652 panfrost_open_device(screen, fd, dev);
653
654 dev->debug = debug_get_flags_option("PAN_MESA_DEBUG", debug_options, 0);
655
656 if (ro) {
657 dev->ro = renderonly_dup(ro);
658 if (!dev->ro) {
659 if (dev->debug & PAN_DBG_MSGS)
660 fprintf(stderr, "Failed to dup renderonly object\n");
661
662 free(screen);
663 return NULL;
664 }
665 }
666
667 /* Check if we're loading against a supported GPU model. */
668
669 switch (dev->gpu_id) {
670 case 0x720: /* T720 */
671 case 0x750: /* T760 */
672 case 0x820: /* T820 */
673 case 0x860: /* T860 */
674 break;
675 case 0x7093: /* G31 */
676 case 0x7212: /* G52 */
677 if (dev->debug & PAN_DBG_BIFROST)
678 break;
679
680 /* fallthrough */
681 default:
682 /* Fail to load against untested models */
683 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
684 panfrost_destroy_screen(&(screen->base));
685 return NULL;
686 }
687
688 if (dev->debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
689 pandecode_initialize(!(dev->debug & PAN_DBG_TRACE));
690
691 screen->base.destroy = panfrost_destroy_screen;
692
693 screen->base.get_name = panfrost_get_name;
694 screen->base.get_vendor = panfrost_get_vendor;
695 screen->base.get_device_vendor = panfrost_get_device_vendor;
696 screen->base.get_param = panfrost_get_param;
697 screen->base.get_shader_param = panfrost_get_shader_param;
698 screen->base.get_compute_param = panfrost_get_compute_param;
699 screen->base.get_paramf = panfrost_get_paramf;
700 screen->base.get_timestamp = panfrost_get_timestamp;
701 screen->base.is_format_supported = panfrost_is_format_supported;
702 screen->base.context_create = panfrost_create_context;
703 screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
704 screen->base.fence_reference = panfrost_fence_reference;
705 screen->base.fence_finish = panfrost_fence_finish;
706 screen->base.set_damage_region = panfrost_resource_set_damage_region;
707
708 panfrost_resource_screen_init(&screen->base);
709
710 if (!(dev->quirks & IS_BIFROST))
711 panfrost_init_blit_shaders(dev);
712
713 return &screen->base;
714 }
715