1 /*
2  * Copyright © 2010 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "brw_fs.h"
27 #include "brw_nir.h"
28 #include "brw_vec4_tes.h"
29 #include "dev/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
32 
33 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type * type)34 brw_type_for_base_type(const struct glsl_type *type)
35 {
36    switch (type->base_type) {
37    case GLSL_TYPE_FLOAT16:
38       return BRW_REGISTER_TYPE_HF;
39    case GLSL_TYPE_FLOAT:
40       return BRW_REGISTER_TYPE_F;
41    case GLSL_TYPE_INT:
42    case GLSL_TYPE_BOOL:
43    case GLSL_TYPE_SUBROUTINE:
44       return BRW_REGISTER_TYPE_D;
45    case GLSL_TYPE_INT16:
46       return BRW_REGISTER_TYPE_W;
47    case GLSL_TYPE_INT8:
48       return BRW_REGISTER_TYPE_B;
49    case GLSL_TYPE_UINT:
50       return BRW_REGISTER_TYPE_UD;
51    case GLSL_TYPE_UINT16:
52       return BRW_REGISTER_TYPE_UW;
53    case GLSL_TYPE_UINT8:
54       return BRW_REGISTER_TYPE_UB;
55    case GLSL_TYPE_ARRAY:
56       return brw_type_for_base_type(type->fields.array);
57    case GLSL_TYPE_STRUCT:
58    case GLSL_TYPE_INTERFACE:
59    case GLSL_TYPE_SAMPLER:
60    case GLSL_TYPE_ATOMIC_UINT:
61       /* These should be overridden with the type of the member when
62        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
63        * way to trip up if we don't.
64        */
65       return BRW_REGISTER_TYPE_UD;
66    case GLSL_TYPE_IMAGE:
67       return BRW_REGISTER_TYPE_UD;
68    case GLSL_TYPE_DOUBLE:
69       return BRW_REGISTER_TYPE_DF;
70    case GLSL_TYPE_UINT64:
71       return BRW_REGISTER_TYPE_UQ;
72    case GLSL_TYPE_INT64:
73       return BRW_REGISTER_TYPE_Q;
74    case GLSL_TYPE_VOID:
75    case GLSL_TYPE_ERROR:
76    case GLSL_TYPE_FUNCTION:
77       unreachable("not reached");
78    }
79 
80    return BRW_REGISTER_TYPE_F;
81 }
82 
83 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op)84 brw_conditional_for_comparison(unsigned int op)
85 {
86    switch (op) {
87    case ir_binop_less:
88       return BRW_CONDITIONAL_L;
89    case ir_binop_gequal:
90       return BRW_CONDITIONAL_GE;
91    case ir_binop_equal:
92    case ir_binop_all_equal: /* same as equal for scalars */
93       return BRW_CONDITIONAL_Z;
94    case ir_binop_nequal:
95    case ir_binop_any_nequal: /* same as nequal for scalars */
96       return BRW_CONDITIONAL_NZ;
97    default:
98       unreachable("not reached: bad operation for comparison");
99    }
100 }
101 
102 uint32_t
brw_math_function(enum opcode op)103 brw_math_function(enum opcode op)
104 {
105    switch (op) {
106    case SHADER_OPCODE_RCP:
107       return BRW_MATH_FUNCTION_INV;
108    case SHADER_OPCODE_RSQ:
109       return BRW_MATH_FUNCTION_RSQ;
110    case SHADER_OPCODE_SQRT:
111       return BRW_MATH_FUNCTION_SQRT;
112    case SHADER_OPCODE_EXP2:
113       return BRW_MATH_FUNCTION_EXP;
114    case SHADER_OPCODE_LOG2:
115       return BRW_MATH_FUNCTION_LOG;
116    case SHADER_OPCODE_POW:
117       return BRW_MATH_FUNCTION_POW;
118    case SHADER_OPCODE_SIN:
119       return BRW_MATH_FUNCTION_SIN;
120    case SHADER_OPCODE_COS:
121       return BRW_MATH_FUNCTION_COS;
122    case SHADER_OPCODE_INT_QUOTIENT:
123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
124    case SHADER_OPCODE_INT_REMAINDER:
125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
126    default:
127       unreachable("not reached: unknown math function");
128    }
129 }
130 
131 bool
brw_texture_offset(const nir_tex_instr * tex,unsigned src,uint32_t * offset_bits_out)132 brw_texture_offset(const nir_tex_instr *tex, unsigned src,
133                    uint32_t *offset_bits_out)
134 {
135    if (!nir_src_is_const(tex->src[src].src))
136       return false;
137 
138    const unsigned num_components = nir_tex_instr_src_size(tex, src);
139 
140    /* Combine all three offsets into a single unsigned dword:
141     *
142     *    bits 11:8 - U Offset (X component)
143     *    bits  7:4 - V Offset (Y component)
144     *    bits  3:0 - R Offset (Z component)
145     */
146    uint32_t offset_bits = 0;
147    for (unsigned i = 0; i < num_components; i++) {
148       int offset = nir_src_comp_as_int(tex->src[src].src, i);
149 
150       /* offset out of bounds; caller will handle it. */
151       if (offset > 7 || offset < -8)
152          return false;
153 
154       const unsigned shift = 4 * (2 - i);
155       offset_bits |= (offset << shift) & (0xF << shift);
156    }
157 
158    *offset_bits_out = offset_bits;
159 
160    return true;
161 }
162 
163 const char *
brw_instruction_name(const struct gen_device_info * devinfo,enum opcode op)164 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
165 {
166    switch (op) {
167    case 0 ... NUM_BRW_OPCODES - 1:
168       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
169        * start of a loop in the IR.
170        */
171       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
172          return "do";
173 
174       /* The following conversion opcodes doesn't exist on Gen8+, but we use
175        * then to mark that we want to do the conversion.
176        */
177       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
178          return "f32to16";
179 
180       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
181          return "f16to32";
182 
183       assert(brw_opcode_desc(devinfo, op)->name);
184       return brw_opcode_desc(devinfo, op)->name;
185    case FS_OPCODE_FB_WRITE:
186       return "fb_write";
187    case FS_OPCODE_FB_WRITE_LOGICAL:
188       return "fb_write_logical";
189    case FS_OPCODE_REP_FB_WRITE:
190       return "rep_fb_write";
191    case FS_OPCODE_FB_READ:
192       return "fb_read";
193    case FS_OPCODE_FB_READ_LOGICAL:
194       return "fb_read_logical";
195 
196    case SHADER_OPCODE_RCP:
197       return "rcp";
198    case SHADER_OPCODE_RSQ:
199       return "rsq";
200    case SHADER_OPCODE_SQRT:
201       return "sqrt";
202    case SHADER_OPCODE_EXP2:
203       return "exp2";
204    case SHADER_OPCODE_LOG2:
205       return "log2";
206    case SHADER_OPCODE_POW:
207       return "pow";
208    case SHADER_OPCODE_INT_QUOTIENT:
209       return "int_quot";
210    case SHADER_OPCODE_INT_REMAINDER:
211       return "int_rem";
212    case SHADER_OPCODE_SIN:
213       return "sin";
214    case SHADER_OPCODE_COS:
215       return "cos";
216 
217    case SHADER_OPCODE_SEND:
218       return "send";
219 
220    case SHADER_OPCODE_UNDEF:
221       return "undef";
222 
223    case SHADER_OPCODE_TEX:
224       return "tex";
225    case SHADER_OPCODE_TEX_LOGICAL:
226       return "tex_logical";
227    case SHADER_OPCODE_TXD:
228       return "txd";
229    case SHADER_OPCODE_TXD_LOGICAL:
230       return "txd_logical";
231    case SHADER_OPCODE_TXF:
232       return "txf";
233    case SHADER_OPCODE_TXF_LOGICAL:
234       return "txf_logical";
235    case SHADER_OPCODE_TXF_LZ:
236       return "txf_lz";
237    case SHADER_OPCODE_TXL:
238       return "txl";
239    case SHADER_OPCODE_TXL_LOGICAL:
240       return "txl_logical";
241    case SHADER_OPCODE_TXL_LZ:
242       return "txl_lz";
243    case SHADER_OPCODE_TXS:
244       return "txs";
245    case SHADER_OPCODE_TXS_LOGICAL:
246       return "txs_logical";
247    case FS_OPCODE_TXB:
248       return "txb";
249    case FS_OPCODE_TXB_LOGICAL:
250       return "txb_logical";
251    case SHADER_OPCODE_TXF_CMS:
252       return "txf_cms";
253    case SHADER_OPCODE_TXF_CMS_LOGICAL:
254       return "txf_cms_logical";
255    case SHADER_OPCODE_TXF_CMS_W:
256       return "txf_cms_w";
257    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
258       return "txf_cms_w_logical";
259    case SHADER_OPCODE_TXF_UMS:
260       return "txf_ums";
261    case SHADER_OPCODE_TXF_UMS_LOGICAL:
262       return "txf_ums_logical";
263    case SHADER_OPCODE_TXF_MCS:
264       return "txf_mcs";
265    case SHADER_OPCODE_TXF_MCS_LOGICAL:
266       return "txf_mcs_logical";
267    case SHADER_OPCODE_LOD:
268       return "lod";
269    case SHADER_OPCODE_LOD_LOGICAL:
270       return "lod_logical";
271    case SHADER_OPCODE_TG4:
272       return "tg4";
273    case SHADER_OPCODE_TG4_LOGICAL:
274       return "tg4_logical";
275    case SHADER_OPCODE_TG4_OFFSET:
276       return "tg4_offset";
277    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
278       return "tg4_offset_logical";
279    case SHADER_OPCODE_SAMPLEINFO:
280       return "sampleinfo";
281    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
282       return "sampleinfo_logical";
283 
284    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
285       return "image_size_logical";
286 
287    case SHADER_OPCODE_SHADER_TIME_ADD:
288       return "shader_time_add";
289 
290    case VEC4_OPCODE_UNTYPED_ATOMIC:
291       return "untyped_atomic";
292    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
293       return "untyped_atomic_logical";
294    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
295       return "untyped_atomic_float_logical";
296    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
297       return "untyped_surface_read";
298    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
299       return "untyped_surface_read_logical";
300    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
301       return "untyped_surface_write";
302    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
303       return "untyped_surface_write_logical";
304    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
305       return "a64_untyped_read_logical";
306    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
307       return "a64_untyped_write_logical";
308    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
309       return "a64_byte_scattered_read_logical";
310    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
311       return "a64_byte_scattered_write_logical";
312    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
313       return "a64_untyped_atomic_logical";
314    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
315       return "a64_untyped_atomic_int64_logical";
316    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
317       return "a64_untyped_atomic_float_logical";
318    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
319       return "typed_atomic_logical";
320    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
321       return "typed_surface_read_logical";
322    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
323       return "typed_surface_write_logical";
324    case SHADER_OPCODE_MEMORY_FENCE:
325       return "memory_fence";
326    case FS_OPCODE_SCHEDULING_FENCE:
327       return "scheduling_fence";
328    case SHADER_OPCODE_INTERLOCK:
329       /* For an interlock we actually issue a memory fence via sendc. */
330       return "interlock";
331 
332    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
333       return "byte_scattered_read_logical";
334    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
335       return "byte_scattered_write_logical";
336    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
337       return "dword_scattered_read_logical";
338    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
339       return "dword_scattered_write_logical";
340 
341    case SHADER_OPCODE_LOAD_PAYLOAD:
342       return "load_payload";
343    case FS_OPCODE_PACK:
344       return "pack";
345 
346    case SHADER_OPCODE_GEN4_SCRATCH_READ:
347       return "gen4_scratch_read";
348    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
349       return "gen4_scratch_write";
350    case SHADER_OPCODE_GEN7_SCRATCH_READ:
351       return "gen7_scratch_read";
352    case SHADER_OPCODE_URB_WRITE_SIMD8:
353       return "gen8_urb_write_simd8";
354    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
355       return "gen8_urb_write_simd8_per_slot";
356    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
357       return "gen8_urb_write_simd8_masked";
358    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
359       return "gen8_urb_write_simd8_masked_per_slot";
360    case SHADER_OPCODE_URB_READ_SIMD8:
361       return "urb_read_simd8";
362    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
363       return "urb_read_simd8_per_slot";
364 
365    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
366       return "find_live_channel";
367    case FS_OPCODE_LOAD_LIVE_CHANNELS:
368       return "load_live_channels";
369 
370    case SHADER_OPCODE_BROADCAST:
371       return "broadcast";
372    case SHADER_OPCODE_SHUFFLE:
373       return "shuffle";
374    case SHADER_OPCODE_SEL_EXEC:
375       return "sel_exec";
376    case SHADER_OPCODE_QUAD_SWIZZLE:
377       return "quad_swizzle";
378    case SHADER_OPCODE_CLUSTER_BROADCAST:
379       return "cluster_broadcast";
380 
381    case SHADER_OPCODE_GET_BUFFER_SIZE:
382       return "get_buffer_size";
383 
384    case VEC4_OPCODE_MOV_BYTES:
385       return "mov_bytes";
386    case VEC4_OPCODE_PACK_BYTES:
387       return "pack_bytes";
388    case VEC4_OPCODE_UNPACK_UNIFORM:
389       return "unpack_uniform";
390    case VEC4_OPCODE_DOUBLE_TO_F32:
391       return "double_to_f32";
392    case VEC4_OPCODE_DOUBLE_TO_D32:
393       return "double_to_d32";
394    case VEC4_OPCODE_DOUBLE_TO_U32:
395       return "double_to_u32";
396    case VEC4_OPCODE_TO_DOUBLE:
397       return "single_to_double";
398    case VEC4_OPCODE_PICK_LOW_32BIT:
399       return "pick_low_32bit";
400    case VEC4_OPCODE_PICK_HIGH_32BIT:
401       return "pick_high_32bit";
402    case VEC4_OPCODE_SET_LOW_32BIT:
403       return "set_low_32bit";
404    case VEC4_OPCODE_SET_HIGH_32BIT:
405       return "set_high_32bit";
406 
407    case FS_OPCODE_DDX_COARSE:
408       return "ddx_coarse";
409    case FS_OPCODE_DDX_FINE:
410       return "ddx_fine";
411    case FS_OPCODE_DDY_COARSE:
412       return "ddy_coarse";
413    case FS_OPCODE_DDY_FINE:
414       return "ddy_fine";
415 
416    case FS_OPCODE_LINTERP:
417       return "linterp";
418 
419    case FS_OPCODE_PIXEL_X:
420       return "pixel_x";
421    case FS_OPCODE_PIXEL_Y:
422       return "pixel_y";
423 
424    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
425       return "uniform_pull_const";
426    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
427       return "uniform_pull_const_gen7";
428    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
429       return "varying_pull_const_gen4";
430    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
431       return "varying_pull_const_logical";
432 
433    case FS_OPCODE_DISCARD_JUMP:
434       return "discard_jump";
435 
436    case FS_OPCODE_SET_SAMPLE_ID:
437       return "set_sample_id";
438 
439    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
440       return "pack_half_2x16_split";
441 
442    case FS_OPCODE_PLACEHOLDER_HALT:
443       return "placeholder_halt";
444 
445    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
446       return "interp_sample";
447    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
448       return "interp_shared_offset";
449    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
450       return "interp_per_slot_offset";
451 
452    case VS_OPCODE_URB_WRITE:
453       return "vs_urb_write";
454    case VS_OPCODE_PULL_CONSTANT_LOAD:
455       return "pull_constant_load";
456    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
457       return "pull_constant_load_gen7";
458 
459    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
460       return "set_simd4x2_header_gen9";
461 
462    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
463       return "unpack_flags_simd4x2";
464 
465    case GS_OPCODE_URB_WRITE:
466       return "gs_urb_write";
467    case GS_OPCODE_URB_WRITE_ALLOCATE:
468       return "gs_urb_write_allocate";
469    case GS_OPCODE_THREAD_END:
470       return "gs_thread_end";
471    case GS_OPCODE_SET_WRITE_OFFSET:
472       return "set_write_offset";
473    case GS_OPCODE_SET_VERTEX_COUNT:
474       return "set_vertex_count";
475    case GS_OPCODE_SET_DWORD_2:
476       return "set_dword_2";
477    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
478       return "prepare_channel_masks";
479    case GS_OPCODE_SET_CHANNEL_MASKS:
480       return "set_channel_masks";
481    case GS_OPCODE_GET_INSTANCE_ID:
482       return "get_instance_id";
483    case GS_OPCODE_FF_SYNC:
484       return "ff_sync";
485    case GS_OPCODE_SET_PRIMITIVE_ID:
486       return "set_primitive_id";
487    case GS_OPCODE_SVB_WRITE:
488       return "gs_svb_write";
489    case GS_OPCODE_SVB_SET_DST_INDEX:
490       return "gs_svb_set_dst_index";
491    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
492       return "gs_ff_sync_set_primitives";
493    case CS_OPCODE_CS_TERMINATE:
494       return "cs_terminate";
495    case SHADER_OPCODE_BARRIER:
496       return "barrier";
497    case SHADER_OPCODE_MULH:
498       return "mulh";
499    case SHADER_OPCODE_ISUB_SAT:
500       return "isub_sat";
501    case SHADER_OPCODE_USUB_SAT:
502       return "usub_sat";
503    case SHADER_OPCODE_MOV_INDIRECT:
504       return "mov_indirect";
505 
506    case VEC4_OPCODE_URB_READ:
507       return "urb_read";
508    case TCS_OPCODE_GET_INSTANCE_ID:
509       return "tcs_get_instance_id";
510    case TCS_OPCODE_URB_WRITE:
511       return "tcs_urb_write";
512    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
513       return "tcs_set_input_urb_offsets";
514    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
515       return "tcs_set_output_urb_offsets";
516    case TCS_OPCODE_GET_PRIMITIVE_ID:
517       return "tcs_get_primitive_id";
518    case TCS_OPCODE_CREATE_BARRIER_HEADER:
519       return "tcs_create_barrier_header";
520    case TCS_OPCODE_SRC0_010_IS_ZERO:
521       return "tcs_src0<0,1,0>_is_zero";
522    case TCS_OPCODE_RELEASE_INPUT:
523       return "tcs_release_input";
524    case TCS_OPCODE_THREAD_END:
525       return "tcs_thread_end";
526    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
527       return "tes_create_input_read_header";
528    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
529       return "tes_add_indirect_urb_offset";
530    case TES_OPCODE_GET_PRIMITIVE_ID:
531       return "tes_get_primitive_id";
532 
533    case SHADER_OPCODE_RND_MODE:
534       return "rnd_mode";
535    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
536       return "float_control_mode";
537    }
538 
539    unreachable("not reached");
540 }
541 
542 bool
brw_saturate_immediate(enum brw_reg_type type,struct brw_reg * reg)543 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
544 {
545    union {
546       unsigned ud;
547       int d;
548       float f;
549       double df;
550    } imm, sat_imm = { 0 };
551 
552    const unsigned size = type_sz(type);
553 
554    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
555     * irrelevant, so just check the size of the type and copy from/to an
556     * appropriately sized field.
557     */
558    if (size < 8)
559       imm.ud = reg->ud;
560    else
561       imm.df = reg->df;
562 
563    switch (type) {
564    case BRW_REGISTER_TYPE_UD:
565    case BRW_REGISTER_TYPE_D:
566    case BRW_REGISTER_TYPE_UW:
567    case BRW_REGISTER_TYPE_W:
568    case BRW_REGISTER_TYPE_UQ:
569    case BRW_REGISTER_TYPE_Q:
570       /* Nothing to do. */
571       return false;
572    case BRW_REGISTER_TYPE_F:
573       sat_imm.f = SATURATE(imm.f);
574       break;
575    case BRW_REGISTER_TYPE_DF:
576       sat_imm.df = SATURATE(imm.df);
577       break;
578    case BRW_REGISTER_TYPE_UB:
579    case BRW_REGISTER_TYPE_B:
580       unreachable("no UB/B immediates");
581    case BRW_REGISTER_TYPE_V:
582    case BRW_REGISTER_TYPE_UV:
583    case BRW_REGISTER_TYPE_VF:
584       unreachable("unimplemented: saturate vector immediate");
585    case BRW_REGISTER_TYPE_HF:
586       unreachable("unimplemented: saturate HF immediate");
587    case BRW_REGISTER_TYPE_NF:
588       unreachable("no NF immediates");
589    }
590 
591    if (size < 8) {
592       if (imm.ud != sat_imm.ud) {
593          reg->ud = sat_imm.ud;
594          return true;
595       }
596    } else {
597       if (imm.df != sat_imm.df) {
598          reg->df = sat_imm.df;
599          return true;
600       }
601    }
602    return false;
603 }
604 
605 bool
brw_negate_immediate(enum brw_reg_type type,struct brw_reg * reg)606 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
607 {
608    switch (type) {
609    case BRW_REGISTER_TYPE_D:
610    case BRW_REGISTER_TYPE_UD:
611       reg->d = -reg->d;
612       return true;
613    case BRW_REGISTER_TYPE_W:
614    case BRW_REGISTER_TYPE_UW: {
615       uint16_t value = -(int16_t)reg->ud;
616       reg->ud = value | (uint32_t)value << 16;
617       return true;
618    }
619    case BRW_REGISTER_TYPE_F:
620       reg->f = -reg->f;
621       return true;
622    case BRW_REGISTER_TYPE_VF:
623       reg->ud ^= 0x80808080;
624       return true;
625    case BRW_REGISTER_TYPE_DF:
626       reg->df = -reg->df;
627       return true;
628    case BRW_REGISTER_TYPE_UQ:
629    case BRW_REGISTER_TYPE_Q:
630       reg->d64 = -reg->d64;
631       return true;
632    case BRW_REGISTER_TYPE_UB:
633    case BRW_REGISTER_TYPE_B:
634       unreachable("no UB/B immediates");
635    case BRW_REGISTER_TYPE_UV:
636    case BRW_REGISTER_TYPE_V:
637       assert(!"unimplemented: negate UV/V immediate");
638    case BRW_REGISTER_TYPE_HF:
639       reg->ud ^= 0x80008000;
640       return true;
641    case BRW_REGISTER_TYPE_NF:
642       unreachable("no NF immediates");
643    }
644 
645    return false;
646 }
647 
648 bool
brw_abs_immediate(enum brw_reg_type type,struct brw_reg * reg)649 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
650 {
651    switch (type) {
652    case BRW_REGISTER_TYPE_D:
653       reg->d = abs(reg->d);
654       return true;
655    case BRW_REGISTER_TYPE_W: {
656       uint16_t value = abs((int16_t)reg->ud);
657       reg->ud = value | (uint32_t)value << 16;
658       return true;
659    }
660    case BRW_REGISTER_TYPE_F:
661       reg->f = fabsf(reg->f);
662       return true;
663    case BRW_REGISTER_TYPE_DF:
664       reg->df = fabs(reg->df);
665       return true;
666    case BRW_REGISTER_TYPE_VF:
667       reg->ud &= ~0x80808080;
668       return true;
669    case BRW_REGISTER_TYPE_Q:
670       reg->d64 = imaxabs(reg->d64);
671       return true;
672    case BRW_REGISTER_TYPE_UB:
673    case BRW_REGISTER_TYPE_B:
674       unreachable("no UB/B immediates");
675    case BRW_REGISTER_TYPE_UQ:
676    case BRW_REGISTER_TYPE_UD:
677    case BRW_REGISTER_TYPE_UW:
678    case BRW_REGISTER_TYPE_UV:
679       /* Presumably the absolute value modifier on an unsigned source is a
680        * nop, but it would be nice to confirm.
681        */
682       assert(!"unimplemented: abs unsigned immediate");
683    case BRW_REGISTER_TYPE_V:
684       assert(!"unimplemented: abs V immediate");
685    case BRW_REGISTER_TYPE_HF:
686       reg->ud &= ~0x80008000;
687       return true;
688    case BRW_REGISTER_TYPE_NF:
689       unreachable("no NF immediates");
690    }
691 
692    return false;
693 }
694 
backend_shader(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,const nir_shader * shader,struct brw_stage_prog_data * stage_prog_data)695 backend_shader::backend_shader(const struct brw_compiler *compiler,
696                                void *log_data,
697                                void *mem_ctx,
698                                const nir_shader *shader,
699                                struct brw_stage_prog_data *stage_prog_data)
700    : compiler(compiler),
701      log_data(log_data),
702      devinfo(compiler->devinfo),
703      nir(shader),
704      stage_prog_data(stage_prog_data),
705      mem_ctx(mem_ctx),
706      cfg(NULL), idom_analysis(this),
707      stage(shader->info.stage)
708 {
709    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
710    stage_name = _mesa_shader_stage_to_string(stage);
711    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
712 }
713 
~backend_shader()714 backend_shader::~backend_shader()
715 {
716 }
717 
718 bool
equals(const backend_reg & r) const719 backend_reg::equals(const backend_reg &r) const
720 {
721    return brw_regs_equal(this, &r) && offset == r.offset;
722 }
723 
724 bool
negative_equals(const backend_reg & r) const725 backend_reg::negative_equals(const backend_reg &r) const
726 {
727    return brw_regs_negative_equal(this, &r) && offset == r.offset;
728 }
729 
730 bool
is_zero() const731 backend_reg::is_zero() const
732 {
733    if (file != IMM)
734       return false;
735 
736    assert(type_sz(type) > 1);
737 
738    switch (type) {
739    case BRW_REGISTER_TYPE_HF:
740       assert((d & 0xffff) == ((d >> 16) & 0xffff));
741       return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
742    case BRW_REGISTER_TYPE_F:
743       return f == 0;
744    case BRW_REGISTER_TYPE_DF:
745       return df == 0;
746    case BRW_REGISTER_TYPE_W:
747    case BRW_REGISTER_TYPE_UW:
748       assert((d & 0xffff) == ((d >> 16) & 0xffff));
749       return (d & 0xffff) == 0;
750    case BRW_REGISTER_TYPE_D:
751    case BRW_REGISTER_TYPE_UD:
752       return d == 0;
753    case BRW_REGISTER_TYPE_UQ:
754    case BRW_REGISTER_TYPE_Q:
755       return u64 == 0;
756    default:
757       return false;
758    }
759 }
760 
761 bool
is_one() const762 backend_reg::is_one() const
763 {
764    if (file != IMM)
765       return false;
766 
767    assert(type_sz(type) > 1);
768 
769    switch (type) {
770    case BRW_REGISTER_TYPE_HF:
771       assert((d & 0xffff) == ((d >> 16) & 0xffff));
772       return (d & 0xffff) == 0x3c00;
773    case BRW_REGISTER_TYPE_F:
774       return f == 1.0f;
775    case BRW_REGISTER_TYPE_DF:
776       return df == 1.0;
777    case BRW_REGISTER_TYPE_W:
778    case BRW_REGISTER_TYPE_UW:
779       assert((d & 0xffff) == ((d >> 16) & 0xffff));
780       return (d & 0xffff) == 1;
781    case BRW_REGISTER_TYPE_D:
782    case BRW_REGISTER_TYPE_UD:
783       return d == 1;
784    case BRW_REGISTER_TYPE_UQ:
785    case BRW_REGISTER_TYPE_Q:
786       return u64 == 1;
787    default:
788       return false;
789    }
790 }
791 
792 bool
is_negative_one() const793 backend_reg::is_negative_one() const
794 {
795    if (file != IMM)
796       return false;
797 
798    assert(type_sz(type) > 1);
799 
800    switch (type) {
801    case BRW_REGISTER_TYPE_HF:
802       assert((d & 0xffff) == ((d >> 16) & 0xffff));
803       return (d & 0xffff) == 0xbc00;
804    case BRW_REGISTER_TYPE_F:
805       return f == -1.0;
806    case BRW_REGISTER_TYPE_DF:
807       return df == -1.0;
808    case BRW_REGISTER_TYPE_W:
809       assert((d & 0xffff) == ((d >> 16) & 0xffff));
810       return (d & 0xffff) == 0xffff;
811    case BRW_REGISTER_TYPE_D:
812       return d == -1;
813    case BRW_REGISTER_TYPE_Q:
814       return d64 == -1;
815    default:
816       return false;
817    }
818 }
819 
820 bool
is_null() const821 backend_reg::is_null() const
822 {
823    return file == ARF && nr == BRW_ARF_NULL;
824 }
825 
826 
827 bool
is_accumulator() const828 backend_reg::is_accumulator() const
829 {
830    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
831 }
832 
833 bool
is_commutative() const834 backend_instruction::is_commutative() const
835 {
836    switch (opcode) {
837    case BRW_OPCODE_AND:
838    case BRW_OPCODE_OR:
839    case BRW_OPCODE_XOR:
840    case BRW_OPCODE_ADD:
841    case BRW_OPCODE_MUL:
842    case SHADER_OPCODE_MULH:
843       return true;
844    case BRW_OPCODE_SEL:
845       /* MIN and MAX are commutative. */
846       if (conditional_mod == BRW_CONDITIONAL_GE ||
847           conditional_mod == BRW_CONDITIONAL_L) {
848          return true;
849       }
850       /* fallthrough */
851    default:
852       return false;
853    }
854 }
855 
856 bool
is_3src(const struct gen_device_info * devinfo) const857 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
858 {
859    return ::is_3src(devinfo, opcode);
860 }
861 
862 bool
is_tex() const863 backend_instruction::is_tex() const
864 {
865    return (opcode == SHADER_OPCODE_TEX ||
866            opcode == FS_OPCODE_TXB ||
867            opcode == SHADER_OPCODE_TXD ||
868            opcode == SHADER_OPCODE_TXF ||
869            opcode == SHADER_OPCODE_TXF_LZ ||
870            opcode == SHADER_OPCODE_TXF_CMS ||
871            opcode == SHADER_OPCODE_TXF_CMS_W ||
872            opcode == SHADER_OPCODE_TXF_UMS ||
873            opcode == SHADER_OPCODE_TXF_MCS ||
874            opcode == SHADER_OPCODE_TXL ||
875            opcode == SHADER_OPCODE_TXL_LZ ||
876            opcode == SHADER_OPCODE_TXS ||
877            opcode == SHADER_OPCODE_LOD ||
878            opcode == SHADER_OPCODE_TG4 ||
879            opcode == SHADER_OPCODE_TG4_OFFSET ||
880            opcode == SHADER_OPCODE_SAMPLEINFO);
881 }
882 
883 bool
is_math() const884 backend_instruction::is_math() const
885 {
886    return (opcode == SHADER_OPCODE_RCP ||
887            opcode == SHADER_OPCODE_RSQ ||
888            opcode == SHADER_OPCODE_SQRT ||
889            opcode == SHADER_OPCODE_EXP2 ||
890            opcode == SHADER_OPCODE_LOG2 ||
891            opcode == SHADER_OPCODE_SIN ||
892            opcode == SHADER_OPCODE_COS ||
893            opcode == SHADER_OPCODE_INT_QUOTIENT ||
894            opcode == SHADER_OPCODE_INT_REMAINDER ||
895            opcode == SHADER_OPCODE_POW);
896 }
897 
898 bool
is_control_flow() const899 backend_instruction::is_control_flow() const
900 {
901    switch (opcode) {
902    case BRW_OPCODE_DO:
903    case BRW_OPCODE_WHILE:
904    case BRW_OPCODE_IF:
905    case BRW_OPCODE_ELSE:
906    case BRW_OPCODE_ENDIF:
907    case BRW_OPCODE_BREAK:
908    case BRW_OPCODE_CONTINUE:
909       return true;
910    default:
911       return false;
912    }
913 }
914 
915 bool
can_do_source_mods() const916 backend_instruction::can_do_source_mods() const
917 {
918    switch (opcode) {
919    case BRW_OPCODE_ADDC:
920    case BRW_OPCODE_BFE:
921    case BRW_OPCODE_BFI1:
922    case BRW_OPCODE_BFI2:
923    case BRW_OPCODE_BFREV:
924    case BRW_OPCODE_CBIT:
925    case BRW_OPCODE_FBH:
926    case BRW_OPCODE_FBL:
927    case BRW_OPCODE_SUBB:
928    case SHADER_OPCODE_BROADCAST:
929    case SHADER_OPCODE_CLUSTER_BROADCAST:
930    case SHADER_OPCODE_MOV_INDIRECT:
931       return false;
932    default:
933       return true;
934    }
935 }
936 
937 bool
can_do_saturate() const938 backend_instruction::can_do_saturate() const
939 {
940    switch (opcode) {
941    case BRW_OPCODE_ADD:
942    case BRW_OPCODE_ASR:
943    case BRW_OPCODE_AVG:
944    case BRW_OPCODE_CSEL:
945    case BRW_OPCODE_DP2:
946    case BRW_OPCODE_DP3:
947    case BRW_OPCODE_DP4:
948    case BRW_OPCODE_DPH:
949    case BRW_OPCODE_F16TO32:
950    case BRW_OPCODE_F32TO16:
951    case BRW_OPCODE_LINE:
952    case BRW_OPCODE_LRP:
953    case BRW_OPCODE_MAC:
954    case BRW_OPCODE_MAD:
955    case BRW_OPCODE_MATH:
956    case BRW_OPCODE_MOV:
957    case BRW_OPCODE_MUL:
958    case SHADER_OPCODE_MULH:
959    case BRW_OPCODE_PLN:
960    case BRW_OPCODE_RNDD:
961    case BRW_OPCODE_RNDE:
962    case BRW_OPCODE_RNDU:
963    case BRW_OPCODE_RNDZ:
964    case BRW_OPCODE_SEL:
965    case BRW_OPCODE_SHL:
966    case BRW_OPCODE_SHR:
967    case FS_OPCODE_LINTERP:
968    case SHADER_OPCODE_COS:
969    case SHADER_OPCODE_EXP2:
970    case SHADER_OPCODE_LOG2:
971    case SHADER_OPCODE_POW:
972    case SHADER_OPCODE_RCP:
973    case SHADER_OPCODE_RSQ:
974    case SHADER_OPCODE_SIN:
975    case SHADER_OPCODE_SQRT:
976       return true;
977    default:
978       return false;
979    }
980 }
981 
982 bool
can_do_cmod() const983 backend_instruction::can_do_cmod() const
984 {
985    switch (opcode) {
986    case BRW_OPCODE_ADD:
987    case BRW_OPCODE_ADDC:
988    case BRW_OPCODE_AND:
989    case BRW_OPCODE_ASR:
990    case BRW_OPCODE_AVG:
991    case BRW_OPCODE_CMP:
992    case BRW_OPCODE_CMPN:
993    case BRW_OPCODE_DP2:
994    case BRW_OPCODE_DP3:
995    case BRW_OPCODE_DP4:
996    case BRW_OPCODE_DPH:
997    case BRW_OPCODE_F16TO32:
998    case BRW_OPCODE_F32TO16:
999    case BRW_OPCODE_FRC:
1000    case BRW_OPCODE_LINE:
1001    case BRW_OPCODE_LRP:
1002    case BRW_OPCODE_LZD:
1003    case BRW_OPCODE_MAC:
1004    case BRW_OPCODE_MACH:
1005    case BRW_OPCODE_MAD:
1006    case BRW_OPCODE_MOV:
1007    case BRW_OPCODE_MUL:
1008    case BRW_OPCODE_NOT:
1009    case BRW_OPCODE_OR:
1010    case BRW_OPCODE_PLN:
1011    case BRW_OPCODE_RNDD:
1012    case BRW_OPCODE_RNDE:
1013    case BRW_OPCODE_RNDU:
1014    case BRW_OPCODE_RNDZ:
1015    case BRW_OPCODE_SAD2:
1016    case BRW_OPCODE_SADA2:
1017    case BRW_OPCODE_SHL:
1018    case BRW_OPCODE_SHR:
1019    case BRW_OPCODE_SUBB:
1020    case BRW_OPCODE_XOR:
1021    case FS_OPCODE_LINTERP:
1022       return true;
1023    default:
1024       return false;
1025    }
1026 }
1027 
1028 bool
reads_accumulator_implicitly() const1029 backend_instruction::reads_accumulator_implicitly() const
1030 {
1031    switch (opcode) {
1032    case BRW_OPCODE_MAC:
1033    case BRW_OPCODE_MACH:
1034    case BRW_OPCODE_SADA2:
1035       return true;
1036    default:
1037       return false;
1038    }
1039 }
1040 
1041 bool
writes_accumulator_implicitly(const struct gen_device_info * devinfo) const1042 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1043 {
1044    return writes_accumulator ||
1045           (devinfo->gen < 6 &&
1046            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1047             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1048           (opcode == FS_OPCODE_LINTERP &&
1049            (!devinfo->has_pln || devinfo->gen <= 6));
1050 }
1051 
1052 bool
has_side_effects() const1053 backend_instruction::has_side_effects() const
1054 {
1055    switch (opcode) {
1056    case SHADER_OPCODE_SEND:
1057       return send_has_side_effects;
1058 
1059    case BRW_OPCODE_SYNC:
1060    case VEC4_OPCODE_UNTYPED_ATOMIC:
1061    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1062    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1063    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1064    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1065    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1066    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1067    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1068    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1069    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1070    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1071    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1072    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
1073    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1074    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1075    case SHADER_OPCODE_MEMORY_FENCE:
1076    case SHADER_OPCODE_INTERLOCK:
1077    case SHADER_OPCODE_URB_WRITE_SIMD8:
1078    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1079    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1080    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1081    case FS_OPCODE_FB_WRITE:
1082    case FS_OPCODE_FB_WRITE_LOGICAL:
1083    case FS_OPCODE_REP_FB_WRITE:
1084    case SHADER_OPCODE_BARRIER:
1085    case TCS_OPCODE_URB_WRITE:
1086    case TCS_OPCODE_RELEASE_INPUT:
1087    case SHADER_OPCODE_RND_MODE:
1088    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1089    case FS_OPCODE_SCHEDULING_FENCE:
1090       return true;
1091    default:
1092       return eot;
1093    }
1094 }
1095 
1096 bool
is_volatile() const1097 backend_instruction::is_volatile() const
1098 {
1099    switch (opcode) {
1100    case SHADER_OPCODE_SEND:
1101       return send_is_volatile;
1102 
1103    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1104    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1105    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1106    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1107    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
1108    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1109    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1110    case SHADER_OPCODE_URB_READ_SIMD8:
1111    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1112    case VEC4_OPCODE_URB_READ:
1113       return true;
1114    default:
1115       return false;
1116    }
1117 }
1118 
1119 #ifndef NDEBUG
1120 static bool
inst_is_in_block(const bblock_t * block,const backend_instruction * inst)1121 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1122 {
1123    bool found = false;
1124    foreach_inst_in_block (backend_instruction, i, block) {
1125       if (inst == i) {
1126          found = true;
1127       }
1128    }
1129    return found;
1130 }
1131 #endif
1132 
1133 static void
adjust_later_block_ips(bblock_t * start_block,int ip_adjustment)1134 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1135 {
1136    for (bblock_t *block_iter = start_block->next();
1137         block_iter;
1138         block_iter = block_iter->next()) {
1139       block_iter->start_ip += ip_adjustment;
1140       block_iter->end_ip += ip_adjustment;
1141    }
1142 }
1143 
1144 void
insert_after(bblock_t * block,backend_instruction * inst)1145 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1146 {
1147    assert(this != inst);
1148 
1149    if (!this->is_head_sentinel())
1150       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1151 
1152    block->end_ip++;
1153 
1154    adjust_later_block_ips(block, 1);
1155 
1156    exec_node::insert_after(inst);
1157 }
1158 
1159 void
insert_before(bblock_t * block,backend_instruction * inst)1160 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1161 {
1162    assert(this != inst);
1163 
1164    if (!this->is_tail_sentinel())
1165       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1166 
1167    block->end_ip++;
1168 
1169    adjust_later_block_ips(block, 1);
1170 
1171    exec_node::insert_before(inst);
1172 }
1173 
1174 void
insert_before(bblock_t * block,exec_list * list)1175 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1176 {
1177    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1178 
1179    unsigned num_inst = list->length();
1180 
1181    block->end_ip += num_inst;
1182 
1183    adjust_later_block_ips(block, num_inst);
1184 
1185    exec_node::insert_before(list);
1186 }
1187 
1188 void
remove(bblock_t * block)1189 backend_instruction::remove(bblock_t *block)
1190 {
1191    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1192 
1193    adjust_later_block_ips(block, -1);
1194 
1195    if (block->start_ip == block->end_ip) {
1196       block->cfg->remove_block(block);
1197    } else {
1198       block->end_ip--;
1199    }
1200 
1201    exec_node::remove();
1202 }
1203 
1204 void
dump_instructions() const1205 backend_shader::dump_instructions() const
1206 {
1207    dump_instructions(NULL);
1208 }
1209 
1210 void
dump_instructions(const char * name) const1211 backend_shader::dump_instructions(const char *name) const
1212 {
1213    FILE *file = stderr;
1214    if (name && geteuid() != 0) {
1215       file = fopen(name, "w");
1216       if (!file)
1217          file = stderr;
1218    }
1219 
1220    if (cfg) {
1221       int ip = 0;
1222       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1223          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1224             fprintf(file, "%4d: ", ip++);
1225          dump_instruction(inst, file);
1226       }
1227    } else {
1228       int ip = 0;
1229       foreach_in_list(backend_instruction, inst, &instructions) {
1230          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1231             fprintf(file, "%4d: ", ip++);
1232          dump_instruction(inst, file);
1233       }
1234    }
1235 
1236    if (file != stderr) {
1237       fclose(file);
1238    }
1239 }
1240 
1241 void
calculate_cfg()1242 backend_shader::calculate_cfg()
1243 {
1244    if (this->cfg)
1245       return;
1246    cfg = new(mem_ctx) cfg_t(this, &this->instructions);
1247 }
1248 
1249 void
invalidate_analysis(brw::analysis_dependency_class c)1250 backend_shader::invalidate_analysis(brw::analysis_dependency_class c)
1251 {
1252    idom_analysis.invalidate(c);
1253 }
1254 
1255 extern "C" const unsigned *
brw_compile_tes(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,const struct brw_tes_prog_key * key,const struct brw_vue_map * input_vue_map,struct brw_tes_prog_data * prog_data,nir_shader * nir,int shader_time_index,struct brw_compile_stats * stats,char ** error_str)1256 brw_compile_tes(const struct brw_compiler *compiler,
1257                 void *log_data,
1258                 void *mem_ctx,
1259                 const struct brw_tes_prog_key *key,
1260                 const struct brw_vue_map *input_vue_map,
1261                 struct brw_tes_prog_data *prog_data,
1262                 nir_shader *nir,
1263                 int shader_time_index,
1264                 struct brw_compile_stats *stats,
1265                 char **error_str)
1266 {
1267    const struct gen_device_info *devinfo = compiler->devinfo;
1268    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1269    const unsigned *assembly;
1270 
1271    nir->info.inputs_read = key->inputs_read;
1272    nir->info.patch_inputs_read = key->patch_inputs_read;
1273 
1274    brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
1275    brw_nir_lower_tes_inputs(nir, input_vue_map);
1276    brw_nir_lower_vue_outputs(nir);
1277    brw_postprocess_nir(nir, compiler, is_scalar);
1278 
1279    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1280                        nir->info.outputs_written,
1281                        nir->info.separate_shader, 1);
1282 
1283    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1284 
1285    assert(output_size_bytes >= 1);
1286    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1287       if (error_str)
1288          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1289       return NULL;
1290    }
1291 
1292    prog_data->base.clip_distance_mask =
1293       ((1 << nir->info.clip_distance_array_size) - 1);
1294    prog_data->base.cull_distance_mask =
1295       ((1 << nir->info.cull_distance_array_size) - 1) <<
1296       nir->info.clip_distance_array_size;
1297 
1298    /* URB entry sizes are stored as a multiple of 64 bytes. */
1299    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1300 
1301    /* On Cannonlake software shall not program an allocation size that
1302     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1303     */
1304    if (devinfo->gen == 10 &&
1305        prog_data->base.urb_entry_size % 3 == 0)
1306       prog_data->base.urb_entry_size++;
1307 
1308    prog_data->base.urb_read_length = 0;
1309 
1310    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1311    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1312                  TESS_SPACING_FRACTIONAL_ODD - 1);
1313    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1314                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1315 
1316    prog_data->partitioning =
1317       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1318 
1319    switch (nir->info.tess.primitive_mode) {
1320    case GL_QUADS:
1321       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1322       break;
1323    case GL_TRIANGLES:
1324       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1325       break;
1326    case GL_ISOLINES:
1327       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1328       break;
1329    default:
1330       unreachable("invalid domain shader primitive mode");
1331    }
1332 
1333    if (nir->info.tess.point_mode) {
1334       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1335    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1336       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1337    } else {
1338       /* Hardware winding order is backwards from OpenGL */
1339       prog_data->output_topology =
1340          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1341                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1342    }
1343 
1344    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1345       fprintf(stderr, "TES Input ");
1346       brw_print_vue_map(stderr, input_vue_map);
1347       fprintf(stderr, "TES Output ");
1348       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1349    }
1350 
1351    if (is_scalar) {
1352       fs_visitor v(compiler, log_data, mem_ctx, &key->base,
1353                    &prog_data->base.base, nir, 8,
1354                    shader_time_index, input_vue_map);
1355       if (!v.run_tes()) {
1356          if (error_str)
1357             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1358          return NULL;
1359       }
1360 
1361       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1362       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1363 
1364       fs_generator g(compiler, log_data, mem_ctx,
1365                      &prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
1366       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1367          g.enable_debug(ralloc_asprintf(mem_ctx,
1368                                         "%s tessellation evaluation shader %s",
1369                                         nir->info.label ? nir->info.label
1370                                                         : "unnamed",
1371                                         nir->info.name));
1372       }
1373 
1374       g.generate_code(v.cfg, 8, v.shader_stats,
1375                       v.performance_analysis.require(), stats);
1376 
1377       assembly = g.get_assembly();
1378    } else {
1379       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1380 			      nir, mem_ctx, shader_time_index);
1381       if (!v.run()) {
1382 	 if (error_str)
1383 	    *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1384 	 return NULL;
1385       }
1386 
1387       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1388 	 v.dump_instructions();
1389 
1390       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1391                                             &prog_data->base, v.cfg,
1392                                             v.performance_analysis.require(),
1393                                             stats);
1394    }
1395 
1396    return assembly;
1397 }
1398