1 /*
2 * Copyright © 2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/format/u_format.h"
25 #include "v3d_context.h"
26 #include "broadcom/common/v3d_tiling.h"
27 #include "broadcom/common/v3d_macros.h"
28 #include "broadcom/cle/v3dx_pack.h"
29
30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 | \
31 PIPE_CLEAR_COLOR1 | \
32 PIPE_CLEAR_COLOR2 | \
33 PIPE_CLEAR_COLOR3) \
34
35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
36
37 /* The HW queues up the load until the tile coordinates show up, but can only
38 * track one at a time. If we need to do more than one load, then we need to
39 * flush out the previous load by emitting the tile coordinates and doing a
40 * dummy store.
41 */
42 static void
flush_last_load(struct v3d_cl * cl)43 flush_last_load(struct v3d_cl *cl)
44 {
45 if (V3D_VERSION >= 40)
46 return;
47
48 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
49 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
50 store.buffer_to_store = NONE;
51 }
52 }
53
54 static void
load_general(struct v3d_cl * cl,struct pipe_surface * psurf,int buffer,int layer,uint32_t pipe_bit,uint32_t * loads_pending)55 load_general(struct v3d_cl *cl, struct pipe_surface *psurf, int buffer,
56 int layer, uint32_t pipe_bit, uint32_t *loads_pending)
57 {
58 struct v3d_surface *surf = v3d_surface(psurf);
59 bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
60 if (separate_stencil) {
61 psurf = surf->separate_stencil;
62 surf = v3d_surface(psurf);
63 }
64
65 struct v3d_resource *rsc = v3d_resource(psurf->texture);
66
67 uint32_t layer_offset =
68 v3d_layer_offset(&rsc->base, psurf->u.tex.level,
69 psurf->u.tex.first_layer + layer);
70 cl_emit(cl, LOAD_TILE_BUFFER_GENERAL, load) {
71 load.buffer_to_load = buffer;
72 load.address = cl_address(rsc->bo, layer_offset);
73
74 #if V3D_VERSION >= 40
75 load.memory_format = surf->tiling;
76 if (separate_stencil)
77 load.input_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
78 else
79 load.input_image_format = surf->format;
80 load.r_b_swap = surf->swap_rb;
81 load.force_alpha_1 = util_format_has_alpha1(psurf->format);
82 if (surf->tiling == V3D_TILING_UIF_NO_XOR ||
83 surf->tiling == V3D_TILING_UIF_XOR) {
84 load.height_in_ub_or_stride =
85 surf->padded_height_of_output_image_in_uif_blocks;
86 } else if (surf->tiling == V3D_TILING_RASTER) {
87 struct v3d_resource_slice *slice =
88 &rsc->slices[psurf->u.tex.level];
89 load.height_in_ub_or_stride = slice->stride;
90 }
91
92 if (psurf->texture->nr_samples > 1)
93 load.decimate_mode = V3D_DECIMATE_MODE_ALL_SAMPLES;
94 else
95 load.decimate_mode = V3D_DECIMATE_MODE_SAMPLE_0;
96
97 #else /* V3D_VERSION < 40 */
98 /* Can't do raw ZSTENCIL loads -- need to load/store them to
99 * separate buffers for Z and stencil.
100 */
101 assert(buffer != ZSTENCIL);
102 load.raw_mode = true;
103 load.padded_height_of_output_image_in_uif_blocks =
104 surf->padded_height_of_output_image_in_uif_blocks;
105 #endif /* V3D_VERSION < 40 */
106 }
107
108 *loads_pending &= ~pipe_bit;
109 if (*loads_pending)
110 flush_last_load(cl);
111 }
112
113 static void
store_general(struct v3d_job * job,struct v3d_cl * cl,struct pipe_surface * psurf,int layer,int buffer,int pipe_bit,uint32_t * stores_pending,bool general_color_clear,bool resolve_4x)114 store_general(struct v3d_job *job,
115 struct v3d_cl *cl, struct pipe_surface *psurf,
116 int layer, int buffer, int pipe_bit,
117 uint32_t *stores_pending, bool general_color_clear,
118 bool resolve_4x)
119 {
120 struct v3d_surface *surf = v3d_surface(psurf);
121 bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
122 if (separate_stencil) {
123 psurf = surf->separate_stencil;
124 surf = v3d_surface(psurf);
125 }
126
127 *stores_pending &= ~pipe_bit;
128 bool last_store = !(*stores_pending);
129
130 struct v3d_resource *rsc = v3d_resource(psurf->texture);
131
132 rsc->writes++;
133
134 uint32_t layer_offset =
135 v3d_layer_offset(&rsc->base, psurf->u.tex.level,
136 psurf->u.tex.first_layer + layer);
137 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
138 store.buffer_to_store = buffer;
139 store.address = cl_address(rsc->bo, layer_offset);
140
141 #if V3D_VERSION >= 40
142 store.clear_buffer_being_stored = false;
143
144 if (separate_stencil)
145 store.output_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
146 else
147 store.output_image_format = surf->format;
148
149 store.r_b_swap = surf->swap_rb;
150 store.memory_format = surf->tiling;
151
152 if (surf->tiling == V3D_TILING_UIF_NO_XOR ||
153 surf->tiling == V3D_TILING_UIF_XOR) {
154 store.height_in_ub_or_stride =
155 surf->padded_height_of_output_image_in_uif_blocks;
156 } else if (surf->tiling == V3D_TILING_RASTER) {
157 struct v3d_resource_slice *slice =
158 &rsc->slices[psurf->u.tex.level];
159 store.height_in_ub_or_stride = slice->stride;
160 }
161
162 assert(!resolve_4x || job->bbuf);
163 if (psurf->texture->nr_samples > 1)
164 store.decimate_mode = V3D_DECIMATE_MODE_ALL_SAMPLES;
165 else if (resolve_4x && job->bbuf->texture->nr_samples > 1)
166 store.decimate_mode = V3D_DECIMATE_MODE_4X;
167 else
168 store.decimate_mode = V3D_DECIMATE_MODE_SAMPLE_0;
169
170 #else /* V3D_VERSION < 40 */
171 /* Can't do raw ZSTENCIL stores -- need to load/store them to
172 * separate buffers for Z and stencil.
173 */
174 assert(buffer != ZSTENCIL);
175 store.raw_mode = true;
176 if (!last_store) {
177 store.disable_color_buffers_clear_on_write = true;
178 store.disable_z_buffer_clear_on_write = true;
179 store.disable_stencil_buffer_clear_on_write = true;
180 } else {
181 store.disable_color_buffers_clear_on_write =
182 !(((pipe_bit & PIPE_CLEAR_COLOR_BUFFERS) &&
183 general_color_clear &&
184 (job->clear & pipe_bit)));
185 store.disable_z_buffer_clear_on_write =
186 !(job->clear & PIPE_CLEAR_DEPTH);
187 store.disable_stencil_buffer_clear_on_write =
188 !(job->clear & PIPE_CLEAR_STENCIL);
189 }
190 store.padded_height_of_output_image_in_uif_blocks =
191 surf->padded_height_of_output_image_in_uif_blocks;
192 #endif /* V3D_VERSION < 40 */
193 }
194
195 /* There must be a TILE_COORDINATES_IMPLICIT between each store. */
196 if (V3D_VERSION < 40 && !last_store) {
197 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
198 }
199 }
200
201 static int
zs_buffer_from_pipe_bits(int pipe_clear_bits)202 zs_buffer_from_pipe_bits(int pipe_clear_bits)
203 {
204 switch (pipe_clear_bits & PIPE_CLEAR_DEPTHSTENCIL) {
205 case PIPE_CLEAR_DEPTHSTENCIL:
206 return ZSTENCIL;
207 case PIPE_CLEAR_DEPTH:
208 return Z;
209 case PIPE_CLEAR_STENCIL:
210 return STENCIL;
211 default:
212 return NONE;
213 }
214 }
215
216 static void
v3d_rcl_emit_loads(struct v3d_job * job,struct v3d_cl * cl,int layer)217 v3d_rcl_emit_loads(struct v3d_job *job, struct v3d_cl *cl, int layer)
218 {
219 /* When blitting, no color or zs buffer is loaded; instead the blit
220 * source buffer is loaded for the aspects that we are going to blit.
221 */
222 assert(!job->bbuf || job->load == 0);
223 assert(!job->bbuf || job->nr_cbufs <= 1);
224 assert(!job->bbuf || V3D_VERSION >= 40);
225
226 uint32_t loads_pending = job->bbuf ? job->store : job->load;
227
228 for (int i = 0; i < job->nr_cbufs; i++) {
229 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
230 if (!(loads_pending & bit))
231 continue;
232
233 struct pipe_surface *psurf = job->bbuf ? job->bbuf : job->cbufs[i];
234 assert(!job->bbuf || i == 0);
235
236 if (!psurf || (V3D_VERSION < 40 &&
237 psurf->texture->nr_samples <= 1)) {
238 continue;
239 }
240
241 load_general(cl, psurf, RENDER_TARGET_0 + i, layer,
242 bit, &loads_pending);
243 }
244
245 if ((loads_pending & PIPE_CLEAR_DEPTHSTENCIL) &&
246 (V3D_VERSION >= 40 ||
247 (job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
248 struct pipe_surface *src = job->bbuf ? job->bbuf : job->zsbuf;
249 struct v3d_resource *rsc = v3d_resource(src->texture);
250
251 if (rsc->separate_stencil &&
252 (loads_pending & PIPE_CLEAR_STENCIL)) {
253 load_general(cl, src,
254 STENCIL, layer,
255 PIPE_CLEAR_STENCIL,
256 &loads_pending);
257 }
258
259 if (loads_pending & PIPE_CLEAR_DEPTHSTENCIL) {
260 load_general(cl, src,
261 zs_buffer_from_pipe_bits(loads_pending),
262 layer,
263 loads_pending & PIPE_CLEAR_DEPTHSTENCIL,
264 &loads_pending);
265 }
266 }
267
268 #if V3D_VERSION < 40
269 /* The initial reload will be queued until we get the
270 * tile coordinates.
271 */
272 if (loads_pending) {
273 cl_emit(cl, RELOAD_TILE_COLOR_BUFFER, load) {
274 load.disable_color_buffer_load =
275 (~loads_pending &
276 PIPE_CLEAR_COLOR_BUFFERS) >>
277 PIPE_FIRST_COLOR_BUFFER_BIT;
278 load.enable_z_load =
279 loads_pending & PIPE_CLEAR_DEPTH;
280 load.enable_stencil_load =
281 loads_pending & PIPE_CLEAR_STENCIL;
282 }
283 }
284 #else /* V3D_VERSION >= 40 */
285 assert(!loads_pending);
286 cl_emit(cl, END_OF_LOADS, end);
287 #endif
288 }
289
290 static void
v3d_rcl_emit_stores(struct v3d_job * job,struct v3d_cl * cl,int layer)291 v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl, int layer)
292 {
293 #if V3D_VERSION < 40
294 UNUSED bool needs_color_clear = job->clear & PIPE_CLEAR_COLOR_BUFFERS;
295 UNUSED bool needs_z_clear = job->clear & PIPE_CLEAR_DEPTH;
296 UNUSED bool needs_s_clear = job->clear & PIPE_CLEAR_STENCIL;
297
298 /* For clearing color in a TLB general on V3D 3.3:
299 *
300 * - NONE buffer store clears all TLB color buffers.
301 * - color buffer store clears just the TLB color buffer being stored.
302 * - Z/S buffers store may not clear the TLB color buffer.
303 *
304 * And on V3D 4.1, we only have one flag for "clear the buffer being
305 * stored" in the general packet, and a separate packet to clear all
306 * color TLB buffers.
307 *
308 * As a result, we only bother flagging TLB color clears in a general
309 * packet when we don't have to emit a separate packet to clear all
310 * TLB color buffers.
311 */
312 bool general_color_clear = (needs_color_clear &&
313 (job->clear & PIPE_CLEAR_COLOR_BUFFERS) ==
314 (job->store & PIPE_CLEAR_COLOR_BUFFERS));
315 #else
316 bool general_color_clear = false;
317 #endif
318
319 uint32_t stores_pending = job->store;
320
321 /* For V3D 4.1, use general stores for all TLB stores.
322 *
323 * For V3D 3.3, we only use general stores to do raw stores for any
324 * MSAA surfaces. These output UIF tiled images where each 4x MSAA
325 * pixel is a 2x2 quad, and the format will be that of the
326 * internal_type/internal_bpp, rather than the format from GL's
327 * perspective. Non-MSAA surfaces will use
328 * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
329 */
330 assert(!job->bbuf || job->nr_cbufs <= 1);
331 for (int i = 0; i < job->nr_cbufs; i++) {
332 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
333 if (!(job->store & bit))
334 continue;
335
336 struct pipe_surface *psurf = job->cbufs[i];
337 if (!psurf ||
338 (V3D_VERSION < 40 && psurf->texture->nr_samples <= 1)) {
339 continue;
340 }
341
342 store_general(job, cl, psurf, layer, RENDER_TARGET_0 + i, bit,
343 &stores_pending, general_color_clear, job->bbuf);
344 }
345
346 if (job->store & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
347 !(V3D_VERSION < 40 && job->zsbuf->texture->nr_samples <= 1)) {
348 struct v3d_resource *rsc = v3d_resource(job->zsbuf->texture);
349 if (rsc->separate_stencil) {
350 if (job->store & PIPE_CLEAR_DEPTH) {
351 store_general(job, cl, job->zsbuf, layer,
352 Z, PIPE_CLEAR_DEPTH,
353 &stores_pending,
354 general_color_clear,
355 false);
356 }
357
358 if (job->store & PIPE_CLEAR_STENCIL) {
359 store_general(job, cl, job->zsbuf, layer,
360 STENCIL, PIPE_CLEAR_STENCIL,
361 &stores_pending,
362 general_color_clear,
363 false);
364 }
365 } else {
366 store_general(job, cl, job->zsbuf, layer,
367 zs_buffer_from_pipe_bits(job->store),
368 job->store & PIPE_CLEAR_DEPTHSTENCIL,
369 &stores_pending, general_color_clear,
370 false);
371 }
372 }
373
374 #if V3D_VERSION < 40
375 if (stores_pending) {
376 cl_emit(cl, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED, store) {
377
378 store.disable_color_buffer_write =
379 (~stores_pending >>
380 PIPE_FIRST_COLOR_BUFFER_BIT) & 0xf;
381 store.enable_z_write = stores_pending & PIPE_CLEAR_DEPTH;
382 store.enable_stencil_write = stores_pending & PIPE_CLEAR_STENCIL;
383
384 /* Note that when set this will clear all of the color
385 * buffers.
386 */
387 store.disable_color_buffers_clear_on_write =
388 !needs_color_clear;
389 store.disable_z_buffer_clear_on_write =
390 !needs_z_clear;
391 store.disable_stencil_buffer_clear_on_write =
392 !needs_s_clear;
393 };
394 } else if (needs_color_clear && !general_color_clear) {
395 /* If we didn't do our color clears in the general packet,
396 * then emit a packet to clear all the TLB color buffers now.
397 */
398 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
399 store.buffer_to_store = NONE;
400 }
401 }
402 #else /* V3D_VERSION >= 40 */
403 /* If we're emitting an RCL with GL_ARB_framebuffer_no_attachments,
404 * we still need to emit some sort of store.
405 */
406 if (!job->store) {
407 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
408 store.buffer_to_store = NONE;
409 }
410 }
411
412 assert(!stores_pending);
413
414 /* GFXH-1461/GFXH-1689: The per-buffer store command's clear
415 * buffer bit is broken for depth/stencil. In addition, the
416 * clear packet's Z/S bit is broken, but the RTs bit ends up
417 * clearing Z/S.
418 */
419 if (job->clear) {
420 cl_emit(cl, CLEAR_TILE_BUFFERS, clear) {
421 clear.clear_z_stencil_buffer = true;
422 clear.clear_all_render_targets = true;
423 }
424 }
425 #endif /* V3D_VERSION >= 40 */
426 }
427
428 static void
v3d_rcl_emit_generic_per_tile_list(struct v3d_job * job,int layer)429 v3d_rcl_emit_generic_per_tile_list(struct v3d_job *job, int layer)
430 {
431 /* Emit the generic list in our indirect state -- the rcl will just
432 * have pointers into it.
433 */
434 struct v3d_cl *cl = &job->indirect;
435 v3d_cl_ensure_space(cl, 200, 1);
436 struct v3d_cl_reloc tile_list_start = cl_get_address(cl);
437
438 if (V3D_VERSION >= 40) {
439 /* V3D 4.x only requires a single tile coordinates, and
440 * END_OF_LOADS switches us between loading and rendering.
441 */
442 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
443 }
444
445 v3d_rcl_emit_loads(job, cl, layer);
446
447 if (V3D_VERSION < 40) {
448 /* Tile Coordinates triggers the last reload and sets where
449 * the stores go. There must be one per store packet.
450 */
451 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
452 }
453
454 /* The binner starts out writing tiles assuming that the initial mode
455 * is triangles, so make sure that's the case.
456 */
457 cl_emit(cl, PRIM_LIST_FORMAT, fmt) {
458 fmt.primitive_type = LIST_TRIANGLES;
459 }
460
461 #if V3D_VERSION >= 41
462 /* PTB assumes that value to be 0, but hw will not set it. */
463 cl_emit(cl, SET_INSTANCEID, set) {
464 set.instance_id = 0;
465 }
466 #endif
467
468 cl_emit(cl, BRANCH_TO_IMPLICIT_TILE_LIST, branch);
469
470 v3d_rcl_emit_stores(job, cl, layer);
471
472 #if V3D_VERSION >= 40
473 cl_emit(cl, END_OF_TILE_MARKER, end);
474 #endif
475
476 cl_emit(cl, RETURN_FROM_SUB_LIST, ret);
477
478 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) {
479 branch.start = tile_list_start;
480 branch.end = cl_get_address(cl);
481 }
482 }
483
484 #if V3D_VERSION >= 40
485 static void
v3d_setup_render_target(struct v3d_job * job,int cbuf,uint32_t * rt_bpp,uint32_t * rt_type,uint32_t * rt_clamp)486 v3d_setup_render_target(struct v3d_job *job, int cbuf,
487 uint32_t *rt_bpp, uint32_t *rt_type, uint32_t *rt_clamp)
488 {
489 if (!job->cbufs[cbuf])
490 return;
491
492 struct v3d_surface *surf = v3d_surface(job->cbufs[cbuf]);
493 *rt_bpp = surf->internal_bpp;
494 if (job->bbuf) {
495 struct v3d_surface *bsurf = v3d_surface(job->bbuf);
496 *rt_bpp = MAX2(*rt_bpp, bsurf->internal_bpp);
497 }
498 *rt_type = surf->internal_type;
499 *rt_clamp = V3D_RENDER_TARGET_CLAMP_NONE;
500 }
501
502 #else /* V3D_VERSION < 40 */
503
504 static void
v3d_emit_z_stencil_config(struct v3d_job * job,struct v3d_surface * surf,struct v3d_resource * rsc,bool is_separate_stencil)505 v3d_emit_z_stencil_config(struct v3d_job *job, struct v3d_surface *surf,
506 struct v3d_resource *rsc, bool is_separate_stencil)
507 {
508 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_Z_STENCIL, zs) {
509 zs.address = cl_address(rsc->bo, surf->offset);
510
511 if (!is_separate_stencil) {
512 zs.internal_type = surf->internal_type;
513 zs.output_image_format = surf->format;
514 } else {
515 zs.z_stencil_id = 1; /* Separate stencil */
516 }
517
518 zs.padded_height_of_output_image_in_uif_blocks =
519 surf->padded_height_of_output_image_in_uif_blocks;
520
521 assert(surf->tiling != V3D_TILING_RASTER);
522 zs.memory_format = surf->tiling;
523 }
524
525 if (job->store & (is_separate_stencil ?
526 PIPE_CLEAR_STENCIL :
527 PIPE_CLEAR_DEPTHSTENCIL)) {
528 rsc->writes++;
529 }
530 }
531 #endif /* V3D_VERSION < 40 */
532
533 #define div_round_up(a, b) (((a) + (b) - 1) / b)
534
535 static bool
supertile_in_job_scissors(struct v3d_job * job,uint32_t x,uint32_t y,uint32_t w,uint32_t h)536 supertile_in_job_scissors(struct v3d_job *job,
537 uint32_t x, uint32_t y, uint32_t w, uint32_t h)
538 {
539 if (job->scissor.disabled || job->scissor.count == 0)
540 return true;
541
542 const uint32_t min_x = x * w;
543 const uint32_t min_y = y * h;
544 const uint32_t max_x = min_x + w - 1;
545 const uint32_t max_y = min_y + h - 1;
546
547 for (uint32_t i = 0; i < job->scissor.count; i++) {
548 const uint32_t min_s_x = job->scissor.rects[i].min_x;
549 const uint32_t min_s_y = job->scissor.rects[i].min_y;
550 const uint32_t max_s_x = job->scissor.rects[i].max_x;
551 const uint32_t max_s_y = job->scissor.rects[i].max_y;
552
553 if (max_x < min_s_x || min_x > max_s_x ||
554 max_y < min_s_y || min_y > max_s_y) {
555 continue;
556 }
557
558 return true;
559 }
560
561 return false;
562 }
563
564 static void
emit_render_layer(struct v3d_job * job,uint32_t layer)565 emit_render_layer(struct v3d_job *job, uint32_t layer)
566 {
567 uint32_t supertile_w = 1, supertile_h = 1;
568
569 /* If doing multicore binning, we would need to initialize each
570 * core's tile list here.
571 */
572 uint32_t tile_alloc_offset =
573 layer * job->draw_tiles_x * job->draw_tiles_y * 64;
574 cl_emit(&job->rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) {
575 list.address = cl_address(job->tile_alloc, tile_alloc_offset);
576 }
577
578 cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) {
579 uint32_t frame_w_in_supertiles, frame_h_in_supertiles;
580 const uint32_t max_supertiles = 256;
581
582 /* Size up our supertiles until we get under the limit. */
583 for (;;) {
584 frame_w_in_supertiles = div_round_up(job->draw_tiles_x,
585 supertile_w);
586 frame_h_in_supertiles = div_round_up(job->draw_tiles_y,
587 supertile_h);
588 if (frame_w_in_supertiles *
589 frame_h_in_supertiles < max_supertiles) {
590 break;
591 }
592
593 if (supertile_w < supertile_h)
594 supertile_w++;
595 else
596 supertile_h++;
597 }
598
599 config.number_of_bin_tile_lists = 1;
600 config.total_frame_width_in_tiles = job->draw_tiles_x;
601 config.total_frame_height_in_tiles = job->draw_tiles_y;
602
603 config.supertile_width_in_tiles = supertile_w;
604 config.supertile_height_in_tiles = supertile_h;
605
606 config.total_frame_width_in_supertiles = frame_w_in_supertiles;
607 config.total_frame_height_in_supertiles = frame_h_in_supertiles;
608 }
609
610 /* Start by clearing the tile buffer. */
611 cl_emit(&job->rcl, TILE_COORDINATES, coords) {
612 coords.tile_column_number = 0;
613 coords.tile_row_number = 0;
614 }
615
616 /* Emit an initial clear of the tile buffers. This is necessary
617 * for any buffers that should be cleared (since clearing
618 * normally happens at the *end* of the generic tile list), but
619 * it's also nice to clear everything so the first tile doesn't
620 * inherit any contents from some previous frame.
621 *
622 * Also, implement the GFXH-1742 workaround. There's a race in
623 * the HW between the RCL updating the TLB's internal type/size
624 * and thespawning of the QPU instances using the TLB's current
625 * internal type/size. To make sure the QPUs get the right
626 * state, we need 1 dummy store in between internal type/size
627 * changes on V3D 3.x, and 2 dummy stores on 4.x.
628 */
629 #if V3D_VERSION < 40
630 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
631 store.buffer_to_store = NONE;
632 }
633 #else
634 for (int i = 0; i < 2; i++) {
635 if (i > 0)
636 cl_emit(&job->rcl, TILE_COORDINATES, coords);
637 cl_emit(&job->rcl, END_OF_LOADS, end);
638 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
639 store.buffer_to_store = NONE;
640 }
641 if (i == 0) {
642 cl_emit(&job->rcl, CLEAR_TILE_BUFFERS, clear) {
643 clear.clear_z_stencil_buffer = true;
644 clear.clear_all_render_targets = true;
645 }
646 }
647 cl_emit(&job->rcl, END_OF_TILE_MARKER, end);
648 }
649 #endif
650
651 cl_emit(&job->rcl, FLUSH_VCD_CACHE, flush);
652
653 v3d_rcl_emit_generic_per_tile_list(job, layer);
654
655 /* XXX perf: We should expose GL_MESA_tile_raster_order to
656 * improve X11 performance, but we should use Morton order
657 * otherwise to improve cache locality.
658 */
659 uint32_t supertile_w_in_pixels = job->tile_width * supertile_w;
660 uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
661 uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
662 uint32_t min_y_supertile = job->draw_min_y / supertile_h_in_pixels;
663
664 uint32_t max_x_supertile = 0;
665 uint32_t max_y_supertile = 0;
666 if (job->draw_max_x != 0 && job->draw_max_y != 0) {
667 max_x_supertile = (job->draw_max_x - 1) / supertile_w_in_pixels;
668 max_y_supertile = (job->draw_max_y - 1) / supertile_h_in_pixels;
669 }
670
671 for (int y = min_y_supertile; y <= max_y_supertile; y++) {
672 for (int x = min_x_supertile; x <= max_x_supertile; x++) {
673 if (supertile_in_job_scissors(job, x, y,
674 supertile_w_in_pixels,
675 supertile_h_in_pixels)) {
676 cl_emit(&job->rcl, SUPERTILE_COORDINATES, coords) {
677 coords.column_number_in_supertiles = x;
678 coords.row_number_in_supertiles = y;
679 }
680 }
681 }
682 }
683 }
684
685 void
v3dX(emit_rcl)686 v3dX(emit_rcl)(struct v3d_job *job)
687 {
688 /* The RCL list should be empty. */
689 assert(!job->rcl.bo);
690
691 v3d_cl_ensure_space_with_branch(&job->rcl, 200 +
692 MAX2(job->num_layers, 1) * 256 *
693 cl_packet_length(SUPERTILE_COORDINATES));
694 job->submit.rcl_start = job->rcl.bo->offset;
695 v3d_job_add_bo(job, job->rcl.bo);
696
697 /* Common config must be the first TILE_RENDERING_MODE_CFG
698 * and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
699 * optional updates to the previous HW state.
700 */
701 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COMMON, config) {
702 #if V3D_VERSION < 40
703 config.enable_z_store = job->store & PIPE_CLEAR_DEPTH;
704 config.enable_stencil_store = job->store & PIPE_CLEAR_STENCIL;
705 #else /* V3D_VERSION >= 40 */
706 if (job->zsbuf) {
707 struct v3d_surface *surf = v3d_surface(job->zsbuf);
708 config.internal_depth_type = surf->internal_type;
709 }
710 #endif /* V3D_VERSION >= 40 */
711
712 /* XXX: Early D/S clear */
713
714 switch (job->first_ez_state) {
715 case V3D_EZ_UNDECIDED:
716 case V3D_EZ_LT_LE:
717 config.early_z_disable = false;
718 config.early_z_test_and_update_direction =
719 EARLY_Z_DIRECTION_LT_LE;
720 break;
721 case V3D_EZ_GT_GE:
722 config.early_z_disable = false;
723 config.early_z_test_and_update_direction =
724 EARLY_Z_DIRECTION_GT_GE;
725 break;
726 case V3D_EZ_DISABLED:
727 config.early_z_disable = true;
728 }
729
730 config.image_width_pixels = job->draw_width;
731 config.image_height_pixels = job->draw_height;
732
733 config.number_of_render_targets = MAX2(job->nr_cbufs, 1);
734
735 config.multisample_mode_4x = job->msaa;
736
737 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
738 }
739
740 for (int i = 0; i < job->nr_cbufs; i++) {
741 struct pipe_surface *psurf = job->cbufs[i];
742 if (!psurf)
743 continue;
744 struct v3d_surface *surf = v3d_surface(psurf);
745 struct v3d_resource *rsc = v3d_resource(psurf->texture);
746
747 UNUSED uint32_t config_pad = 0;
748 uint32_t clear_pad = 0;
749
750 /* XXX: Set the pad for raster. */
751 if (surf->tiling == V3D_TILING_UIF_NO_XOR ||
752 surf->tiling == V3D_TILING_UIF_XOR) {
753 int uif_block_height = v3d_utile_height(rsc->cpp) * 2;
754 uint32_t implicit_padded_height = (align(job->draw_height, uif_block_height) /
755 uif_block_height);
756 if (surf->padded_height_of_output_image_in_uif_blocks -
757 implicit_padded_height < 15) {
758 config_pad = (surf->padded_height_of_output_image_in_uif_blocks -
759 implicit_padded_height);
760 } else {
761 config_pad = 15;
762 clear_pad = surf->padded_height_of_output_image_in_uif_blocks;
763 }
764 }
765
766 #if V3D_VERSION < 40
767 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
768 rt.address = cl_address(rsc->bo, surf->offset);
769 rt.internal_type = surf->internal_type;
770 rt.output_image_format = surf->format;
771 rt.memory_format = surf->tiling;
772 rt.internal_bpp = surf->internal_bpp;
773 rt.render_target_number = i;
774 rt.pad = config_pad;
775
776 if (job->store & PIPE_CLEAR_COLOR0 << i)
777 rsc->writes++;
778 }
779 #endif /* V3D_VERSION < 40 */
780
781 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1,
782 clear) {
783 clear.clear_color_low_32_bits = job->clear_color[i][0];
784 clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
785 clear.render_target_number = i;
786 };
787
788 if (surf->internal_bpp >= V3D_INTERNAL_BPP_64) {
789 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2,
790 clear) {
791 clear.clear_color_mid_low_32_bits =
792 ((job->clear_color[i][1] >> 24) |
793 (job->clear_color[i][2] << 8));
794 clear.clear_color_mid_high_24_bits =
795 ((job->clear_color[i][2] >> 24) |
796 ((job->clear_color[i][3] & 0xffff) << 8));
797 clear.render_target_number = i;
798 };
799 }
800
801 if (surf->internal_bpp >= V3D_INTERNAL_BPP_128 || clear_pad) {
802 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3,
803 clear) {
804 clear.uif_padded_height_in_uif_blocks = clear_pad;
805 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
806 clear.render_target_number = i;
807 };
808 }
809 }
810
811 #if V3D_VERSION >= 40
812 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
813 v3d_setup_render_target(job, 0,
814 &rt.render_target_0_internal_bpp,
815 &rt.render_target_0_internal_type,
816 &rt.render_target_0_clamp);
817 v3d_setup_render_target(job, 1,
818 &rt.render_target_1_internal_bpp,
819 &rt.render_target_1_internal_type,
820 &rt.render_target_1_clamp);
821 v3d_setup_render_target(job, 2,
822 &rt.render_target_2_internal_bpp,
823 &rt.render_target_2_internal_type,
824 &rt.render_target_2_clamp);
825 v3d_setup_render_target(job, 3,
826 &rt.render_target_3_internal_bpp,
827 &rt.render_target_3_internal_type,
828 &rt.render_target_3_clamp);
829 }
830 #endif
831
832 #if V3D_VERSION < 40
833 /* TODO: Don't bother emitting if we don't load/clear Z/S. */
834 if (job->zsbuf) {
835 struct pipe_surface *psurf = job->zsbuf;
836 struct v3d_surface *surf = v3d_surface(psurf);
837 struct v3d_resource *rsc = v3d_resource(psurf->texture);
838
839 v3d_emit_z_stencil_config(job, surf, rsc, false);
840
841 /* Emit the separate stencil packet if we have a resource for
842 * it. The HW will only load/store this buffer if the
843 * Z/Stencil config doesn't have stencil in its format.
844 */
845 if (surf->separate_stencil) {
846 v3d_emit_z_stencil_config(job,
847 v3d_surface(surf->separate_stencil),
848 rsc->separate_stencil, true);
849 }
850 }
851 #endif /* V3D_VERSION < 40 */
852
853 /* Ends rendering mode config. */
854 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES,
855 clear) {
856 clear.z_clear_value = job->clear_z;
857 clear.stencil_clear_value = job->clear_s;
858 };
859
860 /* Always set initial block size before the first branch, which needs
861 * to match the value from binning mode config.
862 */
863 cl_emit(&job->rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) {
864 init.use_auto_chained_tile_lists = true;
865 init.size_of_first_block_in_chained_tile_lists =
866 TILE_ALLOCATION_BLOCK_SIZE_64B;
867 }
868
869 /* ARB_framebuffer_no_attachments allows rendering to happen even when
870 * the framebuffer has no attachments, the idea being that fragment
871 * shaders can still do image load/store, ssbo, etc without having to
872 * write to actual attachments, so always run at least one iteration
873 * of the loop.
874 */
875 assert(job->num_layers > 0 || (job->load == 0 && job->store == 0));
876 for (int layer = 0; layer < MAX2(1, job->num_layers); layer++)
877 emit_render_layer(job, layer);
878
879 cl_emit(&job->rcl, END_OF_RENDERING, end);
880 }
881