1 /*
2  * Copyright 2014, 2015 Red Hat.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * on the rights to use, copy, modify, merge, publish, distribute, sub
8  * license, and/or sell copies of the Software, and to permit persons to whom
9  * the Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #include "util/u_memory.h"
24 #include "util/format/u_format.h"
25 #include "util/format/u_format_s3tc.h"
26 #include "util/u_screen.h"
27 #include "util/u_video.h"
28 #include "util/u_math.h"
29 #include "util/u_inlines.h"
30 #include "util/os_time.h"
31 #include "util/xmlconfig.h"
32 #include "pipe/p_defines.h"
33 #include "pipe/p_screen.h"
34 #include "nir/nir_to_tgsi.h"
35 
36 #include "tgsi/tgsi_exec.h"
37 
38 #include "virgl_screen.h"
39 #include "virgl_resource.h"
40 #include "virgl_public.h"
41 #include "virgl_context.h"
42 #include "virtio-gpu/virgl_protocol.h"
43 #include "virgl_encode.h"
44 
45 int virgl_debug = 0;
46 static const struct debug_named_value virgl_debug_options[] = {
47    { "verbose",   VIRGL_DEBUG_VERBOSE,             NULL },
48    { "tgsi",      VIRGL_DEBUG_TGSI,                NULL },
49    { "nir",       VIRGL_DEBUG_NIR,                 NULL },
50    { "noemubgra", VIRGL_DEBUG_NO_EMULATE_BGRA,     "Disable tweak to emulate BGRA as RGBA on GLES hosts"},
51    { "nobgraswz", VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,"Disable tweak to swizzle emulated BGRA on GLES hosts" },
52    { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
53    { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
54    { "nocoherent", VIRGL_DEBUG_NO_COHERENT,        "Disable coherent memory"},
55    DEBUG_NAMED_VALUE_END
56 };
57 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", virgl_debug_options, 0)
58 
59 static const char *
virgl_get_vendor(struct pipe_screen * screen)60 virgl_get_vendor(struct pipe_screen *screen)
61 {
62    return "Mesa/X.org";
63 }
64 
65 
66 static const char *
virgl_get_name(struct pipe_screen * screen)67 virgl_get_name(struct pipe_screen *screen)
68 {
69    struct virgl_screen *vscreen = virgl_screen(screen);
70    if (vscreen->caps.caps.v2.host_feature_check_version >= 5)
71       return vscreen->caps.caps.v2.renderer;
72 
73    return "virgl";
74 }
75 
76 static int
virgl_get_param(struct pipe_screen * screen,enum pipe_cap param)77 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
78 {
79    struct virgl_screen *vscreen = virgl_screen(screen);
80    switch (param) {
81    case PIPE_CAP_NPOT_TEXTURES:
82       return 1;
83    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
84    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
85    case PIPE_CAP_VERTEX_SHADER_SATURATE:
86       return 1;
87    case PIPE_CAP_ANISOTROPIC_FILTER:
88       return vscreen->caps.caps.v2.max_anisotropy > 1.0;
89    case PIPE_CAP_POINT_SPRITE:
90       return 1;
91    case PIPE_CAP_MAX_RENDER_TARGETS:
92       return vscreen->caps.caps.v1.max_render_targets;
93    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
94       return vscreen->caps.caps.v1.max_dual_source_render_targets;
95    case PIPE_CAP_OCCLUSION_QUERY:
96       return vscreen->caps.caps.v1.bset.occlusion_query;
97    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
98    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
99       return vscreen->caps.caps.v1.bset.mirror_clamp;
100    case PIPE_CAP_TEXTURE_SWIZZLE:
101       return 1;
102    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
103       if (vscreen->caps.caps.v2.max_texture_2d_size)
104          return vscreen->caps.caps.v2.max_texture_2d_size;
105       return 16384;
106    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
107       if (vscreen->caps.caps.v2.max_texture_3d_size)
108          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
109       return 9; /* 256 x 256 x 256 */
110    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
111       if (vscreen->caps.caps.v2.max_texture_cube_size)
112          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
113       return 13; /* 4K x 4K */
114    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
115       return 1;
116    case PIPE_CAP_INDEP_BLEND_ENABLE:
117       return vscreen->caps.caps.v1.bset.indep_blend_enable;
118    case PIPE_CAP_INDEP_BLEND_FUNC:
119       return vscreen->caps.caps.v1.bset.indep_blend_func;
120    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
121    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
122    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
123       return 1;
124    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
125       return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
126    case PIPE_CAP_DEPTH_CLIP_DISABLE:
127       if (vscreen->caps.caps.v1.bset.depth_clip_disable)
128          return 1;
129       if (vscreen->caps.caps.v2.host_feature_check_version >= 3)
130          return 2;
131       return 0;
132    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
133       return vscreen->caps.caps.v1.max_streamout_buffers;
134    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
135    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
136       return 16*4;
137    case PIPE_CAP_PRIMITIVE_RESTART:
138    case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
139       return vscreen->caps.caps.v1.bset.primitive_restart;
140    case PIPE_CAP_SHADER_STENCIL_EXPORT:
141       return vscreen->caps.caps.v1.bset.shader_stencil_export;
142    case PIPE_CAP_TGSI_INSTANCEID:
143    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
144       return 1;
145    case PIPE_CAP_SEAMLESS_CUBE_MAP:
146       return vscreen->caps.caps.v1.bset.seamless_cube_map;
147    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
148       return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
149    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
150       return vscreen->caps.caps.v1.max_texture_array_layers;
151    case PIPE_CAP_MIN_TEXEL_OFFSET:
152       return vscreen->caps.caps.v2.min_texel_offset;
153    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
154       return vscreen->caps.caps.v2.min_texture_gather_offset;
155    case PIPE_CAP_MAX_TEXEL_OFFSET:
156       return vscreen->caps.caps.v2.max_texel_offset;
157    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
158       return vscreen->caps.caps.v2.max_texture_gather_offset;
159    case PIPE_CAP_CONDITIONAL_RENDER:
160       return vscreen->caps.caps.v1.bset.conditional_render;
161    case PIPE_CAP_TEXTURE_BARRIER:
162       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
163    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
164       return 1;
165    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
166    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
167       return vscreen->caps.caps.v1.bset.color_clamping;
168    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
169       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
170             (vscreen->caps.caps.v2.host_feature_check_version < 1);
171    case PIPE_CAP_GLSL_FEATURE_LEVEL:
172       return vscreen->caps.caps.v1.glsl_level;
173    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
174       return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
176       return 1;
177    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
178       return 0;
179    case PIPE_CAP_COMPUTE:
180       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
181    case PIPE_CAP_USER_VERTEX_BUFFERS:
182       return 0;
183    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
184       return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
185    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
186    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
187       return vscreen->caps.caps.v1.bset.streamout_pause_resume;
188    case PIPE_CAP_START_INSTANCE:
189       return vscreen->caps.caps.v1.bset.start_instance;
190    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
191    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
192    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
193    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
194    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
195    case PIPE_CAP_NIR_IMAGES_AS_DEREF:
196       return 0;
197    case PIPE_CAP_QUERY_TIMESTAMP:
198       return 1;
199    case PIPE_CAP_QUERY_TIME_ELAPSED:
200       return 1;
201    case PIPE_CAP_TGSI_TEXCOORD:
202       return 0;
203    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
204       return VIRGL_MAP_BUFFER_ALIGNMENT;
205    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
206       return vscreen->caps.caps.v1.max_tbo_size > 0;
207    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
208       return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
209    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
210       return 0;
211    case PIPE_CAP_CUBE_MAP_ARRAY:
212       return vscreen->caps.caps.v1.bset.cube_map_array;
213    case PIPE_CAP_TEXTURE_MULTISAMPLE:
214       return vscreen->caps.caps.v1.bset.texture_multisample;
215    case PIPE_CAP_MAX_VIEWPORTS:
216       return vscreen->caps.caps.v1.max_viewports;
217    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
218       return vscreen->caps.caps.v1.max_tbo_size;
219    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
220    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
221    case PIPE_CAP_ENDIANNESS:
222       return 0;
223    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
224    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
225       return 1;
226    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
227       return 0;
228    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
229       return vscreen->caps.caps.v2.max_geom_output_vertices;
230    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
231       return vscreen->caps.caps.v2.max_geom_total_output_components;
232    case PIPE_CAP_TEXTURE_QUERY_LOD:
233       return vscreen->caps.caps.v1.bset.texture_query_lod;
234    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
235       return vscreen->caps.caps.v1.max_texture_gather_components;
236    case PIPE_CAP_DRAW_INDIRECT:
237       return vscreen->caps.caps.v1.bset.has_indirect_draw;
238    case PIPE_CAP_SAMPLE_SHADING:
239    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
240       return vscreen->caps.caps.v1.bset.has_sample_shading;
241    case PIPE_CAP_CULL_DISTANCE:
242       return vscreen->caps.caps.v1.bset.has_cull;
243    case PIPE_CAP_MAX_VERTEX_STREAMS:
244       return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
245               (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
246    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
247       return vscreen->caps.caps.v1.bset.conditional_render_inverted;
248    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
249       return vscreen->caps.caps.v1.bset.derivative_control;
250    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
251       return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
252    case PIPE_CAP_QUERY_SO_OVERFLOW:
253       return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
254    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
255       return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
256    case PIPE_CAP_DOUBLES:
257       return vscreen->caps.caps.v1.bset.has_fp64 ||
258             (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
259    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
260       return vscreen->caps.caps.v2.max_shader_patch_varyings;
261    case PIPE_CAP_SAMPLER_VIEW_TARGET:
262       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
263    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
264       return vscreen->caps.caps.v2.max_vertex_attrib_stride;
265    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
266       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
267    case PIPE_CAP_TGSI_TXQS:
268       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
269    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
270       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
271    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
272       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
273    case PIPE_CAP_FBFETCH:
274       return (vscreen->caps.caps.v2.capability_bits &
275               VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
276    case PIPE_CAP_BLEND_EQUATION_ADVANCED:
277       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_BLEND_EQUATION;
278    case PIPE_CAP_TGSI_CLOCK:
279       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
280    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
281       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
282    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
283       return vscreen->caps.caps.v2.max_combined_shader_buffers;
284    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
285       return vscreen->caps.caps.v2.max_combined_atomic_counters;
286    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
287       return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
288    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
289    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
290       return 1; /* TODO: need to introduce a hw-cap for this */
291    case PIPE_CAP_QUERY_BUFFER_OBJECT:
292       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
293    case PIPE_CAP_MAX_VARYINGS:
294       if (vscreen->caps.caps.v1.glsl_level < 150)
295          return vscreen->caps.caps.v2.max_vertex_attribs;
296       return 32;
297    case PIPE_CAP_FAKE_SW_MSAA:
298       /* If the host supports only one sample (e.g., if it is using softpipe),
299        * fake multisampling to able to advertise higher GL versions. */
300       return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
301    case PIPE_CAP_MULTI_DRAW_INDIRECT:
302       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
303    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
304       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
305    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
306       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ARB_BUFFER_STORAGE) &&
307              (vscreen->caps.caps.v2.host_feature_check_version >= 4) &&
308               vscreen->vws->supports_coherent && !vscreen->no_coherent;
309    case PIPE_CAP_PCI_GROUP:
310    case PIPE_CAP_PCI_BUS:
311    case PIPE_CAP_PCI_DEVICE:
312    case PIPE_CAP_PCI_FUNCTION:
313    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
314    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
315       return 0;
316    case PIPE_CAP_CLEAR_TEXTURE:
317       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLEAR_TEXTURE;
318    case PIPE_CAP_CLIP_HALFZ:
319       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
320    case PIPE_CAP_MAX_GS_INVOCATIONS:
321       return 32;
322    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
323       return 1 << 27;
324    case PIPE_CAP_VENDOR_ID:
325       return 0x1af4;
326    case PIPE_CAP_DEVICE_ID:
327       return 0x1010;
328    case PIPE_CAP_ACCELERATED:
329       return 1;
330    case PIPE_CAP_UMA:
331    case PIPE_CAP_VIDEO_MEMORY:
332       if (vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_VIDEO_MEMORY)
333          return vscreen->caps.caps.v2.max_video_memory;
334       return 0;
335    case PIPE_CAP_NATIVE_FENCE_FD:
336       return vscreen->vws->supports_fences;
337    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
338       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
339             (vscreen->caps.caps.v2.host_feature_check_version < 1);
340    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
341       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
342    case PIPE_CAP_SHAREABLE_SHADERS:
343       /* Shader creation emits the shader through the context's command buffer
344        * in virgl_encode_shader_state().
345        */
346       return 0;
347    case PIPE_CAP_QUERY_MEMORY_INFO:
348       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_MEMINFO;
349    case PIPE_CAP_STRING_MARKER:
350        return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_STRING_MARKER;
351    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
352        return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_IMPLICIT_MSAA;
353    default:
354       return u_pipe_screen_get_param_defaults(screen, param);
355    }
356 }
357 
358 static int
virgl_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)359 virgl_get_shader_param(struct pipe_screen *screen,
360                        enum pipe_shader_type shader,
361                        enum pipe_shader_cap param)
362 {
363    struct virgl_screen *vscreen = virgl_screen(screen);
364 
365    if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
366        !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
367       return 0;
368 
369    if (shader == PIPE_SHADER_COMPUTE &&
370        !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
371      return 0;
372 
373    switch(shader)
374    {
375    case PIPE_SHADER_FRAGMENT:
376    case PIPE_SHADER_VERTEX:
377    case PIPE_SHADER_GEOMETRY:
378    case PIPE_SHADER_TESS_CTRL:
379    case PIPE_SHADER_TESS_EVAL:
380    case PIPE_SHADER_COMPUTE:
381       switch (param) {
382       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
383       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
384       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
385       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
386          return INT_MAX;
387       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
388       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
389       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
390          return 1;
391       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
392       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
393          return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
394       case PIPE_SHADER_CAP_MAX_INPUTS:
395          if (vscreen->caps.caps.v1.glsl_level < 150)
396             return vscreen->caps.caps.v2.max_vertex_attribs;
397          return (shader == PIPE_SHADER_VERTEX ||
398                  shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
399       case PIPE_SHADER_CAP_MAX_OUTPUTS:
400          if (shader == PIPE_SHADER_FRAGMENT)
401             return vscreen->caps.caps.v1.max_render_targets;
402          return vscreen->caps.caps.v2.max_vertex_outputs;
403      // case PIPE_SHADER_CAP_MAX_CONSTS:
404      //    return 4096;
405       case PIPE_SHADER_CAP_MAX_TEMPS:
406          return 256;
407       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
408          return vscreen->caps.caps.v1.max_uniform_blocks;
409     //  case PIPE_SHADER_CAP_MAX_ADDRS:
410      //    return 1;
411       case PIPE_SHADER_CAP_SUBROUTINES:
412          return 1;
413       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
414             return 16;
415       case PIPE_SHADER_CAP_INTEGERS:
416          return vscreen->caps.caps.v1.glsl_level >= 130;
417       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
418          return 32;
419       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
420          return 4096 * sizeof(float[4]);
421       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
422          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
423             return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
424          else
425             return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
426       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
427          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
428             return vscreen->caps.caps.v2.max_shader_image_frag_compute;
429          else
430             return vscreen->caps.caps.v2.max_shader_image_other_stages;
431       case PIPE_SHADER_CAP_PREFERRED_IR:
432          return (virgl_debug & VIRGL_DEBUG_NIR) ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
433       case PIPE_SHADER_CAP_SUPPORTED_IRS:
434          return (1 << PIPE_SHADER_IR_TGSI) | ((virgl_debug & VIRGL_DEBUG_NIR) ? (1 << PIPE_SHADER_IR_NIR) : 0);
435       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
436          return vscreen->caps.caps.v2.max_atomic_counters[shader];
437       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
438          return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
439       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
440       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
441       case PIPE_SHADER_CAP_INT64_ATOMICS:
442       case PIPE_SHADER_CAP_FP16:
443       case PIPE_SHADER_CAP_FP16_DERIVATIVES:
444       case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
445       case PIPE_SHADER_CAP_INT16:
446       case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
447          return 0;
448       default:
449          return 0;
450       }
451    default:
452       return 0;
453    }
454 }
455 
456 static float
virgl_get_paramf(struct pipe_screen * screen,enum pipe_capf param)457 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
458 {
459    struct virgl_screen *vscreen = virgl_screen(screen);
460    switch (param) {
461    case PIPE_CAPF_MAX_LINE_WIDTH:
462       return vscreen->caps.caps.v2.max_aliased_line_width;
463    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
464       return vscreen->caps.caps.v2.max_smooth_line_width;
465    case PIPE_CAPF_MAX_POINT_WIDTH:
466       return vscreen->caps.caps.v2.max_aliased_point_size;
467    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
468       return vscreen->caps.caps.v2.max_smooth_point_size;
469    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
470       return vscreen->caps.caps.v2.max_anisotropy;
471    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
472       return vscreen->caps.caps.v2.max_texture_lod_bias;
473    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
474    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
475    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
476       return 0.0f;
477    }
478    /* should only get here on unhandled cases */
479    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
480    return 0.0;
481 }
482 
483 static int
virgl_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)484 virgl_get_compute_param(struct pipe_screen *screen,
485                         enum pipe_shader_ir ir_type,
486                         enum pipe_compute_cap param,
487                         void *ret)
488 {
489    struct virgl_screen *vscreen = virgl_screen(screen);
490    if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
491       return 0;
492    switch (param) {
493    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
494       if (ret) {
495          uint64_t *grid_size = ret;
496          grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
497          grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
498          grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
499       }
500       return 3 * sizeof(uint64_t) ;
501    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
502       if (ret) {
503          uint64_t *block_size = ret;
504          block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
505          block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
506          block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
507       }
508       return 3 * sizeof(uint64_t);
509    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
510       if (ret) {
511          uint64_t *max_threads_per_block = ret;
512          *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
513       }
514       return sizeof(uint64_t);
515    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
516       if (ret) {
517          uint64_t *max_local_size = ret;
518          /* Value reported by the closed source driver. */
519          *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
520       }
521       return sizeof(uint64_t);
522    default:
523       break;
524    }
525    return 0;
526 }
527 
528 static bool
has_format_bit(struct virgl_supported_format_mask * mask,enum virgl_formats fmt)529 has_format_bit(struct virgl_supported_format_mask *mask,
530                enum virgl_formats fmt)
531 {
532    assert(fmt < VIRGL_FORMAT_MAX);
533    unsigned val = (unsigned)fmt;
534    unsigned idx = val / 32;
535    unsigned bit = val % 32;
536    assert(idx < ARRAY_SIZE(mask->bitmask));
537    return (mask->bitmask[idx] & (1u << bit)) != 0;
538 }
539 
540 bool
virgl_has_readback_format(struct pipe_screen * screen,enum virgl_formats fmt)541 virgl_has_readback_format(struct pipe_screen *screen,
542                           enum virgl_formats fmt)
543 {
544    struct virgl_screen *vscreen = virgl_screen(screen);
545    return has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
546                          fmt);
547 }
548 
549 static bool
virgl_is_vertex_format_supported(struct pipe_screen * screen,enum pipe_format format)550 virgl_is_vertex_format_supported(struct pipe_screen *screen,
551                                  enum pipe_format format)
552 {
553    struct virgl_screen *vscreen = virgl_screen(screen);
554    const struct util_format_description *format_desc;
555    int i;
556 
557    format_desc = util_format_description(format);
558    if (!format_desc)
559       return false;
560 
561    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
562       int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
563       int big = vformat / 32;
564       int small = vformat % 32;
565       if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
566          return false;
567       return true;
568    }
569 
570    /* Find the first non-VOID channel. */
571    for (i = 0; i < 4; i++) {
572       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
573          break;
574       }
575    }
576 
577    if (i == 4)
578       return false;
579 
580    if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
581       return false;
582 
583    if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
584       return false;
585    return true;
586 }
587 
588 static bool
virgl_format_check_bitmask(enum pipe_format format,uint32_t bitmask[16],bool may_emulate_bgra)589 virgl_format_check_bitmask(enum pipe_format format,
590                            uint32_t bitmask[16],
591                            bool may_emulate_bgra)
592 {
593    enum virgl_formats vformat = pipe_to_virgl_format(format);
594    int big = vformat / 32;
595    int small = vformat % 32;
596    if ((bitmask[big] & (1 << small)))
597       return true;
598 
599    /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
600     * emulate it by using a swizzled RGBx */
601    if (may_emulate_bgra) {
602       if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
603          format = PIPE_FORMAT_R8G8B8A8_SRGB;
604       else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
605          format = PIPE_FORMAT_R8G8B8X8_SRGB;
606       else {
607          return false;
608       }
609 
610       vformat = pipe_to_virgl_format(format);
611       big = vformat / 32;
612       small = vformat % 32;
613       if (bitmask[big] & (1 << small))
614          return true;
615    }
616    return false;
617 }
618 
619 /**
620  * Query format support for creating a texture, drawing surface, etc.
621  * \param format  the format to test
622  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
623  */
624 static bool
virgl_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bind)625 virgl_is_format_supported( struct pipe_screen *screen,
626                                  enum pipe_format format,
627                                  enum pipe_texture_target target,
628                                  unsigned sample_count,
629                                  unsigned storage_sample_count,
630                                  unsigned bind)
631 {
632    struct virgl_screen *vscreen = virgl_screen(screen);
633    const struct util_format_description *format_desc;
634    int i;
635 
636    union virgl_caps *caps = &vscreen->caps.caps;
637    boolean may_emulate_bgra = (caps->v2.capability_bits &
638                                VIRGL_CAP_APP_TWEAK_SUPPORT) &&
639                                vscreen->tweak_gles_emulate_bgra;
640 
641    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
642       return false;
643 
644    if (!util_is_power_of_two_or_zero(sample_count))
645       return false;
646 
647    assert(target == PIPE_BUFFER ||
648           target == PIPE_TEXTURE_1D ||
649           target == PIPE_TEXTURE_1D_ARRAY ||
650           target == PIPE_TEXTURE_2D ||
651           target == PIPE_TEXTURE_2D_ARRAY ||
652           target == PIPE_TEXTURE_RECT ||
653           target == PIPE_TEXTURE_3D ||
654           target == PIPE_TEXTURE_CUBE ||
655           target == PIPE_TEXTURE_CUBE_ARRAY);
656 
657    format_desc = util_format_description(format);
658    if (!format_desc)
659       return false;
660 
661    if (util_format_is_intensity(format))
662       return false;
663 
664    if (sample_count > 1) {
665       if (!caps->v1.bset.texture_multisample)
666          return false;
667 
668       if (bind & PIPE_BIND_SHADER_IMAGE) {
669          if (sample_count > caps->v2.max_image_samples)
670             return false;
671       }
672 
673       if (sample_count > caps->v1.max_samples)
674          return false;
675    }
676 
677    if (bind & PIPE_BIND_VERTEX_BUFFER) {
678       return virgl_is_vertex_format_supported(screen, format);
679    }
680 
681    if (util_format_is_compressed(format) && target == PIPE_BUFFER)
682       return false;
683 
684    /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
685    if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
686        format == PIPE_FORMAT_R32G32B32_SINT ||
687        format == PIPE_FORMAT_R32G32B32_UINT) &&
688        target != PIPE_BUFFER)
689       return false;
690 
691    if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
692         format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
693         format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
694        target == PIPE_TEXTURE_3D)
695       return false;
696 
697 
698    if (bind & PIPE_BIND_RENDER_TARGET) {
699       /* For ARB_framebuffer_no_attachments. */
700       if (format == PIPE_FORMAT_NONE)
701          return TRUE;
702 
703       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
704          return false;
705 
706       /*
707        * Although possible, it is unnatural to render into compressed or YUV
708        * surfaces. So disable these here to avoid going into weird paths
709        * inside gallium frontends.
710        */
711       if (format_desc->block.width != 1 ||
712           format_desc->block.height != 1)
713          return false;
714 
715       if (!virgl_format_check_bitmask(format,
716                                       caps->v1.render.bitmask,
717                                       may_emulate_bgra))
718          return false;
719    }
720 
721    if (bind & PIPE_BIND_DEPTH_STENCIL) {
722       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
723          return false;
724    }
725 
726    if (bind & PIPE_BIND_SCANOUT) {
727       if (!virgl_format_check_bitmask(format, caps->v2.scanout.bitmask, false))
728          return false;
729    }
730 
731    /*
732     * All other operations (sampling, transfer, etc).
733     */
734 
735    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
736       goto out_lookup;
737    }
738    if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
739       goto out_lookup;
740    }
741    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
742       goto out_lookup;
743    }
744    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
745       goto out_lookup;
746    }
747 
748    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
749       goto out_lookup;
750    } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
751       goto out_lookup;
752    }
753 
754    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
755      goto out_lookup;
756    }
757 
758    /* Find the first non-VOID channel. */
759    for (i = 0; i < 4; i++) {
760       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
761          break;
762       }
763    }
764 
765    if (i == 4)
766       return false;
767 
768    /* no L4A4 */
769    if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
770       return false;
771 
772  out_lookup:
773    return virgl_format_check_bitmask(format,
774                                      caps->v1.sampler.bitmask,
775                                      may_emulate_bgra);
776 }
777 
virgl_flush_frontbuffer(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_resource * res,unsigned level,unsigned layer,void * winsys_drawable_handle,struct pipe_box * sub_box)778 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
779                                     struct pipe_context *ctx,
780                                       struct pipe_resource *res,
781                                       unsigned level, unsigned layer,
782                                     void *winsys_drawable_handle, struct pipe_box *sub_box)
783 {
784    struct virgl_screen *vscreen = virgl_screen(screen);
785    struct virgl_winsys *vws = vscreen->vws;
786    struct virgl_resource *vres = virgl_resource(res);
787 
788    if (vws->flush_frontbuffer)
789       vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
790                              sub_box);
791 }
792 
virgl_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)793 static void virgl_fence_reference(struct pipe_screen *screen,
794                                   struct pipe_fence_handle **ptr,
795                                   struct pipe_fence_handle *fence)
796 {
797    struct virgl_screen *vscreen = virgl_screen(screen);
798    struct virgl_winsys *vws = vscreen->vws;
799 
800    vws->fence_reference(vws, ptr, fence);
801 }
802 
virgl_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)803 static bool virgl_fence_finish(struct pipe_screen *screen,
804                                struct pipe_context *ctx,
805                                struct pipe_fence_handle *fence,
806                                uint64_t timeout)
807 {
808    struct virgl_screen *vscreen = virgl_screen(screen);
809    struct virgl_winsys *vws = vscreen->vws;
810    struct virgl_context *vctx = virgl_context(ctx);
811 
812    if (vctx && timeout)
813       virgl_flush_eq(vctx, NULL, NULL);
814 
815    return vws->fence_wait(vws, fence, timeout);
816 }
817 
virgl_fence_get_fd(struct pipe_screen * screen,struct pipe_fence_handle * fence)818 static int virgl_fence_get_fd(struct pipe_screen *screen,
819             struct pipe_fence_handle *fence)
820 {
821    struct virgl_screen *vscreen = virgl_screen(screen);
822    struct virgl_winsys *vws = vscreen->vws;
823 
824    return vws->fence_get_fd(vws, fence);
825 }
826 
827 static uint64_t
virgl_get_timestamp(struct pipe_screen * _screen)828 virgl_get_timestamp(struct pipe_screen *_screen)
829 {
830    return os_time_get_nano();
831 }
832 
833 static void
virgl_destroy_screen(struct pipe_screen * screen)834 virgl_destroy_screen(struct pipe_screen *screen)
835 {
836    struct virgl_screen *vscreen = virgl_screen(screen);
837    struct virgl_winsys *vws = vscreen->vws;
838 
839    slab_destroy_parent(&vscreen->transfer_pool);
840 
841    if (vws)
842       vws->destroy(vws);
843 
844    disk_cache_destroy(vscreen->disk_cache);
845 
846    FREE(vscreen);
847 }
848 
849 static void
fixup_formats(union virgl_caps * caps,struct virgl_supported_format_mask * mask)850 fixup_formats(union virgl_caps *caps, struct virgl_supported_format_mask *mask)
851 {
852    const size_t size = ARRAY_SIZE(mask->bitmask);
853    for (int i = 0; i < size; ++i) {
854       if (mask->bitmask[i] != 0)
855          return; /* we got some formats, we definitely have a new protocol */
856    }
857 
858    /* old protocol used; fall back to considering all sampleable formats valid
859     * readback-formats
860     */
861    for (int i = 0; i < size; ++i)
862       mask->bitmask[i] = caps->v1.sampler.bitmask[i];
863 }
864 
virgl_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)865 static void virgl_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
866 {
867    struct virgl_screen *vscreen = virgl_screen(screen);
868    struct pipe_context *ctx = screen->context_create(screen, NULL, 0);
869    struct virgl_context *vctx = virgl_context(ctx);
870    struct virgl_resource *res;
871    struct virgl_memory_info virgl_info = {0};
872    const static struct pipe_resource templ = {
873       .target = PIPE_BUFFER,
874       .format = PIPE_FORMAT_R8_UNORM,
875       .bind = PIPE_BIND_CUSTOM,
876       .width0 = sizeof(struct virgl_memory_info),
877       .height0 = 1,
878       .depth0 = 1,
879       .array_size = 1,
880       .last_level = 0,
881       .nr_samples = 0,
882       .flags = 0
883    };
884 
885    res = (struct virgl_resource*) screen->resource_create(screen, &templ);
886 
887    virgl_encode_get_memory_info(vctx, res);
888    ctx->flush(ctx, NULL, 0);
889    vscreen->vws->resource_wait(vscreen->vws, res->hw_res);
890    pipe_buffer_read(ctx, &res->b, 0, sizeof(struct virgl_memory_info), &virgl_info);
891 
892    info->avail_device_memory = virgl_info.avail_device_memory;
893    info->avail_staging_memory = virgl_info.avail_staging_memory;
894    info->device_memory_evicted = virgl_info.device_memory_evicted;
895    info->nr_device_memory_evictions = virgl_info.nr_device_memory_evictions;
896    info->total_device_memory = virgl_info.total_device_memory;
897    info->total_staging_memory = virgl_info.total_staging_memory;
898 
899    screen->resource_destroy(screen, &res->b);
900    ctx->destroy(ctx);
901 }
902 
virgl_get_disk_shader_cache(struct pipe_screen * pscreen)903 static struct disk_cache *virgl_get_disk_shader_cache (struct pipe_screen *pscreen)
904 {
905    struct virgl_screen *screen = virgl_screen(pscreen);
906 
907    return screen->disk_cache;
908 }
909 
virgl_disk_cache_create(struct virgl_screen * screen)910 static void virgl_disk_cache_create(struct virgl_screen *screen)
911 {
912    const struct build_id_note *note =
913       build_id_find_nhdr_for_addr(virgl_disk_cache_create);
914    unsigned build_id_len = build_id_length(note);
915    assert(note && build_id_len == 20); /* sha1 */
916 
917    const uint8_t *id_sha1 = build_id_data(note);
918    assert(id_sha1);
919 
920    struct mesa_sha1 sha1_ctx;
921    _mesa_sha1_init(&sha1_ctx);
922    _mesa_sha1_update(&sha1_ctx, id_sha1, build_id_len);
923 
924    uint32_t shader_debug_flags = virgl_debug & VIRGL_DEBUG_NIR;
925    _mesa_sha1_update(&sha1_ctx, &shader_debug_flags, sizeof(shader_debug_flags));
926 
927    uint8_t sha1[20];
928    _mesa_sha1_final(&sha1_ctx, sha1);
929    char timestamp[41];
930    _mesa_sha1_format(timestamp, sha1);
931 
932    screen->disk_cache = disk_cache_create("virgl", timestamp, 0);
933 }
934 
935 static void
fixup_renderer(union virgl_caps * caps)936 fixup_renderer(union virgl_caps *caps)
937 {
938    if (caps->v2.host_feature_check_version < 5)
939       return;
940 
941    char renderer[64];
942    int renderer_len = snprintf(renderer, sizeof(renderer), "virgl (%s)",
943                                caps->v2.renderer);
944    if (renderer_len >= 64) {
945       memcpy(renderer + 59, "...)", 4);
946       renderer_len = 63;
947    }
948    memcpy(caps->v2.renderer, renderer, renderer_len + 1);
949 }
950 
951 struct pipe_screen *
virgl_create_screen(struct virgl_winsys * vws,const struct pipe_screen_config * config)952 virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
953 {
954    struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
955 
956    const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
957    const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
958    const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
959 
960    if (!screen)
961       return NULL;
962 
963    virgl_debug = debug_get_option_virgl_debug();
964 
965    if (config && config->options) {
966       driParseConfigFiles(config->options, config->options_info, 0, "virtio_gpu",
967                           NULL, NULL, NULL, 0, NULL, 0);
968 
969       screen->tweak_gles_emulate_bgra =
970             driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
971       screen->tweak_gles_apply_bgra_dest_swizzle =
972             driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
973       screen->tweak_gles_tf3_value =
974             driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
975    }
976    screen->tweak_gles_emulate_bgra &= !(virgl_debug & VIRGL_DEBUG_NO_EMULATE_BGRA);
977    screen->tweak_gles_apply_bgra_dest_swizzle &= !(virgl_debug & VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE);
978    screen->no_coherent = virgl_debug & VIRGL_DEBUG_NO_COHERENT;
979 
980    screen->vws = vws;
981    screen->base.get_name = virgl_get_name;
982    screen->base.get_vendor = virgl_get_vendor;
983    screen->base.get_param = virgl_get_param;
984    screen->base.get_shader_param = virgl_get_shader_param;
985    screen->base.get_compute_param = virgl_get_compute_param;
986    screen->base.get_paramf = virgl_get_paramf;
987    screen->base.get_compiler_options = nir_to_tgsi_get_compiler_options;
988    screen->base.is_format_supported = virgl_is_format_supported;
989    screen->base.destroy = virgl_destroy_screen;
990    screen->base.context_create = virgl_context_create;
991    screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
992    screen->base.get_timestamp = virgl_get_timestamp;
993    screen->base.fence_reference = virgl_fence_reference;
994    //screen->base.fence_signalled = virgl_fence_signalled;
995    screen->base.fence_finish = virgl_fence_finish;
996    screen->base.fence_get_fd = virgl_fence_get_fd;
997    screen->base.query_memory_info = virgl_query_memory_info;
998    screen->base.get_disk_shader_cache = virgl_get_disk_shader_cache;
999 
1000    virgl_init_screen_resource_functions(&screen->base);
1001 
1002    vws->get_caps(vws, &screen->caps);
1003    fixup_formats(&screen->caps.caps,
1004                  &screen->caps.caps.v2.supported_readback_formats);
1005    fixup_formats(&screen->caps.caps, &screen->caps.caps.v2.scanout);
1006    fixup_renderer(&screen->caps.caps);
1007 
1008    union virgl_caps *caps = &screen->caps.caps;
1009    screen->tweak_gles_emulate_bgra &= !virgl_format_check_bitmask(PIPE_FORMAT_B8G8R8A8_SRGB, caps->v1.render.bitmask, false);
1010    screen->refcnt = 1;
1011 
1012    slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
1013 
1014    virgl_disk_cache_create(screen);
1015    return &screen->base;
1016 }
1017