1 /*
2  * Copyright 2010 Christoph Bumiller
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/format/u_format.h"
27 #include "util/format/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
30 
31 #include "nouveau_vp3_video.h"
32 
33 #include "codegen/nv50_ir_driver.h"
34 
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37 
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40 #include "nvc0/mme/comc597.mme.h"
41 
42 #include "nv50/g80_texture.xml.h"
43 
44 static bool
nvc0_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)45 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
46                                 enum pipe_format format,
47                                 enum pipe_texture_target target,
48                                 unsigned sample_count,
49                                 unsigned storage_sample_count,
50                                 unsigned bindings)
51 {
52    const struct util_format_description *desc = util_format_description(format);
53 
54    if (sample_count > 8)
55       return false;
56    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
57       return false;
58 
59    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
60       return false;
61 
62    /* Short-circuit the rest of the logic -- this is used by the gallium frontend
63     * to determine valid MS levels in a no-attachments scenario.
64     */
65    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
66       return true;
67 
68    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
69       if (util_format_get_blocksizebits(format) == 3 * 32)
70          return false;
71 
72    if (bindings & PIPE_BIND_LINEAR)
73       if (util_format_is_depth_or_stencil(format) ||
74           (target != PIPE_TEXTURE_1D &&
75            target != PIPE_TEXTURE_2D &&
76            target != PIPE_TEXTURE_RECT) ||
77           sample_count > 1)
78          return false;
79 
80    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A
81     * and GM20B.
82     */
83    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
84         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
85        nouveau_screen(pscreen)->device->chipset != 0x12b &&
86        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
87       return false;
88 
89    /* shared is always supported */
90    bindings &= ~(PIPE_BIND_LINEAR |
91                  PIPE_BIND_SHARED);
92 
93    if (bindings & PIPE_BIND_SHADER_IMAGE) {
94       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
95           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
96          /* This should work on Fermi, but for currently unknown reasons it
97           * does not and results in breaking reads from pbos. */
98          return false;
99       }
100    }
101 
102    if (bindings & PIPE_BIND_INDEX_BUFFER) {
103       if (format != PIPE_FORMAT_R8_UINT &&
104           format != PIPE_FORMAT_R16_UINT &&
105           format != PIPE_FORMAT_R32_UINT)
106          return false;
107       bindings &= ~PIPE_BIND_INDEX_BUFFER;
108    }
109 
110    return (( nvc0_format_table[format].usage |
111             nvc0_vertex_format[format].usage) & bindings) == bindings;
112 }
113 
114 static int
nvc0_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)115 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
116 {
117    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
118    const struct nouveau_screen *screen = nouveau_screen(pscreen);
119    struct nouveau_device *dev = screen->device;
120    static bool debug_cap_printed[PIPE_CAP_LAST] = {};
121 
122    switch (param) {
123    /* non-boolean caps */
124    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
125       return 16384;
126    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
127       return 15;
128    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
129       return 12;
130    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
131       return 2048;
132    case PIPE_CAP_MIN_TEXEL_OFFSET:
133       return -8;
134    case PIPE_CAP_MAX_TEXEL_OFFSET:
135       return 7;
136    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
137       return -32;
138    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
139       return 31;
140    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
141       return 128 * 1024 * 1024;
142    case PIPE_CAP_GLSL_FEATURE_LEVEL:
143       return 430;
144    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
145       return 430;
146    case PIPE_CAP_MAX_RENDER_TARGETS:
147       return 8;
148    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
149       return 1;
150    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
151    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
152       return 8;
153    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
154       return 4;
155    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
156    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
157       return 128;
158    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
159    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
160       return 1024;
161    case PIPE_CAP_MAX_VERTEX_STREAMS:
162       return 4;
163    case PIPE_CAP_MAX_GS_INVOCATIONS:
164       return 32;
165    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
166       return 1 << 27;
167    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
168       return 2048;
169    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
170       return 2047;
171    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
172       return 256;
173    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
174       if (class_3d < GM107_3D_CLASS)
175          return 256; /* IMAGE bindings require alignment to 256 */
176       return 16;
177    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
178       return 16;
179    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
180       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
181    case PIPE_CAP_MAX_VIEWPORTS:
182       return NVC0_MAX_VIEWPORTS;
183    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
184       return 4;
185    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
186       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
187    case PIPE_CAP_ENDIANNESS:
188       return PIPE_ENDIAN_LITTLE;
189    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
190       return 30;
191    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
192       return NVC0_MAX_WINDOW_RECTANGLES;
193    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
194       return class_3d >= GM200_3D_CLASS ? 8 : 0;
195    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
196       return 64 * 1024 * 1024;
197    case PIPE_CAP_MAX_VARYINGS:
198       /* NOTE: These only count our slots for GENERIC varyings.
199        * The address space may be larger, but the actual hard limit seems to be
200        * less than what the address space layout permits, so don't add TEXCOORD,
201        * COLOR, etc. here.
202        */
203       return 0x1f0 / 16;
204    case PIPE_CAP_MAX_VERTEX_BUFFERS:
205       return 16;
206    case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
207       return 512 * 1024; /* TODO: Investigate tuning this */
208    case PIPE_CAP_MAX_TEXTURE_MB:
209       return 0; /* TODO: use 1/2 of VRAM for this? */
210 
211    case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
212    case PIPE_CAP_SUPPORTED_PRIM_MODES:
213       return BITFIELD_MASK(PIPE_PRIM_MAX);
214 
215    /* supported caps */
216    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
217    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
218    case PIPE_CAP_TEXTURE_SWIZZLE:
219    case PIPE_CAP_TEXTURE_SHADOW_MAP:
220    case PIPE_CAP_NPOT_TEXTURES:
221    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
222    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
223    case PIPE_CAP_ANISOTROPIC_FILTER:
224    case PIPE_CAP_SEAMLESS_CUBE_MAP:
225    case PIPE_CAP_CUBE_MAP_ARRAY:
226    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
227    case PIPE_CAP_TEXTURE_MULTISAMPLE:
228    case PIPE_CAP_DEPTH_CLIP_DISABLE:
229    case PIPE_CAP_POINT_SPRITE:
230    case PIPE_CAP_TGSI_TEXCOORD:
231    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
232    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
233    case PIPE_CAP_VERTEX_SHADER_SATURATE:
234    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
235    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
236    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
237    case PIPE_CAP_QUERY_TIMESTAMP:
238    case PIPE_CAP_QUERY_TIME_ELAPSED:
239    case PIPE_CAP_OCCLUSION_QUERY:
240    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
241    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
242    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
243    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
244    case PIPE_CAP_INDEP_BLEND_ENABLE:
245    case PIPE_CAP_INDEP_BLEND_FUNC:
246    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
247    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
248    case PIPE_CAP_PRIMITIVE_RESTART:
249    case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
250    case PIPE_CAP_TGSI_INSTANCEID:
251    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
252    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
253    case PIPE_CAP_CONDITIONAL_RENDER:
254    case PIPE_CAP_TEXTURE_BARRIER:
255    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
256    case PIPE_CAP_START_INSTANCE:
257    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
258    case PIPE_CAP_DRAW_INDIRECT:
259    case PIPE_CAP_USER_VERTEX_BUFFERS:
260    case PIPE_CAP_TEXTURE_QUERY_LOD:
261    case PIPE_CAP_SAMPLE_SHADING:
262    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
263    case PIPE_CAP_TEXTURE_GATHER_SM5:
264    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
265    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
266    case PIPE_CAP_SAMPLER_VIEW_TARGET:
267    case PIPE_CAP_CLIP_HALFZ:
268    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
269    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
270    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
271    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
272    case PIPE_CAP_DEPTH_BOUNDS_TEST:
273    case PIPE_CAP_TGSI_TXQS:
274    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
275    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
276    case PIPE_CAP_CLEAR_TEXTURE:
277    case PIPE_CAP_DRAW_PARAMETERS:
278    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
279    case PIPE_CAP_MULTI_DRAW_INDIRECT:
280    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
281    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
282    case PIPE_CAP_QUERY_BUFFER_OBJECT:
283    case PIPE_CAP_INVALIDATE_BUFFER:
284    case PIPE_CAP_STRING_MARKER:
285    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
286    case PIPE_CAP_CULL_DISTANCE:
287    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
288    case PIPE_CAP_TGSI_VOTE:
289    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
290    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
291    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
292    case PIPE_CAP_DOUBLES:
293    case PIPE_CAP_INT64:
294    case PIPE_CAP_TGSI_TEX_TXF_LZ:
295    case PIPE_CAP_TGSI_CLOCK:
296    case PIPE_CAP_COMPUTE:
297    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
298    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
299    case PIPE_CAP_QUERY_SO_OVERFLOW:
300    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
301    case PIPE_CAP_TGSI_DIV:
302    case PIPE_CAP_TGSI_ATOMINC_WRAP:
303    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
304    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
305    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
306    case PIPE_CAP_FLATSHADE:
307    case PIPE_CAP_ALPHA_TEST:
308    case PIPE_CAP_POINT_SIZE_FIXED:
309    case PIPE_CAP_TWO_SIDED_COLOR:
310    case PIPE_CAP_CLIP_PLANES:
311    case PIPE_CAP_TEXTURE_SHADOW_LOD:
312    case PIPE_CAP_PACKED_STREAM_OUTPUT:
313    case PIPE_CAP_CLEAR_SCISSORED:
314    case PIPE_CAP_GL_CLAMP:
315       return 1;
316    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
317       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
318    case PIPE_CAP_FBFETCH:
319       return class_3d >= NVE4_3D_CLASS ? 1 : 0; /* needs testing on fermi */
320    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
321    case PIPE_CAP_TGSI_BALLOT:
322       return class_3d >= NVE4_3D_CLASS;
323    case PIPE_CAP_BINDLESS_TEXTURE:
324       return class_3d >= NVE4_3D_CLASS;
325    case PIPE_CAP_TGSI_ATOMFADD:
326       return class_3d < GM107_3D_CLASS; /* needs additional lowering */
327    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
328    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
329    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
330    case PIPE_CAP_POST_DEPTH_COVERAGE:
331    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
332    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
333    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
334    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
335    case PIPE_CAP_VIEWPORT_SWIZZLE:
336    case PIPE_CAP_VIEWPORT_MASK:
337    case PIPE_CAP_SAMPLER_REDUCTION_MINMAX:
338       return class_3d >= GM200_3D_CLASS;
339    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
340       return class_3d >= GP100_3D_CLASS;
341    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY_COMPUTE_ONLY:
342    case PIPE_CAP_SYSTEM_SVM:
343       return screen->has_svm ? 1 : 0;
344 
345    /* caps has to be turned on with nir */
346    case PIPE_CAP_GL_SPIRV:
347    case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
348    case PIPE_CAP_INT64_DIVMOD:
349       return screen->prefer_nir ? 1 : 0;
350 
351    /* nir related caps */
352    case PIPE_CAP_NIR_IMAGES_AS_DEREF:
353       return 0;
354 
355    /* unsupported caps */
356    case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
357    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
358    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
359    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
360    case PIPE_CAP_SHADER_STENCIL_EXPORT:
361    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
362    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
363    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
364    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
365    case PIPE_CAP_FAKE_SW_MSAA:
366    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
367    case PIPE_CAP_VERTEXID_NOBASE:
368    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
369    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
370    case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
371    case PIPE_CAP_GENERATE_MIPMAP:
372    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
373    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
374    case PIPE_CAP_QUERY_MEMORY_INFO:
375    case PIPE_CAP_PCI_GROUP:
376    case PIPE_CAP_PCI_BUS:
377    case PIPE_CAP_PCI_DEVICE:
378    case PIPE_CAP_PCI_FUNCTION:
379    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
380    case PIPE_CAP_NATIVE_FENCE_FD:
381    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
382    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
383    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
384    case PIPE_CAP_MEMOBJ:
385    case PIPE_CAP_LOAD_CONSTBUF:
386    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
387    case PIPE_CAP_TILE_RASTER_ORDER:
388    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
389    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
390    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
391    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
392    case PIPE_CAP_FENCE_SIGNAL:
393    case PIPE_CAP_CONSTBUF0_FLAGS:
394    case PIPE_CAP_PACKED_UNIFORMS:
395    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
396    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
397    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
398    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
399    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
400    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
401    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
402    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
403    case PIPE_CAP_NIR_COMPACT_ARRAYS:
404    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
405    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
406    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
407    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
408    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
409    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
410    case PIPE_CAP_FBFETCH_COHERENT:
411    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
412    case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
413    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: /* could be done */
414    case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
415    case PIPE_CAP_FRONTEND_NOOP:
416    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
417    case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
418    case PIPE_CAP_PSIZ_CLAMPED:
419    case PIPE_CAP_TEXTURE_BUFFER_SAMPLER:
420    case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
421    case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE: /* when we fix MT stuff */
422    case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL: /* TODO */
423    case PIPE_CAP_SHADER_ATOMIC_INT64: /* TODO */
424    case PIPE_CAP_GLSL_ZERO_INIT:
425    case PIPE_CAP_BLEND_EQUATION_ADVANCED:
426    case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
427    case PIPE_CAP_DEVICE_PROTECTED_CONTENT:
428    case PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB:
429       return 0;
430 
431    case PIPE_CAP_VENDOR_ID:
432       return 0x10de;
433    case PIPE_CAP_DEVICE_ID: {
434       uint64_t device_id;
435       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
436          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
437          return -1;
438       }
439       return device_id;
440    }
441    case PIPE_CAP_ACCELERATED:
442       return 1;
443    case PIPE_CAP_VIDEO_MEMORY:
444       return dev->vram_size >> 20;
445    case PIPE_CAP_UMA:
446       return 0;
447 
448    default:
449       if (!debug_cap_printed[param]) {
450          debug_printf("%s: unhandled cap %d\n", __func__, param);
451          debug_cap_printed[param] = true;
452       }
453       FALLTHROUGH;
454    /* caps where we want the default value */
455    case PIPE_CAP_DMABUF:
456    case PIPE_CAP_ESSL_FEATURE_LEVEL:
457    case PIPE_CAP_THROTTLE:
458       return u_pipe_screen_get_param_defaults(pscreen, param);
459    }
460 }
461 
462 static int
nvc0_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)463 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
464                              enum pipe_shader_type shader,
465                              enum pipe_shader_cap param)
466 {
467    const struct nouveau_screen *screen = nouveau_screen(pscreen);
468    const uint16_t class_3d = screen->class_3d;
469 
470    switch (shader) {
471    case PIPE_SHADER_VERTEX:
472    case PIPE_SHADER_GEOMETRY:
473    case PIPE_SHADER_FRAGMENT:
474    case PIPE_SHADER_COMPUTE:
475    case PIPE_SHADER_TESS_CTRL:
476    case PIPE_SHADER_TESS_EVAL:
477       break;
478    default:
479       return 0;
480    }
481 
482    switch (param) {
483    case PIPE_SHADER_CAP_PREFERRED_IR:
484       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
485    case PIPE_SHADER_CAP_SUPPORTED_IRS: {
486       uint32_t irs = 1 << PIPE_SHADER_IR_NIR |
487          ((class_3d >= GV100_3D_CLASS) ? 0 : 1 << PIPE_SHADER_IR_TGSI);
488       if (screen->force_enable_cl)
489          irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
490       return irs;
491    }
492    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
493    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
494    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
495    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
496       return 16384;
497    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
498       return 16;
499    case PIPE_SHADER_CAP_MAX_INPUTS:
500       return 0x200 / 16;
501    case PIPE_SHADER_CAP_MAX_OUTPUTS:
502       return 32;
503    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
504       return NVC0_MAX_CONSTBUF_SIZE;
505    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
506       return NVC0_MAX_PIPE_CONSTBUFS;
507    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
508       return shader != PIPE_SHADER_FRAGMENT;
509    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
510       /* HW doesn't support indirect addressing of fragment program inputs
511        * on Volta.  The binary driver generates a function to handle every
512        * possible indirection, and indirectly calls the function to handle
513        * this instead.
514        */
515       if (class_3d >= GV100_3D_CLASS)
516          return shader != PIPE_SHADER_FRAGMENT;
517       return 1;
518    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
519    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
520       return 1;
521    case PIPE_SHADER_CAP_MAX_TEMPS:
522       return NVC0_CAP_MAX_PROGRAM_TEMPS;
523    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
524       return 1;
525    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
526       return 1;
527    case PIPE_SHADER_CAP_SUBROUTINES:
528       return 1;
529    case PIPE_SHADER_CAP_INTEGERS:
530       return 1;
531    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
532       return 1;
533    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
534       return 1;
535    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
536       return 1;
537    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
538    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
539    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
540    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
541    case PIPE_SHADER_CAP_INT64_ATOMICS:
542    case PIPE_SHADER_CAP_FP16:
543    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
544    case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
545    case PIPE_SHADER_CAP_INT16:
546    case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
547    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
548    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
549       return 0;
550    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
551       return NVC0_MAX_BUFFERS;
552    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
553       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
554    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
555       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
556    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
557       return 32;
558    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
559       if (class_3d >= NVE4_3D_CLASS)
560          return NVC0_MAX_IMAGES;
561       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
562          return NVC0_MAX_IMAGES;
563       return 0;
564    default:
565       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
566       return 0;
567    }
568 }
569 
570 static float
nvc0_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)571 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
572 {
573    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
574 
575    switch (param) {
576    case PIPE_CAPF_MAX_LINE_WIDTH:
577    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
578       return 10.0f;
579    case PIPE_CAPF_MAX_POINT_WIDTH:
580       return 63.0f;
581    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
582       return 63.375f;
583    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
584       return 16.0f;
585    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
586       return 15.0f;
587    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
588       return 0.0f;
589    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
590       return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
591    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
592       return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
593    }
594 
595    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
596    return 0.0f;
597 }
598 
599 static int
nvc0_screen_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * data)600 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
601                               enum pipe_shader_ir ir_type,
602                               enum pipe_compute_cap param, void *data)
603 {
604    struct nvc0_screen *screen = nvc0_screen(pscreen);
605    const uint16_t obj_class = screen->compute->oclass;
606 
607 #define RET(x) do {                  \
608    if (data)                         \
609       memcpy(data, x, sizeof(x));    \
610    return sizeof(x);                 \
611 } while (0)
612 
613    switch (param) {
614    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
615       RET((uint64_t []) { 3 });
616    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
617       if (obj_class >= NVE4_COMPUTE_CLASS) {
618          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
619       } else {
620          RET(((uint64_t []) { 65535, 65535, 65535 }));
621       }
622    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
623       RET(((uint64_t []) { 1024, 1024, 64 }));
624    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
625       RET((uint64_t []) { 1024 });
626    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
627       if (obj_class >= NVE4_COMPUTE_CLASS) {
628          RET((uint64_t []) { 1024 });
629       } else {
630          RET((uint64_t []) { 512 });
631       }
632    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
633       RET((uint64_t []) { 1ULL << 40 });
634    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
635       switch (obj_class) {
636       case GM200_COMPUTE_CLASS:
637          RET((uint64_t []) { 96 << 10 });
638       case GM107_COMPUTE_CLASS:
639          RET((uint64_t []) { 64 << 10 });
640       default:
641          RET((uint64_t []) { 48 << 10 });
642       }
643    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
644       RET((uint64_t []) { 512 << 10 });
645    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
646       RET((uint64_t []) { 4096 });
647    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
648       RET((uint32_t []) { 32 });
649    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
650       RET((uint64_t []) { 1ULL << 40 });
651    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
652       RET((uint32_t []) { NVC0_MAX_IMAGES });
653    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
654       RET((uint32_t []) { screen->mp_count_compute });
655    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
656       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
657    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
658       RET((uint32_t []) { 64 });
659    default:
660       return 0;
661    }
662 
663 #undef RET
664 }
665 
666 static void
nvc0_screen_get_sample_pixel_grid(struct pipe_screen * pscreen,unsigned sample_count,unsigned * width,unsigned * height)667 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
668                                   unsigned sample_count,
669                                   unsigned *width, unsigned *height)
670 {
671    switch (sample_count) {
672    case 0:
673    case 1:
674       /* this could be 4x4, but the GL state tracker makes it difficult to
675        * create a 1x MSAA texture and smaller grids save CB space */
676       *width = 2;
677       *height = 4;
678       break;
679    case 2:
680       *width = 2;
681       *height = 4;
682       break;
683    case 4:
684       *width = 2;
685       *height = 2;
686       break;
687    case 8:
688       *width = 1;
689       *height = 2;
690       break;
691    default:
692       assert(0);
693    }
694 }
695 
696 static void
nvc0_screen_destroy(struct pipe_screen * pscreen)697 nvc0_screen_destroy(struct pipe_screen *pscreen)
698 {
699    struct nvc0_screen *screen = nvc0_screen(pscreen);
700 
701    if (!nouveau_drm_screen_unref(&screen->base))
702       return;
703 
704    nouveau_fence_cleanup(&screen->base);
705 
706    if (screen->base.pushbuf)
707       screen->base.pushbuf->user_priv = NULL;
708 
709    if (screen->blitter)
710       nvc0_blitter_destroy(screen);
711    if (screen->pm.prog) {
712       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
713       nvc0_program_destroy(NULL, screen->pm.prog);
714       FREE(screen->pm.prog);
715    }
716 
717    nouveau_bo_ref(NULL, &screen->text);
718    nouveau_bo_ref(NULL, &screen->uniform_bo);
719    nouveau_bo_ref(NULL, &screen->tls);
720    nouveau_bo_ref(NULL, &screen->txc);
721    nouveau_bo_ref(NULL, &screen->fence.bo);
722    nouveau_bo_ref(NULL, &screen->poly_cache);
723 
724    nouveau_heap_destroy(&screen->lib_code);
725    nouveau_heap_destroy(&screen->text_heap);
726 
727    FREE(screen->tic.entries);
728 
729    nouveau_object_del(&screen->eng3d);
730    nouveau_object_del(&screen->eng2d);
731    nouveau_object_del(&screen->m2mf);
732    nouveau_object_del(&screen->compute);
733    nouveau_object_del(&screen->nvsw);
734 
735    nouveau_screen_fini(&screen->base);
736 
737    FREE(screen);
738 }
739 
740 static int
nvc0_graph_set_macro(struct nvc0_screen * screen,uint32_t m,unsigned pos,unsigned size,const uint32_t * data)741 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
742                      unsigned size, const uint32_t *data)
743 {
744    struct nouveau_pushbuf *push = screen->base.pushbuf;
745 
746    size /= 4;
747 
748    assert((pos + size) <= 0x800);
749 
750    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
751    PUSH_DATA (push, (m - 0x3800) / 8);
752    PUSH_DATA (push, pos);
753    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
754    PUSH_DATA (push, pos);
755    PUSH_DATAp(push, data, size);
756 
757    return pos + size;
758 }
759 
760 static int
tu102_graph_set_macro(struct nvc0_screen * screen,uint32_t m,unsigned pos,unsigned size,const uint32_t * data)761 tu102_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
762                      unsigned size, const uint32_t *data)
763 {
764    struct nouveau_pushbuf *push = screen->base.pushbuf;
765 
766    size /= 4;
767 
768    assert((pos + size) <= 0x800);
769 
770    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
771    PUSH_DATA (push, (m - 0x3800) / 8);
772    PUSH_DATA (push, pos);
773    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
774    PUSH_DATA (push, pos);
775    PUSH_DATAp(push, data, size);
776 
777    return pos + (size / 3);
778 }
779 
780 static void
nvc0_magic_3d_init(struct nouveau_pushbuf * push,uint16_t obj_class)781 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
782 {
783    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
784    PUSH_DATA (push, 0xff);
785    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
786    PUSH_DATA (push, 0xff);
787    PUSH_DATA (push, 0xff);
788    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
789    PUSH_DATA (push, 0xff);
790    PUSH_DATA (push, 0xff);
791    if (obj_class < GV100_3D_CLASS) {
792       BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
793       PUSH_DATA (push, 0x3f);
794    }
795 
796    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
797    PUSH_DATA (push, (3 << 16) | 3);
798    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
799    PUSH_DATA (push, (2 << 16) | 2);
800 
801    if (obj_class < GM107_3D_CLASS) {
802       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
803       PUSH_DATA (push, 0);
804    }
805    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
806    PUSH_DATA (push, 0x10);
807    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
808    PUSH_DATA (push, 0x10);
809    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
810    PUSH_DATA (push, 0x10);
811    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
812    PUSH_DATA (push, 0x10);
813    PUSH_DATA (push, 0x10);
814    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
815    PUSH_DATA (push, 0x10);
816    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
817    PUSH_DATA (push, 0xe);
818 
819    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
820    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
821    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
822    PUSH_DATA (push, 0);
823    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
824    PUSH_DATA (push, 3);
825 
826    if (obj_class < GV100_3D_CLASS) {
827       BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
828       PUSH_DATA (push, 0x3fffff);
829    }
830    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
831    PUSH_DATA (push, 1);
832    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
833    PUSH_DATA (push, 1);
834 
835    if (obj_class < GM107_3D_CLASS) {
836       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
837       PUSH_DATA (push, 3);
838 
839       if (obj_class >= NVE4_3D_CLASS) {
840          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
841          PUSH_DATA (push, 1);
842       }
843    }
844 
845    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
846     * are supposed to do */
847 }
848 
849 static void
nvc0_screen_fence_emit(struct pipe_screen * pscreen,u32 * sequence)850 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
851 {
852    struct nvc0_screen *screen = nvc0_screen(pscreen);
853    struct nouveau_pushbuf *push = screen->base.pushbuf;
854 
855    /* we need to do it after possible flush in MARK_RING */
856    *sequence = ++screen->base.fence.sequence;
857 
858    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
859    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
860    PUSH_DATAh(push, screen->fence.bo->offset);
861    PUSH_DATA (push, screen->fence.bo->offset);
862    PUSH_DATA (push, *sequence);
863    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
864               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
865 }
866 
867 static u32
nvc0_screen_fence_update(struct pipe_screen * pscreen)868 nvc0_screen_fence_update(struct pipe_screen *pscreen)
869 {
870    struct nvc0_screen *screen = nvc0_screen(pscreen);
871    return screen->fence.map[0];
872 }
873 
874 static int
nvc0_screen_init_compute(struct nvc0_screen * screen)875 nvc0_screen_init_compute(struct nvc0_screen *screen)
876 {
877    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
878 
879    switch (screen->base.device->chipset & ~0xf) {
880    case 0xc0:
881    case 0xd0:
882       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
883    case 0xe0:
884    case 0xf0:
885    case 0x100:
886    case 0x110:
887    case 0x120:
888    case 0x130:
889    case 0x140:
890    case 0x160:
891       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
892    default:
893       return -1;
894    }
895 }
896 
897 static int
nvc0_screen_resize_tls_area(struct nvc0_screen * screen,uint32_t lpos,uint32_t lneg,uint32_t cstack)898 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
899                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
900 {
901    struct nouveau_bo *bo = NULL;
902    int ret;
903    uint64_t size = (lpos + lneg) * 32 + cstack;
904 
905    if (size >= (1 << 20)) {
906       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
907       return -1;
908    }
909 
910    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
911    size  = align(size, 0x8000);
912    size *= screen->mp_count;
913 
914    size = align(size, 1 << 17);
915 
916    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
917                         NULL, &bo);
918    if (ret)
919       return ret;
920 
921    /* Make sure that the pushbuf has acquired a reference to the old tls
922     * segment, as it may have commands that will reference it.
923     */
924    if (screen->tls)
925       PUSH_REFN(screen->base.pushbuf, screen->tls,
926                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
927    nouveau_bo_ref(NULL, &screen->tls);
928    screen->tls = bo;
929    return 0;
930 }
931 
932 int
nvc0_screen_resize_text_area(struct nvc0_screen * screen,uint64_t size)933 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
934 {
935    struct nouveau_pushbuf *push = screen->base.pushbuf;
936    struct nouveau_bo *bo;
937    int ret;
938 
939    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
940                         1 << 17, size, NULL, &bo);
941    if (ret)
942       return ret;
943 
944    /* Make sure that the pushbuf has acquired a reference to the old text
945     * segment, as it may have commands that will reference it.
946     */
947    if (screen->text)
948       PUSH_REFN(push, screen->text,
949                 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
950    nouveau_bo_ref(NULL, &screen->text);
951    screen->text = bo;
952 
953    nouveau_heap_destroy(&screen->lib_code);
954    nouveau_heap_destroy(&screen->text_heap);
955 
956    /* XXX: getting a page fault at the end of the code buffer every few
957     *  launches, don't use the last 256 bytes to work around them - prefetch ?
958     */
959    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
960 
961    /* update the code segment setup */
962    if (screen->eng3d->oclass < GV100_3D_CLASS) {
963       BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
964       PUSH_DATAh(push, screen->text->offset);
965       PUSH_DATA (push, screen->text->offset);
966       if (screen->compute) {
967          BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
968          PUSH_DATAh(push, screen->text->offset);
969          PUSH_DATA (push, screen->text->offset);
970       }
971    }
972 
973    return 0;
974 }
975 
976 void
nvc0_screen_bind_cb_3d(struct nvc0_screen * screen,bool * can_serialize,int stage,int index,int size,uint64_t addr)977 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
978                        int stage, int index, int size, uint64_t addr)
979 {
980    assert(stage != 5);
981 
982    struct nouveau_pushbuf *push = screen->base.pushbuf;
983 
984    if (screen->base.class_3d >= GM107_3D_CLASS) {
985       struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
986 
987       // TODO: Better figure out the conditions in which this is needed
988       bool serialize = binding->addr == addr && binding->size != size;
989       if (can_serialize)
990          serialize = serialize && *can_serialize;
991       if (serialize) {
992          IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
993          if (can_serialize)
994             *can_serialize = false;
995       }
996 
997       binding->addr = addr;
998       binding->size = size;
999    }
1000 
1001    if (size >= 0) {
1002       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1003       PUSH_DATA (push, size);
1004       PUSH_DATAh(push, addr);
1005       PUSH_DATA (push, addr);
1006    }
1007    IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
1008 }
1009 
1010 static const void *
nvc0_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)1011 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
1012                                  enum pipe_shader_ir ir,
1013                                  enum pipe_shader_type shader)
1014 {
1015    struct nvc0_screen *screen = nvc0_screen(pscreen);
1016    if (ir == PIPE_SHADER_IR_NIR)
1017       return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset);
1018    return NULL;
1019 }
1020 
1021 #define FAIL_SCREEN_INIT(str, err)                    \
1022    do {                                               \
1023       NOUVEAU_ERR(str, err);                          \
1024       goto fail;                                      \
1025    } while(0)
1026 
1027 struct nouveau_screen *
nvc0_screen_create(struct nouveau_device * dev)1028 nvc0_screen_create(struct nouveau_device *dev)
1029 {
1030    struct nvc0_screen *screen;
1031    struct pipe_screen *pscreen;
1032    struct nouveau_object *chan;
1033    struct nouveau_pushbuf *push;
1034    uint64_t value;
1035    uint32_t obj_class;
1036    uint32_t flags;
1037    int ret;
1038    unsigned i;
1039 
1040    switch (dev->chipset & ~0xf) {
1041    case 0xc0:
1042    case 0xd0:
1043    case 0xe0:
1044    case 0xf0:
1045    case 0x100:
1046    case 0x110:
1047    case 0x120:
1048    case 0x130:
1049    case 0x140:
1050    case 0x160:
1051       break;
1052    default:
1053       return NULL;
1054    }
1055 
1056    screen = CALLOC_STRUCT(nvc0_screen);
1057    if (!screen)
1058       return NULL;
1059    pscreen = &screen->base.base;
1060    pscreen->destroy = nvc0_screen_destroy;
1061 
1062    ret = nouveau_screen_init(&screen->base, dev);
1063    if (ret)
1064       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1065    chan = screen->base.channel;
1066    push = screen->base.pushbuf;
1067    push->user_priv = screen;
1068    push->rsvd_kick = 5;
1069 
1070    /* TODO: could this be higher on Kepler+? how does reclocking vs no
1071     * reclocking affect performance?
1072     * TODO: could this be higher on Fermi?
1073     */
1074    if (dev->chipset >= 0xe0)
1075       screen->base.transfer_pushbuf_threshold = 1024;
1076 
1077    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1078       PIPE_BIND_SHADER_BUFFER |
1079       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1080       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1081    screen->base.sysmem_bindings |=
1082       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1083 
1084    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1085       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1086       screen->base.vidmem_bindings = 0;
1087    }
1088 
1089    pscreen->context_create = nvc0_create;
1090    pscreen->is_format_supported = nvc0_screen_is_format_supported;
1091    pscreen->get_param = nvc0_screen_get_param;
1092    pscreen->get_shader_param = nvc0_screen_get_shader_param;
1093    pscreen->get_paramf = nvc0_screen_get_paramf;
1094    pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1095    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1096    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1097    /* nir stuff */
1098    pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1099 
1100    nvc0_screen_init_resource_functions(pscreen);
1101 
1102    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1103    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1104 
1105    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1106    if (screen->base.drm->version >= 0x01000202)
1107       flags |= NOUVEAU_BO_COHERENT;
1108 
1109    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1110    if (ret)
1111       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1112    nouveau_bo_map(screen->fence.bo, 0, NULL);
1113    screen->fence.map = screen->fence.bo->map;
1114    screen->base.fence.emit = nvc0_screen_fence_emit;
1115    screen->base.fence.update = nvc0_screen_fence_update;
1116 
1117    if (dev->chipset < 0x140) {
1118       ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1119                                NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1120       if (ret)
1121          FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1122 
1123       BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1124       PUSH_DATA (push, screen->nvsw->handle);
1125    }
1126 
1127    switch (dev->chipset & ~0xf) {
1128    case 0x160:
1129    case 0x140:
1130    case 0x130:
1131    case 0x120:
1132    case 0x110:
1133    case 0x100:
1134    case 0xf0:
1135       obj_class = NVF0_P2MF_CLASS;
1136       break;
1137    case 0xe0:
1138       obj_class = NVE4_P2MF_CLASS;
1139       break;
1140    default:
1141       obj_class = NVC0_M2MF_CLASS;
1142       break;
1143    }
1144    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1145                             &screen->m2mf);
1146    if (ret)
1147       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1148 
1149    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1150    PUSH_DATA (push, screen->m2mf->oclass);
1151    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1152       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1153       PUSH_DATA (push, NVE4_COPY_CLASS);
1154    }
1155 
1156    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1157                             &screen->eng2d);
1158    if (ret)
1159       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1160 
1161    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1162    PUSH_DATA (push, screen->eng2d->oclass);
1163    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1164    PUSH_DATA (push, 0);
1165    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1166    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1167    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1168    PUSH_DATA (push, 0);
1169    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1170    PUSH_DATA (push, 0);
1171    BEGIN_NVC0(push, NVC0_2D(SET_PIXELS_FROM_MEMORY_CORRAL_SIZE), 1);
1172    PUSH_DATA (push, 0x3f);
1173    BEGIN_NVC0(push, NVC0_2D(SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP), 1);
1174    PUSH_DATA (push, 1);
1175    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1176    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1177 
1178    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1179    PUSH_DATAh(push, screen->fence.bo->offset + 16);
1180    PUSH_DATA (push, screen->fence.bo->offset + 16);
1181 
1182    switch (dev->chipset & ~0xf) {
1183    case 0x160:
1184       obj_class = TU102_3D_CLASS;
1185       break;
1186    case 0x140:
1187       obj_class = GV100_3D_CLASS;
1188       break;
1189    case 0x130:
1190       switch (dev->chipset) {
1191       case 0x130:
1192       case 0x13b:
1193          obj_class = GP100_3D_CLASS;
1194          break;
1195       default:
1196          obj_class = GP102_3D_CLASS;
1197          break;
1198       }
1199       break;
1200    case 0x120:
1201       obj_class = GM200_3D_CLASS;
1202       break;
1203    case 0x110:
1204       obj_class = GM107_3D_CLASS;
1205       break;
1206    case 0x100:
1207    case 0xf0:
1208       obj_class = NVF0_3D_CLASS;
1209       break;
1210    case 0xe0:
1211       switch (dev->chipset) {
1212       case 0xea:
1213          obj_class = NVEA_3D_CLASS;
1214          break;
1215       default:
1216          obj_class = NVE4_3D_CLASS;
1217          break;
1218       }
1219       break;
1220    case 0xd0:
1221       obj_class = NVC8_3D_CLASS;
1222       break;
1223    case 0xc0:
1224    default:
1225       switch (dev->chipset) {
1226       case 0xc8:
1227          obj_class = NVC8_3D_CLASS;
1228          break;
1229       case 0xc1:
1230          obj_class = NVC1_3D_CLASS;
1231          break;
1232       default:
1233          obj_class = NVC0_3D_CLASS;
1234          break;
1235       }
1236       break;
1237    }
1238    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1239                             &screen->eng3d);
1240    if (ret)
1241       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1242    screen->base.class_3d = obj_class;
1243 
1244    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1245    PUSH_DATA (push, screen->eng3d->oclass);
1246 
1247    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1248    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1249 
1250    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1251       /* kill shaders after about 1 second (at 100 MHz) */
1252       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1253       PUSH_DATA (push, 0x17);
1254    }
1255 
1256    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1257                     screen->base.drm->version >= 0x01000101);
1258    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1259    for (i = 0; i < 8; ++i)
1260       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1261 
1262    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1263    PUSH_DATA (push, 1);
1264 
1265    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1266    PUSH_DATA (push, 0);
1267    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1268    PUSH_DATA (push, 0);
1269    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1270    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1271    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1272    PUSH_DATA (push, 0);
1273    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1274    PUSH_DATA (push, 1);
1275    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1276    PUSH_DATA (push, 1);
1277    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1278    PUSH_DATA (push, 1);
1279    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1280    PUSH_DATA (push, 0);
1281    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1282    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1283    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1284       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1285    } else {
1286       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1287       PUSH_DATA (push, 15);
1288    }
1289    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1290    PUSH_DATA (push, 8); /* 128 */
1291    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1292    PUSH_DATA (push, 1);
1293    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1294       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1295       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1296    }
1297 
1298    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1299 
1300    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1301    if (ret)
1302       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1303 
1304    /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1305    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1306                         &screen->uniform_bo);
1307    if (ret)
1308       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1309 
1310    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1311 
1312    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1313    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1314    PUSH_DATA (push, 256);
1315    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1316    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1317    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1318    PUSH_DATA (push, 0);
1319    PUSH_DATAf(push, 0.0f);
1320    PUSH_DATAf(push, 0.0f);
1321    PUSH_DATAf(push, 0.0f);
1322    PUSH_DATAf(push, 0.0f);
1323    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1324    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1325    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1326 
1327    if (screen->base.drm->version >= 0x01000101) {
1328       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1329       if (ret)
1330          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1331    } else {
1332       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1333          value = (8 << 8) | 4;
1334       else
1335          value = (16 << 8) | 4;
1336    }
1337    screen->gpc_count = value & 0x000000ff;
1338    screen->mp_count = value >> 8;
1339    screen->mp_count_compute = screen->mp_count;
1340 
1341    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1342    if (ret)
1343       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1344 
1345    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1346    PUSH_DATAh(push, screen->tls->offset);
1347    PUSH_DATA (push, screen->tls->offset);
1348    PUSH_DATA (push, screen->tls->size >> 32);
1349    PUSH_DATA (push, screen->tls->size);
1350    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1351    PUSH_DATA (push, 0);
1352    /* Reduce likelihood of collision with real buffers by placing the hole at
1353     * the top of the 4G area. This will have to be dealt with for real
1354     * eventually by blocking off that area from the VM.
1355     */
1356    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1357    PUSH_DATA (push, 0xff << 24);
1358 
1359    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1360       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1361                            &screen->poly_cache);
1362       if (ret)
1363          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1364 
1365       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1366       PUSH_DATAh(push, screen->poly_cache->offset);
1367       PUSH_DATA (push, screen->poly_cache->offset);
1368       PUSH_DATA (push, 3);
1369    }
1370 
1371    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1372                         &screen->txc);
1373    if (ret)
1374       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1375 
1376    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1377    PUSH_DATAh(push, screen->txc->offset);
1378    PUSH_DATA (push, screen->txc->offset);
1379    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1380    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1381       screen->tic.maxwell = true;
1382       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1383          screen->tic.maxwell =
1384             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1385          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1386       }
1387    }
1388 
1389    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1390    PUSH_DATAh(push, screen->txc->offset + 65536);
1391    PUSH_DATA (push, screen->txc->offset + 65536);
1392    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1393 
1394    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1395    PUSH_DATA (push, 0);
1396    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1397    PUSH_DATA (push, 0);
1398    PUSH_DATA (push, 0);
1399    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1400    PUSH_DATA (push, 0x3f);
1401 
1402    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1403    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1404    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1405    for (i = 0; i < 8 * 2; ++i)
1406       PUSH_DATA(push, 0);
1407    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1408    PUSH_DATA (push, 0);
1409    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1410    PUSH_DATA (push, 0);
1411 
1412    /* neither scissors, viewport nor stencil mask should affect clears */
1413    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1414    PUSH_DATA (push, 0);
1415 
1416    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1417    PUSH_DATA (push, 1);
1418    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1419       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1420       PUSH_DATAf(push, 0.0f);
1421       PUSH_DATAf(push, 1.0f);
1422    }
1423    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1424    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1425 
1426    /* We use scissors instead of exact view volume clipping,
1427     * so they're always enabled.
1428     */
1429    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1430       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1431       PUSH_DATA (push, 1);
1432       PUSH_DATA (push, 16384 << 16);
1433       PUSH_DATA (push, 16384 << 16);
1434    }
1435 
1436    if (screen->eng3d->oclass < TU102_3D_CLASS) {
1437 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1438 
1439       i = 0;
1440       MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1441       MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1442       MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1443       MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1444       MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1445       MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1446       MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1447       MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1448       MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1449       MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1450       MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1451       MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1452       MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1453       MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1454       MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1455       MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1456    } else {
1457 #undef MK_MACRO
1458 #define MK_MACRO(m, n) i = tu102_graph_set_macro(screen, m, i, sizeof(n), n);
1459 
1460       i = 0;
1461       MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mmec597_per_instance_bf);
1462       MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mmec597_blend_enables);
1463       MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mmec597_vertex_array_select);
1464       MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mmec597_tep_select);
1465       MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mmec597_gp_select);
1466       MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mmec597_poly_mode_front);
1467       MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mmec597_poly_mode_back);
1468       MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mmec597_draw_arrays_indirect);
1469       MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mmec597_draw_elts_indirect);
1470       MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mmec597_draw_arrays_indirect_count);
1471       MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mmec597_draw_elts_indirect_count);
1472       MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mmec597_query_buffer_write);
1473       MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mmec597_conservative_raster_state);
1474       MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mmec597_compute_counter);
1475       MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mmec597_compute_counter_to_query);
1476    }
1477 
1478    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1479    PUSH_DATA (push, 1);
1480    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1481    PUSH_DATA (push, 1);
1482    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1483    PUSH_DATA (push, 0x40);
1484    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1485    PUSH_DATA (push, 0);
1486    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1487    PUSH_DATA (push, 0x30);
1488    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1489    PUSH_DATA (push, 3);
1490    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1491    PUSH_DATA (push, 0x20);
1492    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1493    PUSH_DATA (push, 0x00);
1494    screen->save_state.patch_vertices = 3;
1495 
1496    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1497    PUSH_DATA (push, 0);
1498    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1499    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1500 
1501    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1502 
1503    if (nvc0_screen_init_compute(screen))
1504       goto fail;
1505 
1506    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1507    for (i = 0; i < 5; ++i) {
1508       unsigned j = 0;
1509       for (j = 0; j < 16; j++)
1510          screen->cb_bindings[i][j].size = -1;
1511 
1512       /* TIC and TSC entries for each unit (nve4+ only) */
1513       /* auxiliary constants (6 user clip planes, base instance id) */
1514       nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1515                              screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1516       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1517          unsigned j;
1518          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1519          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1520          for (j = 0; j < 8; ++j)
1521             PUSH_DATA(push, j);
1522       } else {
1523          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1524          PUSH_DATA (push, 0x54);
1525       }
1526 
1527       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1528       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1529       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1530       PUSH_DATA (push, 0); /* 0 */
1531       PUSH_DATA (push, 0);
1532       PUSH_DATA (push, 1); /* 1 */
1533       PUSH_DATA (push, 0);
1534       PUSH_DATA (push, 0); /* 2 */
1535       PUSH_DATA (push, 1);
1536       PUSH_DATA (push, 1); /* 3 */
1537       PUSH_DATA (push, 1);
1538       PUSH_DATA (push, 2); /* 4 */
1539       PUSH_DATA (push, 0);
1540       PUSH_DATA (push, 3); /* 5 */
1541       PUSH_DATA (push, 0);
1542       PUSH_DATA (push, 2); /* 6 */
1543       PUSH_DATA (push, 1);
1544       PUSH_DATA (push, 3); /* 7 */
1545       PUSH_DATA (push, 1);
1546    }
1547    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1548    PUSH_DATA (push, 0);
1549 
1550    PUSH_KICK (push);
1551 
1552    screen->tic.entries = CALLOC(
1553          NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1554          sizeof(void *));
1555    screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1556    screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1557 
1558    if (!nvc0_blitter_create(screen))
1559       goto fail;
1560 
1561    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1562 
1563    return &screen->base;
1564 
1565 fail:
1566    screen->base.base.context_create = NULL;
1567    return &screen->base;
1568 }
1569 
1570 int
nvc0_screen_tic_alloc(struct nvc0_screen * screen,void * entry)1571 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1572 {
1573    int i = screen->tic.next;
1574 
1575    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1576       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1577 
1578    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1579 
1580    if (screen->tic.entries[i])
1581       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1582 
1583    screen->tic.entries[i] = entry;
1584    return i;
1585 }
1586 
1587 int
nvc0_screen_tsc_alloc(struct nvc0_screen * screen,void * entry)1588 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1589 {
1590    int i = screen->tsc.next;
1591 
1592    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1593       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1594 
1595    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1596 
1597    if (screen->tsc.entries[i])
1598       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1599 
1600    screen->tsc.entries[i] = entry;
1601    return i;
1602 }
1603