1 /*
2 * Copyright © 2015-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_compiler.h"
25 #include "brw_shader.h"
26 #include "brw_eu.h"
27 #include "dev/intel_debug.h"
28 #include "compiler/nir/nir.h"
29 #include "main/errors.h"
30 #include "util/debug.h"
31
32 #define COMMON_OPTIONS \
33 .lower_fdiv = true, \
34 .lower_scmp = true, \
35 .lower_flrp16 = true, \
36 .lower_fmod = true, \
37 .lower_bitfield_extract = true, \
38 .lower_bitfield_insert = true, \
39 .lower_uadd_carry = true, \
40 .lower_usub_borrow = true, \
41 .lower_flrp64 = true, \
42 .lower_isign = true, \
43 .lower_ldexp = true, \
44 .lower_device_index_to_zero = true, \
45 .vectorize_io = true, \
46 .use_interpolated_input_intrinsics = true, \
47 .lower_insert_byte = true, \
48 .lower_insert_word = true, \
49 .vertex_id_zero_based = true, \
50 .lower_base_vertex = true, \
51 .use_scoped_barrier = true, \
52 .support_16bit_alu = true, \
53 .lower_uniforms_to_ubo = true, \
54 .has_txs = true
55
56 #define COMMON_SCALAR_OPTIONS \
57 .lower_to_scalar = true, \
58 .lower_pack_half_2x16 = true, \
59 .lower_pack_snorm_2x16 = true, \
60 .lower_pack_snorm_4x8 = true, \
61 .lower_pack_unorm_2x16 = true, \
62 .lower_pack_unorm_4x8 = true, \
63 .lower_unpack_half_2x16 = true, \
64 .lower_unpack_snorm_2x16 = true, \
65 .lower_unpack_snorm_4x8 = true, \
66 .lower_unpack_unorm_2x16 = true, \
67 .lower_unpack_unorm_4x8 = true, \
68 .lower_usub_sat64 = true, \
69 .lower_hadd64 = true, \
70 .avoid_ternary_with_two_constants = true, \
71 .has_pack_32_4x8 = true, \
72 .max_unroll_iterations = 32, \
73 .force_indirect_unrolling = nir_var_function_temp
74
75 static const struct nir_shader_compiler_options scalar_nir_options = {
76 COMMON_OPTIONS,
77 COMMON_SCALAR_OPTIONS,
78 };
79
80 static const struct nir_shader_compiler_options vector_nir_options = {
81 COMMON_OPTIONS,
82
83 /* In the vec4 backend, our dpN instruction replicates its result to all the
84 * components of a vec4. We would like NIR to give us replicated fdot
85 * instructions because it can optimize better for us.
86 */
87 .fdot_replicates = true,
88
89 .lower_pack_snorm_2x16 = true,
90 .lower_pack_unorm_2x16 = true,
91 .lower_unpack_snorm_2x16 = true,
92 .lower_unpack_unorm_2x16 = true,
93 .lower_extract_byte = true,
94 .lower_extract_word = true,
95 .intel_vec4 = true,
96 .max_unroll_iterations = 32,
97 };
98
99 struct brw_compiler *
brw_compiler_create(void * mem_ctx,const struct intel_device_info * devinfo)100 brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
101 {
102 struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
103
104 compiler->devinfo = devinfo;
105
106 brw_fs_alloc_reg_sets(compiler);
107 brw_vec4_alloc_reg_set(compiler);
108
109 compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
110
111 compiler->use_tcs_8_patch =
112 devinfo->ver >= 12 ||
113 (devinfo->ver >= 9 && INTEL_DEBUG(DEBUG_TCS_EIGHT_PATCH));
114
115 /* Default to the sampler since that's what we've done since forever */
116 compiler->indirect_ubos_use_sampler = true;
117
118 /* There is no vec4 mode on Gfx10+, and we don't use it at all on Gfx8+. */
119 for (int i = MESA_SHADER_VERTEX; i < MESA_ALL_SHADER_STAGES; i++) {
120 compiler->scalar_stage[i] = devinfo->ver >= 8 ||
121 i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE;
122 }
123
124 for (int i = MESA_SHADER_TASK; i < MESA_VULKAN_SHADER_STAGES; i++)
125 compiler->scalar_stage[i] = true;
126
127 nir_lower_int64_options int64_options =
128 nir_lower_imul64 |
129 nir_lower_isign64 |
130 nir_lower_divmod64 |
131 nir_lower_imul_high64;
132 nir_lower_doubles_options fp64_options =
133 nir_lower_drcp |
134 nir_lower_dsqrt |
135 nir_lower_drsq |
136 nir_lower_dtrunc |
137 nir_lower_dfloor |
138 nir_lower_dceil |
139 nir_lower_dfract |
140 nir_lower_dround_even |
141 nir_lower_dmod |
142 nir_lower_dsub |
143 nir_lower_ddiv;
144
145 if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64)) {
146 int64_options |= (nir_lower_int64_options)~0;
147 fp64_options |= nir_lower_fp64_full_software;
148 }
149
150 /* The Bspec's section tittled "Instruction_multiply[DevBDW+]" claims that
151 * destination type can be Quadword and source type Doubleword for Gfx8 and
152 * Gfx9. So, lower 64 bit multiply instruction on rest of the platforms.
153 */
154 if (devinfo->ver < 8 || devinfo->ver > 9)
155 int64_options |= nir_lower_imul_2x32_64;
156
157 /* We want the GLSL compiler to emit code that uses condition codes */
158 for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
159 compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
160 compiler->glsl_compiler_options[i].MaxIfDepth =
161 devinfo->ver < 6 ? 16 : UINT_MAX;
162
163 /* We handle this in NIR */
164 compiler->glsl_compiler_options[i].EmitNoIndirectInput = false;
165 compiler->glsl_compiler_options[i].EmitNoIndirectOutput = false;
166 compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
167 compiler->glsl_compiler_options[i].EmitNoIndirectTemp = false;
168
169 bool is_scalar = compiler->scalar_stage[i];
170 compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
171
172 struct nir_shader_compiler_options *nir_options =
173 rzalloc(compiler, struct nir_shader_compiler_options);
174 if (is_scalar) {
175 *nir_options = scalar_nir_options;
176 } else {
177 *nir_options = vector_nir_options;
178 }
179
180 /* Prior to Gfx6, there are no three source operations, and Gfx11 loses
181 * LRP.
182 */
183 nir_options->lower_ffma16 = devinfo->ver < 6;
184 nir_options->lower_ffma32 = devinfo->ver < 6;
185 nir_options->lower_ffma64 = devinfo->ver < 6;
186 nir_options->lower_flrp32 = devinfo->ver < 6 || devinfo->ver >= 11;
187 nir_options->lower_fpow = devinfo->ver >= 12;
188
189 nir_options->lower_rotate = devinfo->ver < 11;
190 nir_options->lower_bitfield_reverse = devinfo->ver < 7;
191 nir_options->has_iadd3 = devinfo->verx10 >= 125;
192
193 nir_options->has_dot_4x8 = devinfo->ver >= 12;
194 nir_options->has_sudot_4x8 = devinfo->ver >= 12;
195
196 nir_options->lower_int64_options = int64_options;
197 nir_options->lower_doubles_options = fp64_options;
198
199 nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
200
201 nir_options->force_indirect_unrolling |=
202 brw_nir_no_indirect_mask(compiler, i);
203
204 compiler->glsl_compiler_options[i].NirOptions = nir_options;
205
206 compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
207 }
208
209 return compiler;
210 }
211
212 static void
insert_u64_bit(uint64_t * val,bool add)213 insert_u64_bit(uint64_t *val, bool add)
214 {
215 *val = (*val << 1) | !!add;
216 }
217
218 uint64_t
brw_get_compiler_config_value(const struct brw_compiler * compiler)219 brw_get_compiler_config_value(const struct brw_compiler *compiler)
220 {
221 uint64_t config = 0;
222 insert_u64_bit(&config, compiler->precise_trig);
223 if (compiler->devinfo->ver >= 8 && compiler->devinfo->ver < 10) {
224 insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
225 insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
226 insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
227 insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
228 }
229 uint64_t mask = DEBUG_DISK_CACHE_MASK;
230 while (mask != 0) {
231 const uint64_t bit = 1ULL << (ffsll(mask) - 1);
232 insert_u64_bit(&config, INTEL_DEBUG(bit));
233 mask &= ~bit;
234 }
235 return config;
236 }
237
238 unsigned
brw_prog_data_size(gl_shader_stage stage)239 brw_prog_data_size(gl_shader_stage stage)
240 {
241 static const size_t stage_sizes[] = {
242 [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data),
243 [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_data),
244 [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_data),
245 [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data),
246 [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data),
247 [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data),
248 [MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_data),
249 [MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_data),
250 [MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_data),
251 [MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_data),
252 [MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_data),
253 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_data),
254 [MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_data),
255 };
256 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
257 return stage_sizes[stage];
258 }
259
260 unsigned
brw_prog_key_size(gl_shader_stage stage)261 brw_prog_key_size(gl_shader_stage stage)
262 {
263 static const size_t stage_sizes[] = {
264 [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key),
265 [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_key),
266 [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_key),
267 [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key),
268 [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key),
269 [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key),
270 [MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_key),
271 [MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_key),
272 [MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_key),
273 [MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_key),
274 [MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_key),
275 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_key),
276 [MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_key),
277 };
278 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
279 return stage_sizes[stage];
280 }
281
282 void
brw_write_shader_relocs(const struct intel_device_info * devinfo,void * program,const struct brw_stage_prog_data * prog_data,struct brw_shader_reloc_value * values,unsigned num_values)283 brw_write_shader_relocs(const struct intel_device_info *devinfo,
284 void *program,
285 const struct brw_stage_prog_data *prog_data,
286 struct brw_shader_reloc_value *values,
287 unsigned num_values)
288 {
289 for (unsigned i = 0; i < prog_data->num_relocs; i++) {
290 assert(prog_data->relocs[i].offset % 8 == 0);
291 void *dst = program + prog_data->relocs[i].offset;
292 for (unsigned j = 0; j < num_values; j++) {
293 if (prog_data->relocs[i].id == values[j].id) {
294 uint32_t value = values[j].value + prog_data->relocs[i].delta;
295 switch (prog_data->relocs[i].type) {
296 case BRW_SHADER_RELOC_TYPE_U32:
297 *(uint32_t *)dst = value;
298 break;
299 case BRW_SHADER_RELOC_TYPE_MOV_IMM:
300 brw_update_reloc_imm(devinfo, dst, value);
301 break;
302 default:
303 unreachable("Invalid relocation type");
304 }
305 break;
306 }
307 }
308 }
309 }
310