1 /*
2 * Copyright (C) 2014-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Christian Gmeiner <christian.gmeiner@gmail.com>
25 */
26
27 #ifndef ETNAVIV_DRMIF_H_
28 #define ETNAVIV_DRMIF_H_
29
30 #include <xf86drm.h>
31 #include <stdbool.h>
32 #include <stdint.h>
33
34 struct etna_bo;
35 struct etna_pipe;
36 struct etna_gpu;
37 struct etna_device;
38 struct etna_cmd_stream;
39 struct etna_perfmon;
40 struct etna_perfmon_domain;
41 struct etna_perfmon_signal;
42
43 enum etna_pipe_id {
44 ETNA_PIPE_3D = 0,
45 ETNA_PIPE_2D = 1,
46 ETNA_PIPE_VG = 2,
47 ETNA_PIPE_MAX
48 };
49
50 enum etna_param_id {
51 ETNA_GPU_MODEL = 0x1,
52 ETNA_GPU_REVISION = 0x2,
53 ETNA_GPU_FEATURES_0 = 0x3,
54 ETNA_GPU_FEATURES_1 = 0x4,
55 ETNA_GPU_FEATURES_2 = 0x5,
56 ETNA_GPU_FEATURES_3 = 0x6,
57 ETNA_GPU_FEATURES_4 = 0x7,
58 ETNA_GPU_FEATURES_5 = 0x8,
59 ETNA_GPU_FEATURES_6 = 0x9,
60 ETNA_GPU_FEATURES_7 = 0xa,
61 ETNA_GPU_FEATURES_8 = 0xb,
62
63 ETNA_GPU_STREAM_COUNT = 0x10,
64 ETNA_GPU_REGISTER_MAX = 0x11,
65 ETNA_GPU_THREAD_COUNT = 0x12,
66 ETNA_GPU_VERTEX_CACHE_SIZE = 0x13,
67 ETNA_GPU_SHADER_CORE_COUNT = 0x14,
68 ETNA_GPU_PIXEL_PIPES = 0x15,
69 ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE = 0x16,
70 ETNA_GPU_BUFFER_SIZE = 0x17,
71 ETNA_GPU_INSTRUCTION_COUNT = 0x18,
72 ETNA_GPU_NUM_CONSTANTS = 0x19,
73 ETNA_GPU_NUM_VARYINGS = 0x1a
74 };
75
76 /* bo flags: */
77 #define DRM_ETNA_GEM_CACHE_CACHED 0x00010000
78 #define DRM_ETNA_GEM_CACHE_WC 0x00020000
79 #define DRM_ETNA_GEM_CACHE_UNCACHED 0x00040000
80 #define DRM_ETNA_GEM_CACHE_MASK 0x000f0000
81 /* map flags */
82 #define DRM_ETNA_GEM_FORCE_MMU 0x00100000
83
84 /* bo access flags: (keep aligned to ETNA_PREP_x) */
85 #define DRM_ETNA_PREP_READ 0x01
86 #define DRM_ETNA_PREP_WRITE 0x02
87 #define DRM_ETNA_PREP_NOSYNC 0x04
88
89 /* device functions:
90 */
91
92 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
93
94 struct etna_device *etna_device_new(int fd);
95 struct etna_device *etna_device_new_dup(int fd);
96 struct etna_device *etna_device_ref(struct etna_device *dev);
97 void etna_device_del(struct etna_device *dev);
98 int etna_device_fd(struct etna_device *dev);
99 bool etnaviv_device_softpin_capable(struct etna_device *dev);
100 uint32_t etnaviv_device_version(struct etna_device *dev);
101
102 /* gpu functions:
103 */
104
105 struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core);
106 void etna_gpu_del(struct etna_gpu *gpu);
107 int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param,
108 uint64_t *value);
109
110
111 /* pipe functions:
112 */
113
114 struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id);
115 void etna_pipe_del(struct etna_pipe *pipe);
116 int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns);
117
118
119 /* buffer-object functions:
120 */
121
122 struct etna_bo *etna_bo_new(struct etna_device *dev,
123 uint32_t size, uint32_t flags);
124 struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name);
125 struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd);
126 struct etna_bo *etna_bo_ref(struct etna_bo *bo);
127 void etna_bo_del(struct etna_bo *bo);
128 int etna_bo_get_name(struct etna_bo *bo, uint32_t *name);
129 uint32_t etna_bo_handle(struct etna_bo *bo);
130 int etna_bo_dmabuf(struct etna_bo *bo);
131 uint32_t etna_bo_size(struct etna_bo *bo);
132 uint32_t etna_bo_gpu_va(struct etna_bo *bo);
133 void * etna_bo_map(struct etna_bo *bo);
134 int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op);
135 void etna_bo_cpu_fini(struct etna_bo *bo);
136
137
138 /* cmd stream functions:
139 */
140
141 struct etna_cmd_stream {
142 uint32_t *buffer;
143 uint32_t offset; /* in 32-bit words */
144 uint32_t size; /* in 32-bit words */
145 };
146
147 struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t size,
148 void (*reset_notify)(struct etna_cmd_stream *stream, void *priv),
149 void *priv);
150 void etna_cmd_stream_del(struct etna_cmd_stream *stream);
151 uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream);
152 void etna_cmd_stream_flush(struct etna_cmd_stream *stream, int in_fence_fd,
153 int *out_fence_fd);
154 void etna_cmd_stream_force_flush(struct etna_cmd_stream *stream);
155
etna_cmd_stream_avail(struct etna_cmd_stream * stream)156 static inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream *stream)
157 {
158 static const uint32_t END_CLEARANCE = 2; /* LINK op code */
159
160 return stream->size - stream->offset - END_CLEARANCE;
161 }
162
163 void etna_cmd_stream_realloc(struct etna_cmd_stream *stream, size_t n);
164
etna_cmd_stream_reserve(struct etna_cmd_stream * stream,size_t n)165 static inline void etna_cmd_stream_reserve(struct etna_cmd_stream *stream, size_t n)
166 {
167 if (etna_cmd_stream_avail(stream) < n)
168 etna_cmd_stream_realloc(stream, n);
169 }
170
etna_cmd_stream_emit(struct etna_cmd_stream * stream,uint32_t data)171 static inline void etna_cmd_stream_emit(struct etna_cmd_stream *stream, uint32_t data)
172 {
173 stream->buffer[stream->offset++] = data;
174 }
175
etna_cmd_stream_get(struct etna_cmd_stream * stream,uint32_t offset)176 static inline uint32_t etna_cmd_stream_get(struct etna_cmd_stream *stream, uint32_t offset)
177 {
178 return stream->buffer[offset];
179 }
180
etna_cmd_stream_set(struct etna_cmd_stream * stream,uint32_t offset,uint32_t data)181 static inline void etna_cmd_stream_set(struct etna_cmd_stream *stream, uint32_t offset,
182 uint32_t data)
183 {
184 stream->buffer[offset] = data;
185 }
186
etna_cmd_stream_offset(struct etna_cmd_stream * stream)187 static inline uint32_t etna_cmd_stream_offset(struct etna_cmd_stream *stream)
188 {
189 return stream->offset;
190 }
191
192 struct etna_reloc {
193 struct etna_bo *bo;
194 #define ETNA_RELOC_READ 0x0001
195 #define ETNA_RELOC_WRITE 0x0002
196 uint32_t flags;
197 uint32_t offset;
198 };
199
200 void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r);
201 void etna_cmd_stream_ref_bo(struct etna_cmd_stream *stream,
202 struct etna_bo *bo, uint32_t flags);
203
204 /* performance monitoring functions:
205 */
206
207 struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe);
208 void etna_perfmon_del(struct etna_perfmon *perfmon);
209 struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name);
210 struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name);
211
212 struct etna_perf {
213 #define ETNA_PM_PROCESS_PRE 0x0001
214 #define ETNA_PM_PROCESS_POST 0x0002
215 uint32_t flags;
216 uint32_t sequence;
217 struct etna_perfmon_signal *signal;
218 struct etna_bo *bo;
219 uint32_t offset;
220 };
221
222 void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p);
223
224 #endif /* ETNAVIV_DRMIF_H_ */
225