1 /* 2 ----------------------------------------------------------------------------- 3 This source file is part of OGRE 4 (Object-oriented Graphics Rendering Engine) 5 For the latest info, see http://www.ogre3d.org/ 6 7 Copyright (c) 2000-2014 Torus Knot Software Ltd 8 9 Permission is hereby granted, free of charge, to any person obtaining a copy 10 of this software and associated documentation files (the "Software"), to deal 11 in the Software without restriction, including without limitation the rights 12 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 copies of the Software, and to permit persons to whom the Software is 14 furnished to do so, subject to the following conditions: 15 16 The above copyright notice and this permission notice shall be included in 17 all copies or substantial portions of the Software. 18 19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 22 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 THE SOFTWARE. 26 ----------------------------------------------------------------------------- 27 */ 28 29 30 //--------------------------------------------------------------------------- 31 #include "ps_1_4.h" 32 33 //--------------------------------------------------------------------------- 34 35 /* ********************* START OF PS_1_4 CLASS STATIC DATA ********************************* */ 36 37 38 // library of built in symbol types 39 40 bool PS_1_4::LibInitialized = false; 41 42 #define SYMSTART { 43 #define SYMDEF ,0,0,0,0},{ 44 #define SYMEND ,0,0,0,0} 45 46 PS_1_4::SymbolDef PS_1_4::PS_1_4_SymbolTypeLib[] = { 47 // pixel shader versions supported 48 { sid_PS_1_4, GL_NONE, ckp_PS_BASE, ckp_PS_1_4, 0, 0, 0 }, 49 { sid_PS_1_1, GL_NONE, ckp_PS_BASE, ckp_PS_1_1, 0, 0, 0 }, 50 { sid_PS_1_2, GL_NONE, ckp_PS_BASE, ckp_PS_1_2 + ckp_PS_1_1, 0, 0, 0 }, 51 { sid_PS_1_3, GL_NONE, ckp_PS_BASE, ckp_PS_1_3 + ckp_PS_1_2 + ckp_PS_1_1, 0, 0, 0 }, 52 53 // PS_BASE 54 55 // constants 56 SYMSTART sid_C0, GL_CON_0_ATI, ckp_PS_BASE 57 SYMDEF sid_C1, GL_CON_1_ATI, ckp_PS_BASE 58 SYMDEF sid_C2, GL_CON_2_ATI, ckp_PS_BASE 59 SYMDEF sid_C3, GL_CON_3_ATI, ckp_PS_BASE 60 SYMDEF sid_C4, GL_CON_4_ATI, ckp_PS_BASE 61 SYMDEF sid_C5, GL_CON_5_ATI, ckp_PS_BASE 62 SYMDEF sid_C6, GL_CON_6_ATI, ckp_PS_BASE 63 SYMDEF sid_C7, GL_CON_7_ATI, ckp_PS_BASE 64 65 // colour 66 SYMDEF sid_V0, GL_PRIMARY_COLOR_ARB, ckp_PS_BASE 67 SYMDEF sid_V1, GL_SECONDARY_INTERPOLATOR_ATI, ckp_PS_BASE 68 69 // instruction ops 70 SYMDEF sid_ADD, GL_ADD_ATI, ckp_PS_BASE 71 SYMDEF sid_SUB, GL_SUB_ATI, ckp_PS_BASE 72 SYMDEF sid_MUL, GL_MUL_ATI, ckp_PS_BASE 73 SYMDEF sid_MAD, GL_MAD_ATI, ckp_PS_BASE 74 SYMDEF sid_LRP, GL_LERP_ATI, ckp_PS_BASE 75 SYMDEF sid_MOV, GL_MOV_ATI, ckp_PS_BASE 76 SYMDEF sid_CMP, GL_CND0_ATI, ckp_PS_BASE 77 SYMDEF sid_CND, GL_CND_ATI, ckp_PS_BASE 78 SYMDEF sid_DP3, GL_DOT3_ATI, ckp_PS_BASE 79 SYMDEF sid_DP4, GL_DOT4_ATI, ckp_PS_BASE 80 81 SYMDEF sid_DEF, GL_NONE, ckp_PS_BASE 82 83 // Masks 84 SYMDEF sid_R, GL_RED_BIT_ATI, ckp_PS_1_4 85 SYMDEF sid_RA, GL_RED_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 86 SYMDEF sid_G, GL_GREEN_BIT_ATI, ckp_PS_1_4 87 SYMDEF sid_GA, GL_GREEN_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 88 SYMDEF sid_B, GL_BLUE_BIT_ATI, ckp_PS_1_4 89 SYMDEF sid_BA, GL_BLUE_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 90 SYMDEF sid_A, ALPHA_BIT, ckp_PS_BASE 91 SYMDEF sid_RGBA, RGB_BITS | ALPHA_BIT, ckp_PS_BASE 92 SYMDEF sid_RGB, RGB_BITS, ckp_PS_BASE 93 SYMDEF sid_RG, GL_RED_BIT_ATI | GL_GREEN_BIT_ATI, ckp_PS_1_4 94 SYMDEF sid_RGA, GL_RED_BIT_ATI | GL_GREEN_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 95 SYMDEF sid_RB, GL_RED_BIT_ATI | GL_BLUE_BIT_ATI, ckp_PS_1_4 96 SYMDEF sid_RBA, GL_RED_BIT_ATI | GL_BLUE_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 97 SYMDEF sid_GB, GL_GREEN_BIT_ATI | GL_BLUE_BIT_ATI, ckp_PS_1_4 98 SYMDEF sid_GBA, GL_GREEN_BIT_ATI | GL_BLUE_BIT_ATI | ALPHA_BIT, ckp_PS_1_4 99 100 // Rep 101 SYMDEF sid_RRRR, GL_RED, ckp_PS_1_4 102 SYMDEF sid_GGGG, GL_GREEN, ckp_PS_1_4 103 SYMDEF sid_BBBB, GL_BLUE, ckp_PS_BASE 104 SYMDEF sid_AAAA, GL_ALPHA, ckp_PS_BASE 105 106 107 // modifiers 108 SYMDEF sid_X2, GL_2X_BIT_ATI, ckp_PS_BASE 109 SYMDEF sid_X4, GL_4X_BIT_ATI, ckp_PS_BASE 110 SYMDEF sid_D2, GL_HALF_BIT_ATI, ckp_PS_BASE 111 SYMDEF sid_SAT, GL_SATURATE_BIT_ATI, ckp_PS_BASE 112 113 // argument modifiers 114 SYMDEF sid_BIAS, GL_BIAS_BIT_ATI, ckp_PS_BASE 115 SYMDEF sid_INVERT, GL_COMP_BIT_ATI, ckp_PS_BASE 116 SYMDEF sid_NEGATE, GL_NEGATE_BIT_ATI, ckp_PS_BASE 117 SYMDEF sid_BX2, GL_2X_BIT_ATI | GL_BIAS_BIT_ATI, ckp_PS_BASE 118 119 // seperator characters 120 SYMDEF sid_COMMA, GL_NONE, ckp_PS_BASE 121 SYMDEF sid_VALUE, GL_NONE, ckp_PS_BASE 122 123 // PS_1_4 124 // temp R/W registers 125 SYMDEF sid_R0, GL_REG_0_ATI, ckp_PS_1_4 126 SYMDEF sid_R1, GL_REG_1_ATI, ckp_PS_1_4 127 SYMDEF sid_R2, GL_REG_2_ATI, ckp_PS_1_4 128 SYMDEF sid_R3, GL_REG_3_ATI, ckp_PS_1_4 129 SYMDEF sid_R4, GL_REG_4_ATI, ckp_PS_1_4 130 SYMDEF sid_R5, GL_REG_5_ATI, ckp_PS_1_4 131 132 // textures 133 SYMDEF sid_T0, GL_TEXTURE0_ARB, ckp_PS_1_4 134 SYMDEF sid_T1, GL_TEXTURE1_ARB, ckp_PS_1_4 135 SYMDEF sid_T2, GL_TEXTURE2_ARB, ckp_PS_1_4 136 SYMDEF sid_T3, GL_TEXTURE3_ARB, ckp_PS_1_4 137 SYMDEF sid_T4, GL_TEXTURE4_ARB, ckp_PS_1_4 138 SYMDEF sid_T5, GL_TEXTURE5_ARB, ckp_PS_1_4 139 SYMDEF sid_DP2ADD, GL_DOT2_ADD_ATI, ckp_PS_1_4 140 141 // modifiers 142 SYMDEF sid_X8, GL_8X_BIT_ATI, ckp_PS_1_4 143 SYMDEF sid_D8, GL_EIGHTH_BIT_ATI, ckp_PS_1_4 144 SYMDEF sid_D4, GL_QUARTER_BIT_ATI, ckp_PS_1_4 145 146 // instructions 147 SYMDEF sid_TEXCRD, GL_NONE, ckp_PS_1_4 148 SYMDEF sid_TEXLD, GL_NONE, ckp_PS_1_4 149 150 // texture swizzlers 151 152 SYMDEF sid_STR, GL_SWIZZLE_STR_ATI - GL_SWIZZLE_STR_ATI, ckp_PS_1_4 153 SYMDEF sid_STQ, GL_SWIZZLE_STQ_ATI - GL_SWIZZLE_STR_ATI, ckp_PS_1_4 154 SYMDEF sid_STRDR, GL_SWIZZLE_STR_DR_ATI - GL_SWIZZLE_STR_ATI, ckp_PS_1_4 155 SYMDEF sid_STQDQ, GL_SWIZZLE_STQ_DQ_ATI - GL_SWIZZLE_STR_ATI, ckp_PS_1_4 156 157 SYMDEF sid_BEM, GL_NONE, ckp_PS_1_4 158 SYMDEF sid_PHASE, GL_NONE, ckp_PS_1_4 159 160 // PS_1_1 161 // temp R/W registers 162 // r0, r1 are mapped to r4, r5 163 // t0 to t3 are mapped to r0 to r3 164 SYMDEF sid_1R0, GL_REG_4_ATI, ckp_PS_1_1 165 SYMDEF sid_1R1, GL_REG_5_ATI, ckp_PS_1_1 166 SYMDEF sid_1T0, GL_REG_0_ATI, ckp_PS_1_1 167 SYMDEF sid_1T1, GL_REG_1_ATI, ckp_PS_1_1 168 SYMDEF sid_1T2, GL_REG_2_ATI, ckp_PS_1_1 169 SYMDEF sid_1T3, GL_REG_3_ATI, ckp_PS_1_1 170 171 // instructions common to PS_1_1, PS_1_2, PS_1_3 172 SYMDEF sid_TEX, GL_NONE, ckp_PS_1_1 173 SYMDEF sid_TEXCOORD, GL_NONE, ckp_PS_1_1 174 SYMDEF sid_TEXM3X2PAD, GL_NONE, ckp_PS_1_1 175 SYMDEF sid_TEXM3X2TEX, GL_NONE, ckp_PS_1_1 176 SYMDEF sid_TEXM3X3PAD, GL_NONE, ckp_PS_1_1 177 SYMDEF sid_TEXM3X3TEX, GL_NONE, ckp_PS_1_1 178 SYMDEF sid_TEXM3X3SPEC, GL_NONE, ckp_PS_1_1 179 SYMDEF sid_TEXM3X3VSPEC, GL_NONE, ckp_PS_1_1 180 SYMDEF sid_TEXREG2AR, GL_NONE, ckp_PS_1_2 181 SYMDEF sid_TEXREG2GB, GL_NONE, ckp_PS_1_2 182 183 // PS_1_2 & PS_1_3 184 SYMDEF sid_TEXREG2RGB, GL_NONE, ckp_PS_1_2 185 SYMDEF sid_TEXDP3, GL_NONE, ckp_PS_1_2 186 SYMDEF sid_TEXDP3TEX, GL_NONE, ckp_PS_1_2 187 188 189 // Common 190 SYMDEF sid_SKIP, GL_NONE, ckp_PS_BASE 191 SYMDEF sid_PLUS, GL_NONE, ckp_PS_BASE 192 193 // Non-Terminal Tokens 194 SYMDEF sid_PROGRAM, GL_NONE, ckp_PS_BASE 195 SYMDEF sid_PROGRAMTYPE, GL_NONE, ckp_PS_BASE 196 SYMDEF sid_DECLCONSTS, GL_NONE, ckp_PS_BASE 197 SYMDEF sid_DEFCONST, GL_NONE, ckp_PS_BASE 198 SYMDEF sid_CONSTANT, GL_NONE, ckp_PS_BASE 199 SYMDEF sid_COLOR, GL_NONE, ckp_PS_BASE 200 SYMDEF sid_TEXSWIZZLE, GL_NONE, ckp_PS_BASE 201 SYMDEF sid_UNARYOP, GL_NONE, ckp_PS_BASE 202 SYMDEF sid_NUMVAL, GL_NONE, ckp_PS_BASE 203 SYMDEF sid_SEPERATOR, GL_NONE, ckp_PS_BASE 204 SYMDEF sid_ALUOPS, GL_NONE, ckp_PS_BASE 205 SYMDEF sid_TEXMASK, GL_NONE, ckp_PS_BASE 206 SYMDEF sid_TEXOP_PS1_1_3, GL_NONE, ckp_PS_1_1 207 SYMDEF sid_TEXOP_PS1_4, GL_NONE, ckp_PS_1_4 208 SYMDEF sid_ALU_STATEMENT, GL_NONE, ckp_PS_BASE 209 SYMDEF sid_DSTMODSAT, GL_NONE, ckp_PS_BASE 210 SYMDEF sid_UNARYOP_ARGS, GL_NONE, ckp_PS_BASE 211 SYMDEF sid_REG_PS1_4, GL_NONE, ckp_PS_1_4 212 SYMDEF sid_TEX_PS1_4, GL_NONE, ckp_PS_1_4 213 SYMDEF sid_REG_PS1_1_3, GL_NONE, ckp_PS_1_1 214 SYMDEF sid_TEX_PS1_1_3, GL_NONE, ckp_PS_1_1 215 SYMDEF sid_DSTINFO, GL_NONE, ckp_PS_BASE 216 SYMDEF sid_SRCINFO, GL_NONE, ckp_PS_BASE 217 SYMDEF sid_BINARYOP_ARGS, GL_NONE, ckp_PS_BASE 218 SYMDEF sid_TERNARYOP_ARGS, GL_NONE, ckp_PS_BASE 219 SYMDEF sid_TEMPREG, GL_NONE, ckp_PS_BASE 220 SYMDEF sid_DSTMASK, GL_NONE, ckp_PS_BASE 221 SYMDEF sid_PRESRCMOD, GL_NONE, ckp_PS_BASE 222 SYMDEF sid_SRCNAME, GL_NONE, ckp_PS_BASE 223 SYMDEF sid_SRCREP, GL_NONE, ckp_PS_BASE 224 SYMDEF sid_POSTSRCMOD, GL_NONE, ckp_PS_BASE 225 SYMDEF sid_DSTMOD, GL_NONE, ckp_PS_BASE 226 SYMDEF sid_DSTSAT, GL_NONE, ckp_PS_BASE 227 SYMDEF sid_BINARYOP, GL_NONE, ckp_PS_BASE 228 SYMDEF sid_TERNARYOP, GL_NONE, ckp_PS_BASE 229 SYMDEF sid_TEXOPS_PHASE1, GL_NONE, ckp_PS_BASE 230 SYMDEF sid_COISSUE, GL_NONE, ckp_PS_BASE 231 SYMDEF sid_PHASEMARKER, GL_NONE, ckp_PS_1_4 232 SYMDEF sid_TEXOPS_PHASE2, GL_NONE, ckp_PS_1_4 233 SYMDEF sid_TEXREG_PS1_4, GL_NONE, ckp_PS_1_4 234 SYMDEF sid_TEXOPS_PS1_4, GL_NONE, ckp_PS_1_4 235 SYMDEF sid_TEXOPS_PS1_1_3, GL_NONE, ckp_PS_1_1 236 SYMDEF sid_TEXCISCOP_PS1_1_3, GL_NONE, ckp_PS_1_1 237 SYMEND 238 }; 239 240 241 // Rule Path Database for ps.1.x code based on extended Backus Naur Form notation 242 243 // <> - non-terminal token 244 #define _rule_ {otRULE, // ::= - rule definition 245 #define _is_ ,0},{otAND, 246 #define _and_ ,0},{otAND, // - blank space is an implied "AND" meaning the token is required 247 #define _or_ ,0},{otOR, // | - or 248 #define _optional_ ,0},{otOPTIONAL, // [] - optional 249 #define _repeat_ ,0},{otREPEAT, // {} - repeat until fail 250 #define _end_ ,0},{otEND,0,0,0}, 251 #define _nt_ ,0 252 // " " - terminal token string 253 254 PS_1_4::TokenRule PS_1_4::PS_1_x_RulePath[] = { 255 256 _rule_ sid_PROGRAM, "Program" 257 258 _is_ sid_PROGRAMTYPE _nt_ 259 _optional_ sid_DECLCONSTS _nt_ 260 _optional_ sid_TEXOPS_PHASE1 _nt_ 261 _optional_ sid_ALUOPS _nt_ 262 _optional_ sid_PHASEMARKER _nt_ 263 _optional_ sid_TEXOPS_PHASE2 _nt_ 264 _optional_ sid_ALUOPS _nt_ 265 _end_ 266 267 _rule_ sid_PROGRAMTYPE, "<ProgramType>" 268 269 _is_ sid_PS_1_4, "ps.1.4" 270 _or_ sid_PS_1_1, "ps.1.1" 271 _or_ sid_PS_1_2, "ps.1.2" 272 _or_ sid_PS_1_3, "ps.1.3" 273 _end_ 274 275 _rule_ sid_PHASEMARKER, "<PhaseMarker>" 276 277 _is_ sid_PHASE, "phase" 278 _end_ 279 280 _rule_ sid_DECLCONSTS, "<DeclareConstants>" 281 282 _repeat_ sid_DEFCONST _nt_ 283 _end_ 284 285 286 _rule_ sid_TEXOPS_PHASE1, "<TexOps_Phase1>" 287 288 _is_ sid_TEXOPS_PS1_1_3 _nt_ 289 _or_ sid_TEXOPS_PS1_4 _nt_ 290 _end_ 291 292 _rule_ sid_TEXOPS_PHASE2, "<TexOps_Phase2>" 293 294 _is_ sid_TEXOPS_PS1_4 _nt_ 295 _end_ 296 297 _rule_ sid_NUMVAL, "<NumVal>" 298 299 _is_ sid_VALUE, "Float Value" 300 _end_ 301 302 _rule_ sid_TEXOPS_PS1_1_3, "<TexOps_PS1_1_3>" 303 304 _repeat_ sid_TEXOP_PS1_1_3 _nt_ 305 _end_ 306 307 _rule_ sid_TEXOPS_PS1_4, "<TexOps_PS1_4>" 308 309 _repeat_ sid_TEXOP_PS1_4 _nt_ 310 _end_ 311 312 _rule_ sid_TEXOP_PS1_1_3, "<TexOp_PS1_1_3>" 313 314 _is_ sid_TEXCISCOP_PS1_1_3 _nt_ 315 _and_ sid_TEX_PS1_1_3 _nt_ 316 _and_ sid_SEPERATOR _nt_ 317 _and_ sid_TEX_PS1_1_3 _nt_ 318 319 _or_ sid_TEXCOORD, "texcoord" 320 _and_ sid_TEX_PS1_1_3 _nt_ 321 322 _or_ sid_TEX, "tex" 323 _and_ sid_TEX_PS1_1_3 _nt_ 324 325 326 327 _end_ 328 329 _rule_ sid_TEXOP_PS1_4, "<TexOp_PS1_4>" 330 331 _is_ sid_TEXCRD, "texcrd" 332 _and_ sid_REG_PS1_4 _nt_ 333 _optional_ sid_TEXMASK _nt_ 334 _and_ sid_SEPERATOR _nt_ 335 _and_ sid_TEXREG_PS1_4 _nt_ 336 337 _or_ sid_TEXLD, "texld" 338 _and_ sid_REG_PS1_4 _nt_ 339 _optional_ sid_TEXMASK _nt_ 340 _and_ sid_SEPERATOR _nt_ 341 _and_ sid_TEXREG_PS1_4 _nt_ 342 _end_ 343 344 _rule_ sid_ALUOPS, "<ALUOps>" 345 346 _repeat_ sid_ALU_STATEMENT _nt_ 347 _end_ 348 349 _rule_ sid_ALU_STATEMENT, "<ALUStatement>" 350 351 _is_ sid_COISSUE _nt_ 352 _and_ sid_UNARYOP _nt_ 353 _optional_ sid_DSTMODSAT _nt_ 354 _and_ sid_UNARYOP_ARGS _nt_ 355 356 _or_ sid_COISSUE _nt_ 357 _and_ sid_BINARYOP _nt_ 358 _optional_ sid_DSTMODSAT _nt_ 359 _and_ sid_BINARYOP_ARGS _nt_ 360 361 _or_ sid_COISSUE _nt_ 362 _and_ sid_TERNARYOP _nt_ 363 _optional_ sid_DSTMODSAT _nt_ 364 _and_ sid_TERNARYOP_ARGS _nt_ 365 _end_ 366 367 368 _rule_ sid_TEXREG_PS1_4, "<TexReg_PS1_4>" 369 370 _is_ sid_TEX_PS1_4 _nt_ 371 _optional_ sid_TEXSWIZZLE _nt_ 372 _or_ sid_REG_PS1_4 _nt_ 373 _optional_ sid_TEXSWIZZLE _nt_ 374 _end_ 375 376 _rule_ sid_UNARYOP_ARGS, "<UnaryOpArgs>" 377 378 _is_ sid_DSTINFO _nt_ 379 _and_ sid_SRCINFO _nt_ 380 _end_ 381 382 _rule_ sid_BINARYOP_ARGS, "<BinaryOpArgs>" 383 384 _is_ sid_DSTINFO _nt_ 385 _and_ sid_SRCINFO _nt_ 386 _and_ sid_SRCINFO _nt_ 387 _end_ 388 389 _rule_ sid_TERNARYOP_ARGS, "<TernaryOpArgs>" 390 391 _is_ sid_DSTINFO _nt_ 392 _and_ sid_SRCINFO _nt_ 393 _and_ sid_SRCINFO _nt_ 394 _and_ sid_SRCINFO _nt_ 395 _end_ 396 397 _rule_ sid_DSTINFO, "<DstInfo>" 398 399 _is_ sid_TEMPREG _nt_ 400 _optional_ sid_DSTMASK _nt_ 401 _end_ 402 403 _rule_ sid_SRCINFO, "<SrcInfo>" 404 405 _is_ sid_SEPERATOR _nt_ 406 _optional_ sid_PRESRCMOD _nt_ 407 _and_ sid_SRCNAME _nt_ 408 _optional_ sid_POSTSRCMOD _nt_ 409 _optional_ sid_SRCREP _nt_ 410 _end_ 411 412 _rule_ sid_SRCNAME, "<SrcName>" 413 414 _is_ sid_TEMPREG _nt_ 415 _or_ sid_CONSTANT _nt_ 416 _or_ sid_COLOR _nt_ 417 _end_ 418 419 _rule_ sid_DEFCONST, "<DefineConstant>" 420 421 _is_ sid_DEF, "def" 422 _and_ sid_CONSTANT _nt_ 423 _and_ sid_SEPERATOR _nt_ 424 _and_ sid_NUMVAL _nt_ 425 _and_ sid_SEPERATOR _nt_ 426 _and_ sid_NUMVAL _nt_ 427 _and_ sid_SEPERATOR _nt_ 428 _and_ sid_NUMVAL _nt_ 429 _and_ sid_SEPERATOR _nt_ 430 _and_ sid_NUMVAL _nt_ 431 _end_ 432 433 _rule_ sid_CONSTANT, "<Constant>" 434 435 _is_ sid_C0, "c0" 436 _or_ sid_C1, "c1" 437 _or_ sid_C2, "c2" 438 _or_ sid_C3, "c3" 439 _or_ sid_C4, "c4" 440 _or_ sid_C5, "c5" 441 _or_ sid_C6, "c6" 442 _or_ sid_C7, "c7" 443 _end_ 444 445 446 _rule_ sid_TEXCISCOP_PS1_1_3, "<TexCISCOp_PS1_1_3>" 447 448 _is_ sid_TEXDP3TEX, "texdp3tex" 449 _or_ sid_TEXDP3, "texdp3" 450 _or_ sid_TEXM3X2PAD, "texm3x2pad" 451 _or_ sid_TEXM3X2TEX, "texm3x2tex" 452 _or_ sid_TEXM3X3PAD, "texm3x3pad" 453 _or_ sid_TEXM3X3TEX, "texm3x3tex" 454 _or_ sid_TEXM3X3SPEC, "texm3x3spec" 455 _or_ sid_TEXM3X3VSPEC, "texm3x3vspec" 456 _or_ sid_TEXREG2RGB, "texreg2rgb" 457 _or_ sid_TEXREG2AR, "texreg2ar" 458 _or_ sid_TEXREG2GB, "texreg2gb" 459 _end_ 460 461 462 _rule_ sid_TEXSWIZZLE, "<TexSwizzle>" 463 464 _is_ sid_STQDQ, "_dw.xyw" 465 _or_ sid_STQDQ, "_dw" 466 _or_ sid_STQDQ, "_da.rga" 467 _or_ sid_STQDQ, "_da" 468 _or_ sid_STRDR, "_dz.xyz" 469 _or_ sid_STRDR, "_dz" 470 _or_ sid_STRDR, "_db.rgb" 471 _or_ sid_STRDR, "_db" 472 _or_ sid_STR, ".xyz" 473 _or_ sid_STR, ".rgb" 474 _or_ sid_STQ, ".xyw" 475 _or_ sid_STQ, ".rga" 476 _end_ 477 478 _rule_ sid_TEXMASK, "<TexMask>" 479 480 _is_ sid_RGB, ".rgb" 481 _or_ sid_RGB, ".xyz" 482 _or_ sid_RG, ".rg" 483 _or_ sid_RG, ".xy" 484 _end_ 485 486 _rule_ sid_SEPERATOR, "<Seperator>" 487 488 _is_ sid_COMMA, "," 489 _end_ 490 491 _rule_ sid_REG_PS1_4, "<Reg_PS1_4>" 492 493 _is_ sid_R0, "r0" 494 _or_ sid_R1, "r1" 495 _or_ sid_R2, "r2" 496 _or_ sid_R3, "r3" 497 _or_ sid_R4, "r4" 498 _or_ sid_R5, "r5" 499 _end_ 500 501 _rule_ sid_TEX_PS1_4, "<Tex_PS1_4>" 502 503 _is_ sid_T0, "t0" 504 _or_ sid_T1, "t1" 505 _or_ sid_T2, "t2" 506 _or_ sid_T3, "t3" 507 _or_ sid_T4, "t4" 508 _or_ sid_T5, "t5" 509 _end_ 510 511 _rule_ sid_REG_PS1_1_3, "<Reg_PS1_1_3>" 512 513 _is_ sid_1R0, "r0" 514 _or_ sid_1R1, "r1" 515 _end_ 516 517 _rule_ sid_TEX_PS1_1_3, "<Tex_PS1_1_3>" 518 519 _is_ sid_1T0, "t0" 520 _or_ sid_1T1, "t1" 521 _or_ sid_1T2, "t2" 522 _or_ sid_1T3, "t3" 523 _end_ 524 525 _rule_ sid_COLOR, "<Color>" 526 527 _is_ sid_V0, "v0" 528 _or_ sid_V1, "v1" 529 _end_ 530 531 532 _rule_ sid_TEMPREG, "<TempReg>" 533 534 _is_ sid_REG_PS1_4 _nt_ 535 _or_ sid_REG_PS1_1_3 _nt_ 536 _or_ sid_TEX_PS1_1_3 _nt_ 537 _end_ 538 539 _rule_ sid_DSTMODSAT, "<DstModSat>" 540 541 _optional_ sid_DSTMOD _nt_ 542 _optional_ sid_DSTSAT _nt_ 543 _end_ 544 545 _rule_ sid_UNARYOP, "<UnaryOp>" 546 547 _is_ sid_MOV, "mov" 548 _end_ 549 550 _rule_ sid_BINARYOP, "<BinaryOP>" 551 552 _is_ sid_ADD, "add" 553 _or_ sid_MUL, "mul" 554 _or_ sid_SUB, "sub" 555 _or_ sid_DP3, "dp3" 556 _or_ sid_DP4, "dp4" 557 _or_ sid_BEM, "bem" 558 _end_ 559 560 _rule_ sid_TERNARYOP, "<TernaryOp>" 561 562 _is_ sid_MAD, "mad" 563 _or_ sid_LRP, "lrp" 564 _or_ sid_CND, "cnd" 565 _or_ sid_CMP, "cmp" 566 _end_ 567 568 _rule_ sid_DSTMASK, "<DstMask>" 569 570 _is_ sid_RGBA, ".rgba" 571 _or_ sid_RGBA, ".xyzw" 572 _or_ sid_RGB, ".rgb" 573 _or_ sid_RGB, ".xyz" 574 _or_ sid_RGA, ".xyw" 575 _or_ sid_RGA, ".rga" 576 _or_ sid_RBA, ".rba" 577 _or_ sid_RBA, ".xzw" 578 _or_ sid_GBA, ".gba" 579 _or_ sid_GBA, ".yzw" 580 _or_ sid_RG, ".rg" 581 _or_ sid_RG, ".xy" 582 _or_ sid_RB, ".xz" 583 _or_ sid_RB, ".rb" 584 _or_ sid_RA, ".xw" 585 _or_ sid_RA, ".ra" 586 _or_ sid_GB, ".gb" 587 _or_ sid_GB, ".yz" 588 _or_ sid_GA, ".yw" 589 _or_ sid_GA, ".ga" 590 _or_ sid_BA, ".zw" 591 _or_ sid_BA, ".ba" 592 _or_ sid_R, ".r" 593 _or_ sid_R, ".x" 594 _or_ sid_G, ".g" 595 _or_ sid_G, ".y" 596 _or_ sid_B, ".b" 597 _or_ sid_B, ".z" 598 _or_ sid_A, ".a" 599 _or_ sid_A, ".w" 600 _end_ 601 602 _rule_ sid_SRCREP, "<SrcRep>" 603 604 _is_ sid_RRRR, ".r" 605 _or_ sid_RRRR, ".x" 606 _or_ sid_GGGG, ".g" 607 _or_ sid_GGGG, ".y" 608 _or_ sid_BBBB, ".b" 609 _or_ sid_BBBB, ".z" 610 _or_ sid_AAAA, ".a" 611 _or_ sid_AAAA, ".w" 612 _end_ 613 614 _rule_ sid_PRESRCMOD, "<PreSrcMod>" 615 616 _is_ sid_INVERT, "1-" 617 _or_ sid_INVERT, "1 -" 618 _or_ sid_NEGATE, "-" 619 _end_ 620 621 _rule_ sid_POSTSRCMOD, "<PostSrcMod>" 622 623 _is_ sid_BX2, "_bx2" 624 _or_ sid_X2, "_x2" 625 _or_ sid_BIAS, "_bias" 626 _end_ 627 628 _rule_ sid_DSTMOD, "<DstMod>" 629 630 _is_ sid_X2, "_x2" 631 _or_ sid_X4, "_x4" 632 _or_ sid_D2, "_d2" 633 _or_ sid_X8, "_x8" 634 _or_ sid_D4, "_d4" 635 _or_ sid_D8, "_d8" 636 _end_ 637 638 _rule_ sid_DSTSAT, "<DstSat>" 639 640 _is_ sid_SAT, "_sat" 641 _end_ 642 643 _rule_ sid_COISSUE, "<CoIssue>" 644 645 _optional_ sid_PLUS, "+" 646 _end_ 647 648 }; 649 650 //***************************** MACROs for PS1_1 , PS1_2, PS1_3 CISC instructions ************************************** 651 652 // macro to make the macro text data easier to read 653 #define _token_ ,0,0},{ 654 #define _token_end_ ,0,0} 655 // macro token expansion for ps_1_2 instruction: texreg2ar 656 PS_1_4::TokenInst PS_1_4::texreg2ar[] = { 657 // mov r(x).r, r(y).a 658 { sid_UNARYOP, sid_MOV 659 _token_ sid_REG_PS1_4, sid_R1 660 _token_ sid_DSTMASK, sid_R 661 _token_ sid_SEPERATOR, sid_COMMA 662 _token_ sid_REG_PS1_4, sid_R0 663 _token_ sid_SRCREP, sid_AAAA 664 665 // mov r(x).g, r(y).r 666 _token_ sid_UNARYOP, sid_MOV 667 _token_ sid_REG_PS1_4, sid_R1 668 _token_ sid_DSTMASK, sid_G 669 _token_ sid_SEPERATOR, sid_COMMA 670 _token_ sid_REG_PS1_4, sid_R0 671 _token_ sid_SRCREP, sid_RRRR 672 673 // texld r(x), r(x) 674 _token_ sid_TEXOP_PS1_4, sid_TEXLD 675 _token_ sid_REG_PS1_4, sid_R1 676 _token_ sid_SEPERATOR, sid_COMMA 677 _token_ sid_REG_PS1_4, sid_R1 678 _token_end_ 679 }; 680 681 PS_1_4::RegModOffset PS_1_4::texreg2xx_RegMods[] = { 682 {1, R_BASE, 0}, 683 {7, R_BASE, 0}, 684 {13, R_BASE, 0}, 685 {15, R_BASE, 0}, 686 {4, R_BASE, 1}, 687 {10, R_BASE, 1}, 688 689 }; 690 691 PS_1_4::MacroRegModify PS_1_4::texreg2ar_MacroMods = { 692 texreg2ar, ARRAYSIZE(texreg2ar), 693 texreg2xx_RegMods, ARRAYSIZE(texreg2xx_RegMods) 694 }; 695 696 // macro token expansion for ps_1_2 instruction: texreg2gb 697 PS_1_4::TokenInst PS_1_4::texreg2gb[] = { 698 // mov r(x).r, r(y).g 699 { sid_UNARYOP, sid_MOV 700 _token_ sid_REG_PS1_4, sid_R1 701 _token_ sid_DSTMASK, sid_R 702 _token_ sid_SEPERATOR, sid_COMMA 703 _token_ sid_REG_PS1_4, sid_R0 704 _token_ sid_SRCREP, sid_GGGG 705 706 // mov r(x).g, r(y).b 707 _token_ sid_UNARYOP, sid_MOV 708 _token_ sid_REG_PS1_4, sid_R1 709 _token_ sid_DSTMASK, sid_G 710 _token_ sid_SEPERATOR, sid_COMMA 711 _token_ sid_REG_PS1_4, sid_R0 712 _token_ sid_SRCREP, sid_BBBB 713 714 // texld r(x), r(x) 715 _token_ sid_TEXOP_PS1_4, sid_TEXLD 716 _token_ sid_REG_PS1_4, sid_R1 717 _token_ sid_SEPERATOR, sid_COMMA 718 _token_ sid_REG_PS1_4, sid_R1 719 _token_end_ 720 }; 721 722 PS_1_4::MacroRegModify PS_1_4::texreg2gb_MacroMods = { 723 texreg2gb, ARRAYSIZE(texreg2gb), 724 texreg2xx_RegMods, ARRAYSIZE(texreg2xx_RegMods) 725 }; 726 727 728 // macro token expansion for ps_1_1 instruction: texdp3 729 PS_1_4::TokenInst PS_1_4::texdp3[] = { 730 // texcoord t(x) 731 { sid_TEXOP_PS1_1_3, sid_TEXCOORD 732 _token_ sid_TEX_PS1_1_3, sid_1T1 733 734 // dp3 r(x), r(x), r(y) 735 _token_ sid_BINARYOP, sid_DP3 736 _token_ sid_REG_PS1_4, sid_R1 737 _token_ sid_SEPERATOR, sid_COMMA 738 _token_ sid_REG_PS1_4, sid_R1 739 _token_ sid_SEPERATOR, sid_COMMA 740 _token_ sid_REG_PS1_4, sid_R0 741 _token_end_ 742 }; 743 744 745 PS_1_4::RegModOffset PS_1_4::texdp3_RegMods[] = { 746 {1, T_BASE, 0}, 747 {3, R_BASE, 0}, 748 {5, R_BASE, 0}, 749 {7, R_BASE, 1}, 750 751 }; 752 753 754 PS_1_4::MacroRegModify PS_1_4::texdp3_MacroMods = { 755 texdp3, ARRAYSIZE(texdp3), 756 texdp3_RegMods, ARRAYSIZE(texdp3_RegMods) 757 }; 758 759 760 // macro token expansion for ps_1_1 instruction: texdp3tex 761 PS_1_4::TokenInst PS_1_4::texdp3tex[] = { 762 // texcoord t(x) 763 { sid_TEXOP_PS1_1_3, sid_TEXCOORD 764 _token_ sid_TEX_PS1_1_3, sid_1T1 765 766 // dp3 r1, r(x), r(y) 767 _token_ sid_BINARYOP, sid_DP3 768 _token_ sid_REG_PS1_4, sid_R1 769 _token_ sid_SEPERATOR, sid_COMMA 770 _token_ sid_REG_PS1_4, sid_R1 771 _token_ sid_SEPERATOR, sid_COMMA 772 _token_ sid_REG_PS1_4, sid_R0 773 774 // texld r(x), r(x) 775 _token_ sid_TEXOP_PS1_4, sid_TEXLD 776 _token_ sid_REG_PS1_4, sid_R1 777 _token_ sid_SEPERATOR, sid_COMMA 778 _token_ sid_REG_PS1_4, sid_R1 779 _token_end_ 780 }; 781 782 783 PS_1_4::RegModOffset PS_1_4::texdp3tex_RegMods[] = { 784 {1, T_BASE, 0}, 785 {3, R_BASE, 0}, 786 {5, R_BASE, 0}, 787 {7, R_BASE, 1}, 788 {9, R_BASE, 1}, 789 {11, R_BASE, 1}, 790 791 }; 792 793 794 PS_1_4::MacroRegModify PS_1_4::texdp3tex_MacroMods = { 795 texdp3tex, ARRAYSIZE(texdp3tex), 796 texdp3tex_RegMods, ARRAYSIZE(texdp3tex_RegMods) 797 }; 798 799 800 // macro token expansion for ps_1_1 instruction: texm3x2pad 801 PS_1_4::TokenInst PS_1_4::texm3x2pad[] = { 802 // texcoord t(x) 803 { sid_TEXOP_PS1_1_3, sid_TEXCOORD 804 _token_ sid_TEX_PS1_1_3, sid_1T0 805 806 // dp3 r4.r, r(x), r(y) 807 _token_ sid_BINARYOP, sid_DP3 808 _token_ sid_REG_PS1_4, sid_R4 809 _token_ sid_DSTMASK, sid_R 810 _token_ sid_SEPERATOR, sid_COMMA 811 _token_ sid_REG_PS1_4, sid_R1 812 _token_ sid_SEPERATOR, sid_COMMA 813 _token_ sid_REG_PS1_4, sid_R0 814 _token_end_ 815 816 }; 817 818 819 PS_1_4::RegModOffset PS_1_4::texm3xxpad_RegMods[] = { 820 {1, T_BASE, 0}, 821 {6, R_BASE, 0}, 822 {8, R_BASE, 1}, 823 }; 824 825 826 PS_1_4::MacroRegModify PS_1_4::texm3x2pad_MacroMods = { 827 texm3x2pad, ARRAYSIZE(texm3x2pad), 828 texm3xxpad_RegMods, ARRAYSIZE(texm3xxpad_RegMods) 829 }; 830 831 832 // macro token expansion for ps_1_1 instruction: texm3x2tex 833 PS_1_4::TokenInst PS_1_4::texm3x2tex[] = { 834 // texcoord t(x) 835 { sid_TEXOP_PS1_1_3, sid_TEXCOORD 836 _token_ sid_TEX_PS1_1_3, sid_1T1 837 838 // dp3 r4.g, r(x), r(y) 839 _token_ sid_BINARYOP, sid_DP3 840 _token_ sid_REG_PS1_4, sid_R4 841 _token_ sid_DSTMASK, sid_G 842 _token_ sid_SEPERATOR, sid_COMMA 843 _token_ sid_REG_PS1_4, sid_R1 844 _token_ sid_SEPERATOR, sid_COMMA 845 _token_ sid_REG_PS1_4, sid_R0 846 847 // texld r(x), r4 848 _token_ sid_TEXOP_PS1_4, sid_TEXLD 849 _token_ sid_REG_PS1_4, sid_R1 850 _token_ sid_SEPERATOR, sid_COMMA 851 _token_ sid_REG_PS1_4, sid_R4 852 _token_end_ 853 854 }; 855 856 PS_1_4::RegModOffset PS_1_4::texm3xxtex_RegMods[] = { 857 {1, T_BASE, 0}, 858 {6, R_BASE, 0}, 859 {8, R_BASE, 1}, 860 {10, R_BASE, 0} 861 }; 862 863 PS_1_4::MacroRegModify PS_1_4::texm3x2tex_MacroMods = { 864 texm3x2tex, ARRAYSIZE(texm3x2tex), 865 texm3xxtex_RegMods, ARRAYSIZE(texm3xxtex_RegMods) 866 }; 867 868 // macro token expansion for ps_1_1 instruction: texm3x3tex 869 PS_1_4::TokenInst PS_1_4::texm3x3pad[] = { 870 // texcoord t(x) 871 { sid_TEXOP_PS1_1_3, sid_TEXCOORD 872 _token_ sid_TEX_PS1_1_3, sid_1T0 873 874 // dp3 r4.b, r(x), r(y) 875 _token_ sid_BINARYOP, sid_DP3 876 _token_ sid_REG_PS1_4, sid_R4 877 _token_ sid_DSTMASK, sid_B 878 _token_ sid_SEPERATOR, sid_COMMA 879 _token_ sid_REG_PS1_4, sid_R1 880 _token_ sid_SEPERATOR, sid_COMMA 881 _token_ sid_REG_PS1_4, sid_R0 882 _token_end_ 883 884 }; 885 886 887 PS_1_4::MacroRegModify PS_1_4::texm3x3pad_MacroMods = { 888 texm3x3pad, ARRAYSIZE(texm3x3pad), 889 texm3xxpad_RegMods, ARRAYSIZE(texm3xxpad_RegMods) 890 }; 891 892 893 // macro token expansion for ps_1_1 instruction: texm3x3pad 894 PS_1_4::TokenInst PS_1_4::texm3x3tex[] = { 895 // texcoord t(x) 896 { sid_TEXOP_PS1_1_3, sid_TEXCOORD 897 _token_ sid_TEX_PS1_1_3, sid_1T1 898 899 // dp3 r4.b, r(x), r(y) 900 _token_ sid_BINARYOP, sid_DP3 901 _token_ sid_REG_PS1_4, sid_R4 902 _token_ sid_DSTMASK, sid_B 903 _token_ sid_SEPERATOR, sid_COMMA 904 _token_ sid_REG_PS1_4, sid_R1 905 _token_ sid_SEPERATOR, sid_COMMA 906 _token_ sid_REG_PS1_4, sid_R0 907 908 // texld r1, r4 909 _token_ sid_TEXOP_PS1_4, sid_TEXLD 910 _token_ sid_REG_PS1_4, sid_R1 911 _token_ sid_SEPERATOR, sid_COMMA 912 _token_ sid_REG_PS1_4, sid_R4 913 _token_end_ 914 }; 915 916 917 918 919 920 921 PS_1_4::MacroRegModify PS_1_4::texm3x3tex_MacroMods = { 922 texm3x3tex, ARRAYSIZE(texm3x3tex), 923 texm3xxtex_RegMods, ARRAYSIZE(texm3xxtex_RegMods) 924 }; 925 926 927 // macro token expansion for ps_1_1 instruction: texm3x3spec 928 PS_1_4::TokenInst PS_1_4::texm3x3spec[] = { 929 // texcoord t(x) 930 { sid_TEXOP_PS1_1_3, sid_TEXCOORD 931 _token_ sid_TEX_PS1_1_3, sid_1T3 932 933 // dp3 r4.b, r3, r(x) 934 _token_ sid_BINARYOP, sid_DP3 935 _token_ sid_REG_PS1_4, sid_R4 936 _token_ sid_DSTMASK, sid_B 937 _token_ sid_SEPERATOR, sid_COMMA 938 _token_ sid_REG_PS1_4, sid_R3 939 _token_ sid_SEPERATOR, sid_COMMA 940 _token_ sid_REG_PS1_4, sid_R0 941 942 // dp3_x2 r3, r4, c(x) 943 _token_ sid_BINARYOP, sid_DP3 944 _token_ sid_DSTMOD, sid_X2 945 _token_ sid_REG_PS1_4, sid_R3 946 _token_ sid_SEPERATOR, sid_COMMA 947 _token_ sid_REG_PS1_4, sid_R4 948 _token_ sid_SEPERATOR, sid_COMMA 949 _token_ sid_CONSTANT, sid_C0 950 951 // mul r3, r3, c(x) 952 _token_ sid_UNARYOP, sid_MUL 953 _token_ sid_REG_PS1_4, sid_R3 954 _token_ sid_SEPERATOR, sid_COMMA 955 _token_ sid_REG_PS1_4, sid_R3 956 _token_ sid_SEPERATOR, sid_COMMA 957 _token_ sid_CONSTANT, sid_C0 958 959 // dp3 r2, r4, r4 960 _token_ sid_BINARYOP, sid_DP3 961 _token_ sid_REG_PS1_4, sid_R2 962 _token_ sid_SEPERATOR, sid_COMMA 963 _token_ sid_REG_PS1_4, sid_R4 964 _token_ sid_SEPERATOR, sid_COMMA 965 _token_ sid_REG_PS1_4, sid_R4 966 967 // mad r4.rgb, 1-c(x), r2, r3 968 _token_ sid_TERNARYOP, sid_MAD 969 _token_ sid_REG_PS1_4, sid_R4 970 _token_ sid_DSTMASK, sid_RGB 971 _token_ sid_SEPERATOR, sid_COMMA 972 _token_ sid_PRESRCMOD, sid_INVERT 973 _token_ sid_CONSTANT, sid_C0 974 _token_ sid_SEPERATOR, sid_COMMA 975 _token_ sid_REG_PS1_4, sid_R2 976 _token_ sid_SEPERATOR, sid_COMMA 977 _token_ sid_REG_PS1_4, sid_R3 978 979 // + mov r4.a, r2.r 980 _token_ sid_UNARYOP, sid_MOV 981 _token_ sid_REG_PS1_4, sid_R4 982 _token_ sid_DSTMASK, sid_A 983 _token_ sid_SEPERATOR, sid_COMMA 984 _token_ sid_REG_PS1_4, sid_R2 985 _token_ sid_SRCREP, sid_RRRR 986 987 // texld r3, r4.xyz_dz 988 _token_ sid_TEXOP_PS1_4, sid_TEXLD 989 _token_ sid_REG_PS1_4, sid_R3 990 _token_ sid_SEPERATOR, sid_COMMA 991 _token_ sid_REG_PS1_4, sid_R4 992 _token_ sid_TEXSWIZZLE, sid_STRDR 993 _token_end_ 994 995 }; 996 997 PS_1_4::RegModOffset PS_1_4::texm3x3spec_RegMods[] = { 998 {8, R_BASE, 1}, 999 {15, R_BASE, 2}, 1000 {21, C_BASE, 2}, 1001 {33, C_BASE, 2}, 1002 1003 }; 1004 1005 PS_1_4::MacroRegModify PS_1_4::texm3x3spec_MacroMods = { 1006 texm3x3spec, ARRAYSIZE(texm3x3spec), 1007 texm3x3spec_RegMods, ARRAYSIZE(texm3x3spec_RegMods) 1008 }; 1009 1010 1011 /* ********************* END OF CLASS STATIC DATA ********************************* */ 1012 1013 PS_1_4::PS_1_4() 1014 { 1015 // allocate enough room for a large pixel shader 1016 mPhase1TEX_mi.reserve(50); 1017 mPhase2TEX_mi.reserve(30); 1018 mPhase1ALU_mi.reserve(100); 1019 mPhase2ALU_mi.reserve(100); 1020 1021 1022 mSymbolTypeLib = PS_1_4_SymbolTypeLib; 1023 mSymbolTypeLibCnt = ARRAYSIZE(PS_1_4_SymbolTypeLib); 1024 mRootRulePath = PS_1_x_RulePath; 1025 mRulePathLibCnt = ARRAYSIZE(PS_1_x_RulePath); 1026 // tell compiler what the symbol id is for a numeric value 1027 mValueID = sid_VALUE; 1028 // The type library must have text definitions initialized 1029 // before compiler is invoked 1030 1031 // only need to initialize the rule database once 1032 if(LibInitialized == false) { 1033 InitSymbolTypeLib(); 1034 LibInitialized = true; 1035 } 1036 1037 // set initial context to recognize PS base instructions 1038 mActiveContexts = ckp_PS_BASE; 1039 1040 } 1041 1042 1043 bool PS_1_4::bindMachineInstInPassToFragmentShader(const MachineInstContainer & PassMachineInstructions) 1044 { 1045 size_t instIDX = 0; 1046 size_t instCount = PassMachineInstructions.size(); 1047 bool error = false; 1048 1049 while ((instIDX < instCount) && !error) { 1050 switch(PassMachineInstructions[instIDX]) { 1051 case mi_COLOROP1: 1052 if((instIDX+7) < instCount) 1053 glColorFragmentOp1ATI(PassMachineInstructions[instIDX+1], // op 1054 PassMachineInstructions[instIDX+2], // dst 1055 PassMachineInstructions[instIDX+3], // dstMask 1056 PassMachineInstructions[instIDX+4], // dstMod 1057 PassMachineInstructions[instIDX+5], // arg1 1058 PassMachineInstructions[instIDX+6], // arg1Rep 1059 PassMachineInstructions[instIDX+7]);// arg1Mod 1060 instIDX += 8; 1061 break; 1062 1063 case mi_COLOROP2: 1064 if((instIDX+10) < instCount) 1065 glColorFragmentOp2ATI(PassMachineInstructions[instIDX+1], // op 1066 PassMachineInstructions[instIDX+2], // dst 1067 PassMachineInstructions[instIDX+3], // dstMask 1068 PassMachineInstructions[instIDX+4], // dstMod 1069 PassMachineInstructions[instIDX+5], // arg1 1070 PassMachineInstructions[instIDX+6], // arg1Rep 1071 PassMachineInstructions[instIDX+7], // arg1Mod 1072 PassMachineInstructions[instIDX+8], // arg2 1073 PassMachineInstructions[instIDX+9], // arg2Rep 1074 PassMachineInstructions[instIDX+10]);// arg2Mod 1075 instIDX += 11; 1076 break; 1077 1078 case mi_COLOROP3: 1079 if((instIDX+13) < instCount) 1080 glColorFragmentOp3ATI(PassMachineInstructions[instIDX+1], // op 1081 PassMachineInstructions[instIDX+2], // dst 1082 PassMachineInstructions[instIDX+3], // dstMask 1083 PassMachineInstructions[instIDX+4], // dstMod 1084 PassMachineInstructions[instIDX+5], // arg1 1085 PassMachineInstructions[instIDX+6], // arg1Rep 1086 PassMachineInstructions[instIDX+7], // arg1Mod 1087 PassMachineInstructions[instIDX+8], // arg2 1088 PassMachineInstructions[instIDX+9], // arg2Rep 1089 PassMachineInstructions[instIDX+10], // arg2Mod 1090 PassMachineInstructions[instIDX+11], // arg2 1091 PassMachineInstructions[instIDX+12], // arg2Rep 1092 PassMachineInstructions[instIDX+13]);// arg2Mod 1093 instIDX += 14; 1094 break; 1095 1096 case mi_ALPHAOP1: 1097 if((instIDX+6) < instCount) 1098 glAlphaFragmentOp1ATI(PassMachineInstructions[instIDX+1], // op 1099 PassMachineInstructions[instIDX+2], // dst 1100 PassMachineInstructions[instIDX+3], // dstMod 1101 PassMachineInstructions[instIDX+4], // arg1 1102 PassMachineInstructions[instIDX+5], // arg1Rep 1103 PassMachineInstructions[instIDX+6]); // arg1Mod 1104 instIDX += 7; 1105 break; 1106 1107 case mi_ALPHAOP2: 1108 if((instIDX+9) < instCount) 1109 glAlphaFragmentOp2ATI(PassMachineInstructions[instIDX+1], // op 1110 PassMachineInstructions[instIDX+2], // dst 1111 PassMachineInstructions[instIDX+3], // dstMod 1112 PassMachineInstructions[instIDX+4], // arg1 1113 PassMachineInstructions[instIDX+5], // arg1Rep 1114 PassMachineInstructions[instIDX+6], // arg1Mod 1115 PassMachineInstructions[instIDX+7], // arg2 1116 PassMachineInstructions[instIDX+8], // arg2Rep 1117 PassMachineInstructions[instIDX+9]); // arg2Mod 1118 instIDX += 10; 1119 break; 1120 1121 case mi_ALPHAOP3: 1122 if((instIDX+12) < instCount) 1123 glAlphaFragmentOp3ATI(PassMachineInstructions[instIDX+1], // op 1124 PassMachineInstructions[instIDX+2], // dst 1125 PassMachineInstructions[instIDX+3], // dstMod 1126 PassMachineInstructions[instIDX+4], // arg1 1127 PassMachineInstructions[instIDX+5], // arg1Rep 1128 PassMachineInstructions[instIDX+6], // arg1Mod 1129 PassMachineInstructions[instIDX+7], // arg2 1130 PassMachineInstructions[instIDX+8], // arg2Rep 1131 PassMachineInstructions[instIDX+9], // arg2Mod 1132 PassMachineInstructions[instIDX+10], // arg2 1133 PassMachineInstructions[instIDX+11], // arg2Rep 1134 PassMachineInstructions[instIDX+12]); // arg2Mod 1135 instIDX += 13; 1136 break; 1137 1138 case mi_SETCONSTANTS: 1139 if((instIDX+2) < instCount) 1140 glSetFragmentShaderConstantATI(PassMachineInstructions[instIDX+1], // dst 1141 &mConstants[PassMachineInstructions[instIDX+2]]); 1142 instIDX += 3; 1143 break; 1144 1145 case mi_PASSTEXCOORD: 1146 if((instIDX+3) < instCount) 1147 glPassTexCoordATI(PassMachineInstructions[instIDX+1], // dst 1148 PassMachineInstructions[instIDX+2], // coord 1149 PassMachineInstructions[instIDX+3]); // swizzle 1150 instIDX += 4; 1151 break; 1152 1153 case mi_SAMPLEMAP: 1154 if((instIDX+3) < instCount) 1155 glSampleMapATI(PassMachineInstructions[instIDX+1], // dst 1156 PassMachineInstructions[instIDX+2], // interp 1157 PassMachineInstructions[instIDX+3]); // swizzle 1158 instIDX += 4; 1159 break; 1160 1161 default: 1162 instIDX = instCount; 1163 // should generate an error since an unknown instruction was found 1164 // instead for now the bind process is terminated and the fragment program may still function 1165 // but its output may not be what was programmed 1166 1167 } // end of switch 1168 1169 error = (glGetError() != GL_NO_ERROR); 1170 }// end of while 1171 1172 return !error; 1173 1174 } 1175 1176 1177 size_t PS_1_4::getMachineInst( size_t Idx) 1178 { 1179 if (Idx < mPhase1TEX_mi.size()) { 1180 return mPhase1TEX_mi[Idx]; 1181 } 1182 else { 1183 Idx -= mPhase1TEX_mi.size(); 1184 if (Idx < mPhase1ALU_mi.size()) { 1185 return mPhase1ALU_mi[Idx]; 1186 } 1187 else { 1188 Idx -= mPhase1ALU_mi.size(); 1189 if (Idx < mPhase2TEX_mi.size()) { 1190 return mPhase2TEX_mi[Idx]; 1191 } 1192 else { 1193 Idx -= mPhase2TEX_mi.size(); 1194 if (Idx < mPhase2ALU_mi.size()) { 1195 return mPhase2ALU_mi[Idx]; 1196 } 1197 1198 } 1199 1200 } 1201 1202 } 1203 1204 return 0; 1205 1206 } 1207 1208 1209 void PS_1_4::addMachineInst(const PhaseType phase, const uint inst) 1210 { 1211 switch(phase) { 1212 1213 case ptPHASE1TEX: 1214 mPhase1TEX_mi.push_back(inst); 1215 break; 1216 1217 case ptPHASE1ALU: 1218 mPhase1ALU_mi.push_back(inst); 1219 break; 1220 1221 case ptPHASE2TEX: 1222 mPhase2TEX_mi.push_back(inst); 1223 1224 break; 1225 1226 case ptPHASE2ALU: 1227 mPhase2ALU_mi.push_back(inst); 1228 break; 1229 1230 1231 } // end switch(phase) 1232 1233 } 1234 1235 size_t PS_1_4::getMachineInstCount() 1236 { 1237 1238 return (mPhase1TEX_mi.size() + mPhase1ALU_mi.size() + mPhase2TEX_mi.size() + mPhase2ALU_mi.size()); 1239 } 1240 1241 1242 bool PS_1_4::bindAllMachineInstToFragmentShader() 1243 { 1244 bool passed; 1245 1246 // there are 4 machine instruction ques to pass to the ATI fragment shader 1247 passed = bindMachineInstInPassToFragmentShader(mPhase1TEX_mi); 1248 passed &= bindMachineInstInPassToFragmentShader(mPhase1ALU_mi); 1249 passed &= bindMachineInstInPassToFragmentShader(mPhase2TEX_mi); 1250 passed &= bindMachineInstInPassToFragmentShader(mPhase2ALU_mi); 1251 return passed; 1252 1253 } 1254 1255 1256 bool PS_1_4::expandMacro(const MacroRegModify & MacroMod) 1257 { 1258 1259 RegModOffset * regmod; 1260 1261 // set source and destination registers in macro expansion 1262 for (uint i = 0; i < MacroMod.RegModSize; i++) { 1263 regmod = &MacroMod.RegMods[i]; 1264 MacroMod.Macro[regmod->MacroOffset].mID = regmod->RegisterBase + mOpParrams[regmod->OpParramsIndex].Arg; 1265 1266 } 1267 1268 // turn macro support on so that ps.1.4 ALU instructions get put in phase 1 alu instruction sequence container 1269 mMacroOn = true; 1270 // pass macro tokens on to be turned into machine instructions 1271 // expand macro to ps.1.4 by doing recursive call to doPass2 1272 bool passed = Pass2scan(MacroMod.Macro, MacroMod.MacroSize); 1273 mMacroOn = false; 1274 1275 return passed; 1276 } 1277 1278 1279 bool PS_1_4::BuildMachineInst() 1280 { 1281 1282 // check the states to see if a machine instruction can be assembled 1283 1284 // assume all arguments have been set up 1285 bool passed = false; 1286 1287 1288 1289 passed = true; // assume everything will go okay until proven otherwise 1290 1291 // start with machine NOP instruction 1292 // this is used after the switch to see if an instruction was set up 1293 // determine which MachineInstID is required based on the op instruction 1294 mOpType = mi_NOP; 1295 1296 switch(mOpInst) { 1297 // ALU operations 1298 case sid_ADD: 1299 case sid_SUB: 1300 case sid_MUL: 1301 case sid_MAD: 1302 case sid_LRP: 1303 case sid_MOV: 1304 case sid_CMP: 1305 case sid_CND: 1306 case sid_DP2ADD: 1307 case sid_DP3: 1308 case sid_DP4: 1309 mOpType = (MachineInstID)(mi_COLOROP1 + mArgCnt - 1); 1310 1311 // if context is ps.1.x and Macro not on or a phase marker was found then put all ALU ops in phase 2 ALU container 1312 if (((mActiveContexts & ckp_PS_1_1) && !mMacroOn) || mPhaseMarkerFound) mInstructionPhase = ptPHASE2ALU; 1313 else mInstructionPhase = ptPHASE1ALU; 1314 // check for alpha op in destination register which is OpParrams[0] 1315 // if no Mask for destination then make it .rgba 1316 if(mOpParrams[0].MaskRep == 0) mOpParrams[0].MaskRep = 1317 GL_RED_BIT_ATI | GL_GREEN_BIT_ATI | GL_BLUE_BIT_ATI | ALPHA_BIT; 1318 if (mOpParrams[0].MaskRep & ALPHA_BIT) { 1319 mDo_Alpha = true; 1320 mOpParrams[0].MaskRep -= ALPHA_BIT; 1321 if(mOpParrams[0].MaskRep == 0) mOpType = mi_NOP; // only do alpha op 1322 } 1323 break; 1324 1325 case sid_TEXCRD: 1326 mOpType = mi_PASSTEXCOORD; 1327 if (mPhaseMarkerFound) mInstructionPhase = ptPHASE2TEX; 1328 else mInstructionPhase = ptPHASE1TEX; 1329 break; 1330 1331 case sid_TEXLD: 1332 mOpType = mi_SAMPLEMAP; 1333 if (mPhaseMarkerFound) mInstructionPhase = ptPHASE2TEX; 1334 else mInstructionPhase = ptPHASE1TEX; 1335 break; 1336 1337 case sid_TEX: // PS_1_1 emulation 1338 mOpType = mi_TEX; 1339 mInstructionPhase = ptPHASE1TEX; 1340 break; 1341 1342 case sid_TEXCOORD: // PS_1_1 emulation 1343 mOpType = mi_TEXCOORD; 1344 mInstructionPhase = ptPHASE1TEX; 1345 break; 1346 1347 case sid_TEXREG2AR: 1348 passed = expandMacro(texreg2ar_MacroMods); 1349 break; 1350 1351 case sid_TEXREG2GB: 1352 passed = expandMacro(texreg2gb_MacroMods); 1353 break; 1354 1355 case sid_TEXDP3: 1356 passed = expandMacro(texdp3_MacroMods); 1357 break; 1358 1359 case sid_TEXDP3TEX: 1360 passed = expandMacro(texdp3tex_MacroMods); 1361 break; 1362 1363 case sid_TEXM3X2PAD: 1364 passed = expandMacro(texm3x2pad_MacroMods); 1365 break; 1366 1367 case sid_TEXM3X2TEX: 1368 passed = expandMacro(texm3x2tex_MacroMods); 1369 break; 1370 1371 case sid_TEXM3X3PAD: 1372 // only 2 texm3x3pad instructions allowed 1373 // use count to modify macro to select which mask to use 1374 if(mTexm3x3padCount<2) { 1375 texm3x3pad[4].mID = sid_R + mTexm3x3padCount; 1376 mTexm3x3padCount++; 1377 passed = expandMacro(texm3x3pad_MacroMods); 1378 1379 } 1380 else passed = false; 1381 1382 break; 1383 1384 case sid_TEXM3X3TEX: 1385 passed = expandMacro(texm3x3tex_MacroMods); 1386 break; 1387 1388 case sid_DEF: 1389 mOpType = mi_SETCONSTANTS; 1390 mInstructionPhase = ptPHASE1TEX; 1391 break; 1392 1393 case sid_PHASE: // PS_1_4 only 1394 mPhaseMarkerFound = true; 1395 break; 1396 1397 } // end of switch 1398 1399 if(passed) passed = expandMachineInstruction(); 1400 1401 return passed; 1402 } 1403 1404 1405 bool PS_1_4::expandMachineInstruction() 1406 { 1407 // now push instructions onto MachineInstructions container 1408 // assume that an instruction will be expanded 1409 bool passed = true; 1410 1411 if (mOpType != mi_NOP) { 1412 1413 // a machine instruction will be built 1414 // this is currently the last one being built so keep track of it 1415 if (mInstructionPhase == ptPHASE2ALU) { 1416 mSecondLastInstructionPos = mLastInstructionPos; 1417 mLastInstructionPos = mPhase2ALU_mi.size(); 1418 } 1419 1420 1421 switch (mOpType) { 1422 case mi_COLOROP1: 1423 case mi_COLOROP2: 1424 case mi_COLOROP3: 1425 { 1426 addMachineInst(mInstructionPhase, mOpType); 1427 addMachineInst(mInstructionPhase, mSymbolTypeLib[mOpInst].mPass2Data); 1428 // send all parameters to machine inst container 1429 for(int i=0; i<=mArgCnt; i++) { 1430 addMachineInst(mInstructionPhase, mOpParrams[i].Arg); 1431 addMachineInst(mInstructionPhase, mOpParrams[i].MaskRep); 1432 addMachineInst(mInstructionPhase, mOpParrams[i].Mod); 1433 // check if source register read is valid in this phase 1434 passed &= isRegisterReadValid(mInstructionPhase, i); 1435 } 1436 1437 // record which registers were written to and in which phase 1438 // mOpParrams[0].Arg is always the destination register r0 -> r5 1439 updateRegisterWriteState(mInstructionPhase); 1440 1441 } 1442 break; 1443 1444 case mi_SETCONSTANTS: 1445 addMachineInst(mInstructionPhase, mOpType); 1446 addMachineInst(mInstructionPhase, mOpParrams[0].Arg); // dst 1447 addMachineInst(mInstructionPhase, mConstantsPos); // index into constants array 1448 break; 1449 1450 case mi_PASSTEXCOORD: 1451 case mi_SAMPLEMAP: 1452 // if source is a temp register than place instruction in phase 2 Texture ops 1453 if ((mOpParrams[1].Arg >= GL_REG_0_ATI) && (mOpParrams[1].Arg <= GL_REG_5_ATI)) { 1454 mInstructionPhase = ptPHASE2TEX; 1455 } 1456 1457 addMachineInst(mInstructionPhase, mOpType); 1458 addMachineInst(mInstructionPhase, mOpParrams[0].Arg); // dst 1459 addMachineInst(mInstructionPhase, mOpParrams[1].Arg); // coord 1460 addMachineInst(mInstructionPhase, mOpParrams[1].MaskRep + GL_SWIZZLE_STR_ATI); // swizzle 1461 // record which registers were written to and in which phase 1462 // mOpParrams[0].Arg is always the destination register r0 -> r5 1463 updateRegisterWriteState(mInstructionPhase); 1464 break; 1465 1466 case mi_TEX: // PS_1_1 emulation - turn CISC into RISC - phase 1 1467 addMachineInst(mInstructionPhase, mi_SAMPLEMAP); 1468 addMachineInst(mInstructionPhase, mOpParrams[0].Arg); // dst 1469 // tex tx becomes texld rx, tx with x: 0 - 3 1470 addMachineInst(mInstructionPhase, mOpParrams[0].Arg - GL_REG_0_ATI + GL_TEXTURE0_ARB); // interp 1471 // default to str which fills rgb of destination register 1472 addMachineInst(mInstructionPhase, GL_SWIZZLE_STR_ATI); // swizzle 1473 // record which registers were written to and in which phase 1474 // mOpParrams[0].Arg is always the destination register r0 -> r5 1475 updateRegisterWriteState(mInstructionPhase); 1476 break; 1477 1478 case mi_TEXCOORD: // PS_1_1 emulation - turn CISC into RISC - phase 1 1479 addMachineInst(mInstructionPhase, mi_PASSTEXCOORD); 1480 addMachineInst(mInstructionPhase, mOpParrams[0].Arg); // dst 1481 // texcoord tx becomes texcrd rx, tx with x: 0 - 3 1482 addMachineInst(mInstructionPhase, mOpParrams[0].Arg - GL_REG_0_ATI + GL_TEXTURE0_ARB); // interp 1483 // default to str which fills rgb of destination register 1484 addMachineInst(mInstructionPhase, GL_SWIZZLE_STR_ATI); // swizzle 1485 // record which registers were written to and in which phase 1486 // mOpParrams[0].Arg is always the destination register r0 -> r5 1487 updateRegisterWriteState(mInstructionPhase); 1488 break; 1489 1490 case mi_ALPHAOP1: 1491 case mi_ALPHAOP2: 1492 case mi_ALPHAOP3: 1493 case mi_TEXREG2RGB: 1494 case mi_NOP: 1495 break; 1496 1497 1498 } // end of switch (mOpType) 1499 } // end of if (mOpType != mi_NOP) 1500 1501 if(mDo_Alpha) { 1502 // process alpha channel 1503 // 1504 // a scaler machine instruction will be built 1505 // this is currently the last one being built so keep track of it 1506 if (mInstructionPhase == ptPHASE2ALU) { 1507 mSecondLastInstructionPos = mLastInstructionPos; 1508 mLastInstructionPos = mPhase2ALU_mi.size(); 1509 } 1510 1511 MachineInstID alphaoptype = (MachineInstID)(mi_ALPHAOP1 + mArgCnt - 1); 1512 addMachineInst(mInstructionPhase, alphaoptype); 1513 addMachineInst(mInstructionPhase, mSymbolTypeLib[mOpInst].mPass2Data); 1514 // put all parameters in instruction que 1515 for(int i=0; i<=mArgCnt; i++) { 1516 addMachineInst(mInstructionPhase, mOpParrams[i].Arg); 1517 // destination parameter has no mask since it is the alpha channel 1518 // don't push mask for parrameter 0 (dst) 1519 if(i>0) addMachineInst(mInstructionPhase, mOpParrams[i].MaskRep); 1520 addMachineInst(mInstructionPhase, mOpParrams[i].Mod); 1521 // check if source register read is valid in this phase 1522 passed &= isRegisterReadValid(mInstructionPhase, i); 1523 } 1524 1525 updateRegisterWriteState(mInstructionPhase); 1526 } 1527 1528 // instruction passed on to machine instruction so clear the pipe 1529 clearMachineInstState(); 1530 1531 return passed; 1532 1533 } 1534 1535 1536 void PS_1_4::updateRegisterWriteState(const PhaseType phase) 1537 { 1538 int reg_offset = mOpParrams[0].Arg - GL_REG_0_ATI; 1539 1540 switch(phase) { 1541 1542 case ptPHASE1TEX: 1543 case ptPHASE1ALU: 1544 Phase_RegisterUsage[reg_offset].Phase1Write = true; 1545 break; 1546 1547 case ptPHASE2TEX: 1548 case ptPHASE2ALU: 1549 Phase_RegisterUsage[reg_offset].Phase2Write = true; 1550 break; 1551 1552 } // end switch(phase) 1553 1554 } 1555 1556 1557 bool PS_1_4::isRegisterReadValid(const PhaseType phase, const int param) 1558 { 1559 bool passed = true; // assume everything will go alright 1560 // if in phase 2 ALU and argument is a source 1561 if((phase == ptPHASE2ALU) && (param>0)) { 1562 // is source argument a temp register r0 - r5? 1563 if((mOpParrams[param].Arg >= GL_REG_0_ATI) && (mOpParrams[param].Arg <= GL_REG_5_ATI)) { 1564 int reg_offset = mOpParrams[param].Arg - GL_REG_0_ATI; 1565 // if register was not written to in phase 2 but was in phase 1 1566 if((Phase_RegisterUsage[reg_offset].Phase2Write == false) && Phase_RegisterUsage[reg_offset].Phase1Write) { 1567 // only perform register pass if there are ALU instructions in phase 1 1568 1569 if(mPhase1ALU_mi.size() > 0) { 1570 // build machine instructions for passing a register from phase 1 to phase 2 1571 // NB: only rgb components of register will get passed 1572 1573 addMachineInst(ptPHASE2TEX, mi_PASSTEXCOORD); 1574 addMachineInst(ptPHASE2TEX, mOpParrams[param].Arg); // dst 1575 addMachineInst(ptPHASE2TEX, mOpParrams[param].Arg); // coord 1576 addMachineInst(ptPHASE2TEX, GL_SWIZZLE_STR_ATI); // swizzle 1577 // mark register as being written to 1578 Phase_RegisterUsage[reg_offset].Phase2Write = true; 1579 } 1580 1581 } 1582 // register can not be used because it has not been written to previously 1583 else passed = false; 1584 } 1585 1586 } 1587 1588 return passed; 1589 1590 } 1591 1592 1593 void PS_1_4::optimize() 1594 { 1595 // perform some optimizations on ps.1.1 machine instructions 1596 if (mActiveContexts & ckp_PS_1_1) { 1597 // need to check last few instructions to make sure r0 is set 1598 // ps.1.1 emulation uses r4 for r0 so last couple of instructions will probably require 1599 // changine destination register back to r0 1600 if (mLastInstructionPos < mPhase2ALU_mi.size()) { 1601 // first argument at mLastInstructionPos + 2 is destination register for all ps.1.1 ALU instructions 1602 mPhase2ALU_mi[mLastInstructionPos + 2] = GL_REG_0_ATI; 1603 // if was an alpha op only then modify second last instruction destination register 1604 if ((mPhase2ALU_mi[mLastInstructionPos] == mi_ALPHAOP1) || 1605 (mPhase2ALU_mi[mLastInstructionPos] == mi_ALPHAOP2) || 1606 (mPhase2ALU_mi[mLastInstructionPos] == mi_ALPHAOP3) 1607 1608 ) { 1609 1610 mPhase2ALU_mi[mSecondLastInstructionPos + 2] = GL_REG_0_ATI; 1611 } 1612 1613 }// end if (mLastInstructionPos < mMachineInstructions.size()) 1614 1615 }// end if (mActiveContexts & ckp_PS_1_1) 1616 1617 } 1618 1619 1620 void PS_1_4::clearMachineInstState() 1621 { 1622 // set current Machine Instruction State to baseline 1623 mOpType = mi_NOP; 1624 mOpInst = sid_INVALID; 1625 mDo_Alpha = false; 1626 mArgCnt = 0; 1627 1628 for(int i=0; i<MAXOPPARRAMS; i++) { 1629 mOpParrams[i].Arg = GL_NONE; 1630 mOpParrams[i].Filled = false; 1631 mOpParrams[i].MaskRep = GL_NONE; 1632 mOpParrams[i].Mod = GL_NONE; 1633 } 1634 1635 } 1636 1637 1638 void PS_1_4::clearAllMachineInst() 1639 { 1640 1641 mPhase1TEX_mi.clear(); 1642 mPhase1ALU_mi.clear(); 1643 mPhase2TEX_mi.clear(); 1644 mPhase2ALU_mi.clear(); 1645 1646 // reset write state for all registers 1647 for(int i = 0; i<6; i++) { 1648 Phase_RegisterUsage[i].Phase1Write = false; 1649 Phase_RegisterUsage[i].Phase2Write = false; 1650 1651 } 1652 1653 mPhaseMarkerFound = false; 1654 mConstantsPos = -4; 1655 // keep track of the last instruction built 1656 // this info is used at the end of pass 2 to optimize the machine code 1657 mLastInstructionPos = 0; 1658 mSecondLastInstructionPos = 0; 1659 1660 mMacroOn = false; // macro's off at the beginning 1661 mTexm3x3padCount = 0; 1662 1663 } 1664 1665 bool PS_1_4::doPass2() 1666 { 1667 clearAllMachineInst(); 1668 // if pass 2 was successful, optimize the machine instructions 1669 bool passed = Pass2scan(&mTokenInstructions[0], mTokenInstructions.size()); 1670 if (passed) optimize(); 1671 1672 return passed; 1673 1674 } 1675 1676 1677 bool PS_1_4::Pass2scan(const TokenInst * Tokens, const size_t size) 1678 { 1679 1680 // execute TokenInstructions to build MachineInstructions 1681 bool passed = true; 1682 SymbolDef* cursymboldef; 1683 uint ActiveNTTRuleID; 1684 1685 clearMachineInstState(); 1686 1687 1688 // iterate through all the tokens and build machine instruction 1689 // for each machine instruction need: optype, opinst, and up to 5 parameters 1690 for(uint i = 0; i < size; i++) { 1691 // lookup instruction type in library 1692 1693 cursymboldef = &mSymbolTypeLib[Tokens[i].mID]; 1694 ActiveNTTRuleID = Tokens[i].mNTTRuleID; 1695 mCurrentLine = Tokens[i].mLine; 1696 mCharPos = Tokens[i].mPos; 1697 1698 switch(ActiveNTTRuleID) { 1699 1700 case sid_CONSTANT: 1701 case sid_COLOR: 1702 case sid_REG_PS1_4: 1703 case sid_TEX_PS1_4: 1704 case sid_REG_PS1_1_3: 1705 case sid_TEX_PS1_1_3: 1706 // registars can be used for read and write so they can be used for dst and arg 1707 passed = setOpParram(cursymboldef); 1708 break; 1709 1710 1711 case sid_DEFCONST: 1712 case sid_UNARYOP: 1713 case sid_BINARYOP: 1714 case sid_TERNARYOP: 1715 case sid_TEXOP_PS1_1_3: 1716 case sid_TEXOP_PS1_4: 1717 case sid_PHASEMARKER: 1718 case sid_TEXCISCOP_PS1_1_3: 1719 // if the last instruction has not been passed on then do it now 1720 // make sure the pipe is clear for a new instruction 1721 BuildMachineInst(); 1722 if(mOpInst == sid_INVALID) { 1723 mOpInst = cursymboldef->mID; 1724 } 1725 else passed = false; 1726 break; 1727 1728 case sid_DSTMASK: 1729 case sid_SRCREP: 1730 case sid_TEXSWIZZLE: 1731 // could be a dst mask or a arg replicator 1732 // if dst mask and alpha included then make up a alpha instruction: maybe best to wait until instruction args completed 1733 mOpParrams[mArgCnt].MaskRep = cursymboldef->mPass2Data; 1734 break; 1735 1736 case sid_DSTMOD: 1737 case sid_DSTSAT: 1738 case sid_PRESRCMOD: 1739 case sid_POSTSRCMOD: 1740 mOpParrams[mArgCnt].Mod |= cursymboldef->mPass2Data; 1741 break; 1742 1743 1744 case sid_NUMVAL: 1745 passed = setOpParram(cursymboldef); 1746 // keep track of how many values are used 1747 // update Constants array position 1748 mConstantsPos++; 1749 break; 1750 1751 case sid_SEPERATOR: 1752 mArgCnt++; 1753 break; 1754 } // end of switch 1755 1756 if(!passed) break; 1757 }// end of for: i<TokenInstCnt 1758 1759 // check to see if there is still an instruction left in the pipe 1760 if(passed) { 1761 BuildMachineInst(); 1762 // if there are no more instructions in the pipe than OpInst should be invalid 1763 if(mOpInst != sid_INVALID) passed = false; 1764 } 1765 1766 1767 return passed; 1768 } 1769 1770 1771 1772 bool PS_1_4::setOpParram(const SymbolDef* symboldef) 1773 { 1774 bool success = true; 1775 if(mArgCnt<MAXOPPARRAMS) { 1776 if(mOpParrams[mArgCnt].Filled) mArgCnt++; 1777 } 1778 if (mArgCnt<MAXOPPARRAMS) { 1779 mOpParrams[mArgCnt].Filled = true; 1780 mOpParrams[mArgCnt].Arg = symboldef->mPass2Data; 1781 } 1782 else success = false; 1783 1784 return success; 1785 } 1786 1787 1788 1789 1790 // ********************************************************************************* 1791 // this is where the tests are carried out to make sure the PS_1_4 compiler works 1792 1793 #ifdef _DEBUG 1794 // check the functionality of functions in PS_1_4: each test will print to the output file PASSED of FAILED 1795 void PS_1_4::test() 1796 { 1797 1798 1799 struct test1result{ 1800 char character; 1801 int line; 1802 }; 1803 1804 struct testfloatresult{ 1805 char *teststr; 1806 float fvalue; 1807 int charsize; 1808 }; 1809 1810 char TestStr1[] = " \n\r //c \n\r// test\n\r \t c - \n\r , e"; 1811 test1result test1results[] = { 1812 {'c', 4}, 1813 {'-', 4}, 1814 {',', 5}, 1815 {'e', 5} 1816 }; 1817 1818 testfloatresult testfloatresults[] = { 1819 {"1 test", 1.0f, 1}, 1820 {"2.3f test", 2.3f, 3}, 1821 {"-0.5 test", -0.5f, 4}, 1822 {" 23.6 test", 23.6f, 5}, 1823 {" -0.021 test", -0.021f, 8}, 1824 {"12 test", 12.0f, 2}, 1825 {"3test", 3.0f, 1} 1826 }; 1827 1828 1829 1830 SymbolID test3result[] = { sid_MOV, sid_COMMA, sid_MUL, sid_ADD, sid_NEGATE, sid_T0 1831 }; 1832 1833 #define PART2INST 17 1834 char TestStr3[] = "mov r0,c1"; 1835 char TestSymbols[] = "mov"; 1836 char passed[] = "PASSED\n"; 1837 char failed[] = "***** FAILED *****\n"; 1838 1839 int resultID = 0; 1840 1841 // loop variable used in for loops 1842 int i; 1843 fp = fopen("ASMTests.txt", "wt"); 1844 1845 // ************************************************************** 1846 // first test: see if positionToNextSymbol can find a valid Symbol 1847 fprintf(fp, "Testing: positionToNextSymbol\n"); 1848 1849 mSource = TestStr1; 1850 mCharPos = 0; 1851 mCurrentLine = 1; 1852 mEndOfSource = (int)strlen(mSource); 1853 while (positionToNextSymbol()) { 1854 fprintf(fp," character found: [%c] Line:%d : " , mSource[mCharPos], mCurrentLine); 1855 if( (mSource[mCharPos] == test1results[resultID].character) && (mCurrentLine==test1results[resultID].line)) fprintf(fp, passed); 1856 else fprintf(fp, failed); 1857 resultID++; 1858 mCharPos++; 1859 } 1860 fprintf(fp, "finished testing: positionToNextSymbol\n"); 1861 1862 1863 // ************************************************************** 1864 // Second Test 1865 // did the type lib get initialized properly with a default name index 1866 fprintf(fp, "\nTesting: getTypeDefText\n"); 1867 const char* resultstr = getTypeDefText(sid_MOV); 1868 fprintf(fp, " default name of mov is: [%s]: %s", resultstr, (strcmp("mov", resultstr)==0)?passed:failed); 1869 fprintf(fp, "finished testing: getTypeDefText\n"); 1870 1871 // ************************************************************** 1872 // ************************************************************** 1873 // fourth test - does isSymbol work correctly 1874 fprintf(fp, "\nTesting: isSymbol\n"); 1875 mSource = TestStr3; 1876 mCharPos = 0; 1877 fprintf(fp, " before: [%s]\n", mSource + mCharPos); 1878 fprintf(fp, " symbol to find: [%s]\n", TestSymbols); 1879 if(isSymbol(TestSymbols, resultID)) { 1880 fprintf(fp, " after: [%s] : %s", mSource + resultID + 1, (mSource[resultID + 1] == 'r')? passed:failed); 1881 } 1882 else fprintf(fp, failed); 1883 fprintf(fp," symbol size: %d\n", resultID); 1884 fprintf(fp, "finished testing: isSymbol\n"); 1885 1886 // ************************************************************** 1887 fprintf(fp, "\nTesting: isFloatValue\n"); 1888 float fvalue = 0; 1889 int charsize = 0; 1890 char teststrfloat1[] = "1 test"; 1891 mCharPos = 0; 1892 int testsize = ARRAYSIZE(testfloatresults); 1893 for(i=0; i<testsize; i++) { 1894 mSource = testfloatresults[i].teststr; 1895 fprintf(fp, " test string [%s]\n", mSource); 1896 isFloatValue(fvalue, charsize); 1897 fprintf(fp, " value is: %f should be %f: %s", fvalue, testfloatresults[i].fvalue, (fvalue == testfloatresults[i].fvalue)?passed:failed); 1898 fprintf(fp, " char size is: %d should be %d: %s", charsize, testfloatresults[i].charsize, (charsize == testfloatresults[i].charsize)?passed:failed); 1899 } 1900 1901 fprintf(fp, "finished testing: isFloatValue\n"); 1902 1903 1904 // ************************************************************** 1905 1906 // simple compile test: 1907 char CompileTest1src[] = "ps.1.4\n"; 1908 SymbolID CompileTest1result[] = {sid_PS_1_4}; 1909 1910 testCompile("Basic PS_1_4", CompileTest1src, CompileTest1result, ARRAYSIZE(CompileTest1result)); 1911 1912 // ************************************************************** 1913 char CompileTest2src[] = "ps.1.1\n"; 1914 SymbolID CompileTest2result[] = {sid_PS_1_1}; 1915 1916 testCompile("Basic PS_1_1", CompileTest2src, CompileTest2result, ARRAYSIZE(CompileTest2result)); 1917 1918 // ************************************************************** 1919 char CompileTest3src[] = "ps.1.4\ndef c0, 1.0, 2.0, 3.0, 4.0\n"; 1920 SymbolID CompileTest3result[] = {sid_PS_1_4, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, 1921 sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE}; 1922 1923 testCompile("PS_1_4 with defines", CompileTest3src, CompileTest3result, ARRAYSIZE(CompileTest3result)); 1924 1925 1926 // ************************************************************** 1927 char CompileTest4src[] = "ps.1.4\n//test kkl \ndef c0, 1.0, 2.0, 3.0, 4.0\ndef c3, 1.0, 2.0, 3.0, 4.0\n"; 1928 SymbolID CompileTest4result[] = {sid_PS_1_4, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, 1929 sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE,sid_DEF, sid_C3, sid_COMMA, sid_VALUE, sid_COMMA, 1930 sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE}; 1931 1932 testCompile("PS_1_4 with 2 defines", CompileTest4src, CompileTest4result, ARRAYSIZE(CompileTest4result)); 1933 1934 // ************************************************************** 1935 char CompileTest5src[] = "ps.1.4\ndef c0, 1.0, 2.0, 3.0, 4.0\n"; 1936 SymbolID CompileTest5result[] = {sid_PS_1_4, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, 1937 sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE}; 1938 GLuint CompileTest5MachinInstResults[] = {mi_SETCONSTANTS, GL_CON_0_ATI, 0}; 1939 1940 testCompile("PS_1_4 with defines", CompileTest3src, CompileTest3result, ARRAYSIZE(CompileTest3result), CompileTest5MachinInstResults, ARRAYSIZE(CompileTest5MachinInstResults)); 1941 // ************************************************************** 1942 char CompileTest6Src[] = "ps.1.4\nmov r0.xzw, c1 \nmul r3, r2, c3"; 1943 SymbolID CompileTest6result[] = {sid_PS_1_4, sid_MOV, sid_R0, sid_RBA, sid_COMMA, sid_C1, 1944 sid_MUL, sid_R3, sid_COMMA, sid_R2, sid_COMMA, sid_C3}; 1945 1946 testCompile("PS_1_4 ALU simple", CompileTest6Src, CompileTest6result, ARRAYSIZE(CompileTest6result)); 1947 1948 // ************************************************************** 1949 // test to see if PS_1_4 compile pass 2 generates the proper machine instructions 1950 char CompileTest7Src[] = "ps.1.4\ndef c0,1.0,2.0,3.0,4.0\nmov_x8 r1,v0\nmov r0,r1.g"; 1951 1952 SymbolID CompileTest7result[] = { 1953 sid_PS_1_4, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, 1954 sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, sid_MOV, sid_X8, sid_R1, sid_COMMA, 1955 sid_V0, sid_MOV, sid_R0, sid_COMMA, sid_R1, sid_GGGG 1956 }; 1957 1958 GLuint CompileTest7MachinInstResults[] = { 1959 mi_SETCONSTANTS, GL_CON_0_ATI, 0, 1960 mi_COLOROP1, GL_MOV_ATI, GL_REG_1_ATI, RGB_BITS, GL_8X_BIT_ATI, GL_PRIMARY_COLOR_ARB, GL_NONE, GL_NONE, 1961 mi_ALPHAOP1, GL_MOV_ATI, GL_REG_1_ATI, GL_8X_BIT_ATI, GL_PRIMARY_COLOR_ARB, GL_NONE, GL_NONE, 1962 mi_COLOROP1, GL_MOV_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE,GL_REG_1_ATI, GL_GREEN, GL_NONE, 1963 mi_ALPHAOP1, GL_MOV_ATI, GL_REG_0_ATI, GL_NONE, GL_REG_1_ATI, GL_GREEN, GL_NONE, 1964 }; 1965 1966 1967 testCompile("PS_1_4 ALU simple modifier", CompileTest7Src, CompileTest7result, ARRAYSIZE(CompileTest7result), CompileTest7MachinInstResults, ARRAYSIZE(CompileTest7MachinInstResults)); 1968 1969 // ************************************************************** 1970 // test to see if a PS_1_1 can be compiled - pass 1 and pass 2 are checked 1971 1972 char TestStr5[] = "ps.1.1\ndef c0,1.0,2.0,3.0,4.0\ntex t0\n// test\ntex t1\ndp3 t0.rgb, t0_bx2, t1_bx2\n+ mov r0,1 - t0"; 1973 1974 SymbolID test5result[] = { 1975 sid_PS_1_1, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, 1976 sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, sid_TEX, sid_1T0, sid_TEX, sid_1T1, 1977 sid_DP3, sid_1T0, sid_RGB, sid_COMMA, sid_1T0, sid_BX2, sid_COMMA, sid_1T1, sid_BX2, 1978 1979 sid_PLUS, sid_MOV, sid_1R0, sid_COMMA, sid_INVERT, sid_1T0 1980 }; 1981 1982 GLuint test5MachinInstResults[] = { 1983 mi_SETCONSTANTS, GL_CON_0_ATI, 0, mi_SAMPLEMAP, GL_REG_0_ATI, GL_TEXTURE0_ARB, GL_SWIZZLE_STR_ATI, mi_SAMPLEMAP, GL_REG_1_ATI, GL_TEXTURE1_ARB, GL_SWIZZLE_STR_ATI, 1984 mi_COLOROP2, GL_DOT3_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_2X_BIT_ATI | GL_BIAS_BIT_ATI, 1985 GL_REG_1_ATI, GL_NONE, GL_2X_BIT_ATI | GL_BIAS_BIT_ATI, 1986 mi_COLOROP1, GL_MOV_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_COMP_BIT_ATI, mi_ALPHAOP1, GL_MOV_ATI, GL_REG_0_ATI, 1987 GL_NONE, GL_REG_0_ATI, GL_NONE, GL_COMP_BIT_ATI, 1988 }; 1989 1990 1991 testCompile("PS_1_1 Texture simple", TestStr5, test5result, ARRAYSIZE(test5result), test5MachinInstResults, ARRAYSIZE(test5MachinInstResults)); 1992 1993 1994 // ************************************************************** 1995 // test to see if a PS_1_2 CISC instructions can be compiled - pass 1 and pass 2 are checked 1996 1997 char TestStr6[] = "ps.1.2\ndef c0,1.0,2.0,3.0,4.0\ntex t0\n// test\ntexreg2ar t1, t0"; 1998 1999 SymbolID test6result[] = { 2000 sid_PS_1_2, sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, 2001 sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, 2002 sid_TEX, sid_1T0, 2003 sid_TEXREG2AR, sid_1T1, sid_COMMA, sid_1T0 2004 }; 2005 2006 GLuint test6MachinInstResults[] = { 2007 // def c0 2008 mi_SETCONSTANTS, GL_CON_0_ATI, 0, 2009 // texld r0, t0.str 2010 mi_SAMPLEMAP, GL_REG_0_ATI, GL_TEXTURE0_ARB, GL_SWIZZLE_STR_ATI, 2011 // mov r1.r, r0.a 2012 mi_COLOROP1, GL_MOV_ATI, GL_REG_1_ATI, GL_RED_BIT_ATI, GL_NONE, GL_REG_0_ATI, GL_ALPHA, GL_NONE, 2013 // mov r1.g, r0.r 2014 mi_COLOROP1, GL_MOV_ATI, GL_REG_1_ATI, GL_GREEN_BIT_ATI, GL_NONE, GL_REG_0_ATI, GL_RED, GL_NONE, 2015 // texld r1, r1 2016 mi_SAMPLEMAP, GL_REG_1_ATI, GL_REG_1_ATI, GL_SWIZZLE_STR_ATI, 2017 }; 2018 2019 2020 testCompile("PS_1_2 CISC instructions", TestStr6, test6result, ARRAYSIZE(test6result), test6MachinInstResults, ARRAYSIZE(test6MachinInstResults)); 2021 2022 // ************************************************************** 2023 // test to see if a PS_1_4 two phase can be compiled - pass 1 and pass 2 are checked 2024 2025 char TestStr7[] = "ps.1.4\ndef c0,1.0,2.0,3.0,4.0\ntexld r0, t0\n// test\nmul r0, r0, c0\nphase\ntexld r1, r0\nmul r0,r0,r1\n"; 2026 2027 SymbolID test7result[] = { 2028 sid_PS_1_4, 2029 // def c0,1.0,2.0,3.0,4.0 2030 sid_DEF, sid_C0, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, sid_COMMA, sid_VALUE, 2031 // texld r0, t0 2032 sid_TEXLD, sid_R0, sid_COMMA, sid_T0, 2033 // mul r0, r0, c0 2034 sid_MUL, sid_R0, sid_COMMA, sid_R0, sid_COMMA, sid_C0, 2035 // phase 2036 sid_PHASE, 2037 // texld r1, r0 2038 sid_TEXLD, sid_R1, sid_COMMA, sid_R0, 2039 // mul r0, r0, r1 2040 sid_MUL, sid_R0, sid_COMMA, sid_R0, sid_COMMA, sid_R1, 2041 2042 }; 2043 2044 GLuint test7MachinInstResults[] = { 2045 // def c0 2046 mi_SETCONSTANTS, GL_CON_0_ATI, 0, 2047 // texld r0, t0.str 2048 mi_SAMPLEMAP, GL_REG_0_ATI, GL_TEXTURE0_ARB, GL_SWIZZLE_STR_ATI, 2049 // mul r0, r0, c0 2050 mi_COLOROP2, GL_MUL_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_NONE, GL_CON_0_ATI, GL_NONE, GL_NONE, 2051 mi_ALPHAOP2, GL_MUL_ATI, GL_REG_0_ATI, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_NONE, GL_CON_0_ATI, GL_NONE, GL_NONE, 2052 // phase 2053 // texld r1, r0.str 2054 mi_SAMPLEMAP, GL_REG_1_ATI, GL_REG_0_ATI, GL_SWIZZLE_STR_ATI, 2055 // pass ro register 2056 mi_PASSTEXCOORD, GL_REG_0_ATI, GL_REG_0_ATI, GL_SWIZZLE_STR_ATI, 2057 // mul r0, r0, r1 2058 mi_COLOROP2, GL_MUL_ATI, GL_REG_0_ATI, RGB_BITS, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_NONE, GL_REG_1_ATI, GL_NONE, GL_NONE, 2059 // mul r0.a, r0 2060 mi_ALPHAOP2, GL_MUL_ATI, GL_REG_0_ATI, GL_NONE, GL_REG_0_ATI, GL_NONE, GL_NONE, GL_REG_1_ATI, GL_NONE, GL_NONE, 2061 }; 2062 2063 2064 testCompile("PS_1_4 texture complex : Phase - instructions", TestStr7, test7result, ARRAYSIZE(test7result), test7MachinInstResults, ARRAYSIZE(test7MachinInstResults)); 2065 2066 2067 fclose(fp); 2068 fp = NULL; 2069 //reset contexts 2070 2071 // ************************************************************** 2072 } 2073 2074 void PS_1_4::testCompile(char* testname, char* teststr, SymbolID* testresult, uint testresultsize, GLuint* MachinInstResults, uint MachinInstResultsSize) 2075 { 2076 2077 char passed[] = "PASSED\n"; 2078 char failed[] = "***** FAILED ****\n"; 2079 2080 setActiveContexts(ckp_PS_BASE); 2081 2082 fprintf(fp, "\n*** TESTING: %s Compile: Check Pass 1 and 2\n", testname); 2083 fprintf(fp, " source to compile:\n[\n%s\n]\n", teststr); 2084 bool compiled = compile(teststr); 2085 fprintf(fp, " Pass 1 Lines scaned: %d, Tokens produced: %d out of %d: %s", 2086 mCurrentLine, mTokenInstructions.size(), testresultsize, 2087 (mTokenInstructions.size() == (uint)testresultsize) ? passed : failed); 2088 2089 fprintf(fp, "\n Validating Pass 1:\n"); 2090 2091 fprintf(fp, "\n Tokens:\n"); 2092 uint i; 2093 for(i = 0; i<(mTokenInstructions.size()); i++) { 2094 fprintf(fp," Token[%d] [%s] %d: [%s] %d: %s", i, getTypeDefText(mTokenInstructions[i].mID), 2095 mTokenInstructions[i].mID, getTypeDefText(testresult[i]), testresult[i], 2096 (mTokenInstructions[i].mID == (uint)testresult[i]) ? passed : failed); 2097 } 2098 2099 if(MachinInstResults != NULL) { 2100 fprintf(fp, "\n Machine Instructions:\n"); 2101 2102 fprintf(fp, " Pass 2 Machine Instructions generated: %d out of %d: %s", getMachineInstCount(), 2103 MachinInstResultsSize, (getMachineInstCount() == MachinInstResultsSize) ? passed : failed); 2104 2105 size_t MIcount = getMachineInstCount(); 2106 2107 fprintf(fp, "\n Validating Pass 2:\n"); 2108 for(i = 0; i<MIcount; i++) { 2109 fprintf(fp," instruction[%d] = 0x%x : 0x%x : %s", i, getMachineInst(i), MachinInstResults[i], (getMachineInst(i) == MachinInstResults[i]) ? passed : failed); 2110 } 2111 2112 fprintf(fp, "\n Constants:\n"); 2113 for(i=0; i<4; i++) { 2114 fprintf(fp, " Constants[%d] = %f : %s", i, mConstants[i], (mConstants[i] == (1.0f+i)) ? passed : failed); 2115 } 2116 } 2117 if(!compiled) fprintf(fp, failed); 2118 2119 fprintf(fp, "\nfinished testing: %s Compile: Check Pass 2\n\n", testname); 2120 2121 setActiveContexts(ckp_PS_BASE); 2122 } 2123 2124 void PS_1_4::testbinder() 2125 { 2126 FILE* fp; 2127 char BindTestStr[] = "mov_x8 r0,v0"; 2128 char passed[] = "PASSED\n"; 2129 char failed[] = "FAILED\n"; 2130 #define BinderInstCnt 8 2131 GLuint BindMachinInst[BinderInstCnt] = {mi_COLOROP1, GL_MOV_ATI, GL_REG_0_ATI, GL_NONE, GL_8X_BIT_ATI, 2132 GL_PRIMARY_COLOR_ARB, GL_NONE, GL_NONE}; 2133 2134 fp = fopen("ASMTests.txt", "at"); 2135 fprintf(fp,"Testing: bindMachineInstToFragmentShader\n"); 2136 // fill Machin instruction container with predefined code 2137 clearAllMachineInst(); 2138 for(int i=0; i<BinderInstCnt; i++) { 2139 mPhase2ALU_mi.push_back(BindMachinInst[i]); 2140 } 2141 fprintf(fp,"bindMachineInstToFragmentShader succes: %s\n",bindAllMachineInstToFragmentShader()?passed:failed); 2142 fprintf(fp,"finished testing: bindAllMachineInstToFragmentShader\n"); 2143 fclose(fp); 2144 } 2145 2146 #endif 2147 2148 2149 2150