1 /*
2 * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "c1/c1_FrameMap.hpp"
28 #include "c1/c1_LIR.hpp"
29 #include "runtime/sharedRuntime.hpp"
30 #include "vmreg_ppc.inline.hpp"
31
32
33 const int FrameMap::pd_c_runtime_reserved_arg_size = 7;
34
35
map_to_opr(BasicType type,VMRegPair * reg,bool outgoing)36 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
37 LIR_Opr opr = LIR_OprFact::illegalOpr;
38 VMReg r_1 = reg->first();
39 VMReg r_2 = reg->second();
40 if (r_1->is_stack()) {
41 // Convert stack slot to an SP offset.
42 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
43 // so we must add it in here.
44 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
45 opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type));
46 } else if (r_1->is_Register()) {
47 Register reg = r_1->as_Register();
48 //if (outgoing) {
49 // assert(!reg->is_in(), "should be using I regs");
50 //} else {
51 // assert(!reg->is_out(), "should be using O regs");
52 //}
53 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
54 opr = as_long_opr(reg);
55 } else if (type == T_OBJECT || type == T_ARRAY) {
56 opr = as_oop_opr(reg);
57 } else if (type == T_METADATA) {
58 opr = as_metadata_opr(reg);
59 } else if (type == T_ADDRESS) {
60 opr = as_address_opr(reg);
61 } else {
62 opr = as_opr(reg);
63 }
64 } else if (r_1->is_FloatRegister()) {
65 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
66 FloatRegister f = r_1->as_FloatRegister();
67 if (type == T_DOUBLE) {
68 opr = as_double_opr(f);
69 } else {
70 opr = as_float_opr(f);
71 }
72 }
73 return opr;
74 }
75
76 // FrameMap
77 //--------------------------------------------------------
78
79 FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs];
80
81 LIR_Opr FrameMap::R0_opr;
82 LIR_Opr FrameMap::R1_opr;
83 LIR_Opr FrameMap::R2_opr;
84 LIR_Opr FrameMap::R3_opr;
85 LIR_Opr FrameMap::R4_opr;
86 LIR_Opr FrameMap::R5_opr;
87 LIR_Opr FrameMap::R6_opr;
88 LIR_Opr FrameMap::R7_opr;
89 LIR_Opr FrameMap::R8_opr;
90 LIR_Opr FrameMap::R9_opr;
91 LIR_Opr FrameMap::R10_opr;
92 LIR_Opr FrameMap::R11_opr;
93 LIR_Opr FrameMap::R12_opr;
94 LIR_Opr FrameMap::R13_opr;
95 LIR_Opr FrameMap::R14_opr;
96 LIR_Opr FrameMap::R15_opr;
97 LIR_Opr FrameMap::R16_opr;
98 LIR_Opr FrameMap::R17_opr;
99 LIR_Opr FrameMap::R18_opr;
100 LIR_Opr FrameMap::R19_opr;
101 LIR_Opr FrameMap::R20_opr;
102 LIR_Opr FrameMap::R21_opr;
103 LIR_Opr FrameMap::R22_opr;
104 LIR_Opr FrameMap::R23_opr;
105 LIR_Opr FrameMap::R24_opr;
106 LIR_Opr FrameMap::R25_opr;
107 LIR_Opr FrameMap::R26_opr;
108 LIR_Opr FrameMap::R27_opr;
109 LIR_Opr FrameMap::R28_opr;
110 LIR_Opr FrameMap::R29_opr;
111 LIR_Opr FrameMap::R30_opr;
112 LIR_Opr FrameMap::R31_opr;
113
114 LIR_Opr FrameMap::R0_oop_opr;
115 //LIR_Opr FrameMap::R1_oop_opr;
116 LIR_Opr FrameMap::R2_oop_opr;
117 LIR_Opr FrameMap::R3_oop_opr;
118 LIR_Opr FrameMap::R4_oop_opr;
119 LIR_Opr FrameMap::R5_oop_opr;
120 LIR_Opr FrameMap::R6_oop_opr;
121 LIR_Opr FrameMap::R7_oop_opr;
122 LIR_Opr FrameMap::R8_oop_opr;
123 LIR_Opr FrameMap::R9_oop_opr;
124 LIR_Opr FrameMap::R10_oop_opr;
125 LIR_Opr FrameMap::R11_oop_opr;
126 LIR_Opr FrameMap::R12_oop_opr;
127 //LIR_Opr FrameMap::R13_oop_opr;
128 LIR_Opr FrameMap::R14_oop_opr;
129 LIR_Opr FrameMap::R15_oop_opr;
130 //LIR_Opr FrameMap::R16_oop_opr;
131 LIR_Opr FrameMap::R17_oop_opr;
132 LIR_Opr FrameMap::R18_oop_opr;
133 LIR_Opr FrameMap::R19_oop_opr;
134 LIR_Opr FrameMap::R20_oop_opr;
135 LIR_Opr FrameMap::R21_oop_opr;
136 LIR_Opr FrameMap::R22_oop_opr;
137 LIR_Opr FrameMap::R23_oop_opr;
138 LIR_Opr FrameMap::R24_oop_opr;
139 LIR_Opr FrameMap::R25_oop_opr;
140 LIR_Opr FrameMap::R26_oop_opr;
141 LIR_Opr FrameMap::R27_oop_opr;
142 LIR_Opr FrameMap::R28_oop_opr;
143 //LIR_Opr FrameMap::R29_oop_opr;
144 LIR_Opr FrameMap::R30_oop_opr;
145 LIR_Opr FrameMap::R31_oop_opr;
146
147 LIR_Opr FrameMap::R0_metadata_opr;
148 //LIR_Opr FrameMap::R1_metadata_opr;
149 LIR_Opr FrameMap::R2_metadata_opr;
150 LIR_Opr FrameMap::R3_metadata_opr;
151 LIR_Opr FrameMap::R4_metadata_opr;
152 LIR_Opr FrameMap::R5_metadata_opr;
153 LIR_Opr FrameMap::R6_metadata_opr;
154 LIR_Opr FrameMap::R7_metadata_opr;
155 LIR_Opr FrameMap::R8_metadata_opr;
156 LIR_Opr FrameMap::R9_metadata_opr;
157 LIR_Opr FrameMap::R10_metadata_opr;
158 LIR_Opr FrameMap::R11_metadata_opr;
159 LIR_Opr FrameMap::R12_metadata_opr;
160 //LIR_Opr FrameMap::R13_metadata_opr;
161 LIR_Opr FrameMap::R14_metadata_opr;
162 LIR_Opr FrameMap::R15_metadata_opr;
163 //LIR_Opr FrameMap::R16_metadata_opr;
164 LIR_Opr FrameMap::R17_metadata_opr;
165 LIR_Opr FrameMap::R18_metadata_opr;
166 LIR_Opr FrameMap::R19_metadata_opr;
167 LIR_Opr FrameMap::R20_metadata_opr;
168 LIR_Opr FrameMap::R21_metadata_opr;
169 LIR_Opr FrameMap::R22_metadata_opr;
170 LIR_Opr FrameMap::R23_metadata_opr;
171 LIR_Opr FrameMap::R24_metadata_opr;
172 LIR_Opr FrameMap::R25_metadata_opr;
173 LIR_Opr FrameMap::R26_metadata_opr;
174 LIR_Opr FrameMap::R27_metadata_opr;
175 LIR_Opr FrameMap::R28_metadata_opr;
176 //LIR_Opr FrameMap::R29_metadata_opr;
177 LIR_Opr FrameMap::R30_metadata_opr;
178 LIR_Opr FrameMap::R31_metadata_opr;
179
180 LIR_Opr FrameMap::SP_opr;
181
182 LIR_Opr FrameMap::R0_long_opr;
183 LIR_Opr FrameMap::R3_long_opr;
184
185 LIR_Opr FrameMap::F1_opr;
186 LIR_Opr FrameMap::F1_double_opr;
187
188 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
189 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
190
nr2floatreg(int rnr)191 FloatRegister FrameMap::nr2floatreg (int rnr) {
192 assert(_init_done, "tables not initialized");
193 debug_only(fpu_range_check(rnr);)
194 return _fpu_regs[rnr];
195 }
196
197
198 // Returns true if reg could be smashed by a callee.
is_caller_save_register(LIR_Opr reg)199 bool FrameMap::is_caller_save_register (LIR_Opr reg) {
200 if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; }
201 if (reg->is_double_cpu()) {
202 return is_caller_save_register(reg->as_register_lo()) ||
203 is_caller_save_register(reg->as_register_hi());
204 }
205 return is_caller_save_register(reg->as_register());
206 }
207
208
is_caller_save_register(Register r)209 bool FrameMap::is_caller_save_register (Register r) {
210 // not visible to allocator: R0: scratch, R1: SP
211 // r->encoding() < 2 + nof_caller_save_cpu_regs();
212 return true; // Currently all regs are caller save.
213 }
214
215
initialize()216 void FrameMap::initialize() {
217 assert(!_init_done, "once");
218
219 int i = 0;
220
221 // Put generally available registers at the beginning (allocated, saved for GC).
222 for (int j = 0; j < nof_cpu_regs; ++j) {
223 Register rj = as_Register(j);
224 if (reg_needs_save(rj)) {
225 map_register(i++, rj);
226 }
227 }
228 assert(i == nof_cpu_regs_reg_alloc, "number of allocated registers");
229
230 // The following registers are not normally available.
231 for (int j = 0; j < nof_cpu_regs; ++j) {
232 Register rj = as_Register(j);
233 if (!reg_needs_save(rj)) {
234 map_register(i++, rj);
235 }
236 }
237 assert(i == nof_cpu_regs, "number of CPU registers");
238
239 for (i = 0; i < nof_fpu_regs; i++) {
240 _fpu_regs[i] = as_FloatRegister(i);
241 }
242
243 _init_done = true;
244
245 R0_opr = as_opr(R0);
246 R1_opr = as_opr(R1);
247 R2_opr = as_opr(R2);
248 R3_opr = as_opr(R3);
249 R4_opr = as_opr(R4);
250 R5_opr = as_opr(R5);
251 R6_opr = as_opr(R6);
252 R7_opr = as_opr(R7);
253 R8_opr = as_opr(R8);
254 R9_opr = as_opr(R9);
255 R10_opr = as_opr(R10);
256 R11_opr = as_opr(R11);
257 R12_opr = as_opr(R12);
258 R13_opr = as_opr(R13);
259 R14_opr = as_opr(R14);
260 R15_opr = as_opr(R15);
261 R16_opr = as_opr(R16);
262 R17_opr = as_opr(R17);
263 R18_opr = as_opr(R18);
264 R19_opr = as_opr(R19);
265 R20_opr = as_opr(R20);
266 R21_opr = as_opr(R21);
267 R22_opr = as_opr(R22);
268 R23_opr = as_opr(R23);
269 R24_opr = as_opr(R24);
270 R25_opr = as_opr(R25);
271 R26_opr = as_opr(R26);
272 R27_opr = as_opr(R27);
273 R28_opr = as_opr(R28);
274 R29_opr = as_opr(R29);
275 R30_opr = as_opr(R30);
276 R31_opr = as_opr(R31);
277
278 R0_oop_opr = as_oop_opr(R0);
279 //R1_oop_opr = as_oop_opr(R1);
280 R2_oop_opr = as_oop_opr(R2);
281 R3_oop_opr = as_oop_opr(R3);
282 R4_oop_opr = as_oop_opr(R4);
283 R5_oop_opr = as_oop_opr(R5);
284 R6_oop_opr = as_oop_opr(R6);
285 R7_oop_opr = as_oop_opr(R7);
286 R8_oop_opr = as_oop_opr(R8);
287 R9_oop_opr = as_oop_opr(R9);
288 R10_oop_opr = as_oop_opr(R10);
289 R11_oop_opr = as_oop_opr(R11);
290 R12_oop_opr = as_oop_opr(R12);
291 //R13_oop_opr = as_oop_opr(R13);
292 R14_oop_opr = as_oop_opr(R14);
293 R15_oop_opr = as_oop_opr(R15);
294 //R16_oop_opr = as_oop_opr(R16);
295 R17_oop_opr = as_oop_opr(R17);
296 R18_oop_opr = as_oop_opr(R18);
297 R19_oop_opr = as_oop_opr(R19);
298 R20_oop_opr = as_oop_opr(R20);
299 R21_oop_opr = as_oop_opr(R21);
300 R22_oop_opr = as_oop_opr(R22);
301 R23_oop_opr = as_oop_opr(R23);
302 R24_oop_opr = as_oop_opr(R24);
303 R25_oop_opr = as_oop_opr(R25);
304 R26_oop_opr = as_oop_opr(R26);
305 R27_oop_opr = as_oop_opr(R27);
306 R28_oop_opr = as_oop_opr(R28);
307 //R29_oop_opr = as_oop_opr(R29);
308 R30_oop_opr = as_oop_opr(R30);
309 R31_oop_opr = as_oop_opr(R31);
310
311 R0_metadata_opr = as_metadata_opr(R0);
312 //R1_metadata_opr = as_metadata_opr(R1);
313 R2_metadata_opr = as_metadata_opr(R2);
314 R3_metadata_opr = as_metadata_opr(R3);
315 R4_metadata_opr = as_metadata_opr(R4);
316 R5_metadata_opr = as_metadata_opr(R5);
317 R6_metadata_opr = as_metadata_opr(R6);
318 R7_metadata_opr = as_metadata_opr(R7);
319 R8_metadata_opr = as_metadata_opr(R8);
320 R9_metadata_opr = as_metadata_opr(R9);
321 R10_metadata_opr = as_metadata_opr(R10);
322 R11_metadata_opr = as_metadata_opr(R11);
323 R12_metadata_opr = as_metadata_opr(R12);
324 //R13_metadata_opr = as_metadata_opr(R13);
325 R14_metadata_opr = as_metadata_opr(R14);
326 R15_metadata_opr = as_metadata_opr(R15);
327 //R16_metadata_opr = as_metadata_opr(R16);
328 R17_metadata_opr = as_metadata_opr(R17);
329 R18_metadata_opr = as_metadata_opr(R18);
330 R19_metadata_opr = as_metadata_opr(R19);
331 R20_metadata_opr = as_metadata_opr(R20);
332 R21_metadata_opr = as_metadata_opr(R21);
333 R22_metadata_opr = as_metadata_opr(R22);
334 R23_metadata_opr = as_metadata_opr(R23);
335 R24_metadata_opr = as_metadata_opr(R24);
336 R25_metadata_opr = as_metadata_opr(R25);
337 R26_metadata_opr = as_metadata_opr(R26);
338 R27_metadata_opr = as_metadata_opr(R27);
339 R28_metadata_opr = as_metadata_opr(R28);
340 //R29_metadata_opr = as_metadata_opr(R29);
341 R30_metadata_opr = as_metadata_opr(R30);
342 R31_metadata_opr = as_metadata_opr(R31);
343
344 SP_opr = as_pointer_opr(R1_SP);
345
346 R0_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(R0), cpu_reg2rnr(R0));
347 R3_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(R3), cpu_reg2rnr(R3));
348
349 F1_opr = as_float_opr(F1);
350 F1_double_opr = as_double_opr(F1);
351
352 // All the allocated cpu regs are caller saved.
353 for (int i = 0; i < max_nof_caller_save_cpu_regs; i++) {
354 _caller_save_cpu_regs[i] = LIR_OprFact::single_cpu(i);
355 }
356
357 // All the fpu regs are caller saved.
358 for (int i = 0; i < nof_caller_save_fpu_regs; i++) {
359 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
360 }
361 }
362
363
make_new_address(ByteSize sp_offset) const364 Address FrameMap::make_new_address(ByteSize sp_offset) const {
365 return Address(R1_SP, STACK_BIAS + in_bytes(sp_offset));
366 }
367
368
fpu_regname(int n)369 VMReg FrameMap::fpu_regname (int n) {
370 return as_FloatRegister(n)->as_VMReg();
371 }
372
373
stack_pointer()374 LIR_Opr FrameMap::stack_pointer() {
375 return SP_opr;
376 }
377
378
379 // JSR 292
380 // On PPC64, there is no need to save the SP, because neither
381 // method handle intrinsics, nor compiled lambda forms modify it.
method_handle_invoke_SP_save_opr()382 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
383 return LIR_OprFact::illegalOpr;
384 }
385
386
validate_frame()387 bool FrameMap::validate_frame() {
388 int max_offset = in_bytes(framesize_in_bytes());
389 int java_index = 0;
390 for (int i = 0; i < _incoming_arguments->length(); i++) {
391 LIR_Opr opr = _incoming_arguments->at(i);
392 if (opr->is_stack()) {
393 max_offset = MAX2(_argument_locations->at(java_index), max_offset);
394 }
395 java_index += type2size[opr->type()];
396 }
397 return Assembler::is_simm16(max_offset + STACK_BIAS);
398 }
399