1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_FRAME_SPARC_HPP 26 #define CPU_SPARC_VM_FRAME_SPARC_HPP 27 28 #include "runtime/synchronizer.hpp" 29 30 // A frame represents a physical stack frame (an activation). Frames can be 31 // C or Java frames, and the Java frames can be interpreted or compiled. 32 // In contrast, vframes represent source-level activations, so that one physical frame 33 // can correspond to multiple source level frames because of inlining. 34 // A frame is comprised of {pc, sp, younger_sp} 35 36 37 // Layout of asm interpreter frame: 38 // 39 // 0xfffffff 40 // ...... 41 // [last extra incoming arg, (local # Nargs > 6 ? Nargs-1 : undef)] 42 // .. Note: incoming args are copied to local frame area upon entry 43 // [first extra incoming arg, (local # Nargs > 6 ? 6 : undef)] 44 // [6 words for C-arg storage (unused)] Are this and next one really needed? 45 // [C-aggregate-word (unused)] Yes, if want extra params to be in same place as C convention 46 // [16 words for register saving] <--- FP 47 // [interpreter_frame_vm_locals ] (see below) 48 49 // Note: Llocals is always double-word aligned 50 // [first local i.e. local # 0] <-- Llocals 51 // ... 52 // [last local, i.e. local # Nlocals-1] 53 54 // [monitors ] 55 // .... 56 // [monitors ] <-- Lmonitors (same as Llocals + 6*4 if none) 57 // (must be double-word aligned because 58 // monitor element size is constrained to 59 // doubleword) 60 // 61 // <-- Lesp (points 1 past TOS) 62 // [bottom word used for stack ] 63 // ... 64 // [top word used for stack] (first word of stack is double-word aligned) 65 66 // [space for outgoing args (conservatively allocated as max_stack - 6 + interpreter_frame_extra_outgoing_argument_words)] 67 // [6 words for C-arg storage] 68 // [C-aggregate-word (unused)] 69 // [16 words for register saving] <--- SP 70 // ... 71 // 0x0000000 72 // 73 // The in registers and local registers are preserved in a block at SP. 74 // 75 // The first six in registers (I0..I5) hold the first six locals. 76 // The locals are used as follows: 77 // Lesp first free element of expression stack 78 // (which grows towards __higher__ addresses) 79 // Lbcp is set to address of bytecode to execute 80 // It may at times (during GC) be an index instead. 81 // Lmethod the method being interpreted 82 // Llocals the base pointer for accessing the locals array 83 // (lower-numbered locals have lower addresses) 84 // Lmonitors the base pointer for accessing active monitors 85 // Lcache a saved pointer to the method's constant pool cache 86 // 87 // 88 // When calling out to another method, 89 // G5_method is set to method to call, G5_inline_cache_klass may be set, 90 // parameters are put in O registers, and also extra parameters 91 // must be cleverly copied from the top of stack to the outgoing param area in the frame, 92 93 // All frames: 94 95 public: 96 97 enum { 98 // normal return address is 2 words past PC 99 pc_return_offset = 2 * BytesPerInstWord, 100 101 // size of each block, in order of increasing address: 102 register_save_words = 16, 103 callee_aggregate_return_pointer_words = 0, 104 callee_register_argument_save_area_words = 6, 105 // memory_parameter_words = <arbitrary>, 106 107 // offset of each block, in order of increasing address: 108 // (note: callee_register_argument_save_area_words == Assembler::n_register_parameters) 109 register_save_words_sp_offset = 0, 110 callee_aggregate_return_pointer_sp_offset = register_save_words_sp_offset + register_save_words, 111 callee_register_argument_save_area_sp_offset = callee_aggregate_return_pointer_sp_offset + callee_aggregate_return_pointer_words, 112 memory_parameter_word_sp_offset = callee_register_argument_save_area_sp_offset + callee_register_argument_save_area_words, 113 varargs_offset = memory_parameter_word_sp_offset 114 }; 115 116 private: 117 intptr_t* _younger_sp; // optional SP of callee (used to locate O7) 118 int _sp_adjustment_by_callee; // adjustment in words to SP by callee for making locals contiguous 119 120 // Note: On SPARC, unlike Intel, the saved PC for a stack frame 121 // is stored at a __variable__ distance from that frame's SP. 122 // (In fact, it may be in the register save area of the callee frame, 123 // but that fact need not bother us.) Thus, we must store the 124 // address of that saved PC explicitly. On the other hand, SPARC 125 // stores the FP for a frame at a fixed offset from the frame's SP, 126 // so there is no need for a separate "frame::_fp" field. 127 128 public: 129 // Accessors 130 131 intptr_t* younger_sp() const { 132 assert(_younger_sp != NULL, "frame must possess a younger_sp"); 133 return _younger_sp; 134 } 135 callee_sp_adjustment() const136 int callee_sp_adjustment() const { return _sp_adjustment_by_callee; } set_sp_adjustment_by_callee(int number_of_words)137 void set_sp_adjustment_by_callee(int number_of_words) { _sp_adjustment_by_callee = number_of_words; } 138 139 // Constructors 140 141 // This constructor relies on the fact that the creator of a frame 142 // has flushed register windows which the frame will refer to, and 143 // that those register windows will not be reloaded until the frame is 144 // done reading and writing the stack. Moreover, if the "younger_sp" 145 // argument points into the register save area of the next younger 146 // frame (though it need not), the register window for that next 147 // younger frame must also stay flushed. (The caller is responsible 148 // for ensuring this.) 149 150 frame(intptr_t* sp, intptr_t* younger_sp, bool younger_frame_adjusted_stack = false); 151 152 // make a deficient frame which doesn't know where its PC is: 153 enum unpatchable_t { unpatchable }; 154 frame(intptr_t* sp, unpatchable_t, address pc = NULL, CodeBlob* cb = NULL); 155 156 void init(intptr_t* sp, address pc, CodeBlob* cb); 157 158 // Walk from sp outward looking for old_sp, and return old_sp's predecessor 159 // (i.e. return the sp from the frame where old_sp is the fp). 160 // Register windows are assumed to be flushed for the stack in question. 161 162 static intptr_t* next_younger_sp_or_null(intptr_t* old_sp, intptr_t* sp); 163 164 // Return true if sp is a younger sp in the stack described by valid_sp. 165 static bool is_valid_stack_pointer(intptr_t* valid_sp, intptr_t* sp); 166 167 public: 168 // accessors for the instance variables 169 intptr_t* fp() const { return (intptr_t*) ((intptr_t)(sp()[FP->sp_offset_in_saved_window()]) + STACK_BIAS ); } 170 171 // All frames 172 fp_addr_at(int index) const173 intptr_t* fp_addr_at(int index) const { return &fp()[index]; } sp_addr_at(int index) const174 intptr_t* sp_addr_at(int index) const { return &sp()[index]; } fp_at(int index) const175 intptr_t fp_at( int index) const { return *fp_addr_at(index); } sp_at(int index) const176 intptr_t sp_at( int index) const { return *sp_addr_at(index); } 177 178 private: 179 inline address* I7_addr() const; 180 inline address* O7_addr() const; 181 182 inline address* I0_addr() const; 183 inline address* O0_addr() const; younger_sp_addr_at(int index) const184 intptr_t* younger_sp_addr_at(int index) const { return &younger_sp()[index]; } 185 186 public: 187 // access to SPARC arguments and argument registers 188 189 // Assumes reg is an in/local register 190 intptr_t* register_addr(Register reg) const { 191 return sp_addr_at(reg->sp_offset_in_saved_window()); 192 } 193 194 // Assumes reg is an out register out_register_addr(Register reg) const195 intptr_t* out_register_addr(Register reg) const { 196 return younger_sp_addr_at(reg->after_save()->sp_offset_in_saved_window()); 197 } 198 199 200 // Interpreter frames 201 202 public: 203 // Asm interpreter 204 enum interpreter_frame_vm_locals { 205 // 2 words, also used to save float regs across calls to C 206 interpreter_frame_d_scratch_fp_offset = -2, 207 interpreter_frame_l_scratch_fp_offset = -4, 208 interpreter_frame_mirror_offset = -5, // keep interpreted method alive 209 210 interpreter_frame_oop_temp_offset = -6, // for native calls only 211 interpreter_frame_vm_locals_fp_offset = -6, // should be same as above, and should be zero mod 8 212 213 interpreter_frame_vm_local_words = -interpreter_frame_vm_locals_fp_offset, 214 215 216 // interpreter frame set-up needs to save 2 extra words in outgoing param area 217 // for class and jnienv arguments for native stubs (see nativeStubGen_sparc.cpp_ 218 219 interpreter_frame_extra_outgoing_argument_words = 2 220 }; 221 222 enum compiler_frame_fixed_locals { 223 compiler_frame_vm_locals_fp_offset = -2 224 }; 225 226 private: 227 ConstantPoolCache** interpreter_frame_cpoolcache_addr() const; 228 229 // where Lmonitors is saved: 230 inline BasicObjectLock** interpreter_frame_monitors_addr() const; 231 inline intptr_t** interpreter_frame_esp_addr() const; 232 233 inline void interpreter_frame_set_tos_address(intptr_t* x); 234 235 // monitors: 236 237 // next two fns read and write Lmonitors value, 238 private: 239 BasicObjectLock* interpreter_frame_monitors() const; 240 void interpreter_frame_set_monitors(BasicObjectLock* monitors); 241 public: 242 243 static jint interpreter_frame_expression_stack_direction() { return -1; } 244 245 #endif // CPU_SPARC_VM_FRAME_SPARC_HPP 246