1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
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23 */
24
25 #ifndef CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
26 #define CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30
31 // <sys/trap.h> promises that the system will not use traps 16-31
32 #define ST_RESERVED_FOR_USER_0 0x10
33
34 class BiasedLockingCounters;
35
36
37 // Register aliases for parts of the system:
38
39 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
40 // across context switches in V8+ ABI. Of course, there are no 64 bit regs
41 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
42
43 // g2-g4 are scratch registers called "application globals". Their
44 // meaning is reserved to the "compilation system"--which means us!
45 // They are are not supposed to be touched by ordinary C code, although
46 // highly-optimized C code might steal them for temps. They are safe
47 // across thread switches, and the ABI requires that they be safe
48 // across function calls.
49 //
50 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
51 // across func calls, and V8+ also allows g5 to be clobbered across
52 // func calls. Also, g1 and g5 can get touched while doing shared
53 // library loading.
54 //
55 // We must not touch g7 (it is the thread-self register) and g6 is
56 // reserved for certain tools. g0, of course, is always zero.
57 //
58 // (Sources: SunSoft Compilers Group, thread library engineers.)
59
60 // %%%% The interpreter should be revisited to reduce global scratch regs.
61
62 // This global always holds the current JavaThread pointer:
63
64 REGISTER_DECLARATION(Register, G2_thread , G2);
65 REGISTER_DECLARATION(Register, G6_heapbase , G6);
66
67 // The following globals are part of the Java calling convention:
68
69 REGISTER_DECLARATION(Register, G5_method , G5);
70 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
71 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
72
73 // The following globals are used for the new C1 & interpreter calling convention:
74 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
75
76 // This local is used to preserve G2_thread in the interpreter and in stubs:
77 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
78
79 // These globals are used as scratch registers in the interpreter:
80
81 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
82 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
83 REGISTER_DECLARATION(Register, G3_scratch , G3);
84 REGISTER_DECLARATION(Register, G4_scratch , G4);
85
86 // These globals are used as short-lived scratch registers in the compiler:
87
88 REGISTER_DECLARATION(Register, Gtemp , G5);
89
90 // JSR 292 fixed register usages:
91 REGISTER_DECLARATION(Register, G5_method_type , G5);
92 REGISTER_DECLARATION(Register, G3_method_handle , G3);
93 REGISTER_DECLARATION(Register, L7_mh_SP_save , L7);
94
95 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
96 // because a single patchable "set" instruction (NativeMovConstReg,
97 // or NativeMovConstPatching for compiler1) instruction
98 // serves to set up either quantity, depending on whether the compiled
99 // call site is an inline cache or is megamorphic. See the function
100 // CompiledIC::set_to_megamorphic.
101 //
102 // If a inline cache targets an interpreted method, then the
103 // G5 register will be used twice during the call. First,
104 // the call site will be patched to load a compiledICHolder
105 // into G5. (This is an ordered pair of ic_klass, method.)
106 // The c2i adapter will first check the ic_klass, then load
107 // G5_method with the method part of the pair just before
108 // jumping into the interpreter.
109 //
110 // Note that G5_method is only the method-self for the interpreter,
111 // and is logically unrelated to G5_megamorphic_method.
112 //
113 // Invariants on G2_thread (the JavaThread pointer):
114 // - it should not be used for any other purpose anywhere
115 // - it must be re-initialized by StubRoutines::call_stub()
116 // - it must be preserved around every use of call_VM
117
118 // We can consider using g2/g3/g4 to cache more values than the
119 // JavaThread, such as the card-marking base or perhaps pointers into
120 // Eden. It's something of a waste to use them as scratch temporaries,
121 // since they are not supposed to be volatile. (Of course, if we find
122 // that Java doesn't benefit from application globals, then we can just
123 // use them as ordinary temporaries.)
124 //
125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
126 // it makes sense to use them routinely for procedure linkage,
127 // whenever the On registers are not applicable. Examples: G5_method,
128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
129 // stubs. This means that compiler stubs, etc., should be kept to a
130 // maximum of two or three G-register arguments.
131
132
133 // stub frames
134
135 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
136
137 // Interpreter frames
138
139 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
140 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
141 REGISTER_DECLARATION(Register, Lmethod , L2);
142 REGISTER_DECLARATION(Register, Llocals , L3);
143 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
144 // must match Llocals in asm interpreter
145 REGISTER_DECLARATION(Register, Lmonitors , L4);
146 REGISTER_DECLARATION(Register, Lbyte_code , L5);
147 // When calling out from the interpreter we record SP so that we can remove any extra stack
148 // space allocated during adapter transitions. This register is only live from the point
149 // of the call until we return.
150 REGISTER_DECLARATION(Register, Llast_SP , L5);
151 REGISTER_DECLARATION(Register, Lscratch , L5);
152 REGISTER_DECLARATION(Register, Lscratch2 , L6);
153 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
154
155 REGISTER_DECLARATION(Register, O5_savedSP , O5);
156 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
157 // a copy SP, so in 64-bit it's a biased value. The bias
158 // is added and removed as needed in the frame code.
159 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
160 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
161
162 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
163 // the interpreter code. If Lscratch2 needs to be used for some
164 // purpose than LcpoolCache should be restore after that for
165 // the interpreter to work right
166 // (These assignments must be compatible with L7_thread_cache; see above.)
167
168 // Lbcp points into the middle of the method object.
169
170 // Exception processing
171 // These registers are passed into exception handlers.
172 // All exception handlers require the exception object being thrown.
173 // In addition, an nmethod's exception handler must be passed
174 // the address of the call site within the nmethod, to allow
175 // proper selection of the applicable catch block.
176 // (Interpreter frames use their own bcp() for this purpose.)
177 //
178 // The Oissuing_pc value is not always needed. When jumping to a
179 // handler that is known to be interpreted, the Oissuing_pc value can be
180 // omitted. An actual catch block in compiled code receives (from its
181 // nmethod's exception handler) the thrown exception in the Oexception,
182 // but it doesn't need the Oissuing_pc.
183 //
184 // If an exception handler (either interpreted or compiled)
185 // discovers there is no applicable catch block, it updates
186 // the Oissuing_pc to the continuation PC of its own caller,
187 // pops back to that caller's stack frame, and executes that
188 // caller's exception handler. Obviously, this process will
189 // iterate until the control stack is popped back to a method
190 // containing an applicable catch block. A key invariant is
191 // that the Oissuing_pc value is always a value local to
192 // the method whose exception handler is currently executing.
193 //
194 // Note: The issuing PC value is __not__ a raw return address (I7 value).
195 // It is a "return pc", the address __following__ the call.
196 // Raw return addresses are converted to issuing PCs by frame::pc(),
197 // or by stubs. Issuing PCs can be used directly with PC range tables.
198 //
199 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
200 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
201
202 // Address is an abstraction used to represent a memory location.
203 //
204 // Note: A register location is represented via a Register, not
205 // via an address for efficiency & simplicity reasons.
206
207 class Address {
208 private:
209 Register _base; // Base register.
210 RegisterOrConstant _index_or_disp; // Index register or constant displacement.
211 RelocationHolder _rspec;
212
213 public:
Address()214 Address() : _base(noreg), _index_or_disp(noreg) {}
215
Address(Register base,RegisterOrConstant index_or_disp)216 Address(Register base, RegisterOrConstant index_or_disp)
217 : _base(base),
218 _index_or_disp(index_or_disp) {
219 }
220
Address(Register base,Register index)221 Address(Register base, Register index)
222 : _base(base),
223 _index_or_disp(index) {
224 }
225
Address(Register base,int disp)226 Address(Register base, int disp)
227 : _base(base),
228 _index_or_disp(disp) {
229 }
230
231 #ifdef ASSERT
232 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
Address(Register base,ByteSize disp)233 Address(Register base, ByteSize disp)
234 : _base(base),
235 _index_or_disp(in_bytes(disp)) {
236 }
237 #endif
238
239 // accessors
base() const240 Register base() const { return _base; }
index() const241 Register index() const { return _index_or_disp.as_register(); }
disp() const242 int disp() const { return _index_or_disp.as_constant(); }
243
has_index() const244 bool has_index() const { return _index_or_disp.is_register(); }
has_disp() const245 bool has_disp() const { return _index_or_disp.is_constant(); }
246
uses(Register reg) const247 bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
248
rtype()249 const relocInfo::relocType rtype() { return _rspec.type(); }
rspec()250 const RelocationHolder& rspec() { return _rspec; }
251
rspec(int offset) const252 RelocationHolder rspec(int offset) const {
253 return offset == 0 ? _rspec : _rspec.plus(offset);
254 }
255
256 inline bool is_simm13(int offset = 0); // check disp+offset for overflow
257
plus_disp(int plusdisp) const258 Address plus_disp(int plusdisp) const { // bump disp by a small amount
259 assert(_index_or_disp.is_constant(), "must have a displacement");
260 Address a(base(), disp() + plusdisp);
261 return a;
262 }
is_same_address(Address a) const263 bool is_same_address(Address a) const {
264 // disregard _rspec
265 return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp());
266 }
267
after_save() const268 Address after_save() const {
269 Address a = (*this);
270 a._base = a._base->after_save();
271 return a;
272 }
273
after_restore() const274 Address after_restore() const {
275 Address a = (*this);
276 a._base = a._base->after_restore();
277 return a;
278 }
279
280 // Convert the raw encoding form into the form expected by the
281 // constructor for Address.
282 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
283
284 friend class Assembler;
285 };
286
287
288 class AddressLiteral {
289 private:
290 address _address;
291 RelocationHolder _rspec;
292
rspec_from_rtype(relocInfo::relocType rtype,address addr)293 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
294 switch (rtype) {
295 case relocInfo::external_word_type:
296 return external_word_Relocation::spec(addr);
297 case relocInfo::internal_word_type:
298 return internal_word_Relocation::spec(addr);
299 case relocInfo::opt_virtual_call_type:
300 return opt_virtual_call_Relocation::spec();
301 case relocInfo::static_call_type:
302 return static_call_Relocation::spec();
303 case relocInfo::runtime_call_type:
304 return runtime_call_Relocation::spec();
305 case relocInfo::none:
306 return RelocationHolder();
307 default:
308 ShouldNotReachHere();
309 return RelocationHolder();
310 }
311 }
312
313 protected:
314 // creation
AddressLiteral()315 AddressLiteral() : _address(NULL), _rspec(NULL) {}
316
317 public:
AddressLiteral(address addr,RelocationHolder const & rspec)318 AddressLiteral(address addr, RelocationHolder const& rspec)
319 : _address(addr),
320 _rspec(rspec) {}
321
322 // Some constructors to avoid casting at the call site.
AddressLiteral(jobject obj,RelocationHolder const & rspec)323 AddressLiteral(jobject obj, RelocationHolder const& rspec)
324 : _address((address) obj),
325 _rspec(rspec) {}
326
AddressLiteral(intptr_t value,RelocationHolder const & rspec)327 AddressLiteral(intptr_t value, RelocationHolder const& rspec)
328 : _address((address) value),
329 _rspec(rspec) {}
330
AddressLiteral(address addr,relocInfo::relocType rtype=relocInfo::none)331 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
332 : _address((address) addr),
333 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
334
335 // Some constructors to avoid casting at the call site.
AddressLiteral(address * addr,relocInfo::relocType rtype=relocInfo::none)336 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
337 : _address((address) addr),
338 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
339
AddressLiteral(bool * addr,relocInfo::relocType rtype=relocInfo::none)340 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
341 : _address((address) addr),
342 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
343
AddressLiteral(const bool * addr,relocInfo::relocType rtype=relocInfo::none)344 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
345 : _address((address) addr),
346 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
347
AddressLiteral(signed char * addr,relocInfo::relocType rtype=relocInfo::none)348 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
349 : _address((address) addr),
350 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
351
AddressLiteral(int * addr,relocInfo::relocType rtype=relocInfo::none)352 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
353 : _address((address) addr),
354 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
355
AddressLiteral(intptr_t addr,relocInfo::relocType rtype=relocInfo::none)356 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
357 : _address((address) addr),
358 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
359
360 // 32-bit complains about a multiple declaration for int*.
AddressLiteral(intptr_t * addr,relocInfo::relocType rtype=relocInfo::none)361 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
362 : _address((address) addr),
363 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
364
AddressLiteral(Metadata * addr,relocInfo::relocType rtype=relocInfo::none)365 AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none)
366 : _address((address) addr),
367 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
368
AddressLiteral(Metadata ** addr,relocInfo::relocType rtype=relocInfo::none)369 AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none)
370 : _address((address) addr),
371 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
372
AddressLiteral(float * addr,relocInfo::relocType rtype=relocInfo::none)373 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
374 : _address((address) addr),
375 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
376
AddressLiteral(double * addr,relocInfo::relocType rtype=relocInfo::none)377 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
378 : _address((address) addr),
379 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
380
value() const381 intptr_t value() const { return (intptr_t) _address; }
382 int low10() const;
383
rtype() const384 const relocInfo::relocType rtype() const { return _rspec.type(); }
rspec() const385 const RelocationHolder& rspec() const { return _rspec; }
386
rspec(int offset) const387 RelocationHolder rspec(int offset) const {
388 return offset == 0 ? _rspec : _rspec.plus(offset);
389 }
390 };
391
392 // Convenience classes
393 class ExternalAddress: public AddressLiteral {
394 private:
reloc_for_target(address target)395 static relocInfo::relocType reloc_for_target(address target) {
396 // Sometimes ExternalAddress is used for values which aren't
397 // exactly addresses, like the card table base.
398 // external_word_type can't be used for values in the first page
399 // so just skip the reloc in that case.
400 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
401 }
402
403 public:
ExternalAddress(address target)404 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {}
ExternalAddress(Metadata ** target)405 ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {}
406 };
407
address_in_saved_window() const408 inline Address RegisterImpl::address_in_saved_window() const {
409 return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
410 }
411
412
413
414 // Argument is an abstraction used to represent an outgoing
415 // actual argument or an incoming formal parameter, whether
416 // it resides in memory or in a register, in a manner consistent
417 // with the SPARC Application Binary Interface, or ABI. This is
418 // often referred to as the native or C calling convention.
419
420 class Argument {
421 private:
422 int _number;
423 bool _is_in;
424
425 public:
426 enum {
427 n_register_parameters = 6, // only 6 registers may contain integer parameters
428 n_float_register_parameters = 16 // Can have up to 16 floating registers
429 };
430
431 // creation
Argument(int number,bool is_in)432 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
433
number() const434 int number() const { return _number; }
is_in() const435 bool is_in() const { return _is_in; }
is_out() const436 bool is_out() const { return !is_in(); }
437
successor() const438 Argument successor() const { return Argument(number() + 1, is_in()); }
as_in() const439 Argument as_in() const { return Argument(number(), true ); }
as_out() const440 Argument as_out() const { return Argument(number(), false); }
441
442 // locating register-based arguments:
is_register() const443 bool is_register() const { return _number < n_register_parameters; }
444
445 // locating Floating Point register-based arguments:
is_float_register() const446 bool is_float_register() const { return _number < n_float_register_parameters; }
447
as_float_register() const448 FloatRegister as_float_register() const {
449 assert(is_float_register(), "must be a register argument");
450 return as_FloatRegister(( number() *2 ) + 1);
451 }
as_double_register() const452 FloatRegister as_double_register() const {
453 assert(is_float_register(), "must be a register argument");
454 return as_FloatRegister(( number() *2 ));
455 }
456
as_register() const457 Register as_register() const {
458 assert(is_register(), "must be a register argument");
459 return is_in() ? as_iRegister(number()) : as_oRegister(number());
460 }
461
462 // locating memory-based arguments
as_address() const463 Address as_address() const {
464 assert(!is_register(), "must be a memory argument");
465 return address_in_frame();
466 }
467
468 // When applied to a register-based argument, give the corresponding address
469 // into the 6-word area "into which callee may store register arguments"
470 // (This is a different place than the corresponding register-save area location.)
471 Address address_in_frame() const;
472
473 // debugging
474 const char* name() const;
475
476 friend class Assembler;
477 };
478
479
480 class RegistersForDebugging : public StackObj {
481 public:
482 intptr_t i[8], l[8], o[8], g[8];
483 float f[32];
484 double d[32];
485
486 void print(outputStream* s);
487
i_offset(int j)488 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
l_offset(int j)489 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
o_offset(int j)490 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
g_offset(int j)491 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
f_offset(int j)492 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
d_offset(int j)493 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
494
495 // gen asm code to save regs
496 static void save_registers(MacroAssembler* a);
497
498 // restore global registers in case C code disturbed them
499 static void restore_registers(MacroAssembler* a, Register r);
500 };
501
502
503 // MacroAssembler extends Assembler by a few frequently used macros.
504 //
505 // Most of the standard SPARC synthetic ops are defined here.
506 // Instructions for which a 'better' code sequence exists depending
507 // on arguments should also go in here.
508
509 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
510 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
511 #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__)
512 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
513
514
515 class MacroAssembler : public Assembler {
516 // code patchers need various routines like inv_wdisp()
517 friend class NativeInstruction;
518 friend class NativeGeneralJump;
519 friend class Relocation;
520 friend class Label;
521
522 protected:
523 static int patched_branch(int dest_pos, int inst, int inst_pos);
524 static int branch_destination(int inst, int pos);
525
526 // Support for VM calls
527 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
528 // may customize this version by overriding it for its purposes (e.g., to save/restore
529 // additional registers when doing a VM call).
530 virtual void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
531
532 //
533 // It is imperative that all calls into the VM are handled via the call_VM macros.
534 // They make sure that the stack linkage is setup correctly. call_VM's correspond
535 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
536 //
537 // This is the base routine called by the different versions of call_VM. The interpreter
538 // may customize this version by overriding it for its purposes (e.g., to save/restore
539 // additional registers when doing a VM call).
540 //
541 // A non-volatile java_thread_cache register should be specified so
542 // that the G2_thread value can be preserved across the call.
543 // (If java_thread_cache is noreg, then a slow get_thread call
544 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
545 // thread.
546 //
547 // If no last_java_sp is specified (noreg) than SP will be used instead.
548
549 virtual void call_VM_base(
550 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
551 Register java_thread_cache, // the thread if computed before ; use noreg otherwise
552 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
553 address entry_point, // the entry point
554 int number_of_arguments, // the number of arguments (w/o thread) to pop after call
555 bool check_exception=true // flag which indicates if exception should be checked
556 );
557
558 public:
MacroAssembler(CodeBuffer * code)559 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
560
561 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
562 // The implementation is only non-empty for the InterpreterMacroAssembler,
563 // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
564 virtual void check_and_handle_popframe(Register scratch_reg);
565 virtual void check_and_handle_earlyret(Register scratch_reg);
566
567 // Support for NULL-checks
568 //
569 // Generates code that causes a NULL OS exception if the content of reg is NULL.
570 // If the accessed location is M[reg + offset] and the offset is known, provide the
571 // offset. No explicit code generation is needed if the offset is within a certain
572 // range (0 <= offset <= page_size).
573 //
574 // FIXME: Currently not done for SPARC
575
576 void null_check(Register reg, int offset = -1);
577 static bool needs_explicit_null_check(intptr_t offset);
578
579 // support for delayed instructions
delayed()580 MacroAssembler* delayed() { Assembler::delayed(); return this; }
581
582 // branches that use right instruction for v8 vs. v9
583 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
584 inline void br( Condition c, bool a, Predict p, Label& L );
585
586 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
587 inline void fb( Condition c, bool a, Predict p, Label& L );
588
589 // compares register with zero (32 bit) and branches (V9 and V8 instructions)
590 void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
591 // Compares a pointer register with zero and branches on (not)null.
592 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
593 void br_null ( Register s1, bool a, Predict p, Label& L );
594 void br_notnull( Register s1, bool a, Predict p, Label& L );
595
596 //
597 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
598 //
599 // ATTENTION: use these instructions with caution because cbcond instruction
600 // has very short distance: 512 instructions (2Kbyte).
601
602 // Compare integer (32 bit) values (icc only).
603 void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
604 void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
605 // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
606 void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
607 void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
608
609 // Short branch version for compares a pointer pwith zero.
610 void br_null_short ( Register s1, Predict p, Label& L );
611 void br_notnull_short( Register s1, Predict p, Label& L );
612
613 // unconditional short branch
614 void ba_short(Label& L);
615
616 // Branch on icc.z (true or not).
617 void br_icc_zero(bool iszero, Predict p, Label &L);
618
619 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
620 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
621
622 // Branch that tests xcc in LP64 and icc in !LP64
623 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
624 inline void brx( Condition c, bool a, Predict p, Label& L );
625
626 // unconditional branch
627 inline void ba( Label& L );
628
629 // Branch that tests fp condition codes
630 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
631 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
632
633 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
634 inline void cmp( Register s1, Register s2 );
635 inline void cmp( Register s1, int simm13a );
636
637 inline void jmp( Register s1, Register s2 );
638 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
639
640 // Check if the call target is out of wdisp30 range (relative to the code cache)
641 static inline bool is_far_target(address d);
642 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
643 inline void call( address d, RelocationHolder const& rspec);
644
645 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
646 inline void call( Label& L, RelocationHolder const& rspec);
647
648 inline void callr( Register s1, Register s2 );
649 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
650
651 // Emits nothing on V8
652 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
653 inline void iprefetch( Label& L);
654
655 inline void tst( Register s );
656
657 inline void ret( bool trace = false );
658 inline void retl( bool trace = false );
659
660 // Required platform-specific helpers for Label::patch_instructions.
661 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
662 void pd_patch_instruction(address branch, address target);
663
664 // sethi Macro handles optimizations and relocations
665 private:
666 void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
667 public:
668 void sethi(const AddressLiteral& addrlit, Register d);
669 void patchable_sethi(const AddressLiteral& addrlit, Register d);
670
671 // compute the number of instructions for a sethi/set
672 static int insts_for_sethi( address a, bool worst_case = false );
673 static int worst_case_insts_for_set();
674
675 // set may be either setsw or setuw (high 32 bits may be zero or sign)
676 private:
677 void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
678 static int insts_for_internal_set(intptr_t value);
679 public:
680 void set(const AddressLiteral& addrlit, Register d);
681 void set(intptr_t value, Register d);
682 void set(address addr, Register d, RelocationHolder const& rspec);
insts_for_set(intptr_t value)683 static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
684
685 void patchable_set(const AddressLiteral& addrlit, Register d);
686 void patchable_set(intptr_t value, Register d);
687 void set64(jlong value, Register d, Register tmp);
688 static int insts_for_set64(jlong value);
689
690 // sign-extend 32 to 64
691 inline void signx( Register s, Register d );
692 inline void signx( Register d );
693
694 inline void not1( Register s, Register d );
695 inline void not1( Register d );
696
697 inline void neg( Register s, Register d );
698 inline void neg( Register d );
699
700 inline void cas( Register s1, Register s2, Register d);
701 inline void casx( Register s1, Register s2, Register d);
702 // Functions for isolating 64 bit atomic swaps for LP64
703 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
704 inline void cas_ptr( Register s1, Register s2, Register d);
705
706 // Resolve a jobject or jweak
707 void resolve_jobject(Register value, Register tmp);
708
709 // Functions for isolating 64 bit shifts for LP64
710 inline void sll_ptr( Register s1, Register s2, Register d );
711 inline void sll_ptr( Register s1, int imm6a, Register d );
712 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
713 inline void srl_ptr( Register s1, Register s2, Register d );
714 inline void srl_ptr( Register s1, int imm6a, Register d );
715
716 // little-endian
717 inline void casl( Register s1, Register s2, Register d);
718 inline void casxl( Register s1, Register s2, Register d);
719
720 inline void inc( Register d, int const13 = 1 );
721 inline void inccc( Register d, int const13 = 1 );
722
723 inline void dec( Register d, int const13 = 1 );
724 inline void deccc( Register d, int const13 = 1 );
725
726 using Assembler::add;
727 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype);
728 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
729 inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
730 inline void add(const Address& a, Register d, int offset = 0);
731
732 using Assembler::andn;
733 inline void andn( Register s1, RegisterOrConstant s2, Register d);
734
735 inline void btst( Register s1, Register s2 );
736 inline void btst( int simm13a, Register s );
737
738 inline void bset( Register s1, Register s2 );
739 inline void bset( int simm13a, Register s );
740
741 inline void bclr( Register s1, Register s2 );
742 inline void bclr( int simm13a, Register s );
743
744 inline void btog( Register s1, Register s2 );
745 inline void btog( int simm13a, Register s );
746
747 inline void clr( Register d );
748
749 inline void clrb( Register s1, Register s2);
750 inline void clrh( Register s1, Register s2);
751 inline void clr( Register s1, Register s2);
752 inline void clrx( Register s1, Register s2);
753
754 inline void clrb( Register s1, int simm13a);
755 inline void clrh( Register s1, int simm13a);
756 inline void clr( Register s1, int simm13a);
757 inline void clrx( Register s1, int simm13a);
758
759 // copy & clear upper word
760 inline void clruw( Register s, Register d );
761 // clear upper word
762 inline void clruwu( Register d );
763
764 using Assembler::ldsb;
765 using Assembler::ldsh;
766 using Assembler::ldsw;
767 using Assembler::ldub;
768 using Assembler::lduh;
769 using Assembler::lduw;
770 using Assembler::ldx;
771 using Assembler::ldd;
772
773 #ifdef ASSERT
774 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
775 inline void ld(Register s1, ByteSize simm13a, Register d);
776 #endif
777
778 inline void ld(Register s1, Register s2, Register d);
779 inline void ld(Register s1, int simm13a, Register d);
780
781 inline void ldsb(const Address& a, Register d, int offset = 0);
782 inline void ldsh(const Address& a, Register d, int offset = 0);
783 inline void ldsw(const Address& a, Register d, int offset = 0);
784 inline void ldub(const Address& a, Register d, int offset = 0);
785 inline void lduh(const Address& a, Register d, int offset = 0);
786 inline void lduw(const Address& a, Register d, int offset = 0);
787 inline void ldx( const Address& a, Register d, int offset = 0);
788 inline void ld( const Address& a, Register d, int offset = 0);
789 inline void ldd( const Address& a, Register d, int offset = 0);
790
791 inline void ldub(Register s1, RegisterOrConstant s2, Register d );
792 inline void ldsb(Register s1, RegisterOrConstant s2, Register d );
793 inline void lduh(Register s1, RegisterOrConstant s2, Register d );
794 inline void ldsh(Register s1, RegisterOrConstant s2, Register d );
795 inline void lduw(Register s1, RegisterOrConstant s2, Register d );
796 inline void ldsw(Register s1, RegisterOrConstant s2, Register d );
797 inline void ldx( Register s1, RegisterOrConstant s2, Register d );
798 inline void ld( Register s1, RegisterOrConstant s2, Register d );
799 inline void ldd( Register s1, RegisterOrConstant s2, Register d );
800
801 using Assembler::ldf;
802 inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
803 inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
804
805 // little-endian
806 inline void lduwl(Register s1, Register s2, Register d);
807 inline void ldswl(Register s1, Register s2, Register d);
808 inline void ldxl( Register s1, Register s2, Register d);
809 inline void ldfl(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
810
811 // membar psuedo instruction. takes into account target memory model.
812 inline void membar( Assembler::Membar_mask_bits const7a );
813
814 // returns if membar generates anything.
815 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
816
817 // mov pseudo instructions
818 inline void mov( Register s, Register d);
819
820 inline void mov_or_nop( Register s, Register d);
821
822 inline void mov( int simm13a, Register d);
823
824 using Assembler::prefetch;
825 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
826
827 using Assembler::stb;
828 using Assembler::sth;
829 using Assembler::stw;
830 using Assembler::stx;
831 using Assembler::std;
832
833 #ifdef ASSERT
834 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
835 inline void st(Register d, Register s1, ByteSize simm13a);
836 #endif
837
838 inline void st(Register d, Register s1, Register s2);
839 inline void st(Register d, Register s1, int simm13a);
840
841 inline void stb(Register d, const Address& a, int offset = 0 );
842 inline void sth(Register d, const Address& a, int offset = 0 );
843 inline void stw(Register d, const Address& a, int offset = 0 );
844 inline void stx(Register d, const Address& a, int offset = 0 );
845 inline void st( Register d, const Address& a, int offset = 0 );
846 inline void std(Register d, const Address& a, int offset = 0 );
847
848 inline void stb(Register d, Register s1, RegisterOrConstant s2 );
849 inline void sth(Register d, Register s1, RegisterOrConstant s2 );
850 inline void stw(Register d, Register s1, RegisterOrConstant s2 );
851 inline void stx(Register d, Register s1, RegisterOrConstant s2 );
852 inline void std(Register d, Register s1, RegisterOrConstant s2 );
853 inline void st( Register d, Register s1, RegisterOrConstant s2 );
854
855 using Assembler::stf;
856 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
857 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
858
859 // Note: offset is added to s2.
860 using Assembler::sub;
861 inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
862
863 using Assembler::swap;
864 inline void swap(const Address& a, Register d, int offset = 0);
865
866 // address pseudos: make these names unlike instruction names to avoid confusion
867 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
868 inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
869 inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
870 inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
871 inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
872 inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
873 inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
874 inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
875 inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
876
877 // ring buffer traceable jumps
878
879 void jmp2( Register r1, Register r2, const char* file, int line );
880 void jmp ( Register r1, int offset, const char* file, int line );
881
882 void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
883 void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line);
884
885
886 // argument pseudos:
887
888 inline void load_argument( Argument& a, Register d );
889 inline void store_argument( Register s, Argument& a );
890 inline void store_ptr_argument( Register s, Argument& a );
891 inline void store_float_argument( FloatRegister s, Argument& a );
892 inline void store_double_argument( FloatRegister s, Argument& a );
893 inline void store_long_argument( Register s, Argument& a );
894
895 // handy macros:
896
897 inline void round_to( Register r, int modulus );
898
899 // --------------------------------------------------
900
901 // Functions for isolating 64 bit loads for LP64
902 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
903 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
904 inline void ld_ptr(Register s1, Register s2, Register d);
905 inline void ld_ptr(Register s1, int simm13a, Register d);
906 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
907 inline void ld_ptr(const Address& a, Register d, int offset = 0);
908 inline void st_ptr(Register d, Register s1, Register s2);
909 inline void st_ptr(Register d, Register s1, int simm13a);
910 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
911 inline void st_ptr(Register d, const Address& a, int offset = 0);
912
913 #ifdef ASSERT
914 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
915 inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
916 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
917 #endif
918
919 // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
920 // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
921 inline void ld_long(Register s1, Register s2, Register d);
922 inline void ld_long(Register s1, int simm13a, Register d);
923 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
924 inline void ld_long(const Address& a, Register d, int offset = 0);
925 inline void st_long(Register d, Register s1, Register s2);
926 inline void st_long(Register d, Register s1, int simm13a);
927 inline void st_long(Register d, Register s1, RegisterOrConstant s2);
928 inline void st_long(Register d, const Address& a, int offset = 0);
929
930 // Helpers for address formation.
931 // - They emit only a move if s2 is a constant zero.
932 // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
933 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
934 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
935 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
936 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
937
ensure_simm13_or_reg(RegisterOrConstant src,Register temp)938 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
939 if (is_simm13(src.constant_or_zero()))
940 return src; // register or short constant
941 guarantee(temp != noreg, "constant offset overflow");
942 set(src.as_constant(), temp);
943 return temp;
944 }
945
946 // --------------------------------------------------
947
948 public:
949 // traps as per trap.h (SPARC ABI?)
950
951 void breakpoint_trap();
952 void breakpoint_trap(Condition c, CC cc);
953
954 // Support for serializing memory accesses between threads
955 void serialize_memory(Register thread, Register tmp1, Register tmp2);
956
957 void safepoint_poll(Label& slow_path, bool a, Register thread_reg, Register temp_reg);
958
959 // Stack frame creation/removal
960 void enter();
961 void leave();
962
963 // Manipulation of C++ bools
964 // These are idioms to flag the need for care with accessing bools but on
965 // this platform we assume byte size
966
967 inline void stbool(Register d, const Address& a);
968 inline void ldbool(const Address& a, Register d);
969 inline void movbool( bool boolconst, Register d);
970
971 void resolve_oop_handle(Register result, Register tmp);
972 void load_mirror(Register mirror, Register method, Register tmp);
973
974 // klass oop manipulations if compressed
975 void load_klass(Register src_oop, Register klass);
976 void store_klass(Register klass, Register dst_oop);
977 void store_klass_gap(Register s, Register dst_oop);
978
979 // oop manipulations
980 void access_store_at(BasicType type, DecoratorSet decorators,
981 Register src, Address dst, Register tmp);
982 void access_load_at(BasicType type, DecoratorSet decorators,
983 Address src, Register dst, Register tmp);
984
985 void load_heap_oop(const Address& s, Register d,
986 Register tmp = noreg, DecoratorSet decorators = 0);
987 void load_heap_oop(Register s1, Register s2, Register d,
988 Register tmp = noreg, DecoratorSet decorators = 0);
989 void load_heap_oop(Register s1, int simm13a, Register d,
990 Register tmp = noreg, DecoratorSet decorators = 0);
991 void load_heap_oop(Register s1, RegisterOrConstant s2, Register d,
992 Register tmp = noreg, DecoratorSet decorators = 0);
993 void store_heap_oop(Register d, Register s1, Register s2,
994 Register tmp = noreg, DecoratorSet decorators = 0);
995 void store_heap_oop(Register d, Register s1, int simm13a,
996 Register tmp = noreg, DecoratorSet decorators = 0);
997 void store_heap_oop(Register d, const Address& a, int offset = 0,
998 Register tmp = noreg, DecoratorSet decorators = 0);
999
1000 void encode_heap_oop(Register src, Register dst);
encode_heap_oop(Register r)1001 void encode_heap_oop(Register r) {
1002 encode_heap_oop(r, r);
1003 }
1004 void decode_heap_oop(Register src, Register dst);
decode_heap_oop(Register r)1005 void decode_heap_oop(Register r) {
1006 decode_heap_oop(r, r);
1007 }
1008 void encode_heap_oop_not_null(Register r);
1009 void decode_heap_oop_not_null(Register r);
1010 void encode_heap_oop_not_null(Register src, Register dst);
1011 void decode_heap_oop_not_null(Register src, Register dst);
1012
1013 void encode_klass_not_null(Register r);
1014 void decode_klass_not_null(Register r);
1015 void encode_klass_not_null(Register src, Register dst);
1016 void decode_klass_not_null(Register src, Register dst);
1017
1018 // Support for managing the JavaThread pointer (i.e.; the reference to
1019 // thread-local information).
1020 void get_thread(); // load G2_thread
1021 void verify_thread(); // verify G2_thread contents
1022 void save_thread (const Register threache); // save to cache
1023 void restore_thread(const Register thread_cache); // restore from cache
1024
1025 // Support for last Java frame (but use call_VM instead where possible)
1026 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
1027 void reset_last_Java_frame(void);
1028
1029 // Call into the VM.
1030 // Passes the thread pointer (in O0) as a prepended argument.
1031 // Makes sure oop return values are visible to the GC.
1032 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1033 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
1034 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1035 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1036
1037 // these overloadings are not presently used on SPARC:
1038 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1039 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1040 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1041 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1042
1043 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
1044 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
1045 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
1046 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
1047
1048 void get_vm_result (Register oop_result);
1049 void get_vm_result_2(Register metadata_result);
1050
1051 // vm result is currently getting hijacked to for oop preservation
1052 void set_vm_result(Register oop_result);
1053
1054 // Emit the CompiledIC call idiom
1055 void ic_call(address entry, bool emit_delay = true, jint method_index = 0);
1056
1057 // if call_VM_base was called with check_exceptions=false, then call
1058 // check_and_forward_exception to handle exceptions when it is safe
1059 void check_and_forward_exception(Register scratch_reg);
1060
1061 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1062 void push_fTOS();
1063
1064 // pops double TOS element from CPU stack and pushes on FPU stack
1065 void pop_fTOS();
1066
1067 void empty_FPU_stack();
1068
1069 void push_IU_state();
1070 void pop_IU_state();
1071
1072 void push_FPU_state();
1073 void pop_FPU_state();
1074
1075 void push_CPU_state();
1076 void pop_CPU_state();
1077
1078 // Returns the byte size of the instructions generated by decode_klass_not_null().
1079 static int instr_size_for_decode_klass_not_null();
1080
1081 // if heap base register is used - reinit it with the correct value
1082 void reinit_heapbase();
1083
1084 // Debugging
1085 void _verify_oop(Register reg, const char * msg, const char * file, int line);
1086 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
1087
1088 // TODO: verify_method and klass metadata (compare against vptr?)
_verify_method_ptr(Register reg,const char * msg,const char * file,int line)1089 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
_verify_klass_ptr(Register reg,const char * msg,const char * file,int line)1090 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1091
1092 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
1093 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
1094 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1095 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1096
1097 // only if +VerifyOops
1098 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1099 // only if +VerifyFPU
1100 void stop(const char* msg); // prints msg, dumps registers and stops execution
1101 void warn(const char* msg); // prints msg, but don't stop
1102 void untested(const char* what = "");
1103 void unimplemented(const char* what = "");
should_not_reach_here()1104 void should_not_reach_here() { stop("should not reach here"); }
1105 void print_CPU_state();
1106
1107 // oops in code
1108 AddressLiteral allocate_oop_address(jobject obj); // allocate_index
1109 AddressLiteral constant_oop_address(jobject obj); // find_index
1110 inline void set_oop (jobject obj, Register d); // uses allocate_oop_address
1111 inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address
1112 inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address
1113
1114 // metadata in code that we have to keep track of
1115 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
1116 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
1117 inline void set_metadata (Metadata* obj, Register d); // uses allocate_metadata_address
1118 inline void set_metadata_constant (Metadata* obj, Register d); // uses constant_metadata_address
1119 inline void set_metadata (const AddressLiteral& obj_addr, Register d); // same as load_address
1120
1121 void set_narrow_oop( jobject obj, Register d );
1122 void set_narrow_klass( Klass* k, Register d );
1123
1124 // nop padding
1125 void align(int modulus);
1126
1127 // declare a safepoint
1128 void safepoint();
1129
1130 // factor out part of stop into subroutine to save space
1131 void stop_subroutine();
1132 // factor out part of verify_oop into subroutine to save space
1133 void verify_oop_subroutine();
1134
1135 // side-door communication with signalHandler in os_solaris.cpp
1136 static address _verify_oop_implicit_branch[3];
1137
1138 int total_frame_size_in_bytes(int extraWords);
1139
1140 // used when extraWords known statically
1141 void save_frame(int extraWords = 0);
1142 void save_frame_c1(int size_in_bytes);
1143 // make a frame, and simultaneously pass up one or two register value
1144 // into the new register window
1145 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
1146
1147 // give no. (outgoing) params, calc # of words will need on frame
1148 void calc_mem_param_words(Register Rparam_words, Register Rresult);
1149
1150 // used to calculate frame size dynamically
1151 // result is in bytes and must be negated for save inst
1152 void calc_frame_size(Register extraWords, Register resultReg);
1153
1154 // calc and also save
1155 void calc_frame_size_and_save(Register extraWords, Register resultReg);
1156
1157 static void debug(char* msg, RegistersForDebugging* outWindow);
1158
1159 // implementations of bytecodes used by both interpreter and compiler
1160
1161 void lcmp( Register Ra_hi, Register Ra_low,
1162 Register Rb_hi, Register Rb_low,
1163 Register Rresult);
1164
1165 void lneg( Register Rhi, Register Rlow );
1166
1167 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
1168 Register Rout_high, Register Rout_low, Register Rtemp );
1169
1170 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
1171 Register Rout_high, Register Rout_low, Register Rtemp );
1172
1173 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
1174 Register Rout_high, Register Rout_low, Register Rtemp );
1175
1176 void lcmp( Register Ra, Register Rb, Register Rresult);
1177
1178 // Load and store values by size and signed-ness
1179 void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
1180 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1181
1182 void float_cmp( bool is_float, int unordered_result,
1183 FloatRegister Fa, FloatRegister Fb,
1184 Register Rresult);
1185
1186 void save_all_globals_into_locals();
1187 void restore_globals_from_locals();
1188
1189 // These set the icc condition code to equal if the lock succeeded
1190 // and notEqual if it failed and requires a slow case
1191 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
1192 Register Rscratch,
1193 BiasedLockingCounters* counters = NULL,
1194 bool try_bias = UseBiasedLocking);
1195 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
1196 Register Rscratch,
1197 bool try_bias = UseBiasedLocking);
1198
1199 // Biased locking support
1200 // Upon entry, lock_reg must point to the lock record on the stack,
1201 // obj_reg must contain the target object, and mark_reg must contain
1202 // the target object's header.
1203 // Destroys mark_reg if an attempt is made to bias an anonymously
1204 // biased lock. In this case a failure will go either to the slow
1205 // case or fall through with the notEqual condition code set with
1206 // the expectation that the slow case in the runtime will be called.
1207 // In the fall-through case where the CAS-based lock is done,
1208 // mark_reg is not destroyed.
1209 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
1210 Label& done, Label* slow_case = NULL,
1211 BiasedLockingCounters* counters = NULL);
1212 // Upon entry, the base register of mark_addr must contain the oop.
1213 // Destroys temp_reg.
1214
1215 // If allow_delay_slot_filling is set to true, the next instruction
1216 // emitted after this one will go in an annulled delay slot if the
1217 // biased locking exit case failed.
1218 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
1219
1220 // allocation
1221 void eden_allocate(
1222 Register obj, // result: pointer to object after successful allocation
1223 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1224 int con_size_in_bytes, // object size in bytes if known at compile time
1225 Register t1, // temp register
1226 Register t2, // temp register
1227 Label& slow_case // continuation point if fast allocation fails
1228 );
1229 void tlab_allocate(
1230 Register obj, // result: pointer to object after successful allocation
1231 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1232 int con_size_in_bytes, // object size in bytes if known at compile time
1233 Register t1, // temp register
1234 Label& slow_case // continuation point if fast allocation fails
1235 );
1236 void zero_memory(Register base, Register index);
1237 void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
1238 Register t1, Register t2);
1239
1240 // interface method calling
1241 void lookup_interface_method(Register recv_klass,
1242 Register intf_klass,
1243 RegisterOrConstant itable_index,
1244 Register method_result,
1245 Register temp_reg, Register temp2_reg,
1246 Label& no_such_interface,
1247 bool return_method = true);
1248
1249 // virtual method calling
1250 void lookup_virtual_method(Register recv_klass,
1251 RegisterOrConstant vtable_index,
1252 Register method_result);
1253
1254 // Test sub_klass against super_klass, with fast and slow paths.
1255
1256 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1257 // One of the three labels can be NULL, meaning take the fall-through.
1258 // If super_check_offset is -1, the value is loaded up from super_klass.
1259 // No registers are killed, except temp_reg and temp2_reg.
1260 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
1261 void check_klass_subtype_fast_path(Register sub_klass,
1262 Register super_klass,
1263 Register temp_reg,
1264 Register temp2_reg,
1265 Label* L_success,
1266 Label* L_failure,
1267 Label* L_slow_path,
1268 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1269
1270 // The rest of the type check; must be wired to a corresponding fast path.
1271 // It does not repeat the fast path logic, so don't use it standalone.
1272 // The temp_reg can be noreg, if no temps are available.
1273 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
1274 // Updates the sub's secondary super cache as necessary.
1275 void check_klass_subtype_slow_path(Register sub_klass,
1276 Register super_klass,
1277 Register temp_reg,
1278 Register temp2_reg,
1279 Register temp3_reg,
1280 Register temp4_reg,
1281 Label* L_success,
1282 Label* L_failure);
1283
1284 // Simplified, combined version, good for typical uses.
1285 // Falls through on failure.
1286 void check_klass_subtype(Register sub_klass,
1287 Register super_klass,
1288 Register temp_reg,
1289 Register temp2_reg,
1290 Label& L_success);
1291
1292 // method handles (JSR 292)
1293 // offset relative to Gargs of argument at tos[arg_slot].
1294 // (arg_slot == 0 means the last argument, not the first).
1295 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
1296 Register temp_reg,
1297 int extra_slot_offset = 0);
1298 // Address of Gargs and argument_offset.
1299 Address argument_address(RegisterOrConstant arg_slot,
1300 Register temp_reg = noreg,
1301 int extra_slot_offset = 0);
1302
1303 // Stack overflow checking
1304
1305 // Note: this clobbers G3_scratch
1306 void bang_stack_with_offset(int offset);
1307
1308 // Writes to stack successive pages until offset reached to check for
1309 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
1310 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
1311
1312 // Check for reserved stack access in method being exited (for JIT)
1313 void reserved_stack_check();
1314
1315 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
1316
1317 void verify_tlab();
1318
1319 Condition negate_condition(Condition cond);
1320
1321 // Helper functions for statistics gathering.
1322 // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
1323 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
1324 // Unconditional increment.
1325 void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
1326 void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2);
1327
1328 #ifdef COMPILER2
1329 // Compress char[] to byte[] by compressing 16 bytes at once. Return 0 on failure.
1330 void string_compress_16(Register src, Register dst, Register cnt, Register result,
1331 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
1332 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, Label& Ldone);
1333
1334 // Compress char[] to byte[]. Return 0 on failure.
1335 void string_compress(Register src, Register dst, Register cnt, Register tmp, Register result, Label& Ldone);
1336
1337 // Inflate byte[] to char[] by inflating 16 bytes at once.
1338 void string_inflate_16(Register src, Register dst, Register cnt, Register tmp,
1339 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, FloatRegister ftmp4, Label& Ldone);
1340
1341 // Inflate byte[] to char[].
1342 void string_inflate(Register src, Register dst, Register cnt, Register tmp, Label& Ldone);
1343
1344 void string_compare(Register str1, Register str2,
1345 Register cnt1, Register cnt2,
1346 Register tmp1, Register tmp2,
1347 Register result, int ae);
1348
1349 void array_equals(bool is_array_equ, Register ary1, Register ary2,
1350 Register limit, Register tmp, Register result, bool is_byte);
1351 // test for negative bytes in input string of a given size, result 0 if none
1352 void has_negatives(Register inp, Register size, Register result,
1353 Register t2, Register t3, Register t4,
1354 Register t5);
1355
1356 #endif
1357
1358 // Use BIS for zeroing
1359 void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
1360
1361 // Update CRC-32[C] with a byte value according to constants in table
1362 void update_byte_crc32(Register crc, Register val, Register table);
1363
1364 // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros
1365 void reverse_bytes_32(Register src, Register dst, Register tmp);
1366 void movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2);
1367 void movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2);
1368
1369 // CRC32 code for java.util.zip.CRC32::updateBytes0() intrinsic.
1370 void kernel_crc32(Register crc, Register buf, Register len, Register table);
1371 // Fold 128-bit data chunk
1372 void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset);
1373 void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo);
1374 // Fold 8-bit data
1375 void fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp);
1376 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1377 // CRC32C code for java.util.zip.CRC32C::updateBytes/updateDirectByteBuffer intrinsic.
1378 void kernel_crc32c(Register crc, Register buf, Register len, Register table);
1379
1380 };
1381
1382 /**
1383 * class SkipIfEqual:
1384 *
1385 * Instantiating this class will result in assembly code being output that will
1386 * jump around any code emitted between the creation of the instance and it's
1387 * automatic destruction at the end of a scope block, depending on the value of
1388 * the flag passed to the constructor, which will be checked at run-time.
1389 */
1390 class SkipIfEqual : public StackObj {
1391 private:
1392 MacroAssembler* _masm;
1393 Label _label;
1394
1395 public:
1396 // 'temp' is a temp register that this object can use (and trash)
1397 SkipIfEqual(MacroAssembler*, Register temp,
1398 const bool* flag_addr, Assembler::Condition condition);
1399 ~SkipIfEqual();
1400 };
1401
1402 #endif // CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
1403