1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP 26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP 27 28 #include "runtime/abstract_vm_version.hpp" 29 #include "runtime/globals_extension.hpp" 30 31 class VM_Version: public Abstract_VM_Version { 32 friend class VMStructs; 33 friend class JVMCIVMStructs; 34 35 protected: 36 enum { 37 ISA_V9, 38 ISA_POPC, 39 ISA_VIS1, 40 ISA_VIS2, 41 ISA_BLK_INIT, 42 ISA_FMAF, 43 ISA_VIS3, 44 ISA_HPC, 45 ISA_FJATHHPC, 46 ISA_IMA, 47 ISA_AES, 48 ISA_DES, 49 ISA_KASUMI, 50 ISA_CAMELLIA, 51 ISA_MD5, 52 ISA_SHA1, 53 ISA_SHA256, 54 ISA_SHA512, 55 ISA_MPMUL, 56 ISA_MONT, 57 ISA_PAUSE, 58 ISA_CBCOND, 59 ISA_CRC32C, 60 61 ISA_FJATHPLUS, 62 ISA_VIS3B, 63 ISA_ADI, 64 ISA_SPARC5, 65 ISA_MWAIT, 66 ISA_XMPMUL, 67 ISA_XMONT, 68 ISA_PAUSE_NSEC, 69 ISA_VAMASK, 70 71 ISA_SPARC6, 72 ISA_DICTUNP, 73 ISA_FPCMPSHL, 74 ISA_RLE, 75 ISA_SHA3, 76 ISA_FJATHPLUS2, 77 ISA_VIS3C, 78 ISA_SPARC5B, 79 ISA_MME, 80 81 // Synthesised properties: 82 83 CPU_FAST_IDIV, 84 CPU_FAST_RDPC, 85 CPU_FAST_BIS, 86 CPU_FAST_LD, 87 CPU_FAST_CMOVE, 88 CPU_FAST_IND_BR, 89 CPU_BLK_ZEROING 90 }; 91 92 private: 93 enum { ISA_last_feature = ISA_MME, 94 CPU_last_feature = CPU_BLK_ZEROING }; 95 96 enum { 97 ISA_unknown_msk = 0, 98 99 ISA_v9_msk = UINT64_C(1) << ISA_V9, 100 101 ISA_popc_msk = UINT64_C(1) << ISA_POPC, 102 ISA_vis1_msk = UINT64_C(1) << ISA_VIS1, 103 ISA_vis2_msk = UINT64_C(1) << ISA_VIS2, 104 ISA_blk_init_msk = UINT64_C(1) << ISA_BLK_INIT, 105 ISA_fmaf_msk = UINT64_C(1) << ISA_FMAF, 106 ISA_vis3_msk = UINT64_C(1) << ISA_VIS3, 107 ISA_hpc_msk = UINT64_C(1) << ISA_HPC, 108 ISA_fjathhpc_msk = UINT64_C(1) << ISA_FJATHHPC, 109 ISA_ima_msk = UINT64_C(1) << ISA_IMA, 110 ISA_aes_msk = UINT64_C(1) << ISA_AES, 111 ISA_des_msk = UINT64_C(1) << ISA_DES, 112 ISA_kasumi_msk = UINT64_C(1) << ISA_KASUMI, 113 ISA_camellia_msk = UINT64_C(1) << ISA_CAMELLIA, 114 ISA_md5_msk = UINT64_C(1) << ISA_MD5, 115 ISA_sha1_msk = UINT64_C(1) << ISA_SHA1, 116 ISA_sha256_msk = UINT64_C(1) << ISA_SHA256, 117 ISA_sha512_msk = UINT64_C(1) << ISA_SHA512, 118 ISA_mpmul_msk = UINT64_C(1) << ISA_MPMUL, 119 ISA_mont_msk = UINT64_C(1) << ISA_MONT, 120 ISA_pause_msk = UINT64_C(1) << ISA_PAUSE, 121 ISA_cbcond_msk = UINT64_C(1) << ISA_CBCOND, 122 ISA_crc32c_msk = UINT64_C(1) << ISA_CRC32C, 123 124 ISA_fjathplus_msk = UINT64_C(1) << ISA_FJATHPLUS, 125 ISA_vis3b_msk = UINT64_C(1) << ISA_VIS3B, 126 ISA_adi_msk = UINT64_C(1) << ISA_ADI, 127 ISA_sparc5_msk = UINT64_C(1) << ISA_SPARC5, 128 ISA_mwait_msk = UINT64_C(1) << ISA_MWAIT, 129 ISA_xmpmul_msk = UINT64_C(1) << ISA_XMPMUL, 130 ISA_xmont_msk = UINT64_C(1) << ISA_XMONT, 131 ISA_pause_nsec_msk = UINT64_C(1) << ISA_PAUSE_NSEC, 132 ISA_vamask_msk = UINT64_C(1) << ISA_VAMASK, 133 134 ISA_sparc6_msk = UINT64_C(1) << ISA_SPARC6, 135 ISA_dictunp_msk = UINT64_C(1) << ISA_DICTUNP, 136 ISA_fpcmpshl_msk = UINT64_C(1) << ISA_FPCMPSHL, 137 ISA_rle_msk = UINT64_C(1) << ISA_RLE, 138 ISA_sha3_msk = UINT64_C(1) << ISA_SHA3, 139 ISA_fjathplus2_msk = UINT64_C(1) << ISA_FJATHPLUS2, 140 ISA_vis3c_msk = UINT64_C(1) << ISA_VIS3C, 141 ISA_sparc5b_msk = UINT64_C(1) << ISA_SPARC5B, 142 ISA_mme_msk = UINT64_C(1) << ISA_MME, 143 144 CPU_fast_idiv_msk = UINT64_C(1) << CPU_FAST_IDIV, 145 CPU_fast_rdpc_msk = UINT64_C(1) << CPU_FAST_RDPC, 146 CPU_fast_bis_msk = UINT64_C(1) << CPU_FAST_BIS, 147 CPU_fast_ld_msk = UINT64_C(1) << CPU_FAST_LD, 148 CPU_fast_cmove_msk = UINT64_C(1) << CPU_FAST_CMOVE, 149 CPU_fast_ind_br_msk = UINT64_C(1) << CPU_FAST_IND_BR, 150 CPU_blk_zeroing_msk = UINT64_C(1) << CPU_BLK_ZEROING, 151 152 last_feature_msk = CPU_blk_zeroing_msk, 153 full_feature_msk = (last_feature_msk << 1) - 1 154 }; 155 156 /* The following, previously supported, SPARC implementations are no longer 157 * supported. 158 * 159 * UltraSPARC I/II: 160 * SPARC-V9, VIS 161 * UltraSPARC III/+: (Cheetah/+) 162 * SPARC-V9, VIS 163 * UltraSPARC IV: (Jaguar) 164 * SPARC-V9, VIS 165 * UltraSPARC IV+: (Panther) 166 * SPARC-V9, VIS, POPC 167 * 168 * The currently supported SPARC implementations are listed below (including 169 * generic V9 support). 170 * 171 * UltraSPARC T1: (Niagara) 172 * SPARC-V9, VIS, ASI_BIS (Crypto/hash in SPU) 173 * UltraSPARC T2: (Niagara-2) 174 * SPARC-V9, VIS, ASI_BIS, POPC (Crypto/hash in SPU) 175 * UltraSPARC T2+: (Victoria Falls, etc.) 176 * SPARC-V9, VIS, VIS2, ASI_BIS, POPC (Crypto/hash in SPU) 177 * 178 * UltraSPARC T3: (Rainbow Falls/C2) 179 * SPARC-V9, VIS, VIS2, ASI_BIS, POPC (Crypto/hash in SPU) 180 * 181 * Oracle SPARC T4/T5/M5: (Core C3) 182 * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND, 183 * AES, DES, Kasumi, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL 184 * 185 * Oracle SPARC M7: (Core C4) 186 * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND, 187 * AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b, 188 * ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK 189 * 190 * Oracle SPARC M8: (Core C5) 191 * SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND, 192 * AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b, 193 * ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK, SPARC6, FPCMPSHL, 194 * DICTUNP, RLE, SHA3, MME 195 * 196 * NOTE: Oracle Number support ignored. 197 */ 198 enum { 199 niagara1_msk = ISA_v9_msk | ISA_vis1_msk | ISA_blk_init_msk, 200 niagara2_msk = niagara1_msk | ISA_popc_msk, 201 202 core_C2_msk = niagara2_msk | ISA_vis2_msk, 203 204 core_C3_msk = core_C2_msk | ISA_fmaf_msk | ISA_vis3_msk | ISA_hpc_msk | 205 ISA_ima_msk | ISA_aes_msk | ISA_des_msk | ISA_kasumi_msk | 206 ISA_camellia_msk | ISA_md5_msk | ISA_sha1_msk | ISA_sha256_msk | 207 ISA_sha512_msk | ISA_mpmul_msk | ISA_mont_msk | ISA_pause_msk | 208 ISA_cbcond_msk | ISA_crc32c_msk, 209 210 core_C4_msk = core_C3_msk - ISA_kasumi_msk | 211 ISA_vis3b_msk | ISA_adi_msk | ISA_sparc5_msk | ISA_mwait_msk | 212 ISA_xmpmul_msk | ISA_xmont_msk | ISA_pause_nsec_msk | ISA_vamask_msk, 213 214 core_C5_msk = core_C4_msk | ISA_sparc6_msk | ISA_dictunp_msk | 215 ISA_fpcmpshl_msk | ISA_rle_msk | ISA_sha3_msk | ISA_mme_msk, 216 217 ultra_sparc_t1_msk = niagara1_msk, 218 ultra_sparc_t2_msk = niagara2_msk, 219 ultra_sparc_t3_msk = core_C2_msk, 220 ultra_sparc_m5_msk = core_C3_msk, // NOTE: First out-of-order pipeline. 221 ultra_sparc_m7_msk = core_C4_msk, 222 ultra_sparc_m8_msk = core_C5_msk 223 }; 224 225 static uint _L2_data_cache_line_size; L2_data_cache_line_size()226 static uint L2_data_cache_line_size() { return _L2_data_cache_line_size; } 227 228 static void determine_features(); 229 static void platform_features(); 230 static void print_features(); 231 232 public: 233 enum { 234 // Adopt a conservative behaviour (modelling single-insn-fetch-n-issue) for 235 // Niagara (and SPARC64). While there are at least two entries/slots in the 236 // instruction fetch buffer on any Niagara core (and as many as eight on a 237 // SPARC64), the performance improvement from keeping hot branch targets on 238 // optimally aligned addresses is such a small one (if any) that we choose 239 // not to use the extra code space required. 240 241 insn_fetch_alignment = 4 // Byte alignment in L1 insn. cache. 242 }; 243 244 static void initialize(); 245 init_before_ergo()246 static void init_before_ergo() { determine_features(); } 247 248 // Instruction feature support: 249 has_v9()250 static bool has_v9() { return (_features & ISA_v9_msk) != 0; } has_popc()251 static bool has_popc() { return (_features & ISA_popc_msk) != 0; } has_vis1()252 static bool has_vis1() { return (_features & ISA_vis1_msk) != 0; } has_vis2()253 static bool has_vis2() { return (_features & ISA_vis2_msk) != 0; } has_blk_init()254 static bool has_blk_init() { return (_features & ISA_blk_init_msk) != 0; } has_fmaf()255 static bool has_fmaf() { return (_features & ISA_fmaf_msk) != 0; } has_vis3()256 static bool has_vis3() { return (_features & ISA_vis3_msk) != 0; } has_hpc()257 static bool has_hpc() { return (_features & ISA_hpc_msk) != 0; } has_athena()258 static bool has_athena() { return (_features & ISA_fjathhpc_msk) != 0; } has_ima()259 static bool has_ima() { return (_features & ISA_ima_msk) != 0; } has_aes()260 static bool has_aes() { return (_features & ISA_aes_msk) != 0; } has_des()261 static bool has_des() { return (_features & ISA_des_msk) != 0; } has_kasumi()262 static bool has_kasumi() { return (_features & ISA_kasumi_msk) != 0; } has_camellia()263 static bool has_camellia() { return (_features & ISA_camellia_msk) != 0; } has_md5()264 static bool has_md5() { return (_features & ISA_md5_msk) != 0; } has_sha1()265 static bool has_sha1() { return (_features & ISA_sha1_msk) != 0; } has_sha256()266 static bool has_sha256() { return (_features & ISA_sha256_msk) != 0; } has_sha512()267 static bool has_sha512() { return (_features & ISA_sha512_msk) != 0; } has_mpmul()268 static bool has_mpmul() { return (_features & ISA_mpmul_msk) != 0; } has_mont()269 static bool has_mont() { return (_features & ISA_mont_msk) != 0; } has_pause()270 static bool has_pause() { return (_features & ISA_pause_msk) != 0; } has_cbcond()271 static bool has_cbcond() { return (_features & ISA_cbcond_msk) != 0; } has_crc32c()272 static bool has_crc32c() { return (_features & ISA_crc32c_msk) != 0; } 273 has_athena_plus()274 static bool has_athena_plus() { return (_features & ISA_fjathplus_msk) != 0; } has_vis3b()275 static bool has_vis3b() { return (_features & ISA_vis3b_msk) != 0; } has_adi()276 static bool has_adi() { return (_features & ISA_adi_msk) != 0; } has_sparc5()277 static bool has_sparc5() { return (_features & ISA_sparc5_msk) != 0; } has_mwait()278 static bool has_mwait() { return (_features & ISA_mwait_msk) != 0; } has_xmpmul()279 static bool has_xmpmul() { return (_features & ISA_xmpmul_msk) != 0; } has_xmont()280 static bool has_xmont() { return (_features & ISA_xmont_msk) != 0; } has_pause_nsec()281 static bool has_pause_nsec() { return (_features & ISA_pause_nsec_msk) != 0; } has_vamask()282 static bool has_vamask() { return (_features & ISA_vamask_msk) != 0; } 283 has_sparc6()284 static bool has_sparc6() { return (_features & ISA_sparc6_msk) != 0; } has_dictunp()285 static bool has_dictunp() { return (_features & ISA_dictunp_msk) != 0; } has_fpcmpshl()286 static bool has_fpcmpshl() { return (_features & ISA_fpcmpshl_msk) != 0; } has_rle()287 static bool has_rle() { return (_features & ISA_rle_msk) != 0; } has_sha3()288 static bool has_sha3() { return (_features & ISA_sha3_msk) != 0; } has_athena_plus2()289 static bool has_athena_plus2() { return (_features & ISA_fjathplus2_msk) != 0; } has_vis3c()290 static bool has_vis3c() { return (_features & ISA_vis3c_msk) != 0; } has_sparc5b()291 static bool has_sparc5b() { return (_features & ISA_sparc5b_msk) != 0; } has_mme()292 static bool has_mme() { return (_features & ISA_mme_msk) != 0; } 293 has_fast_idiv()294 static bool has_fast_idiv() { return (_features & CPU_fast_idiv_msk) != 0; } has_fast_rdpc()295 static bool has_fast_rdpc() { return (_features & CPU_fast_rdpc_msk) != 0; } has_fast_bis()296 static bool has_fast_bis() { return (_features & CPU_fast_bis_msk) != 0; } has_fast_ld()297 static bool has_fast_ld() { return (_features & CPU_fast_ld_msk) != 0; } has_fast_cmove()298 static bool has_fast_cmove() { return (_features & CPU_fast_cmove_msk) != 0; } 299 300 // If indirect and direct branching is equally fast. has_fast_ind_br()301 static bool has_fast_ind_br() { return (_features & CPU_fast_ind_br_msk) != 0; } 302 // If SPARC BIS to the beginning of cache line always zeros it. has_blk_zeroing()303 static bool has_blk_zeroing() { return (_features & CPU_blk_zeroing_msk) != 0; } 304 supports_compare_and_exchange()305 static bool supports_compare_and_exchange() { return true; } 306 307 // FIXME: To be removed. is_post_niagara()308 static bool is_post_niagara() { 309 return (_features & niagara2_msk) == niagara2_msk; 310 } 311 is_athena()312 static bool is_athena() { 313 return has_athena() || has_athena_plus() || has_athena_plus2(); 314 } 315 316 // Default prefetch block size on SPARC. prefetch_data_size()317 static uint prefetch_data_size() { return L2_data_cache_line_size(); } 318 319 private: 320 // Prefetch policy and characteristics: 321 // 322 // These support routines are used in order to isolate any CPU/core specific 323 // logic from the actual flag/option processing. They should reflect the HW 324 // characteristics for the associated options on the current platform. 325 // 326 // The three Prefetch* options below (assigned -1 in the configuration) are 327 // treated according to (given the accepted range [-1..<maxint>]): 328 // -1: Determine a proper HW-specific value for the current HW. 329 // 0: Off 330 // >0: Command-line supplied value to use. 331 // 332 // FIXME: The documentation string in the configuration is wrong, saying that 333 // -1 is also interpreted as off. 334 // prefetch_copy_interval_in_bytes()335 static intx prefetch_copy_interval_in_bytes() { 336 intx bytes = PrefetchCopyIntervalInBytes; 337 return bytes < 0 ? 512 : bytes; 338 } prefetch_scan_interval_in_bytes()339 static intx prefetch_scan_interval_in_bytes() { 340 intx bytes = PrefetchScanIntervalInBytes; 341 return bytes < 0 ? 512 : bytes; 342 } prefetch_fields_ahead()343 static intx prefetch_fields_ahead() { 344 intx count = PrefetchFieldsAhead; 345 return count < 0 ? 0 : count; 346 } 347 348 // AllocatePrefetchDistance is treated under the same interpretation as the 349 // Prefetch* options above (i.e., -1, 0, >0). allocate_prefetch_distance()350 static intx allocate_prefetch_distance() { 351 intx count = AllocatePrefetchDistance; 352 return count < 0 ? 512 : count; 353 } 354 355 // AllocatePrefetchStyle is guaranteed to be in range [0..3] defined by the 356 // configuration. allocate_prefetch_style()357 static intx allocate_prefetch_style() { 358 intx distance = allocate_prefetch_distance(); 359 // Return 0 (off/none) if AllocatePrefetchDistance was not defined. 360 return distance > 0 ? AllocatePrefetchStyle : 0; 361 } 362 363 public: 364 // Assembler testing 365 static void allow_all(); 366 static void revert(); 367 368 // Override the Abstract_VM_Version implementation. 369 // 370 // FIXME: Removed broken test on sun4v (always false when invoked prior to the 371 // proper capability setup), thus always returning 2. Still need to fix 372 // this properly in order to enable complete page size support. page_size_count()373 static uint page_size_count() { return 2; } 374 375 // Calculates the number of parallel threads 376 static unsigned int calc_parallel_worker_threads(); 377 }; 378 379 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP 380