1 /*
2 * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/barrierSet.hpp"
39 #include "gc/shared/cardTableBarrierSet.hpp"
40 #include "gc/shared/collectedHeap.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "utilities/macros.hpp"
46 #include "vmreg_aarch64.inline.hpp"
47
48
49
50 #ifndef PRODUCT
51 #define COMMENT(x) do { __ block_comment(x); } while (0)
52 #else
53 #define COMMENT(x)
54 #endif
55
56 NEEDS_CLEANUP // remove this definitions ?
57 const Register IC_Klass = rscratch2; // where the IC klass is cached
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
select_different_registers(Register preserve,Register extra,Register & tmp1,Register & tmp2)64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
select_different_registers(Register preserve,Register extra,Register & tmp1,Register & tmp2,Register & tmp3)80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
is_small_constant(LIR_Opr opr)99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
receiverOpr()102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
osrBufferPointer()106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
float_constant(float f)113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == NULL) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
double_constant(double d)124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == NULL) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
int_constant(jlong n)134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == NULL) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
set_24bit_FPU()144 void LIR_Assembler::set_24bit_FPU() { Unimplemented(); }
145
reset_FPU()146 void LIR_Assembler::reset_FPU() { Unimplemented(); }
147
fpop()148 void LIR_Assembler::fpop() { Unimplemented(); }
149
fxch(int i)150 void LIR_Assembler::fxch(int i) { Unimplemented(); }
151
fld(int i)152 void LIR_Assembler::fld(int i) { Unimplemented(); }
153
ffree(int i)154 void LIR_Assembler::ffree(int i) { Unimplemented(); }
155
breakpoint()156 void LIR_Assembler::breakpoint() { Unimplemented(); }
157
push(LIR_Opr opr)158 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
159
pop(LIR_Opr opr)160 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
161
is_literal_address(LIR_Address * addr)162 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
163 //-------------------------------------------
164
as_reg(LIR_Opr op)165 static Register as_reg(LIR_Opr op) {
166 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
167 }
168
as_long(LIR_Opr data)169 static jlong as_long(LIR_Opr data) {
170 jlong result;
171 switch (data->type()) {
172 case T_INT:
173 result = (data->as_jint());
174 break;
175 case T_LONG:
176 result = (data->as_jlong());
177 break;
178 default:
179 ShouldNotReachHere();
180 result = 0; // unreachable
181 }
182 return result;
183 }
184
as_Address(LIR_Address * addr,Register tmp)185 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
186 Register base = addr->base()->as_pointer_register();
187 LIR_Opr opr = addr->index();
188 if (opr->is_cpu_register()) {
189 Register index;
190 if (opr->is_single_cpu())
191 index = opr->as_register();
192 else
193 index = opr->as_register_lo();
194 assert(addr->disp() == 0, "must be");
195 switch(opr->type()) {
196 case T_INT:
197 return Address(base, index, Address::sxtw(addr->scale()));
198 case T_LONG:
199 return Address(base, index, Address::lsl(addr->scale()));
200 default:
201 ShouldNotReachHere();
202 }
203 } else {
204 intptr_t addr_offset = intptr_t(addr->disp());
205 if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
206 return Address(base, addr_offset, Address::lsl(addr->scale()));
207 else {
208 __ mov(tmp, addr_offset);
209 return Address(base, tmp, Address::lsl(addr->scale()));
210 }
211 }
212 return Address();
213 }
214
as_Address_hi(LIR_Address * addr)215 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
216 ShouldNotReachHere();
217 return Address();
218 }
219
as_Address(LIR_Address * addr)220 Address LIR_Assembler::as_Address(LIR_Address* addr) {
221 return as_Address(addr, rscratch1);
222 }
223
as_Address_lo(LIR_Address * addr)224 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
225 return as_Address(addr, rscratch1); // Ouch
226 // FIXME: This needs to be much more clever. See x86.
227 }
228
229 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
230 // not encodable as a base + (immediate) offset, generate an explicit address
231 // calculation to hold the address in a temporary register.
stack_slot_address(int index,uint size,Register tmp,int adjust)232 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
233 precond(size == 4 || size == 8);
234 Address addr = frame_map()->address_for_slot(index, adjust);
235 precond(addr.getMode() == Address::base_plus_offset);
236 precond(addr.base() == sp);
237 precond(addr.offset() > 0);
238 uint mask = size - 1;
239 assert((addr.offset() & mask) == 0, "scaled offsets only");
240 return __ legitimize_address(addr, size, tmp);
241 }
242
osr_entry()243 void LIR_Assembler::osr_entry() {
244 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
245 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
246 ValueStack* entry_state = osr_entry->state();
247 int number_of_locks = entry_state->locks_size();
248
249 // we jump here if osr happens with the interpreter
250 // state set up to continue at the beginning of the
251 // loop that triggered osr - in particular, we have
252 // the following registers setup:
253 //
254 // r2: osr buffer
255 //
256
257 // build frame
258 ciMethod* m = compilation()->method();
259 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
260
261 // OSR buffer is
262 //
263 // locals[nlocals-1..0]
264 // monitors[0..number_of_locks]
265 //
266 // locals is a direct copy of the interpreter frame so in the osr buffer
267 // so first slot in the local array is the last local from the interpreter
268 // and last slot is local[0] (receiver) from the interpreter
269 //
270 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
271 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
272 // in the interpreter frame (the method lock if a sync method)
273
274 // Initialize monitors in the compiled activation.
275 // r2: pointer to osr buffer
276 //
277 // All other registers are dead at this point and the locals will be
278 // copied into place by code emitted in the IR.
279
280 Register OSR_buf = osrBufferPointer()->as_pointer_register();
281 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
282 int monitor_offset = BytesPerWord * method()->max_locals() +
283 (2 * BytesPerWord) * (number_of_locks - 1);
284 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
285 // the OSR buffer using 2 word entries: first the lock and then
286 // the oop.
287 for (int i = 0; i < number_of_locks; i++) {
288 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
289 #ifdef ASSERT
290 // verify the interpreter's monitor has a non-null object
291 {
292 Label L;
293 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
294 __ cbnz(rscratch1, L);
295 __ stop("locked object is NULL");
296 __ bind(L);
297 }
298 #endif
299 __ ldr(r19, Address(OSR_buf, slot_offset + 0));
300 __ str(r19, frame_map()->address_for_monitor_lock(i));
301 __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
302 __ str(r19, frame_map()->address_for_monitor_object(i));
303 }
304 }
305 }
306
307
308 // inline cache check; done before the frame is built.
check_icache()309 int LIR_Assembler::check_icache() {
310 Register receiver = FrameMap::receiver_opr->as_register();
311 Register ic_klass = IC_Klass;
312 int start_offset = __ offset();
313 __ inline_cache_check(receiver, ic_klass);
314
315 // if icache check fails, then jump to runtime routine
316 // Note: RECEIVER must still contain the receiver!
317 Label dont;
318 __ br(Assembler::EQ, dont);
319 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
320
321 // We align the verified entry point unless the method body
322 // (including its inline cache check) will fit in a single 64-byte
323 // icache line.
324 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
325 // force alignment after the cache check.
326 __ align(CodeEntryAlignment);
327 }
328
329 __ bind(dont);
330 return start_offset;
331 }
332
333
jobject2reg(jobject o,Register reg)334 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
335 if (o == NULL) {
336 __ mov(reg, zr);
337 } else {
338 __ movoop(reg, o, /*immediate*/true);
339 }
340 }
341
deoptimize_trap(CodeEmitInfo * info)342 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
343 address target = NULL;
344 relocInfo::relocType reloc_type = relocInfo::none;
345
346 switch (patching_id(info)) {
347 case PatchingStub::access_field_id:
348 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
349 reloc_type = relocInfo::section_word_type;
350 break;
351 case PatchingStub::load_klass_id:
352 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
353 reloc_type = relocInfo::metadata_type;
354 break;
355 case PatchingStub::load_mirror_id:
356 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
357 reloc_type = relocInfo::oop_type;
358 break;
359 case PatchingStub::load_appendix_id:
360 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
361 reloc_type = relocInfo::oop_type;
362 break;
363 default: ShouldNotReachHere();
364 }
365
366 __ far_call(RuntimeAddress(target));
367 add_call_info_here(info);
368 }
369
jobject2reg_with_patching(Register reg,CodeEmitInfo * info)370 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
371 deoptimize_trap(info);
372 }
373
374
375 // This specifies the rsp decrement needed to build the frame
initial_frame_size_in_bytes() const376 int LIR_Assembler::initial_frame_size_in_bytes() const {
377 // if rounding, must let FrameMap know!
378
379 // The frame_map records size in slots (32bit word)
380
381 // subtract two words to account for return address and link
382 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
383 }
384
385
emit_exception_handler()386 int LIR_Assembler::emit_exception_handler() {
387 // if the last instruction is a call (typically to do a throw which
388 // is coming at the end after block reordering) the return address
389 // must still point into the code area in order to avoid assertion
390 // failures when searching for the corresponding bci => add a nop
391 // (was bug 5/14/1999 - gri)
392 __ nop();
393
394 // generate code for exception handler
395 address handler_base = __ start_a_stub(exception_handler_size());
396 if (handler_base == NULL) {
397 // not enough space left for the handler
398 bailout("exception handler overflow");
399 return -1;
400 }
401
402 int offset = code_offset();
403
404 // the exception oop and pc are in r0, and r3
405 // no other registers need to be preserved, so invalidate them
406 __ invalidate_registers(false, true, true, false, true, true);
407
408 // check that there is really an exception
409 __ verify_not_null_oop(r0);
410
411 // search an exception handler (r0: exception oop, r3: throwing pc)
412 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); __ should_not_reach_here();
413 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
414 __ end_a_stub();
415
416 return offset;
417 }
418
419
420 // Emit the code to remove the frame from the stack in the exception
421 // unwind path.
emit_unwind_handler()422 int LIR_Assembler::emit_unwind_handler() {
423 #ifndef PRODUCT
424 if (CommentedAssembly) {
425 _masm->block_comment("Unwind handler");
426 }
427 #endif
428
429 int offset = code_offset();
430
431 // Fetch the exception from TLS and clear out exception related thread state
432 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
433 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
434 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
435
436 __ bind(_unwind_handler_entry);
437 __ verify_not_null_oop(r0);
438 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
439 __ mov(r19, r0); // Preserve the exception
440 }
441
442 // Preform needed unlocking
443 MonitorExitStub* stub = NULL;
444 if (method()->is_synchronized()) {
445 monitor_address(0, FrameMap::r0_opr);
446 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
447 __ unlock_object(r5, r4, r0, *stub->entry());
448 __ bind(*stub->continuation());
449 }
450
451 if (compilation()->env()->dtrace_method_probes()) {
452 __ mov(c_rarg0, rthread);
453 __ mov_metadata(c_rarg1, method()->constant_encoding());
454 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
455 }
456
457 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
458 __ mov(r0, r19); // Restore the exception
459 }
460
461 // remove the activation and dispatch to the unwind handler
462 __ block_comment("remove_frame and dispatch to the unwind handler");
463 __ remove_frame(initial_frame_size_in_bytes());
464 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
465
466 // Emit the slow path assembly
467 if (stub != NULL) {
468 stub->emit_code(this);
469 }
470
471 return offset;
472 }
473
474
emit_deopt_handler()475 int LIR_Assembler::emit_deopt_handler() {
476 // if the last instruction is a call (typically to do a throw which
477 // is coming at the end after block reordering) the return address
478 // must still point into the code area in order to avoid assertion
479 // failures when searching for the corresponding bci => add a nop
480 // (was bug 5/14/1999 - gri)
481 __ nop();
482
483 // generate code for exception handler
484 address handler_base = __ start_a_stub(deopt_handler_size());
485 if (handler_base == NULL) {
486 // not enough space left for the handler
487 bailout("deopt handler overflow");
488 return -1;
489 }
490
491 int offset = code_offset();
492
493 __ adr(lr, pc());
494 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
495 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
496 __ end_a_stub();
497
498 return offset;
499 }
500
add_debug_info_for_branch(address adr,CodeEmitInfo * info)501 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
502 _masm->code_section()->relocate(adr, relocInfo::poll_type);
503 int pc_offset = code_offset();
504 flush_debug_info(pc_offset);
505 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
506 if (info->exception_handlers() != NULL) {
507 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
508 }
509 }
510
return_op(LIR_Opr result)511 void LIR_Assembler::return_op(LIR_Opr result) {
512 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
513
514 // Pop the stack before the safepoint code
515 __ remove_frame(initial_frame_size_in_bytes());
516
517 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
518 __ reserved_stack_check();
519 }
520
521 address polling_page(os::get_polling_page());
522 __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);
523 __ ret(lr);
524 }
525
safepoint_poll(LIR_Opr tmp,CodeEmitInfo * info)526 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
527 address polling_page(os::get_polling_page());
528 guarantee(info != NULL, "Shouldn't be NULL");
529 assert(os::is_poll_address(polling_page), "should be");
530 __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);
531 add_debug_info_for_branch(info); // This isn't just debug info:
532 // it's the oop map
533 __ read_polling_page(rscratch1, relocInfo::poll_type);
534 return __ offset();
535 }
536
537
move_regs(Register from_reg,Register to_reg)538 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
539 if (from_reg == r31_sp)
540 from_reg = sp;
541 if (to_reg == r31_sp)
542 to_reg = sp;
543 __ mov(to_reg, from_reg);
544 }
545
swap_reg(Register a,Register b)546 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
547
548
const2reg(LIR_Opr src,LIR_Opr dest,LIR_PatchCode patch_code,CodeEmitInfo * info)549 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
550 assert(src->is_constant(), "should not call otherwise");
551 assert(dest->is_register(), "should not call otherwise");
552 LIR_Const* c = src->as_constant_ptr();
553
554 switch (c->type()) {
555 case T_INT: {
556 assert(patch_code == lir_patch_none, "no patching handled here");
557 __ movw(dest->as_register(), c->as_jint());
558 break;
559 }
560
561 case T_ADDRESS: {
562 assert(patch_code == lir_patch_none, "no patching handled here");
563 __ mov(dest->as_register(), c->as_jint());
564 break;
565 }
566
567 case T_LONG: {
568 assert(patch_code == lir_patch_none, "no patching handled here");
569 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
570 break;
571 }
572
573 case T_OBJECT: {
574 if (patch_code == lir_patch_none) {
575 jobject2reg(c->as_jobject(), dest->as_register());
576 } else {
577 jobject2reg_with_patching(dest->as_register(), info);
578 }
579 break;
580 }
581
582 case T_METADATA: {
583 if (patch_code != lir_patch_none) {
584 klass2reg_with_patching(dest->as_register(), info);
585 } else {
586 __ mov_metadata(dest->as_register(), c->as_metadata());
587 }
588 break;
589 }
590
591 case T_FLOAT: {
592 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
593 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
594 } else {
595 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
596 __ ldrs(dest->as_float_reg(), Address(rscratch1));
597 }
598 break;
599 }
600
601 case T_DOUBLE: {
602 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
603 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
604 } else {
605 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
606 __ ldrd(dest->as_double_reg(), Address(rscratch1));
607 }
608 break;
609 }
610
611 default:
612 ShouldNotReachHere();
613 }
614 }
615
const2stack(LIR_Opr src,LIR_Opr dest)616 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
617 LIR_Const* c = src->as_constant_ptr();
618 switch (c->type()) {
619 case T_OBJECT:
620 {
621 if (! c->as_jobject())
622 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
623 else {
624 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
625 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
626 }
627 }
628 break;
629 case T_ADDRESS:
630 {
631 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
632 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
633 }
634 case T_INT:
635 case T_FLOAT:
636 {
637 Register reg = zr;
638 if (c->as_jint_bits() == 0)
639 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
640 else {
641 __ movw(rscratch1, c->as_jint_bits());
642 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
643 }
644 }
645 break;
646 case T_LONG:
647 case T_DOUBLE:
648 {
649 Register reg = zr;
650 if (c->as_jlong_bits() == 0)
651 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
652 lo_word_offset_in_bytes));
653 else {
654 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
655 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
656 lo_word_offset_in_bytes));
657 }
658 }
659 break;
660 default:
661 ShouldNotReachHere();
662 }
663 }
664
const2mem(LIR_Opr src,LIR_Opr dest,BasicType type,CodeEmitInfo * info,bool wide)665 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
666 assert(src->is_constant(), "should not call otherwise");
667 LIR_Const* c = src->as_constant_ptr();
668 LIR_Address* to_addr = dest->as_address_ptr();
669
670 void (Assembler::* insn)(Register Rt, const Address &adr);
671
672 switch (type) {
673 case T_ADDRESS:
674 assert(c->as_jint() == 0, "should be");
675 insn = &Assembler::str;
676 break;
677 case T_LONG:
678 assert(c->as_jlong() == 0, "should be");
679 insn = &Assembler::str;
680 break;
681 case T_INT:
682 assert(c->as_jint() == 0, "should be");
683 insn = &Assembler::strw;
684 break;
685 case T_OBJECT:
686 case T_ARRAY:
687 assert(c->as_jobject() == 0, "should be");
688 if (UseCompressedOops && !wide) {
689 insn = &Assembler::strw;
690 } else {
691 insn = &Assembler::str;
692 }
693 break;
694 case T_CHAR:
695 case T_SHORT:
696 assert(c->as_jint() == 0, "should be");
697 insn = &Assembler::strh;
698 break;
699 case T_BOOLEAN:
700 case T_BYTE:
701 assert(c->as_jint() == 0, "should be");
702 insn = &Assembler::strb;
703 break;
704 default:
705 ShouldNotReachHere();
706 insn = &Assembler::str; // unreachable
707 }
708
709 if (info) add_debug_info_for_null_check_here(info);
710 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
711 }
712
reg2reg(LIR_Opr src,LIR_Opr dest)713 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
714 assert(src->is_register(), "should not call otherwise");
715 assert(dest->is_register(), "should not call otherwise");
716
717 // move between cpu-registers
718 if (dest->is_single_cpu()) {
719 if (src->type() == T_LONG) {
720 // Can do LONG -> OBJECT
721 move_regs(src->as_register_lo(), dest->as_register());
722 return;
723 }
724 assert(src->is_single_cpu(), "must match");
725 if (src->type() == T_OBJECT) {
726 __ verify_oop(src->as_register());
727 }
728 move_regs(src->as_register(), dest->as_register());
729
730 } else if (dest->is_double_cpu()) {
731 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
732 // Surprising to me but we can see move of a long to t_object
733 __ verify_oop(src->as_register());
734 move_regs(src->as_register(), dest->as_register_lo());
735 return;
736 }
737 assert(src->is_double_cpu(), "must match");
738 Register f_lo = src->as_register_lo();
739 Register f_hi = src->as_register_hi();
740 Register t_lo = dest->as_register_lo();
741 Register t_hi = dest->as_register_hi();
742 assert(f_hi == f_lo, "must be same");
743 assert(t_hi == t_lo, "must be same");
744 move_regs(f_lo, t_lo);
745
746 } else if (dest->is_single_fpu()) {
747 __ fmovs(dest->as_float_reg(), src->as_float_reg());
748
749 } else if (dest->is_double_fpu()) {
750 __ fmovd(dest->as_double_reg(), src->as_double_reg());
751
752 } else {
753 ShouldNotReachHere();
754 }
755 }
756
reg2stack(LIR_Opr src,LIR_Opr dest,BasicType type,bool pop_fpu_stack)757 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
758 precond(src->is_register() && dest->is_stack());
759
760 uint const c_sz32 = sizeof(uint32_t);
761 uint const c_sz64 = sizeof(uint64_t);
762
763 if (src->is_single_cpu()) {
764 int index = dest->single_stack_ix();
765 if (type == T_ARRAY || type == T_OBJECT) {
766 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
767 __ verify_oop(src->as_register());
768 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
769 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
770 } else {
771 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
772 }
773
774 } else if (src->is_double_cpu()) {
775 int index = dest->double_stack_ix();
776 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
777 __ str(src->as_register_lo(), dest_addr_LO);
778
779 } else if (src->is_single_fpu()) {
780 int index = dest->single_stack_ix();
781 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
782
783 } else if (src->is_double_fpu()) {
784 int index = dest->double_stack_ix();
785 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
786
787 } else {
788 ShouldNotReachHere();
789 }
790 }
791
792
reg2mem(LIR_Opr src,LIR_Opr dest,BasicType type,LIR_PatchCode patch_code,CodeEmitInfo * info,bool pop_fpu_stack,bool wide,bool)793 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
794 LIR_Address* to_addr = dest->as_address_ptr();
795 PatchingStub* patch = NULL;
796 Register compressed_src = rscratch1;
797
798 if (patch_code != lir_patch_none) {
799 deoptimize_trap(info);
800 return;
801 }
802
803 if (type == T_ARRAY || type == T_OBJECT) {
804 __ verify_oop(src->as_register());
805
806 if (UseCompressedOops && !wide) {
807 __ encode_heap_oop(compressed_src, src->as_register());
808 } else {
809 compressed_src = src->as_register();
810 }
811 }
812
813 int null_check_here = code_offset();
814 switch (type) {
815 case T_FLOAT: {
816 __ strs(src->as_float_reg(), as_Address(to_addr));
817 break;
818 }
819
820 case T_DOUBLE: {
821 __ strd(src->as_double_reg(), as_Address(to_addr));
822 break;
823 }
824
825 case T_ARRAY: // fall through
826 case T_OBJECT: // fall through
827 if (UseCompressedOops && !wide) {
828 __ strw(compressed_src, as_Address(to_addr, rscratch2));
829 } else {
830 __ str(compressed_src, as_Address(to_addr));
831 }
832 break;
833 case T_METADATA:
834 // We get here to store a method pointer to the stack to pass to
835 // a dtrace runtime call. This can't work on 64 bit with
836 // compressed klass ptrs: T_METADATA can be a compressed klass
837 // ptr or a 64 bit method pointer.
838 ShouldNotReachHere();
839 __ str(src->as_register(), as_Address(to_addr));
840 break;
841 case T_ADDRESS:
842 __ str(src->as_register(), as_Address(to_addr));
843 break;
844 case T_INT:
845 __ strw(src->as_register(), as_Address(to_addr));
846 break;
847
848 case T_LONG: {
849 __ str(src->as_register_lo(), as_Address_lo(to_addr));
850 break;
851 }
852
853 case T_BYTE: // fall through
854 case T_BOOLEAN: {
855 __ strb(src->as_register(), as_Address(to_addr));
856 break;
857 }
858
859 case T_CHAR: // fall through
860 case T_SHORT:
861 __ strh(src->as_register(), as_Address(to_addr));
862 break;
863
864 default:
865 ShouldNotReachHere();
866 }
867 if (info != NULL) {
868 add_debug_info_for_null_check(null_check_here, info);
869 }
870 }
871
872
stack2reg(LIR_Opr src,LIR_Opr dest,BasicType type)873 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
874 precond(src->is_stack() && dest->is_register());
875
876 uint const c_sz32 = sizeof(uint32_t);
877 uint const c_sz64 = sizeof(uint64_t);
878
879 if (dest->is_single_cpu()) {
880 int index = src->single_stack_ix();
881 if (type == T_ARRAY || type == T_OBJECT) {
882 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
883 __ verify_oop(dest->as_register());
884 } else if (type == T_METADATA || type == T_ADDRESS) {
885 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
886 } else {
887 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
888 }
889
890 } else if (dest->is_double_cpu()) {
891 int index = src->double_stack_ix();
892 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
893 __ ldr(dest->as_register_lo(), src_addr_LO);
894
895 } else if (dest->is_single_fpu()) {
896 int index = src->single_stack_ix();
897 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
898
899 } else if (dest->is_double_fpu()) {
900 int index = src->double_stack_ix();
901 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
902
903 } else {
904 ShouldNotReachHere();
905 }
906 }
907
908
klass2reg_with_patching(Register reg,CodeEmitInfo * info)909 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
910 address target = NULL;
911 relocInfo::relocType reloc_type = relocInfo::none;
912
913 switch (patching_id(info)) {
914 case PatchingStub::access_field_id:
915 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
916 reloc_type = relocInfo::section_word_type;
917 break;
918 case PatchingStub::load_klass_id:
919 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
920 reloc_type = relocInfo::metadata_type;
921 break;
922 case PatchingStub::load_mirror_id:
923 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
924 reloc_type = relocInfo::oop_type;
925 break;
926 case PatchingStub::load_appendix_id:
927 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
928 reloc_type = relocInfo::oop_type;
929 break;
930 default: ShouldNotReachHere();
931 }
932
933 __ far_call(RuntimeAddress(target));
934 add_call_info_here(info);
935 }
936
stack2stack(LIR_Opr src,LIR_Opr dest,BasicType type)937 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
938
939 LIR_Opr temp;
940 if (type == T_LONG || type == T_DOUBLE)
941 temp = FrameMap::rscratch1_long_opr;
942 else
943 temp = FrameMap::rscratch1_opr;
944
945 stack2reg(src, temp, src->type());
946 reg2stack(temp, dest, dest->type(), false);
947 }
948
949
mem2reg(LIR_Opr src,LIR_Opr dest,BasicType type,LIR_PatchCode patch_code,CodeEmitInfo * info,bool wide,bool)950 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
951 LIR_Address* addr = src->as_address_ptr();
952 LIR_Address* from_addr = src->as_address_ptr();
953
954 if (addr->base()->type() == T_OBJECT) {
955 __ verify_oop(addr->base()->as_pointer_register());
956 }
957
958 if (patch_code != lir_patch_none) {
959 deoptimize_trap(info);
960 return;
961 }
962
963 if (info != NULL) {
964 add_debug_info_for_null_check_here(info);
965 }
966 int null_check_here = code_offset();
967 switch (type) {
968 case T_FLOAT: {
969 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
970 break;
971 }
972
973 case T_DOUBLE: {
974 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
975 break;
976 }
977
978 case T_ARRAY: // fall through
979 case T_OBJECT: // fall through
980 if (UseCompressedOops && !wide) {
981 __ ldrw(dest->as_register(), as_Address(from_addr));
982 } else {
983 __ ldr(dest->as_register(), as_Address(from_addr));
984 }
985 break;
986 case T_METADATA:
987 // We get here to store a method pointer to the stack to pass to
988 // a dtrace runtime call. This can't work on 64 bit with
989 // compressed klass ptrs: T_METADATA can be a compressed klass
990 // ptr or a 64 bit method pointer.
991 ShouldNotReachHere();
992 __ ldr(dest->as_register(), as_Address(from_addr));
993 break;
994 case T_ADDRESS:
995 // FIXME: OMG this is a horrible kludge. Any offset from an
996 // address that matches klass_offset_in_bytes() will be loaded
997 // as a word, not a long.
998 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
999 __ ldrw(dest->as_register(), as_Address(from_addr));
1000 } else {
1001 __ ldr(dest->as_register(), as_Address(from_addr));
1002 }
1003 break;
1004 case T_INT:
1005 __ ldrw(dest->as_register(), as_Address(from_addr));
1006 break;
1007
1008 case T_LONG: {
1009 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1010 break;
1011 }
1012
1013 case T_BYTE:
1014 __ ldrsb(dest->as_register(), as_Address(from_addr));
1015 break;
1016 case T_BOOLEAN: {
1017 __ ldrb(dest->as_register(), as_Address(from_addr));
1018 break;
1019 }
1020
1021 case T_CHAR:
1022 __ ldrh(dest->as_register(), as_Address(from_addr));
1023 break;
1024 case T_SHORT:
1025 __ ldrsh(dest->as_register(), as_Address(from_addr));
1026 break;
1027
1028 default:
1029 ShouldNotReachHere();
1030 }
1031
1032 if (type == T_ARRAY || type == T_OBJECT) {
1033 if (UseCompressedOops && !wide) {
1034 __ decode_heap_oop(dest->as_register());
1035 }
1036 __ verify_oop(dest->as_register());
1037 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1038 if (UseCompressedClassPointers) {
1039 __ decode_klass_not_null(dest->as_register());
1040 }
1041 }
1042 }
1043
1044
array_element_size(BasicType type) const1045 int LIR_Assembler::array_element_size(BasicType type) const {
1046 int elem_size = type2aelembytes(type);
1047 return exact_log2(elem_size);
1048 }
1049
1050
emit_op3(LIR_Op3 * op)1051 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1052 switch (op->code()) {
1053 case lir_idiv:
1054 case lir_irem:
1055 arithmetic_idiv(op->code(),
1056 op->in_opr1(),
1057 op->in_opr2(),
1058 op->in_opr3(),
1059 op->result_opr(),
1060 op->info());
1061 break;
1062 case lir_fmad:
1063 __ fmaddd(op->result_opr()->as_double_reg(),
1064 op->in_opr1()->as_double_reg(),
1065 op->in_opr2()->as_double_reg(),
1066 op->in_opr3()->as_double_reg());
1067 break;
1068 case lir_fmaf:
1069 __ fmadds(op->result_opr()->as_float_reg(),
1070 op->in_opr1()->as_float_reg(),
1071 op->in_opr2()->as_float_reg(),
1072 op->in_opr3()->as_float_reg());
1073 break;
1074 default: ShouldNotReachHere(); break;
1075 }
1076 }
1077
emit_opBranch(LIR_OpBranch * op)1078 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1079 #ifdef ASSERT
1080 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1081 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1082 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1083 #endif
1084
1085 if (op->cond() == lir_cond_always) {
1086 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1087 __ b(*(op->label()));
1088 } else {
1089 Assembler::Condition acond;
1090 if (op->code() == lir_cond_float_branch) {
1091 bool is_unordered = (op->ublock() == op->block());
1092 // Assembler::EQ does not permit unordered branches, so we add
1093 // another branch here. Likewise, Assembler::NE does not permit
1094 // ordered branches.
1095 if ((is_unordered && op->cond() == lir_cond_equal)
1096 || (!is_unordered && op->cond() == lir_cond_notEqual))
1097 __ br(Assembler::VS, *(op->ublock()->label()));
1098 switch(op->cond()) {
1099 case lir_cond_equal: acond = Assembler::EQ; break;
1100 case lir_cond_notEqual: acond = Assembler::NE; break;
1101 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1102 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1103 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1104 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1105 default: ShouldNotReachHere();
1106 acond = Assembler::EQ; // unreachable
1107 }
1108 } else {
1109 switch (op->cond()) {
1110 case lir_cond_equal: acond = Assembler::EQ; break;
1111 case lir_cond_notEqual: acond = Assembler::NE; break;
1112 case lir_cond_less: acond = Assembler::LT; break;
1113 case lir_cond_lessEqual: acond = Assembler::LE; break;
1114 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1115 case lir_cond_greater: acond = Assembler::GT; break;
1116 case lir_cond_belowEqual: acond = Assembler::LS; break;
1117 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1118 default: ShouldNotReachHere();
1119 acond = Assembler::EQ; // unreachable
1120 }
1121 }
1122 __ br(acond,*(op->label()));
1123 }
1124 }
1125
1126
1127
emit_opConvert(LIR_OpConvert * op)1128 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1129 LIR_Opr src = op->in_opr();
1130 LIR_Opr dest = op->result_opr();
1131
1132 switch (op->bytecode()) {
1133 case Bytecodes::_i2f:
1134 {
1135 __ scvtfws(dest->as_float_reg(), src->as_register());
1136 break;
1137 }
1138 case Bytecodes::_i2d:
1139 {
1140 __ scvtfwd(dest->as_double_reg(), src->as_register());
1141 break;
1142 }
1143 case Bytecodes::_l2d:
1144 {
1145 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1146 break;
1147 }
1148 case Bytecodes::_l2f:
1149 {
1150 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1151 break;
1152 }
1153 case Bytecodes::_f2d:
1154 {
1155 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1156 break;
1157 }
1158 case Bytecodes::_d2f:
1159 {
1160 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1161 break;
1162 }
1163 case Bytecodes::_i2c:
1164 {
1165 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1166 break;
1167 }
1168 case Bytecodes::_i2l:
1169 {
1170 __ sxtw(dest->as_register_lo(), src->as_register());
1171 break;
1172 }
1173 case Bytecodes::_i2s:
1174 {
1175 __ sxth(dest->as_register(), src->as_register());
1176 break;
1177 }
1178 case Bytecodes::_i2b:
1179 {
1180 __ sxtb(dest->as_register(), src->as_register());
1181 break;
1182 }
1183 case Bytecodes::_l2i:
1184 {
1185 _masm->block_comment("FIXME: This could be a no-op");
1186 __ uxtw(dest->as_register(), src->as_register_lo());
1187 break;
1188 }
1189 case Bytecodes::_d2l:
1190 {
1191 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1192 break;
1193 }
1194 case Bytecodes::_f2i:
1195 {
1196 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1197 break;
1198 }
1199 case Bytecodes::_f2l:
1200 {
1201 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1202 break;
1203 }
1204 case Bytecodes::_d2i:
1205 {
1206 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1207 break;
1208 }
1209 default: ShouldNotReachHere();
1210 }
1211 }
1212
emit_alloc_obj(LIR_OpAllocObj * op)1213 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1214 if (op->init_check()) {
1215 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1216 InstanceKlass::init_state_offset()));
1217 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1218 add_debug_info_for_null_check_here(op->stub()->info());
1219 __ br(Assembler::NE, *op->stub()->entry());
1220 }
1221 __ allocate_object(op->obj()->as_register(),
1222 op->tmp1()->as_register(),
1223 op->tmp2()->as_register(),
1224 op->header_size(),
1225 op->object_size(),
1226 op->klass()->as_register(),
1227 *op->stub()->entry());
1228 __ bind(*op->stub()->continuation());
1229 }
1230
emit_alloc_array(LIR_OpAllocArray * op)1231 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1232 Register len = op->len()->as_register();
1233 __ uxtw(len, len);
1234
1235 if (UseSlowPath ||
1236 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1237 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1238 __ b(*op->stub()->entry());
1239 } else {
1240 Register tmp1 = op->tmp1()->as_register();
1241 Register tmp2 = op->tmp2()->as_register();
1242 Register tmp3 = op->tmp3()->as_register();
1243 if (len == tmp1) {
1244 tmp1 = tmp3;
1245 } else if (len == tmp2) {
1246 tmp2 = tmp3;
1247 } else if (len == tmp3) {
1248 // everything is ok
1249 } else {
1250 __ mov(tmp3, len);
1251 }
1252 __ allocate_array(op->obj()->as_register(),
1253 len,
1254 tmp1,
1255 tmp2,
1256 arrayOopDesc::header_size(op->type()),
1257 array_element_size(op->type()),
1258 op->klass()->as_register(),
1259 *op->stub()->entry());
1260 }
1261 __ bind(*op->stub()->continuation());
1262 }
1263
type_profile_helper(Register mdo,ciMethodData * md,ciProfileData * data,Register recv,Label * update_done)1264 void LIR_Assembler::type_profile_helper(Register mdo,
1265 ciMethodData *md, ciProfileData *data,
1266 Register recv, Label* update_done) {
1267 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1268 Label next_test;
1269 // See if the receiver is receiver[n].
1270 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1271 __ ldr(rscratch1, Address(rscratch2));
1272 __ cmp(recv, rscratch1);
1273 __ br(Assembler::NE, next_test);
1274 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1275 __ addptr(data_addr, DataLayout::counter_increment);
1276 __ b(*update_done);
1277 __ bind(next_test);
1278 }
1279
1280 // Didn't find receiver; find next empty slot and fill it in
1281 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1282 Label next_test;
1283 __ lea(rscratch2,
1284 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1285 Address recv_addr(rscratch2);
1286 __ ldr(rscratch1, recv_addr);
1287 __ cbnz(rscratch1, next_test);
1288 __ str(recv, recv_addr);
1289 __ mov(rscratch1, DataLayout::counter_increment);
1290 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1291 __ str(rscratch1, Address(rscratch2));
1292 __ b(*update_done);
1293 __ bind(next_test);
1294 }
1295 }
1296
emit_typecheck_helper(LIR_OpTypeCheck * op,Label * success,Label * failure,Label * obj_is_null)1297 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1298 // we always need a stub for the failure case.
1299 CodeStub* stub = op->stub();
1300 Register obj = op->object()->as_register();
1301 Register k_RInfo = op->tmp1()->as_register();
1302 Register klass_RInfo = op->tmp2()->as_register();
1303 Register dst = op->result_opr()->as_register();
1304 ciKlass* k = op->klass();
1305 Register Rtmp1 = noreg;
1306
1307 // check if it needs to be profiled
1308 ciMethodData* md;
1309 ciProfileData* data;
1310
1311 const bool should_profile = op->should_profile();
1312
1313 if (should_profile) {
1314 ciMethod* method = op->profiled_method();
1315 assert(method != NULL, "Should have method");
1316 int bci = op->profiled_bci();
1317 md = method->method_data_or_null();
1318 assert(md != NULL, "Sanity");
1319 data = md->bci_to_data(bci);
1320 assert(data != NULL, "need data for type check");
1321 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1322 }
1323 Label profile_cast_success, profile_cast_failure;
1324 Label *success_target = should_profile ? &profile_cast_success : success;
1325 Label *failure_target = should_profile ? &profile_cast_failure : failure;
1326
1327 if (obj == k_RInfo) {
1328 k_RInfo = dst;
1329 } else if (obj == klass_RInfo) {
1330 klass_RInfo = dst;
1331 }
1332 if (k->is_loaded() && !UseCompressedClassPointers) {
1333 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1334 } else {
1335 Rtmp1 = op->tmp3()->as_register();
1336 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1337 }
1338
1339 assert_different_registers(obj, k_RInfo, klass_RInfo);
1340
1341 if (should_profile) {
1342 Label not_null;
1343 __ cbnz(obj, not_null);
1344 // Object is null; update MDO and exit
1345 Register mdo = klass_RInfo;
1346 __ mov_metadata(mdo, md->constant_encoding());
1347 Address data_addr
1348 = __ form_address(rscratch2, mdo,
1349 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1350 0);
1351 __ ldrb(rscratch1, data_addr);
1352 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1353 __ strb(rscratch1, data_addr);
1354 __ b(*obj_is_null);
1355 __ bind(not_null);
1356 } else {
1357 __ cbz(obj, *obj_is_null);
1358 }
1359
1360 if (!k->is_loaded()) {
1361 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1362 } else {
1363 __ mov_metadata(k_RInfo, k->constant_encoding());
1364 }
1365 __ verify_oop(obj);
1366
1367 if (op->fast_check()) {
1368 // get object class
1369 // not a safepoint as obj null check happens earlier
1370 __ load_klass(rscratch1, obj);
1371 __ cmp( rscratch1, k_RInfo);
1372
1373 __ br(Assembler::NE, *failure_target);
1374 // successful cast, fall through to profile or jump
1375 } else {
1376 // get object class
1377 // not a safepoint as obj null check happens earlier
1378 __ load_klass(klass_RInfo, obj);
1379 if (k->is_loaded()) {
1380 // See if we get an immediate positive hit
1381 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1382 __ cmp(k_RInfo, rscratch1);
1383 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1384 __ br(Assembler::NE, *failure_target);
1385 // successful cast, fall through to profile or jump
1386 } else {
1387 // See if we get an immediate positive hit
1388 __ br(Assembler::EQ, *success_target);
1389 // check for self
1390 __ cmp(klass_RInfo, k_RInfo);
1391 __ br(Assembler::EQ, *success_target);
1392
1393 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1394 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1395 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1396 // result is a boolean
1397 __ cbzw(klass_RInfo, *failure_target);
1398 // successful cast, fall through to profile or jump
1399 }
1400 } else {
1401 // perform the fast part of the checking logic
1402 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1403 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1404 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1405 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1406 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1407 // result is a boolean
1408 __ cbz(k_RInfo, *failure_target);
1409 // successful cast, fall through to profile or jump
1410 }
1411 }
1412 if (should_profile) {
1413 Register mdo = klass_RInfo, recv = k_RInfo;
1414 __ bind(profile_cast_success);
1415 __ mov_metadata(mdo, md->constant_encoding());
1416 __ load_klass(recv, obj);
1417 Label update_done;
1418 type_profile_helper(mdo, md, data, recv, success);
1419 __ b(*success);
1420
1421 __ bind(profile_cast_failure);
1422 __ mov_metadata(mdo, md->constant_encoding());
1423 Address counter_addr
1424 = __ form_address(rscratch2, mdo,
1425 md->byte_offset_of_slot(data, CounterData::count_offset()),
1426 0);
1427 __ ldr(rscratch1, counter_addr);
1428 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1429 __ str(rscratch1, counter_addr);
1430 __ b(*failure);
1431 }
1432 __ b(*success);
1433 }
1434
1435
emit_opTypeCheck(LIR_OpTypeCheck * op)1436 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1437 const bool should_profile = op->should_profile();
1438
1439 LIR_Code code = op->code();
1440 if (code == lir_store_check) {
1441 Register value = op->object()->as_register();
1442 Register array = op->array()->as_register();
1443 Register k_RInfo = op->tmp1()->as_register();
1444 Register klass_RInfo = op->tmp2()->as_register();
1445 Register Rtmp1 = op->tmp3()->as_register();
1446
1447 CodeStub* stub = op->stub();
1448
1449 // check if it needs to be profiled
1450 ciMethodData* md;
1451 ciProfileData* data;
1452
1453 if (should_profile) {
1454 ciMethod* method = op->profiled_method();
1455 assert(method != NULL, "Should have method");
1456 int bci = op->profiled_bci();
1457 md = method->method_data_or_null();
1458 assert(md != NULL, "Sanity");
1459 data = md->bci_to_data(bci);
1460 assert(data != NULL, "need data for type check");
1461 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1462 }
1463 Label profile_cast_success, profile_cast_failure, done;
1464 Label *success_target = should_profile ? &profile_cast_success : &done;
1465 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1466
1467 if (should_profile) {
1468 Label not_null;
1469 __ cbnz(value, not_null);
1470 // Object is null; update MDO and exit
1471 Register mdo = klass_RInfo;
1472 __ mov_metadata(mdo, md->constant_encoding());
1473 Address data_addr
1474 = __ form_address(rscratch2, mdo,
1475 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1476 0);
1477 __ ldrb(rscratch1, data_addr);
1478 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1479 __ strb(rscratch1, data_addr);
1480 __ b(done);
1481 __ bind(not_null);
1482 } else {
1483 __ cbz(value, done);
1484 }
1485
1486 add_debug_info_for_null_check_here(op->info_for_exception());
1487 __ load_klass(k_RInfo, array);
1488 __ load_klass(klass_RInfo, value);
1489
1490 // get instance klass (it's already uncompressed)
1491 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1492 // perform the fast part of the checking logic
1493 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1494 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1495 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1496 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1497 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1498 // result is a boolean
1499 __ cbzw(k_RInfo, *failure_target);
1500 // fall through to the success case
1501
1502 if (should_profile) {
1503 Register mdo = klass_RInfo, recv = k_RInfo;
1504 __ bind(profile_cast_success);
1505 __ mov_metadata(mdo, md->constant_encoding());
1506 __ load_klass(recv, value);
1507 Label update_done;
1508 type_profile_helper(mdo, md, data, recv, &done);
1509 __ b(done);
1510
1511 __ bind(profile_cast_failure);
1512 __ mov_metadata(mdo, md->constant_encoding());
1513 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1514 __ lea(rscratch2, counter_addr);
1515 __ ldr(rscratch1, Address(rscratch2));
1516 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1517 __ str(rscratch1, Address(rscratch2));
1518 __ b(*stub->entry());
1519 }
1520
1521 __ bind(done);
1522 } else if (code == lir_checkcast) {
1523 Register obj = op->object()->as_register();
1524 Register dst = op->result_opr()->as_register();
1525 Label success;
1526 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1527 __ bind(success);
1528 if (dst != obj) {
1529 __ mov(dst, obj);
1530 }
1531 } else if (code == lir_instanceof) {
1532 Register obj = op->object()->as_register();
1533 Register dst = op->result_opr()->as_register();
1534 Label success, failure, done;
1535 emit_typecheck_helper(op, &success, &failure, &failure);
1536 __ bind(failure);
1537 __ mov(dst, zr);
1538 __ b(done);
1539 __ bind(success);
1540 __ mov(dst, 1);
1541 __ bind(done);
1542 } else {
1543 ShouldNotReachHere();
1544 }
1545 }
1546
casw(Register addr,Register newval,Register cmpval)1547 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1548 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1549 __ cset(rscratch1, Assembler::NE);
1550 __ membar(__ AnyAny);
1551 }
1552
casl(Register addr,Register newval,Register cmpval)1553 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1554 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1555 __ cset(rscratch1, Assembler::NE);
1556 __ membar(__ AnyAny);
1557 }
1558
1559
emit_compare_and_swap(LIR_OpCompareAndSwap * op)1560 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1561 assert(VM_Version::supports_cx8(), "wrong machine");
1562 Register addr;
1563 if (op->addr()->is_register()) {
1564 addr = as_reg(op->addr());
1565 } else {
1566 assert(op->addr()->is_address(), "what else?");
1567 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1568 assert(addr_ptr->disp() == 0, "need 0 disp");
1569 assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1570 addr = as_reg(addr_ptr->base());
1571 }
1572 Register newval = as_reg(op->new_value());
1573 Register cmpval = as_reg(op->cmp_value());
1574 Label succeed, fail, around;
1575
1576 if (op->code() == lir_cas_obj) {
1577 if (UseCompressedOops) {
1578 Register t1 = op->tmp1()->as_register();
1579 assert(op->tmp1()->is_valid(), "must be");
1580 __ encode_heap_oop(t1, cmpval);
1581 cmpval = t1;
1582 __ encode_heap_oop(rscratch2, newval);
1583 newval = rscratch2;
1584 casw(addr, newval, cmpval);
1585 } else {
1586 casl(addr, newval, cmpval);
1587 }
1588 } else if (op->code() == lir_cas_int) {
1589 casw(addr, newval, cmpval);
1590 } else {
1591 casl(addr, newval, cmpval);
1592 }
1593 }
1594
1595
cmove(LIR_Condition condition,LIR_Opr opr1,LIR_Opr opr2,LIR_Opr result,BasicType type)1596 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1597
1598 Assembler::Condition acond, ncond;
1599 switch (condition) {
1600 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1601 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1602 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1603 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1604 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1605 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1606 case lir_cond_belowEqual:
1607 case lir_cond_aboveEqual:
1608 default: ShouldNotReachHere();
1609 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1610 }
1611
1612 assert(result->is_single_cpu() || result->is_double_cpu(),
1613 "expect single register for result");
1614 if (opr1->is_constant() && opr2->is_constant()
1615 && opr1->type() == T_INT && opr2->type() == T_INT) {
1616 jint val1 = opr1->as_jint();
1617 jint val2 = opr2->as_jint();
1618 if (val1 == 0 && val2 == 1) {
1619 __ cset(result->as_register(), ncond);
1620 return;
1621 } else if (val1 == 1 && val2 == 0) {
1622 __ cset(result->as_register(), acond);
1623 return;
1624 }
1625 }
1626
1627 if (opr1->is_constant() && opr2->is_constant()
1628 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1629 jlong val1 = opr1->as_jlong();
1630 jlong val2 = opr2->as_jlong();
1631 if (val1 == 0 && val2 == 1) {
1632 __ cset(result->as_register_lo(), ncond);
1633 return;
1634 } else if (val1 == 1 && val2 == 0) {
1635 __ cset(result->as_register_lo(), acond);
1636 return;
1637 }
1638 }
1639
1640 if (opr1->is_stack()) {
1641 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1642 opr1 = FrameMap::rscratch1_opr;
1643 } else if (opr1->is_constant()) {
1644 LIR_Opr tmp
1645 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1646 const2reg(opr1, tmp, lir_patch_none, NULL);
1647 opr1 = tmp;
1648 }
1649
1650 if (opr2->is_stack()) {
1651 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1652 opr2 = FrameMap::rscratch2_opr;
1653 } else if (opr2->is_constant()) {
1654 LIR_Opr tmp
1655 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1656 const2reg(opr2, tmp, lir_patch_none, NULL);
1657 opr2 = tmp;
1658 }
1659
1660 if (result->type() == T_LONG)
1661 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1662 else
1663 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1664 }
1665
arith_op(LIR_Code code,LIR_Opr left,LIR_Opr right,LIR_Opr dest,CodeEmitInfo * info,bool pop_fpu_stack)1666 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1667 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1668
1669 if (left->is_single_cpu()) {
1670 Register lreg = left->as_register();
1671 Register dreg = as_reg(dest);
1672
1673 if (right->is_single_cpu()) {
1674 // cpu register - cpu register
1675
1676 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1677 "should be");
1678 Register rreg = right->as_register();
1679 switch (code) {
1680 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1681 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1682 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1683 default: ShouldNotReachHere();
1684 }
1685
1686 } else if (right->is_double_cpu()) {
1687 Register rreg = right->as_register_lo();
1688 // single_cpu + double_cpu: can happen with obj+long
1689 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1690 switch (code) {
1691 case lir_add: __ add(dreg, lreg, rreg); break;
1692 case lir_sub: __ sub(dreg, lreg, rreg); break;
1693 default: ShouldNotReachHere();
1694 }
1695 } else if (right->is_constant()) {
1696 // cpu register - constant
1697 jlong c;
1698
1699 // FIXME. This is fugly: we really need to factor all this logic.
1700 switch(right->type()) {
1701 case T_LONG:
1702 c = right->as_constant_ptr()->as_jlong();
1703 break;
1704 case T_INT:
1705 case T_ADDRESS:
1706 c = right->as_constant_ptr()->as_jint();
1707 break;
1708 default:
1709 ShouldNotReachHere();
1710 c = 0; // unreachable
1711 break;
1712 }
1713
1714 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1715 if (c == 0 && dreg == lreg) {
1716 COMMENT("effective nop elided");
1717 return;
1718 }
1719 switch(left->type()) {
1720 case T_INT:
1721 switch (code) {
1722 case lir_add: __ addw(dreg, lreg, c); break;
1723 case lir_sub: __ subw(dreg, lreg, c); break;
1724 default: ShouldNotReachHere();
1725 }
1726 break;
1727 case T_OBJECT:
1728 case T_ADDRESS:
1729 switch (code) {
1730 case lir_add: __ add(dreg, lreg, c); break;
1731 case lir_sub: __ sub(dreg, lreg, c); break;
1732 default: ShouldNotReachHere();
1733 }
1734 break;
1735 ShouldNotReachHere();
1736 }
1737 } else {
1738 ShouldNotReachHere();
1739 }
1740
1741 } else if (left->is_double_cpu()) {
1742 Register lreg_lo = left->as_register_lo();
1743
1744 if (right->is_double_cpu()) {
1745 // cpu register - cpu register
1746 Register rreg_lo = right->as_register_lo();
1747 switch (code) {
1748 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1749 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1750 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1751 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1752 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1753 default:
1754 ShouldNotReachHere();
1755 }
1756
1757 } else if (right->is_constant()) {
1758 jlong c = right->as_constant_ptr()->as_jlong();
1759 Register dreg = as_reg(dest);
1760 switch (code) {
1761 case lir_add:
1762 case lir_sub:
1763 if (c == 0 && dreg == lreg_lo) {
1764 COMMENT("effective nop elided");
1765 return;
1766 }
1767 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1768 break;
1769 case lir_div:
1770 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1771 if (c == 1) {
1772 // move lreg_lo to dreg if divisor is 1
1773 __ mov(dreg, lreg_lo);
1774 } else {
1775 unsigned int shift = exact_log2_long(c);
1776 // use rscratch1 as intermediate result register
1777 __ asr(rscratch1, lreg_lo, 63);
1778 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1779 __ asr(dreg, rscratch1, shift);
1780 }
1781 break;
1782 case lir_rem:
1783 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1784 if (c == 1) {
1785 // move 0 to dreg if divisor is 1
1786 __ mov(dreg, zr);
1787 } else {
1788 // use rscratch1 as intermediate result register
1789 __ negs(rscratch1, lreg_lo);
1790 __ andr(dreg, lreg_lo, c - 1);
1791 __ andr(rscratch1, rscratch1, c - 1);
1792 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1793 }
1794 break;
1795 default:
1796 ShouldNotReachHere();
1797 }
1798 } else {
1799 ShouldNotReachHere();
1800 }
1801 } else if (left->is_single_fpu()) {
1802 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1803 switch (code) {
1804 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1805 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1806 case lir_mul_strictfp: // fall through
1807 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1808 case lir_div_strictfp: // fall through
1809 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1810 default:
1811 ShouldNotReachHere();
1812 }
1813 } else if (left->is_double_fpu()) {
1814 if (right->is_double_fpu()) {
1815 // fpu register - fpu register
1816 switch (code) {
1817 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1818 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1819 case lir_mul_strictfp: // fall through
1820 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1821 case lir_div_strictfp: // fall through
1822 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1823 default:
1824 ShouldNotReachHere();
1825 }
1826 } else {
1827 if (right->is_constant()) {
1828 ShouldNotReachHere();
1829 }
1830 ShouldNotReachHere();
1831 }
1832 } else if (left->is_single_stack() || left->is_address()) {
1833 assert(left == dest, "left and dest must be equal");
1834 ShouldNotReachHere();
1835 } else {
1836 ShouldNotReachHere();
1837 }
1838 }
1839
arith_fpu_implementation(LIR_Code code,int left_index,int right_index,int dest_index,bool pop_fpu_stack)1840 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1841
1842
intrinsic_op(LIR_Code code,LIR_Opr value,LIR_Opr unused,LIR_Opr dest,LIR_Op * op)1843 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1844 switch(code) {
1845 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1846 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1847 default : ShouldNotReachHere();
1848 }
1849 }
1850
logic_op(LIR_Code code,LIR_Opr left,LIR_Opr right,LIR_Opr dst)1851 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1852
1853 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1854 Register Rleft = left->is_single_cpu() ? left->as_register() :
1855 left->as_register_lo();
1856 if (dst->is_single_cpu()) {
1857 Register Rdst = dst->as_register();
1858 if (right->is_constant()) {
1859 switch (code) {
1860 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1861 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1862 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1863 default: ShouldNotReachHere(); break;
1864 }
1865 } else {
1866 Register Rright = right->is_single_cpu() ? right->as_register() :
1867 right->as_register_lo();
1868 switch (code) {
1869 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1870 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1871 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1872 default: ShouldNotReachHere(); break;
1873 }
1874 }
1875 } else {
1876 Register Rdst = dst->as_register_lo();
1877 if (right->is_constant()) {
1878 switch (code) {
1879 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1880 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1881 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1882 default: ShouldNotReachHere(); break;
1883 }
1884 } else {
1885 Register Rright = right->is_single_cpu() ? right->as_register() :
1886 right->as_register_lo();
1887 switch (code) {
1888 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1889 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1890 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1891 default: ShouldNotReachHere(); break;
1892 }
1893 }
1894 }
1895 }
1896
1897
1898
arithmetic_idiv(LIR_Code code,LIR_Opr left,LIR_Opr right,LIR_Opr illegal,LIR_Opr result,CodeEmitInfo * info)1899 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1900
1901 // opcode check
1902 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1903 bool is_irem = (code == lir_irem);
1904
1905 // operand check
1906 assert(left->is_single_cpu(), "left must be register");
1907 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1908 assert(result->is_single_cpu(), "result must be register");
1909 Register lreg = left->as_register();
1910 Register dreg = result->as_register();
1911
1912 // power-of-2 constant check and codegen
1913 if (right->is_constant()) {
1914 int c = right->as_constant_ptr()->as_jint();
1915 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1916 if (is_irem) {
1917 if (c == 1) {
1918 // move 0 to dreg if divisor is 1
1919 __ movw(dreg, zr);
1920 } else {
1921 // use rscratch1 as intermediate result register
1922 __ negsw(rscratch1, lreg);
1923 __ andw(dreg, lreg, c - 1);
1924 __ andw(rscratch1, rscratch1, c - 1);
1925 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1926 }
1927 } else {
1928 if (c == 1) {
1929 // move lreg to dreg if divisor is 1
1930 __ movw(dreg, lreg);
1931 } else {
1932 unsigned int shift = exact_log2(c);
1933 // use rscratch1 as intermediate result register
1934 __ asrw(rscratch1, lreg, 31);
1935 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1936 __ asrw(dreg, rscratch1, shift);
1937 }
1938 }
1939 } else {
1940 Register rreg = right->as_register();
1941 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1942 }
1943 }
1944
1945
comp_op(LIR_Condition condition,LIR_Opr opr1,LIR_Opr opr2,LIR_Op2 * op)1946 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1947 if (opr1->is_constant() && opr2->is_single_cpu()) {
1948 // tableswitch
1949 Register reg = as_reg(opr2);
1950 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1951 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1952 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1953 Register reg1 = as_reg(opr1);
1954 if (opr2->is_single_cpu()) {
1955 // cpu register - cpu register
1956 Register reg2 = opr2->as_register();
1957 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1958 __ cmpoop(reg1, reg2);
1959 } else {
1960 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1961 __ cmpw(reg1, reg2);
1962 }
1963 return;
1964 }
1965 if (opr2->is_double_cpu()) {
1966 // cpu register - cpu register
1967 Register reg2 = opr2->as_register_lo();
1968 __ cmp(reg1, reg2);
1969 return;
1970 }
1971
1972 if (opr2->is_constant()) {
1973 bool is_32bit = false; // width of register operand
1974 jlong imm;
1975
1976 switch(opr2->type()) {
1977 case T_INT:
1978 imm = opr2->as_constant_ptr()->as_jint();
1979 is_32bit = true;
1980 break;
1981 case T_LONG:
1982 imm = opr2->as_constant_ptr()->as_jlong();
1983 break;
1984 case T_ADDRESS:
1985 imm = opr2->as_constant_ptr()->as_jint();
1986 break;
1987 case T_METADATA:
1988 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1989 break;
1990 case T_OBJECT:
1991 case T_ARRAY:
1992 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1993 __ cmpoop(reg1, rscratch1);
1994 return;
1995 default:
1996 ShouldNotReachHere();
1997 imm = 0; // unreachable
1998 break;
1999 }
2000
2001 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2002 if (is_32bit)
2003 __ cmpw(reg1, imm);
2004 else
2005 __ cmp(reg1, imm);
2006 return;
2007 } else {
2008 __ mov(rscratch1, imm);
2009 if (is_32bit)
2010 __ cmpw(reg1, rscratch1);
2011 else
2012 __ cmp(reg1, rscratch1);
2013 return;
2014 }
2015 } else
2016 ShouldNotReachHere();
2017 } else if (opr1->is_single_fpu()) {
2018 FloatRegister reg1 = opr1->as_float_reg();
2019 assert(opr2->is_single_fpu(), "expect single float register");
2020 FloatRegister reg2 = opr2->as_float_reg();
2021 __ fcmps(reg1, reg2);
2022 } else if (opr1->is_double_fpu()) {
2023 FloatRegister reg1 = opr1->as_double_reg();
2024 assert(opr2->is_double_fpu(), "expect double float register");
2025 FloatRegister reg2 = opr2->as_double_reg();
2026 __ fcmpd(reg1, reg2);
2027 } else {
2028 ShouldNotReachHere();
2029 }
2030 }
2031
comp_fl2i(LIR_Code code,LIR_Opr left,LIR_Opr right,LIR_Opr dst,LIR_Op2 * op)2032 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2033 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2034 bool is_unordered_less = (code == lir_ucmp_fd2i);
2035 if (left->is_single_fpu()) {
2036 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2037 } else if (left->is_double_fpu()) {
2038 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2039 } else {
2040 ShouldNotReachHere();
2041 }
2042 } else if (code == lir_cmp_l2i) {
2043 Label done;
2044 __ cmp(left->as_register_lo(), right->as_register_lo());
2045 __ mov(dst->as_register(), (uint64_t)-1L);
2046 __ br(Assembler::LT, done);
2047 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2048 __ bind(done);
2049 } else {
2050 ShouldNotReachHere();
2051 }
2052 }
2053
2054
align_call(LIR_Code code)2055 void LIR_Assembler::align_call(LIR_Code code) { }
2056
2057
call(LIR_OpJavaCall * op,relocInfo::relocType rtype)2058 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2059 address call = __ trampoline_call(Address(op->addr(), rtype));
2060 if (call == NULL) {
2061 bailout("trampoline stub overflow");
2062 return;
2063 }
2064 add_call_info(code_offset(), op->info());
2065 }
2066
2067
ic_call(LIR_OpJavaCall * op)2068 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2069 address call = __ ic_call(op->addr());
2070 if (call == NULL) {
2071 bailout("trampoline stub overflow");
2072 return;
2073 }
2074 add_call_info(code_offset(), op->info());
2075 }
2076
2077
2078 /* Currently, vtable-dispatch is only enabled for sparc platforms */
vtable_call(LIR_OpJavaCall * op)2079 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2080 ShouldNotReachHere();
2081 }
2082
2083
emit_static_call_stub()2084 void LIR_Assembler::emit_static_call_stub() {
2085 address call_pc = __ pc();
2086 address stub = __ start_a_stub(call_stub_size());
2087 if (stub == NULL) {
2088 bailout("static call stub overflow");
2089 return;
2090 }
2091
2092 int start = __ offset();
2093
2094 __ relocate(static_stub_Relocation::spec(call_pc));
2095 __ emit_static_call_stub();
2096
2097 assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2098 <= call_stub_size(), "stub too big");
2099 __ end_a_stub();
2100 }
2101
2102
throw_op(LIR_Opr exceptionPC,LIR_Opr exceptionOop,CodeEmitInfo * info)2103 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2104 assert(exceptionOop->as_register() == r0, "must match");
2105 assert(exceptionPC->as_register() == r3, "must match");
2106
2107 // exception object is not added to oop map by LinearScan
2108 // (LinearScan assumes that no oops are in fixed registers)
2109 info->add_register_oop(exceptionOop);
2110 Runtime1::StubID unwind_id;
2111
2112 // get current pc information
2113 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2114 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2115 // As no instructions have been generated yet for this LIR node it's
2116 // possible that an oop map already exists for the current offset.
2117 // In that case insert an dummy NOP here to ensure all oop map PCs
2118 // are unique. See JDK-8237483.
2119 __ nop();
2120 }
2121 int pc_for_athrow_offset = __ offset();
2122 InternalAddress pc_for_athrow(__ pc());
2123 __ adr(exceptionPC->as_register(), pc_for_athrow);
2124 add_call_info(pc_for_athrow_offset, info); // for exception handler
2125
2126 __ verify_not_null_oop(r0);
2127 // search an exception handler (r0: exception oop, r3: throwing pc)
2128 if (compilation()->has_fpu_code()) {
2129 unwind_id = Runtime1::handle_exception_id;
2130 } else {
2131 unwind_id = Runtime1::handle_exception_nofpu_id;
2132 }
2133 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2134
2135 // FIXME: enough room for two byte trap ????
2136 __ nop();
2137 }
2138
2139
unwind_op(LIR_Opr exceptionOop)2140 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2141 assert(exceptionOop->as_register() == r0, "must match");
2142
2143 __ b(_unwind_handler_entry);
2144 }
2145
2146
shift_op(LIR_Code code,LIR_Opr left,LIR_Opr count,LIR_Opr dest,LIR_Opr tmp)2147 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2148 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2149 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2150
2151 switch (left->type()) {
2152 case T_INT: {
2153 switch (code) {
2154 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2155 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2156 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2157 default:
2158 ShouldNotReachHere();
2159 break;
2160 }
2161 break;
2162 case T_LONG:
2163 case T_ADDRESS:
2164 case T_OBJECT:
2165 switch (code) {
2166 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2167 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2168 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2169 default:
2170 ShouldNotReachHere();
2171 break;
2172 }
2173 break;
2174 default:
2175 ShouldNotReachHere();
2176 break;
2177 }
2178 }
2179 }
2180
2181
shift_op(LIR_Code code,LIR_Opr left,jint count,LIR_Opr dest)2182 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2183 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2184 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2185
2186 switch (left->type()) {
2187 case T_INT: {
2188 switch (code) {
2189 case lir_shl: __ lslw (dreg, lreg, count); break;
2190 case lir_shr: __ asrw (dreg, lreg, count); break;
2191 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2192 default:
2193 ShouldNotReachHere();
2194 break;
2195 }
2196 break;
2197 case T_LONG:
2198 case T_ADDRESS:
2199 case T_OBJECT:
2200 switch (code) {
2201 case lir_shl: __ lsl (dreg, lreg, count); break;
2202 case lir_shr: __ asr (dreg, lreg, count); break;
2203 case lir_ushr: __ lsr (dreg, lreg, count); break;
2204 default:
2205 ShouldNotReachHere();
2206 break;
2207 }
2208 break;
2209 default:
2210 ShouldNotReachHere();
2211 break;
2212 }
2213 }
2214 }
2215
2216
store_parameter(Register r,int offset_from_rsp_in_words)2217 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2218 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2219 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2220 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2221 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2222 }
2223
2224
store_parameter(jint c,int offset_from_rsp_in_words)2225 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2226 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2227 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2228 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2229 __ mov (rscratch1, c);
2230 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2231 }
2232
2233
store_parameter(jobject o,int offset_from_rsp_in_words)2234 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2235 ShouldNotReachHere();
2236 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2237 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2238 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2239 __ lea(rscratch1, __ constant_oop_address(o));
2240 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2241 }
2242
2243
2244 // This code replaces a call to arraycopy; no exception may
2245 // be thrown in this code, they must be thrown in the System.arraycopy
2246 // activation frame; we could save some checks if this would not be the case
emit_arraycopy(LIR_OpArrayCopy * op)2247 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2248 ciArrayKlass* default_type = op->expected_type();
2249 Register src = op->src()->as_register();
2250 Register dst = op->dst()->as_register();
2251 Register src_pos = op->src_pos()->as_register();
2252 Register dst_pos = op->dst_pos()->as_register();
2253 Register length = op->length()->as_register();
2254 Register tmp = op->tmp()->as_register();
2255
2256 CodeStub* stub = op->stub();
2257 int flags = op->flags();
2258 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2259 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2260
2261 // if we don't know anything, just go through the generic arraycopy
2262 if (default_type == NULL // || basic_type == T_OBJECT
2263 ) {
2264 Label done;
2265 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2266
2267 // Save the arguments in case the generic arraycopy fails and we
2268 // have to fall back to the JNI stub
2269 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2270 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2271 __ str(src, Address(sp, 4*BytesPerWord));
2272
2273 address copyfunc_addr = StubRoutines::generic_arraycopy();
2274 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2275
2276 // The arguments are in java calling convention so we shift them
2277 // to C convention
2278 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2279 __ mov(c_rarg0, j_rarg0);
2280 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2281 __ mov(c_rarg1, j_rarg1);
2282 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2283 __ mov(c_rarg2, j_rarg2);
2284 assert_different_registers(c_rarg3, j_rarg4);
2285 __ mov(c_rarg3, j_rarg3);
2286 __ mov(c_rarg4, j_rarg4);
2287 #ifndef PRODUCT
2288 if (PrintC1Statistics) {
2289 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2290 }
2291 #endif
2292 __ far_call(RuntimeAddress(copyfunc_addr));
2293
2294 __ cbz(r0, *stub->continuation());
2295
2296 // Reload values from the stack so they are where the stub
2297 // expects them.
2298 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2299 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2300 __ ldr(src, Address(sp, 4*BytesPerWord));
2301
2302 // r0 is -1^K where K == partial copied count
2303 __ eonw(rscratch1, r0, zr);
2304 // adjust length down and src/end pos up by partial copied count
2305 __ subw(length, length, rscratch1);
2306 __ addw(src_pos, src_pos, rscratch1);
2307 __ addw(dst_pos, dst_pos, rscratch1);
2308 __ b(*stub->entry());
2309
2310 __ bind(*stub->continuation());
2311 return;
2312 }
2313
2314 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2315
2316 int elem_size = type2aelembytes(basic_type);
2317 int scale = exact_log2(elem_size);
2318
2319 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2320 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2321 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2322 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2323
2324 // test for NULL
2325 if (flags & LIR_OpArrayCopy::src_null_check) {
2326 __ cbz(src, *stub->entry());
2327 }
2328 if (flags & LIR_OpArrayCopy::dst_null_check) {
2329 __ cbz(dst, *stub->entry());
2330 }
2331
2332 // If the compiler was not able to prove that exact type of the source or the destination
2333 // of the arraycopy is an array type, check at runtime if the source or the destination is
2334 // an instance type.
2335 if (flags & LIR_OpArrayCopy::type_check) {
2336 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2337 __ load_klass(tmp, dst);
2338 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2339 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2340 __ br(Assembler::GE, *stub->entry());
2341 }
2342
2343 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2344 __ load_klass(tmp, src);
2345 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2346 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2347 __ br(Assembler::GE, *stub->entry());
2348 }
2349 }
2350
2351 // check if negative
2352 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2353 __ cmpw(src_pos, 0);
2354 __ br(Assembler::LT, *stub->entry());
2355 }
2356 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2357 __ cmpw(dst_pos, 0);
2358 __ br(Assembler::LT, *stub->entry());
2359 }
2360
2361 if (flags & LIR_OpArrayCopy::length_positive_check) {
2362 __ cmpw(length, 0);
2363 __ br(Assembler::LT, *stub->entry());
2364 }
2365
2366 if (flags & LIR_OpArrayCopy::src_range_check) {
2367 __ addw(tmp, src_pos, length);
2368 __ ldrw(rscratch1, src_length_addr);
2369 __ cmpw(tmp, rscratch1);
2370 __ br(Assembler::HI, *stub->entry());
2371 }
2372 if (flags & LIR_OpArrayCopy::dst_range_check) {
2373 __ addw(tmp, dst_pos, length);
2374 __ ldrw(rscratch1, dst_length_addr);
2375 __ cmpw(tmp, rscratch1);
2376 __ br(Assembler::HI, *stub->entry());
2377 }
2378
2379 if (flags & LIR_OpArrayCopy::type_check) {
2380 // We don't know the array types are compatible
2381 if (basic_type != T_OBJECT) {
2382 // Simple test for basic type arrays
2383 if (UseCompressedClassPointers) {
2384 __ ldrw(tmp, src_klass_addr);
2385 __ ldrw(rscratch1, dst_klass_addr);
2386 __ cmpw(tmp, rscratch1);
2387 } else {
2388 __ ldr(tmp, src_klass_addr);
2389 __ ldr(rscratch1, dst_klass_addr);
2390 __ cmp(tmp, rscratch1);
2391 }
2392 __ br(Assembler::NE, *stub->entry());
2393 } else {
2394 // For object arrays, if src is a sub class of dst then we can
2395 // safely do the copy.
2396 Label cont, slow;
2397
2398 #define PUSH(r1, r2) \
2399 stp(r1, r2, __ pre(sp, -2 * wordSize));
2400
2401 #define POP(r1, r2) \
2402 ldp(r1, r2, __ post(sp, 2 * wordSize));
2403
2404 __ PUSH(src, dst);
2405
2406 __ load_klass(src, src);
2407 __ load_klass(dst, dst);
2408
2409 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2410
2411 __ PUSH(src, dst);
2412 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2413 __ POP(src, dst);
2414
2415 __ cbnz(src, cont);
2416
2417 __ bind(slow);
2418 __ POP(src, dst);
2419
2420 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2421 if (copyfunc_addr != NULL) { // use stub if available
2422 // src is not a sub class of dst so we have to do a
2423 // per-element check.
2424
2425 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2426 if ((flags & mask) != mask) {
2427 // Check that at least both of them object arrays.
2428 assert(flags & mask, "one of the two should be known to be an object array");
2429
2430 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2431 __ load_klass(tmp, src);
2432 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2433 __ load_klass(tmp, dst);
2434 }
2435 int lh_offset = in_bytes(Klass::layout_helper_offset());
2436 Address klass_lh_addr(tmp, lh_offset);
2437 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2438 __ ldrw(rscratch1, klass_lh_addr);
2439 __ mov(rscratch2, objArray_lh);
2440 __ eorw(rscratch1, rscratch1, rscratch2);
2441 __ cbnzw(rscratch1, *stub->entry());
2442 }
2443
2444 // Spill because stubs can use any register they like and it's
2445 // easier to restore just those that we care about.
2446 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2447 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2448 __ str(src, Address(sp, 4*BytesPerWord));
2449
2450 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2451 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2452 assert_different_registers(c_rarg0, dst, dst_pos, length);
2453 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2454 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2455 assert_different_registers(c_rarg1, dst, length);
2456 __ uxtw(c_rarg2, length);
2457 assert_different_registers(c_rarg2, dst);
2458
2459 __ load_klass(c_rarg4, dst);
2460 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2461 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2462 __ far_call(RuntimeAddress(copyfunc_addr));
2463
2464 #ifndef PRODUCT
2465 if (PrintC1Statistics) {
2466 Label failed;
2467 __ cbnz(r0, failed);
2468 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2469 __ bind(failed);
2470 }
2471 #endif
2472
2473 __ cbz(r0, *stub->continuation());
2474
2475 #ifndef PRODUCT
2476 if (PrintC1Statistics) {
2477 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2478 }
2479 #endif
2480 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2481
2482 // Restore previously spilled arguments
2483 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2484 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2485 __ ldr(src, Address(sp, 4*BytesPerWord));
2486
2487 // return value is -1^K where K is partial copied count
2488 __ eonw(rscratch1, r0, zr);
2489 // adjust length down and src/end pos up by partial copied count
2490 __ subw(length, length, rscratch1);
2491 __ addw(src_pos, src_pos, rscratch1);
2492 __ addw(dst_pos, dst_pos, rscratch1);
2493 }
2494
2495 __ b(*stub->entry());
2496
2497 __ bind(cont);
2498 __ POP(src, dst);
2499 }
2500 }
2501
2502 #ifdef ASSERT
2503 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2504 // Sanity check the known type with the incoming class. For the
2505 // primitive case the types must match exactly with src.klass and
2506 // dst.klass each exactly matching the default type. For the
2507 // object array case, if no type check is needed then either the
2508 // dst type is exactly the expected type and the src type is a
2509 // subtype which we can't check or src is the same array as dst
2510 // but not necessarily exactly of type default_type.
2511 Label known_ok, halt;
2512 __ mov_metadata(tmp, default_type->constant_encoding());
2513 if (UseCompressedClassPointers) {
2514 __ encode_klass_not_null(tmp);
2515 }
2516
2517 if (basic_type != T_OBJECT) {
2518
2519 if (UseCompressedClassPointers) {
2520 __ ldrw(rscratch1, dst_klass_addr);
2521 __ cmpw(tmp, rscratch1);
2522 } else {
2523 __ ldr(rscratch1, dst_klass_addr);
2524 __ cmp(tmp, rscratch1);
2525 }
2526 __ br(Assembler::NE, halt);
2527 if (UseCompressedClassPointers) {
2528 __ ldrw(rscratch1, src_klass_addr);
2529 __ cmpw(tmp, rscratch1);
2530 } else {
2531 __ ldr(rscratch1, src_klass_addr);
2532 __ cmp(tmp, rscratch1);
2533 }
2534 __ br(Assembler::EQ, known_ok);
2535 } else {
2536 if (UseCompressedClassPointers) {
2537 __ ldrw(rscratch1, dst_klass_addr);
2538 __ cmpw(tmp, rscratch1);
2539 } else {
2540 __ ldr(rscratch1, dst_klass_addr);
2541 __ cmp(tmp, rscratch1);
2542 }
2543 __ br(Assembler::EQ, known_ok);
2544 __ cmp(src, dst);
2545 __ br(Assembler::EQ, known_ok);
2546 }
2547 __ bind(halt);
2548 __ stop("incorrect type information in arraycopy");
2549 __ bind(known_ok);
2550 }
2551 #endif
2552
2553 #ifndef PRODUCT
2554 if (PrintC1Statistics) {
2555 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2556 }
2557 #endif
2558
2559 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2560 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2561 assert_different_registers(c_rarg0, dst, dst_pos, length);
2562 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2563 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2564 assert_different_registers(c_rarg1, dst, length);
2565 __ uxtw(c_rarg2, length);
2566 assert_different_registers(c_rarg2, dst);
2567
2568 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2569 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2570 const char *name;
2571 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2572
2573 CodeBlob *cb = CodeCache::find_blob(entry);
2574 if (cb) {
2575 __ far_call(RuntimeAddress(entry));
2576 } else {
2577 __ call_VM_leaf(entry, 3);
2578 }
2579
2580 __ bind(*stub->continuation());
2581 }
2582
2583
2584
2585
emit_lock(LIR_OpLock * op)2586 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2587 Register obj = op->obj_opr()->as_register(); // may not be an oop
2588 Register hdr = op->hdr_opr()->as_register();
2589 Register lock = op->lock_opr()->as_register();
2590 if (!UseFastLocking) {
2591 __ b(*op->stub()->entry());
2592 } else if (op->code() == lir_lock) {
2593 Register scratch = noreg;
2594 if (UseBiasedLocking) {
2595 scratch = op->scratch_opr()->as_register();
2596 }
2597 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2598 // add debug info for NullPointerException only if one is possible
2599 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2600 if (op->info() != NULL) {
2601 add_debug_info_for_null_check(null_check_offset, op->info());
2602 }
2603 // done
2604 } else if (op->code() == lir_unlock) {
2605 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2606 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2607 } else {
2608 Unimplemented();
2609 }
2610 __ bind(*op->stub()->continuation());
2611 }
2612
2613
emit_profile_call(LIR_OpProfileCall * op)2614 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2615 ciMethod* method = op->profiled_method();
2616 int bci = op->profiled_bci();
2617 ciMethod* callee = op->profiled_callee();
2618
2619 // Update counter for all call types
2620 ciMethodData* md = method->method_data_or_null();
2621 assert(md != NULL, "Sanity");
2622 ciProfileData* data = md->bci_to_data(bci);
2623 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2624 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2625 Register mdo = op->mdo()->as_register();
2626 __ mov_metadata(mdo, md->constant_encoding());
2627 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2628 // Perform additional virtual call profiling for invokevirtual and
2629 // invokeinterface bytecodes
2630 if (op->should_profile_receiver_type()) {
2631 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2632 Register recv = op->recv()->as_register();
2633 assert_different_registers(mdo, recv);
2634 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2635 ciKlass* known_klass = op->known_holder();
2636 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2637 // We know the type that will be seen at this call site; we can
2638 // statically update the MethodData* rather than needing to do
2639 // dynamic tests on the receiver type
2640
2641 // NOTE: we should probably put a lock around this search to
2642 // avoid collisions by concurrent compilations
2643 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2644 uint i;
2645 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2646 ciKlass* receiver = vc_data->receiver(i);
2647 if (known_klass->equals(receiver)) {
2648 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2649 __ addptr(data_addr, DataLayout::counter_increment);
2650 return;
2651 }
2652 }
2653
2654 // Receiver type not found in profile data; select an empty slot
2655
2656 // Note that this is less efficient than it should be because it
2657 // always does a write to the receiver part of the
2658 // VirtualCallData rather than just the first time
2659 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2660 ciKlass* receiver = vc_data->receiver(i);
2661 if (receiver == NULL) {
2662 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2663 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2664 __ lea(rscratch2, recv_addr);
2665 __ str(rscratch1, Address(rscratch2));
2666 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2667 __ addptr(data_addr, DataLayout::counter_increment);
2668 return;
2669 }
2670 }
2671 } else {
2672 __ load_klass(recv, recv);
2673 Label update_done;
2674 type_profile_helper(mdo, md, data, recv, &update_done);
2675 // Receiver did not match any saved receiver and there is no empty row for it.
2676 // Increment total counter to indicate polymorphic case.
2677 __ addptr(counter_addr, DataLayout::counter_increment);
2678
2679 __ bind(update_done);
2680 }
2681 } else {
2682 // Static call
2683 __ addptr(counter_addr, DataLayout::counter_increment);
2684 }
2685 }
2686
2687
emit_delay(LIR_OpDelay *)2688 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2689 Unimplemented();
2690 }
2691
2692
monitor_address(int monitor_no,LIR_Opr dst)2693 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2694 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2695 }
2696
emit_updatecrc32(LIR_OpUpdateCRC32 * op)2697 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2698 assert(op->crc()->is_single_cpu(), "crc must be register");
2699 assert(op->val()->is_single_cpu(), "byte value must be register");
2700 assert(op->result_opr()->is_single_cpu(), "result must be register");
2701 Register crc = op->crc()->as_register();
2702 Register val = op->val()->as_register();
2703 Register res = op->result_opr()->as_register();
2704
2705 assert_different_registers(val, crc, res);
2706 uint64_t offset;
2707 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2708 if (offset) __ add(res, res, offset);
2709
2710 __ mvnw(crc, crc); // ~crc
2711 __ update_byte_crc32(crc, val, res);
2712 __ mvnw(res, crc); // ~crc
2713 }
2714
emit_profile_type(LIR_OpProfileType * op)2715 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2716 COMMENT("emit_profile_type {");
2717 Register obj = op->obj()->as_register();
2718 Register tmp = op->tmp()->as_pointer_register();
2719 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2720 ciKlass* exact_klass = op->exact_klass();
2721 intptr_t current_klass = op->current_klass();
2722 bool not_null = op->not_null();
2723 bool no_conflict = op->no_conflict();
2724
2725 Label update, next, none;
2726
2727 bool do_null = !not_null;
2728 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2729 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2730
2731 assert(do_null || do_update, "why are we here?");
2732 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2733 assert(mdo_addr.base() != rscratch1, "wrong register");
2734
2735 __ verify_oop(obj);
2736
2737 if (tmp != obj) {
2738 __ mov(tmp, obj);
2739 }
2740 if (do_null) {
2741 __ cbnz(tmp, update);
2742 if (!TypeEntries::was_null_seen(current_klass)) {
2743 __ ldr(rscratch2, mdo_addr);
2744 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2745 __ str(rscratch2, mdo_addr);
2746 }
2747 if (do_update) {
2748 #ifndef ASSERT
2749 __ b(next);
2750 }
2751 #else
2752 __ b(next);
2753 }
2754 } else {
2755 __ cbnz(tmp, update);
2756 __ stop("unexpected null obj");
2757 #endif
2758 }
2759
2760 __ bind(update);
2761
2762 if (do_update) {
2763 #ifdef ASSERT
2764 if (exact_klass != NULL) {
2765 Label ok;
2766 __ load_klass(tmp, tmp);
2767 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2768 __ eor(rscratch1, tmp, rscratch1);
2769 __ cbz(rscratch1, ok);
2770 __ stop("exact klass and actual klass differ");
2771 __ bind(ok);
2772 }
2773 #endif
2774 if (!no_conflict) {
2775 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2776 if (exact_klass != NULL) {
2777 __ mov_metadata(tmp, exact_klass->constant_encoding());
2778 } else {
2779 __ load_klass(tmp, tmp);
2780 }
2781
2782 __ ldr(rscratch2, mdo_addr);
2783 __ eor(tmp, tmp, rscratch2);
2784 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2785 // klass seen before, nothing to do. The unknown bit may have been
2786 // set already but no need to check.
2787 __ cbz(rscratch1, next);
2788
2789 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2790
2791 if (TypeEntries::is_type_none(current_klass)) {
2792 __ cbz(rscratch2, none);
2793 __ cmp(rscratch2, TypeEntries::null_seen);
2794 __ br(Assembler::EQ, none);
2795 // There is a chance that the checks above (re-reading profiling
2796 // data from memory) fail if another thread has just set the
2797 // profiling to this obj's klass
2798 __ dmb(Assembler::ISHLD);
2799 __ ldr(rscratch2, mdo_addr);
2800 __ eor(tmp, tmp, rscratch2);
2801 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2802 __ cbz(rscratch1, next);
2803 }
2804 } else {
2805 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2806 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2807
2808 __ ldr(tmp, mdo_addr);
2809 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2810 }
2811
2812 // different than before. Cannot keep accurate profile.
2813 __ ldr(rscratch2, mdo_addr);
2814 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2815 __ str(rscratch2, mdo_addr);
2816
2817 if (TypeEntries::is_type_none(current_klass)) {
2818 __ b(next);
2819
2820 __ bind(none);
2821 // first time here. Set profile type.
2822 __ str(tmp, mdo_addr);
2823 }
2824 } else {
2825 // There's a single possible klass at this profile point
2826 assert(exact_klass != NULL, "should be");
2827 if (TypeEntries::is_type_none(current_klass)) {
2828 __ mov_metadata(tmp, exact_klass->constant_encoding());
2829 __ ldr(rscratch2, mdo_addr);
2830 __ eor(tmp, tmp, rscratch2);
2831 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2832 __ cbz(rscratch1, next);
2833 #ifdef ASSERT
2834 {
2835 Label ok;
2836 __ ldr(rscratch1, mdo_addr);
2837 __ cbz(rscratch1, ok);
2838 __ cmp(rscratch1, TypeEntries::null_seen);
2839 __ br(Assembler::EQ, ok);
2840 // may have been set by another thread
2841 __ dmb(Assembler::ISHLD);
2842 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2843 __ ldr(rscratch2, mdo_addr);
2844 __ eor(rscratch2, rscratch1, rscratch2);
2845 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2846 __ cbz(rscratch2, ok);
2847
2848 __ stop("unexpected profiling mismatch");
2849 __ bind(ok);
2850 }
2851 #endif
2852 // first time here. Set profile type.
2853 __ str(tmp, mdo_addr);
2854 } else {
2855 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2856 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2857
2858 __ ldr(tmp, mdo_addr);
2859 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2860
2861 __ orr(tmp, tmp, TypeEntries::type_unknown);
2862 __ str(tmp, mdo_addr);
2863 // FIXME: Write barrier needed here?
2864 }
2865 }
2866
2867 __ bind(next);
2868 }
2869 COMMENT("} emit_profile_type");
2870 }
2871
2872
align_backward_branch_target()2873 void LIR_Assembler::align_backward_branch_target() {
2874 }
2875
2876
negate(LIR_Opr left,LIR_Opr dest,LIR_Opr tmp)2877 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2878 // tmp must be unused
2879 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2880
2881 if (left->is_single_cpu()) {
2882 assert(dest->is_single_cpu(), "expect single result reg");
2883 __ negw(dest->as_register(), left->as_register());
2884 } else if (left->is_double_cpu()) {
2885 assert(dest->is_double_cpu(), "expect double result reg");
2886 __ neg(dest->as_register_lo(), left->as_register_lo());
2887 } else if (left->is_single_fpu()) {
2888 assert(dest->is_single_fpu(), "expect single float result reg");
2889 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2890 } else {
2891 assert(left->is_double_fpu(), "expect double float operand reg");
2892 assert(dest->is_double_fpu(), "expect double float result reg");
2893 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2894 }
2895 }
2896
2897
leal(LIR_Opr addr,LIR_Opr dest,LIR_PatchCode patch_code,CodeEmitInfo * info)2898 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2899 #if INCLUDE_SHENANDOAHGC
2900 if (UseShenandoahGC && patch_code != lir_patch_none) {
2901 deoptimize_trap(info);
2902 return;
2903 }
2904 #endif
2905 assert(patch_code == lir_patch_none, "Patch code not supported");
2906 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2907 }
2908
2909
rt_call(LIR_Opr result,address dest,const LIR_OprList * args,LIR_Opr tmp,CodeEmitInfo * info)2910 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2911 assert(!tmp->is_valid(), "don't need temporary");
2912
2913 CodeBlob *cb = CodeCache::find_blob(dest);
2914 if (cb) {
2915 __ far_call(RuntimeAddress(dest));
2916 } else {
2917 __ mov(rscratch1, RuntimeAddress(dest));
2918 __ blr(rscratch1);
2919 }
2920
2921 if (info != NULL) {
2922 add_call_info_here(info);
2923 }
2924 __ maybe_isb();
2925 }
2926
volatile_move_op(LIR_Opr src,LIR_Opr dest,BasicType type,CodeEmitInfo * info)2927 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2928 if (dest->is_address() || src->is_address()) {
2929 move_op(src, dest, type, lir_patch_none, info,
2930 /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
2931 } else {
2932 ShouldNotReachHere();
2933 }
2934 }
2935
2936 #ifdef ASSERT
2937 // emit run-time assertion
emit_assert(LIR_OpAssert * op)2938 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2939 assert(op->code() == lir_assert, "must be");
2940
2941 if (op->in_opr1()->is_valid()) {
2942 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2943 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2944 } else {
2945 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2946 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2947 }
2948
2949 Label ok;
2950 if (op->condition() != lir_cond_always) {
2951 Assembler::Condition acond = Assembler::AL;
2952 switch (op->condition()) {
2953 case lir_cond_equal: acond = Assembler::EQ; break;
2954 case lir_cond_notEqual: acond = Assembler::NE; break;
2955 case lir_cond_less: acond = Assembler::LT; break;
2956 case lir_cond_lessEqual: acond = Assembler::LE; break;
2957 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2958 case lir_cond_greater: acond = Assembler::GT; break;
2959 case lir_cond_belowEqual: acond = Assembler::LS; break;
2960 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2961 default: ShouldNotReachHere();
2962 }
2963 __ br(acond, ok);
2964 }
2965 if (op->halt()) {
2966 const char* str = __ code_string(op->msg());
2967 __ stop(str);
2968 } else {
2969 breakpoint();
2970 }
2971 __ bind(ok);
2972 }
2973 #endif
2974
2975 #ifndef PRODUCT
2976 #define COMMENT(x) do { __ block_comment(x); } while (0)
2977 #else
2978 #define COMMENT(x)
2979 #endif
2980
membar()2981 void LIR_Assembler::membar() {
2982 COMMENT("membar");
2983 __ membar(MacroAssembler::AnyAny);
2984 }
2985
membar_acquire()2986 void LIR_Assembler::membar_acquire() {
2987 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2988 }
2989
membar_release()2990 void LIR_Assembler::membar_release() {
2991 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2992 }
2993
membar_loadload()2994 void LIR_Assembler::membar_loadload() {
2995 __ membar(Assembler::LoadLoad);
2996 }
2997
membar_storestore()2998 void LIR_Assembler::membar_storestore() {
2999 __ membar(MacroAssembler::StoreStore);
3000 }
3001
membar_loadstore()3002 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3003
membar_storeload()3004 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3005
on_spin_wait()3006 void LIR_Assembler::on_spin_wait() {
3007 Unimplemented();
3008 }
3009
get_thread(LIR_Opr result_reg)3010 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3011 __ mov(result_reg->as_register(), rthread);
3012 }
3013
3014
peephole(LIR_List * lir)3015 void LIR_Assembler::peephole(LIR_List *lir) {
3016 #if 0
3017 if (tableswitch_count >= max_tableswitches)
3018 return;
3019
3020 /*
3021 This finite-state automaton recognizes sequences of compare-and-
3022 branch instructions. We will turn them into a tableswitch. You
3023 could argue that C1 really shouldn't be doing this sort of
3024 optimization, but without it the code is really horrible.
3025 */
3026
3027 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3028 int first_key, last_key = -2147483648;
3029 int next_key = 0;
3030 int start_insn = -1;
3031 int last_insn = -1;
3032 Register reg = noreg;
3033 LIR_Opr reg_opr;
3034 state = start_s;
3035
3036 LIR_OpList* inst = lir->instructions_list();
3037 for (int i = 0; i < inst->length(); i++) {
3038 LIR_Op* op = inst->at(i);
3039 switch (state) {
3040 case start_s:
3041 first_key = -1;
3042 start_insn = i;
3043 switch (op->code()) {
3044 case lir_cmp:
3045 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3046 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3047 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3048 && opr2->is_constant()
3049 && opr2->type() == T_INT) {
3050 reg_opr = opr1;
3051 reg = opr1->as_register();
3052 first_key = opr2->as_constant_ptr()->as_jint();
3053 next_key = first_key + 1;
3054 state = cmp_s;
3055 goto next_state;
3056 }
3057 break;
3058 }
3059 break;
3060 case cmp_s:
3061 switch (op->code()) {
3062 case lir_branch:
3063 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3064 state = beq_s;
3065 last_insn = i;
3066 goto next_state;
3067 }
3068 }
3069 state = start_s;
3070 break;
3071 case beq_s:
3072 switch (op->code()) {
3073 case lir_cmp: {
3074 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3075 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3076 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3077 && opr1->as_register() == reg
3078 && opr2->is_constant()
3079 && opr2->type() == T_INT
3080 && opr2->as_constant_ptr()->as_jint() == next_key) {
3081 last_key = next_key;
3082 next_key++;
3083 state = cmp_s;
3084 goto next_state;
3085 }
3086 }
3087 }
3088 last_key = next_key;
3089 state = start_s;
3090 break;
3091 default:
3092 assert(false, "impossible state");
3093 }
3094 if (state == start_s) {
3095 if (first_key < last_key - 5L && reg != noreg) {
3096 {
3097 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3098 // reg->encoding(),
3099 // start_insn, first_key, last_key);
3100 // for (int i = 0; i < inst->length(); i++) {
3101 // inst->at(i)->print();
3102 // tty->print("\n");
3103 // }
3104 // tty->print("\n");
3105 }
3106
3107 struct tableswitch *sw = &switches[tableswitch_count];
3108 sw->_insn_index = start_insn, sw->_first_key = first_key,
3109 sw->_last_key = last_key, sw->_reg = reg;
3110 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3111 {
3112 // Insert the new table of branches
3113 int offset = last_insn;
3114 for (int n = first_key; n < last_key; n++) {
3115 inst->insert_before
3116 (last_insn + 1,
3117 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3118 inst->at(offset)->as_OpBranch()->label()));
3119 offset -= 2, i++;
3120 }
3121 }
3122 // Delete all the old compare-and-branch instructions
3123 for (int n = first_key; n < last_key; n++) {
3124 inst->remove_at(start_insn);
3125 inst->remove_at(start_insn);
3126 }
3127 // Insert the tableswitch instruction
3128 inst->insert_before(start_insn,
3129 new LIR_Op2(lir_cmp, lir_cond_always,
3130 LIR_OprFact::intConst(tableswitch_count),
3131 reg_opr));
3132 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3133 tableswitch_count++;
3134 }
3135 reg = noreg;
3136 last_key = -2147483648;
3137 }
3138 next_state:
3139 ;
3140 }
3141 #endif
3142 }
3143
atomic_op(LIR_Code code,LIR_Opr src,LIR_Opr data,LIR_Opr dest,LIR_Opr tmp_op)3144 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3145 Address addr = as_Address(src->as_address_ptr());
3146 BasicType type = src->type();
3147 bool is_oop = type == T_OBJECT || type == T_ARRAY;
3148
3149 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3150 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3151
3152 switch(type) {
3153 case T_INT:
3154 xchg = &MacroAssembler::atomic_xchgalw;
3155 add = &MacroAssembler::atomic_addalw;
3156 break;
3157 case T_LONG:
3158 xchg = &MacroAssembler::atomic_xchgal;
3159 add = &MacroAssembler::atomic_addal;
3160 break;
3161 case T_OBJECT:
3162 case T_ARRAY:
3163 if (UseCompressedOops) {
3164 xchg = &MacroAssembler::atomic_xchgalw;
3165 add = &MacroAssembler::atomic_addalw;
3166 } else {
3167 xchg = &MacroAssembler::atomic_xchgal;
3168 add = &MacroAssembler::atomic_addal;
3169 }
3170 break;
3171 default:
3172 ShouldNotReachHere();
3173 xchg = &MacroAssembler::atomic_xchgal;
3174 add = &MacroAssembler::atomic_addal; // unreachable
3175 }
3176
3177 switch (code) {
3178 case lir_xadd:
3179 {
3180 RegisterOrConstant inc;
3181 Register tmp = as_reg(tmp_op);
3182 Register dst = as_reg(dest);
3183 if (data->is_constant()) {
3184 inc = RegisterOrConstant(as_long(data));
3185 assert_different_registers(dst, addr.base(), tmp,
3186 rscratch1, rscratch2);
3187 } else {
3188 inc = RegisterOrConstant(as_reg(data));
3189 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3190 rscratch1, rscratch2);
3191 }
3192 __ lea(tmp, addr);
3193 (_masm->*add)(dst, inc, tmp);
3194 break;
3195 }
3196 case lir_xchg:
3197 {
3198 Register tmp = tmp_op->as_register();
3199 Register obj = as_reg(data);
3200 Register dst = as_reg(dest);
3201 if (is_oop && UseCompressedOops) {
3202 __ encode_heap_oop(rscratch2, obj);
3203 obj = rscratch2;
3204 }
3205 assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3206 __ lea(tmp, addr);
3207 (_masm->*xchg)(dst, obj, tmp);
3208 if (is_oop && UseCompressedOops) {
3209 __ decode_heap_oop(dst);
3210 }
3211 }
3212 break;
3213 default:
3214 ShouldNotReachHere();
3215 }
3216 __ membar(__ AnyAny);
3217 }
3218
3219 #undef __
3220