1 /*
2 * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "gc/shared/barrierSet.hpp"
38 #include "gc/shared/cardTableBarrierSet.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "vmreg_aarch64.inline.hpp"
45
46
47
48 #ifndef PRODUCT
49 #define COMMENT(x) do { __ block_comment(x); } while (0)
50 #else
51 #define COMMENT(x)
52 #endif
53
54 NEEDS_CLEANUP // remove this definitions ?
55 const Register IC_Klass = rscratch2; // where the IC klass is cached
56 const Register SYNC_header = r0; // synchronization header
57 const Register SHIFT_count = r0; // where count for shift operations must be
58
59 #define __ _masm->
60
61
select_different_registers(Register preserve,Register extra,Register & tmp1,Register & tmp2)62 static void select_different_registers(Register preserve,
63 Register extra,
64 Register &tmp1,
65 Register &tmp2) {
66 if (tmp1 == preserve) {
67 assert_different_registers(tmp1, tmp2, extra);
68 tmp1 = extra;
69 } else if (tmp2 == preserve) {
70 assert_different_registers(tmp1, tmp2, extra);
71 tmp2 = extra;
72 }
73 assert_different_registers(preserve, tmp1, tmp2);
74 }
75
76
77
select_different_registers(Register preserve,Register extra,Register & tmp1,Register & tmp2,Register & tmp3)78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2,
82 Register &tmp3) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, tmp3, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, tmp3, extra);
88 tmp2 = extra;
89 } else if (tmp3 == preserve) {
90 assert_different_registers(tmp1, tmp2, tmp3, extra);
91 tmp3 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2, tmp3);
94 }
95
96
is_small_constant(LIR_Opr opr)97 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
98
99
receiverOpr()100 LIR_Opr LIR_Assembler::receiverOpr() {
101 return FrameMap::receiver_opr;
102 }
103
osrBufferPointer()104 LIR_Opr LIR_Assembler::osrBufferPointer() {
105 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
106 }
107
108 //--------------fpu register translations-----------------------
109
110
float_constant(float f)111 address LIR_Assembler::float_constant(float f) {
112 address const_addr = __ float_constant(f);
113 if (const_addr == NULL) {
114 bailout("const section overflow");
115 return __ code()->consts()->start();
116 } else {
117 return const_addr;
118 }
119 }
120
121
double_constant(double d)122 address LIR_Assembler::double_constant(double d) {
123 address const_addr = __ double_constant(d);
124 if (const_addr == NULL) {
125 bailout("const section overflow");
126 return __ code()->consts()->start();
127 } else {
128 return const_addr;
129 }
130 }
131
int_constant(jlong n)132 address LIR_Assembler::int_constant(jlong n) {
133 address const_addr = __ long_constant(n);
134 if (const_addr == NULL) {
135 bailout("const section overflow");
136 return __ code()->consts()->start();
137 } else {
138 return const_addr;
139 }
140 }
141
set_24bit_FPU()142 void LIR_Assembler::set_24bit_FPU() { Unimplemented(); }
143
reset_FPU()144 void LIR_Assembler::reset_FPU() { Unimplemented(); }
145
fpop()146 void LIR_Assembler::fpop() { Unimplemented(); }
147
fxch(int i)148 void LIR_Assembler::fxch(int i) { Unimplemented(); }
149
fld(int i)150 void LIR_Assembler::fld(int i) { Unimplemented(); }
151
ffree(int i)152 void LIR_Assembler::ffree(int i) { Unimplemented(); }
153
breakpoint()154 void LIR_Assembler::breakpoint() { Unimplemented(); }
155
push(LIR_Opr opr)156 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
157
pop(LIR_Opr opr)158 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
159
is_literal_address(LIR_Address * addr)160 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
161 //-------------------------------------------
162
as_reg(LIR_Opr op)163 static Register as_reg(LIR_Opr op) {
164 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
165 }
166
as_long(LIR_Opr data)167 static jlong as_long(LIR_Opr data) {
168 jlong result;
169 switch (data->type()) {
170 case T_INT:
171 result = (data->as_jint());
172 break;
173 case T_LONG:
174 result = (data->as_jlong());
175 break;
176 default:
177 ShouldNotReachHere();
178 result = 0; // unreachable
179 }
180 return result;
181 }
182
as_Address(LIR_Address * addr,Register tmp)183 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
184 Register base = addr->base()->as_pointer_register();
185 LIR_Opr opr = addr->index();
186 if (opr->is_cpu_register()) {
187 Register index;
188 if (opr->is_single_cpu())
189 index = opr->as_register();
190 else
191 index = opr->as_register_lo();
192 assert(addr->disp() == 0, "must be");
193 switch(opr->type()) {
194 case T_INT:
195 return Address(base, index, Address::sxtw(addr->scale()));
196 case T_LONG:
197 return Address(base, index, Address::lsl(addr->scale()));
198 default:
199 ShouldNotReachHere();
200 }
201 } else {
202 intptr_t addr_offset = intptr_t(addr->disp());
203 if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
204 return Address(base, addr_offset, Address::lsl(addr->scale()));
205 else {
206 __ mov(tmp, addr_offset);
207 return Address(base, tmp, Address::lsl(addr->scale()));
208 }
209 }
210 return Address();
211 }
212
as_Address_hi(LIR_Address * addr)213 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
214 ShouldNotReachHere();
215 return Address();
216 }
217
as_Address(LIR_Address * addr)218 Address LIR_Assembler::as_Address(LIR_Address* addr) {
219 return as_Address(addr, rscratch1);
220 }
221
as_Address_lo(LIR_Address * addr)222 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
223 return as_Address(addr, rscratch1); // Ouch
224 // FIXME: This needs to be much more clever. See x86.
225 }
226
227
osr_entry()228 void LIR_Assembler::osr_entry() {
229 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
230 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
231 ValueStack* entry_state = osr_entry->state();
232 int number_of_locks = entry_state->locks_size();
233
234 // we jump here if osr happens with the interpreter
235 // state set up to continue at the beginning of the
236 // loop that triggered osr - in particular, we have
237 // the following registers setup:
238 //
239 // r2: osr buffer
240 //
241
242 // build frame
243 ciMethod* m = compilation()->method();
244 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
245
246 // OSR buffer is
247 //
248 // locals[nlocals-1..0]
249 // monitors[0..number_of_locks]
250 //
251 // locals is a direct copy of the interpreter frame so in the osr buffer
252 // so first slot in the local array is the last local from the interpreter
253 // and last slot is local[0] (receiver) from the interpreter
254 //
255 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
256 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
257 // in the interpreter frame (the method lock if a sync method)
258
259 // Initialize monitors in the compiled activation.
260 // r2: pointer to osr buffer
261 //
262 // All other registers are dead at this point and the locals will be
263 // copied into place by code emitted in the IR.
264
265 Register OSR_buf = osrBufferPointer()->as_pointer_register();
266 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
267 int monitor_offset = BytesPerWord * method()->max_locals() +
268 (2 * BytesPerWord) * (number_of_locks - 1);
269 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
270 // the OSR buffer using 2 word entries: first the lock and then
271 // the oop.
272 for (int i = 0; i < number_of_locks; i++) {
273 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
274 #ifdef ASSERT
275 // verify the interpreter's monitor has a non-null object
276 {
277 Label L;
278 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
279 __ cbnz(rscratch1, L);
280 __ stop("locked object is NULL");
281 __ bind(L);
282 }
283 #endif
284 __ ldr(r19, Address(OSR_buf, slot_offset + 0));
285 __ str(r19, frame_map()->address_for_monitor_lock(i));
286 __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
287 __ str(r19, frame_map()->address_for_monitor_object(i));
288 }
289 }
290 }
291
292
293 // inline cache check; done before the frame is built.
check_icache()294 int LIR_Assembler::check_icache() {
295 Register receiver = FrameMap::receiver_opr->as_register();
296 Register ic_klass = IC_Klass;
297 int start_offset = __ offset();
298 __ inline_cache_check(receiver, ic_klass);
299
300 // if icache check fails, then jump to runtime routine
301 // Note: RECEIVER must still contain the receiver!
302 Label dont;
303 __ br(Assembler::EQ, dont);
304 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
305
306 // We align the verified entry point unless the method body
307 // (including its inline cache check) will fit in a single 64-byte
308 // icache line.
309 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
310 // force alignment after the cache check.
311 __ align(CodeEntryAlignment);
312 }
313
314 __ bind(dont);
315 return start_offset;
316 }
317
318
jobject2reg(jobject o,Register reg)319 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
320 if (o == NULL) {
321 __ mov(reg, zr);
322 } else {
323 __ movoop(reg, o, /*immediate*/true);
324 }
325 }
326
deoptimize_trap(CodeEmitInfo * info)327 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
328 address target = NULL;
329 relocInfo::relocType reloc_type = relocInfo::none;
330
331 switch (patching_id(info)) {
332 case PatchingStub::access_field_id:
333 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
334 reloc_type = relocInfo::section_word_type;
335 break;
336 case PatchingStub::load_klass_id:
337 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
338 reloc_type = relocInfo::metadata_type;
339 break;
340 case PatchingStub::load_mirror_id:
341 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
342 reloc_type = relocInfo::oop_type;
343 break;
344 case PatchingStub::load_appendix_id:
345 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
346 reloc_type = relocInfo::oop_type;
347 break;
348 default: ShouldNotReachHere();
349 }
350
351 __ far_call(RuntimeAddress(target));
352 add_call_info_here(info);
353 }
354
jobject2reg_with_patching(Register reg,CodeEmitInfo * info)355 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
356 deoptimize_trap(info);
357 }
358
359
360 // This specifies the rsp decrement needed to build the frame
initial_frame_size_in_bytes() const361 int LIR_Assembler::initial_frame_size_in_bytes() const {
362 // if rounding, must let FrameMap know!
363
364 // The frame_map records size in slots (32bit word)
365
366 // subtract two words to account for return address and link
367 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
368 }
369
370
emit_exception_handler()371 int LIR_Assembler::emit_exception_handler() {
372 // if the last instruction is a call (typically to do a throw which
373 // is coming at the end after block reordering) the return address
374 // must still point into the code area in order to avoid assertion
375 // failures when searching for the corresponding bci => add a nop
376 // (was bug 5/14/1999 - gri)
377 __ nop();
378
379 // generate code for exception handler
380 address handler_base = __ start_a_stub(exception_handler_size());
381 if (handler_base == NULL) {
382 // not enough space left for the handler
383 bailout("exception handler overflow");
384 return -1;
385 }
386
387 int offset = code_offset();
388
389 // the exception oop and pc are in r0, and r3
390 // no other registers need to be preserved, so invalidate them
391 __ invalidate_registers(false, true, true, false, true, true);
392
393 // check that there is really an exception
394 __ verify_not_null_oop(r0);
395
396 // search an exception handler (r0: exception oop, r3: throwing pc)
397 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); __ should_not_reach_here();
398 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
399 __ end_a_stub();
400
401 return offset;
402 }
403
404
405 // Emit the code to remove the frame from the stack in the exception
406 // unwind path.
emit_unwind_handler()407 int LIR_Assembler::emit_unwind_handler() {
408 #ifndef PRODUCT
409 if (CommentedAssembly) {
410 _masm->block_comment("Unwind handler");
411 }
412 #endif
413
414 int offset = code_offset();
415
416 // Fetch the exception from TLS and clear out exception related thread state
417 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
418 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
419 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
420
421 __ bind(_unwind_handler_entry);
422 __ verify_not_null_oop(r0);
423 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
424 __ mov(r19, r0); // Preserve the exception
425 }
426
427 // Preform needed unlocking
428 MonitorExitStub* stub = NULL;
429 if (method()->is_synchronized()) {
430 monitor_address(0, FrameMap::r0_opr);
431 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
432 __ unlock_object(r5, r4, r0, *stub->entry());
433 __ bind(*stub->continuation());
434 }
435
436 if (compilation()->env()->dtrace_method_probes()) {
437 __ call_Unimplemented();
438 #if 0
439 __ movptr(Address(rsp, 0), rax);
440 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
441 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
442 #endif
443 }
444
445 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
446 __ mov(r0, r19); // Restore the exception
447 }
448
449 // remove the activation and dispatch to the unwind handler
450 __ block_comment("remove_frame and dispatch to the unwind handler");
451 __ remove_frame(initial_frame_size_in_bytes());
452 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
453
454 // Emit the slow path assembly
455 if (stub != NULL) {
456 stub->emit_code(this);
457 }
458
459 return offset;
460 }
461
462
emit_deopt_handler()463 int LIR_Assembler::emit_deopt_handler() {
464 // if the last instruction is a call (typically to do a throw which
465 // is coming at the end after block reordering) the return address
466 // must still point into the code area in order to avoid assertion
467 // failures when searching for the corresponding bci => add a nop
468 // (was bug 5/14/1999 - gri)
469 __ nop();
470
471 // generate code for exception handler
472 address handler_base = __ start_a_stub(deopt_handler_size());
473 if (handler_base == NULL) {
474 // not enough space left for the handler
475 bailout("deopt handler overflow");
476 return -1;
477 }
478
479 int offset = code_offset();
480
481 __ adr(lr, pc());
482 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
483 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
484 __ end_a_stub();
485
486 return offset;
487 }
488
add_debug_info_for_branch(address adr,CodeEmitInfo * info)489 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
490 _masm->code_section()->relocate(adr, relocInfo::poll_type);
491 int pc_offset = code_offset();
492 flush_debug_info(pc_offset);
493 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
494 if (info->exception_handlers() != NULL) {
495 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
496 }
497 }
498
return_op(LIR_Opr result)499 void LIR_Assembler::return_op(LIR_Opr result) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
501
502 // Pop the stack before the safepoint code
503 __ remove_frame(initial_frame_size_in_bytes());
504
505 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
506 __ reserved_stack_check();
507 }
508
509 address polling_page(os::get_polling_page());
510 __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);
511 __ ret(lr);
512 }
513
safepoint_poll(LIR_Opr tmp,CodeEmitInfo * info)514 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
515 address polling_page(os::get_polling_page());
516 guarantee(info != NULL, "Shouldn't be NULL");
517 assert(os::is_poll_address(polling_page), "should be");
518 __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);
519 add_debug_info_for_branch(info); // This isn't just debug info:
520 // it's the oop map
521 __ read_polling_page(rscratch1, relocInfo::poll_type);
522 return __ offset();
523 }
524
525
move_regs(Register from_reg,Register to_reg)526 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
527 if (from_reg == r31_sp)
528 from_reg = sp;
529 if (to_reg == r31_sp)
530 to_reg = sp;
531 __ mov(to_reg, from_reg);
532 }
533
swap_reg(Register a,Register b)534 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
535
536
const2reg(LIR_Opr src,LIR_Opr dest,LIR_PatchCode patch_code,CodeEmitInfo * info)537 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
538 assert(src->is_constant(), "should not call otherwise");
539 assert(dest->is_register(), "should not call otherwise");
540 LIR_Const* c = src->as_constant_ptr();
541
542 switch (c->type()) {
543 case T_INT: {
544 assert(patch_code == lir_patch_none, "no patching handled here");
545 __ movw(dest->as_register(), c->as_jint());
546 break;
547 }
548
549 case T_ADDRESS: {
550 assert(patch_code == lir_patch_none, "no patching handled here");
551 __ mov(dest->as_register(), c->as_jint());
552 break;
553 }
554
555 case T_LONG: {
556 assert(patch_code == lir_patch_none, "no patching handled here");
557 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
558 break;
559 }
560
561 case T_OBJECT: {
562 if (patch_code == lir_patch_none) {
563 jobject2reg(c->as_jobject(), dest->as_register());
564 } else {
565 jobject2reg_with_patching(dest->as_register(), info);
566 }
567 break;
568 }
569
570 case T_METADATA: {
571 if (patch_code != lir_patch_none) {
572 klass2reg_with_patching(dest->as_register(), info);
573 } else {
574 __ mov_metadata(dest->as_register(), c->as_metadata());
575 }
576 break;
577 }
578
579 case T_FLOAT: {
580 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
581 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
582 } else {
583 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
584 __ ldrs(dest->as_float_reg(), Address(rscratch1));
585 }
586 break;
587 }
588
589 case T_DOUBLE: {
590 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
591 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
592 } else {
593 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
594 __ ldrd(dest->as_double_reg(), Address(rscratch1));
595 }
596 break;
597 }
598
599 default:
600 ShouldNotReachHere();
601 }
602 }
603
const2stack(LIR_Opr src,LIR_Opr dest)604 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
605 LIR_Const* c = src->as_constant_ptr();
606 switch (c->type()) {
607 case T_OBJECT:
608 {
609 if (! c->as_jobject())
610 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
611 else {
612 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
613 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
614 }
615 }
616 break;
617 case T_ADDRESS:
618 {
619 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
620 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
621 }
622 case T_INT:
623 case T_FLOAT:
624 {
625 Register reg = zr;
626 if (c->as_jint_bits() == 0)
627 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
628 else {
629 __ movw(rscratch1, c->as_jint_bits());
630 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
631 }
632 }
633 break;
634 case T_LONG:
635 case T_DOUBLE:
636 {
637 Register reg = zr;
638 if (c->as_jlong_bits() == 0)
639 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
640 lo_word_offset_in_bytes));
641 else {
642 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
643 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
644 lo_word_offset_in_bytes));
645 }
646 }
647 break;
648 default:
649 ShouldNotReachHere();
650 }
651 }
652
const2mem(LIR_Opr src,LIR_Opr dest,BasicType type,CodeEmitInfo * info,bool wide)653 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
654 assert(src->is_constant(), "should not call otherwise");
655 LIR_Const* c = src->as_constant_ptr();
656 LIR_Address* to_addr = dest->as_address_ptr();
657
658 void (Assembler::* insn)(Register Rt, const Address &adr);
659
660 switch (type) {
661 case T_ADDRESS:
662 assert(c->as_jint() == 0, "should be");
663 insn = &Assembler::str;
664 break;
665 case T_LONG:
666 assert(c->as_jlong() == 0, "should be");
667 insn = &Assembler::str;
668 break;
669 case T_INT:
670 assert(c->as_jint() == 0, "should be");
671 insn = &Assembler::strw;
672 break;
673 case T_OBJECT:
674 case T_ARRAY:
675 assert(c->as_jobject() == 0, "should be");
676 if (UseCompressedOops && !wide) {
677 insn = &Assembler::strw;
678 } else {
679 insn = &Assembler::str;
680 }
681 break;
682 case T_CHAR:
683 case T_SHORT:
684 assert(c->as_jint() == 0, "should be");
685 insn = &Assembler::strh;
686 break;
687 case T_BOOLEAN:
688 case T_BYTE:
689 assert(c->as_jint() == 0, "should be");
690 insn = &Assembler::strb;
691 break;
692 default:
693 ShouldNotReachHere();
694 insn = &Assembler::str; // unreachable
695 }
696
697 if (info) add_debug_info_for_null_check_here(info);
698 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
699 }
700
reg2reg(LIR_Opr src,LIR_Opr dest)701 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
702 assert(src->is_register(), "should not call otherwise");
703 assert(dest->is_register(), "should not call otherwise");
704
705 // move between cpu-registers
706 if (dest->is_single_cpu()) {
707 if (src->type() == T_LONG) {
708 // Can do LONG -> OBJECT
709 move_regs(src->as_register_lo(), dest->as_register());
710 return;
711 }
712 assert(src->is_single_cpu(), "must match");
713 if (src->type() == T_OBJECT) {
714 __ verify_oop(src->as_register());
715 }
716 move_regs(src->as_register(), dest->as_register());
717
718 } else if (dest->is_double_cpu()) {
719 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
720 // Surprising to me but we can see move of a long to t_object
721 __ verify_oop(src->as_register());
722 move_regs(src->as_register(), dest->as_register_lo());
723 return;
724 }
725 assert(src->is_double_cpu(), "must match");
726 Register f_lo = src->as_register_lo();
727 Register f_hi = src->as_register_hi();
728 Register t_lo = dest->as_register_lo();
729 Register t_hi = dest->as_register_hi();
730 assert(f_hi == f_lo, "must be same");
731 assert(t_hi == t_lo, "must be same");
732 move_regs(f_lo, t_lo);
733
734 } else if (dest->is_single_fpu()) {
735 __ fmovs(dest->as_float_reg(), src->as_float_reg());
736
737 } else if (dest->is_double_fpu()) {
738 __ fmovd(dest->as_double_reg(), src->as_double_reg());
739
740 } else {
741 ShouldNotReachHere();
742 }
743 }
744
reg2stack(LIR_Opr src,LIR_Opr dest,BasicType type,bool pop_fpu_stack)745 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
746 if (src->is_single_cpu()) {
747 if (type == T_ARRAY || type == T_OBJECT) {
748 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
749 __ verify_oop(src->as_register());
750 } else if (type == T_METADATA || type == T_DOUBLE) {
751 __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
752 } else {
753 __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
754 }
755
756 } else if (src->is_double_cpu()) {
757 Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
758 __ str(src->as_register_lo(), dest_addr_LO);
759
760 } else if (src->is_single_fpu()) {
761 Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
762 __ strs(src->as_float_reg(), dest_addr);
763
764 } else if (src->is_double_fpu()) {
765 Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
766 __ strd(src->as_double_reg(), dest_addr);
767
768 } else {
769 ShouldNotReachHere();
770 }
771
772 }
773
774
reg2mem(LIR_Opr src,LIR_Opr dest,BasicType type,LIR_PatchCode patch_code,CodeEmitInfo * info,bool pop_fpu_stack,bool wide,bool)775 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
776 LIR_Address* to_addr = dest->as_address_ptr();
777 PatchingStub* patch = NULL;
778 Register compressed_src = rscratch1;
779
780 if (patch_code != lir_patch_none) {
781 deoptimize_trap(info);
782 return;
783 }
784
785 if (type == T_ARRAY || type == T_OBJECT) {
786 __ verify_oop(src->as_register());
787
788 if (UseCompressedOops && !wide) {
789 __ encode_heap_oop(compressed_src, src->as_register());
790 } else {
791 compressed_src = src->as_register();
792 }
793 }
794
795 int null_check_here = code_offset();
796 switch (type) {
797 case T_FLOAT: {
798 __ strs(src->as_float_reg(), as_Address(to_addr));
799 break;
800 }
801
802 case T_DOUBLE: {
803 __ strd(src->as_double_reg(), as_Address(to_addr));
804 break;
805 }
806
807 case T_ARRAY: // fall through
808 case T_OBJECT: // fall through
809 if (UseCompressedOops && !wide) {
810 __ strw(compressed_src, as_Address(to_addr, rscratch2));
811 } else {
812 __ str(compressed_src, as_Address(to_addr));
813 }
814 break;
815 case T_METADATA:
816 // We get here to store a method pointer to the stack to pass to
817 // a dtrace runtime call. This can't work on 64 bit with
818 // compressed klass ptrs: T_METADATA can be a compressed klass
819 // ptr or a 64 bit method pointer.
820 ShouldNotReachHere();
821 __ str(src->as_register(), as_Address(to_addr));
822 break;
823 case T_ADDRESS:
824 __ str(src->as_register(), as_Address(to_addr));
825 break;
826 case T_INT:
827 __ strw(src->as_register(), as_Address(to_addr));
828 break;
829
830 case T_LONG: {
831 __ str(src->as_register_lo(), as_Address_lo(to_addr));
832 break;
833 }
834
835 case T_BYTE: // fall through
836 case T_BOOLEAN: {
837 __ strb(src->as_register(), as_Address(to_addr));
838 break;
839 }
840
841 case T_CHAR: // fall through
842 case T_SHORT:
843 __ strh(src->as_register(), as_Address(to_addr));
844 break;
845
846 default:
847 ShouldNotReachHere();
848 }
849 if (info != NULL) {
850 add_debug_info_for_null_check(null_check_here, info);
851 }
852 }
853
854
stack2reg(LIR_Opr src,LIR_Opr dest,BasicType type)855 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
856 assert(src->is_stack(), "should not call otherwise");
857 assert(dest->is_register(), "should not call otherwise");
858
859 if (dest->is_single_cpu()) {
860 if (type == T_ARRAY || type == T_OBJECT) {
861 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
862 __ verify_oop(dest->as_register());
863 } else if (type == T_METADATA) {
864 __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
865 } else {
866 __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
867 }
868
869 } else if (dest->is_double_cpu()) {
870 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
871 __ ldr(dest->as_register_lo(), src_addr_LO);
872
873 } else if (dest->is_single_fpu()) {
874 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
875 __ ldrs(dest->as_float_reg(), src_addr);
876
877 } else if (dest->is_double_fpu()) {
878 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
879 __ ldrd(dest->as_double_reg(), src_addr);
880
881 } else {
882 ShouldNotReachHere();
883 }
884 }
885
886
klass2reg_with_patching(Register reg,CodeEmitInfo * info)887 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
888 address target = NULL;
889 relocInfo::relocType reloc_type = relocInfo::none;
890
891 switch (patching_id(info)) {
892 case PatchingStub::access_field_id:
893 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
894 reloc_type = relocInfo::section_word_type;
895 break;
896 case PatchingStub::load_klass_id:
897 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
898 reloc_type = relocInfo::metadata_type;
899 break;
900 case PatchingStub::load_mirror_id:
901 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
902 reloc_type = relocInfo::oop_type;
903 break;
904 case PatchingStub::load_appendix_id:
905 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
906 reloc_type = relocInfo::oop_type;
907 break;
908 default: ShouldNotReachHere();
909 }
910
911 __ far_call(RuntimeAddress(target));
912 add_call_info_here(info);
913 }
914
stack2stack(LIR_Opr src,LIR_Opr dest,BasicType type)915 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
916
917 LIR_Opr temp;
918 if (type == T_LONG || type == T_DOUBLE)
919 temp = FrameMap::rscratch1_long_opr;
920 else
921 temp = FrameMap::rscratch1_opr;
922
923 stack2reg(src, temp, src->type());
924 reg2stack(temp, dest, dest->type(), false);
925 }
926
927
mem2reg(LIR_Opr src,LIR_Opr dest,BasicType type,LIR_PatchCode patch_code,CodeEmitInfo * info,bool wide,bool)928 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
929 LIR_Address* addr = src->as_address_ptr();
930 LIR_Address* from_addr = src->as_address_ptr();
931
932 if (addr->base()->type() == T_OBJECT) {
933 __ verify_oop(addr->base()->as_pointer_register());
934 }
935
936 if (patch_code != lir_patch_none) {
937 deoptimize_trap(info);
938 return;
939 }
940
941 if (info != NULL) {
942 add_debug_info_for_null_check_here(info);
943 }
944 int null_check_here = code_offset();
945 switch (type) {
946 case T_FLOAT: {
947 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
948 break;
949 }
950
951 case T_DOUBLE: {
952 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
953 break;
954 }
955
956 case T_ARRAY: // fall through
957 case T_OBJECT: // fall through
958 if (UseCompressedOops && !wide) {
959 __ ldrw(dest->as_register(), as_Address(from_addr));
960 } else {
961 __ ldr(dest->as_register(), as_Address(from_addr));
962 }
963 break;
964 case T_METADATA:
965 // We get here to store a method pointer to the stack to pass to
966 // a dtrace runtime call. This can't work on 64 bit with
967 // compressed klass ptrs: T_METADATA can be a compressed klass
968 // ptr or a 64 bit method pointer.
969 ShouldNotReachHere();
970 __ ldr(dest->as_register(), as_Address(from_addr));
971 break;
972 case T_ADDRESS:
973 // FIXME: OMG this is a horrible kludge. Any offset from an
974 // address that matches klass_offset_in_bytes() will be loaded
975 // as a word, not a long.
976 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
977 __ ldrw(dest->as_register(), as_Address(from_addr));
978 } else {
979 __ ldr(dest->as_register(), as_Address(from_addr));
980 }
981 break;
982 case T_INT:
983 __ ldrw(dest->as_register(), as_Address(from_addr));
984 break;
985
986 case T_LONG: {
987 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
988 break;
989 }
990
991 case T_BYTE:
992 __ ldrsb(dest->as_register(), as_Address(from_addr));
993 break;
994 case T_BOOLEAN: {
995 __ ldrb(dest->as_register(), as_Address(from_addr));
996 break;
997 }
998
999 case T_CHAR:
1000 __ ldrh(dest->as_register(), as_Address(from_addr));
1001 break;
1002 case T_SHORT:
1003 __ ldrsh(dest->as_register(), as_Address(from_addr));
1004 break;
1005
1006 default:
1007 ShouldNotReachHere();
1008 }
1009
1010 if (type == T_ARRAY || type == T_OBJECT) {
1011 if (UseCompressedOops && !wide) {
1012 __ decode_heap_oop(dest->as_register());
1013 }
1014 __ verify_oop(dest->as_register());
1015 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1016 if (UseCompressedClassPointers) {
1017 __ decode_klass_not_null(dest->as_register());
1018 }
1019 }
1020 }
1021
1022
array_element_size(BasicType type) const1023 int LIR_Assembler::array_element_size(BasicType type) const {
1024 int elem_size = type2aelembytes(type);
1025 return exact_log2(elem_size);
1026 }
1027
1028
emit_op3(LIR_Op3 * op)1029 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1030 switch (op->code()) {
1031 case lir_idiv:
1032 case lir_irem:
1033 arithmetic_idiv(op->code(),
1034 op->in_opr1(),
1035 op->in_opr2(),
1036 op->in_opr3(),
1037 op->result_opr(),
1038 op->info());
1039 break;
1040 case lir_fmad:
1041 __ fmaddd(op->result_opr()->as_double_reg(),
1042 op->in_opr1()->as_double_reg(),
1043 op->in_opr2()->as_double_reg(),
1044 op->in_opr3()->as_double_reg());
1045 break;
1046 case lir_fmaf:
1047 __ fmadds(op->result_opr()->as_float_reg(),
1048 op->in_opr1()->as_float_reg(),
1049 op->in_opr2()->as_float_reg(),
1050 op->in_opr3()->as_float_reg());
1051 break;
1052 default: ShouldNotReachHere(); break;
1053 }
1054 }
1055
emit_opBranch(LIR_OpBranch * op)1056 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1057 #ifdef ASSERT
1058 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1059 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1060 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1061 #endif
1062
1063 if (op->cond() == lir_cond_always) {
1064 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1065 __ b(*(op->label()));
1066 } else {
1067 Assembler::Condition acond;
1068 if (op->code() == lir_cond_float_branch) {
1069 bool is_unordered = (op->ublock() == op->block());
1070 // Assembler::EQ does not permit unordered branches, so we add
1071 // another branch here. Likewise, Assembler::NE does not permit
1072 // ordered branches.
1073 if ((is_unordered && op->cond() == lir_cond_equal)
1074 || (!is_unordered && op->cond() == lir_cond_notEqual))
1075 __ br(Assembler::VS, *(op->ublock()->label()));
1076 switch(op->cond()) {
1077 case lir_cond_equal: acond = Assembler::EQ; break;
1078 case lir_cond_notEqual: acond = Assembler::NE; break;
1079 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1080 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1081 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1082 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1083 default: ShouldNotReachHere();
1084 acond = Assembler::EQ; // unreachable
1085 }
1086 } else {
1087 switch (op->cond()) {
1088 case lir_cond_equal: acond = Assembler::EQ; break;
1089 case lir_cond_notEqual: acond = Assembler::NE; break;
1090 case lir_cond_less: acond = Assembler::LT; break;
1091 case lir_cond_lessEqual: acond = Assembler::LE; break;
1092 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1093 case lir_cond_greater: acond = Assembler::GT; break;
1094 case lir_cond_belowEqual: acond = Assembler::LS; break;
1095 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1096 default: ShouldNotReachHere();
1097 acond = Assembler::EQ; // unreachable
1098 }
1099 }
1100 __ br(acond,*(op->label()));
1101 }
1102 }
1103
1104
1105
emit_opConvert(LIR_OpConvert * op)1106 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1107 LIR_Opr src = op->in_opr();
1108 LIR_Opr dest = op->result_opr();
1109
1110 switch (op->bytecode()) {
1111 case Bytecodes::_i2f:
1112 {
1113 __ scvtfws(dest->as_float_reg(), src->as_register());
1114 break;
1115 }
1116 case Bytecodes::_i2d:
1117 {
1118 __ scvtfwd(dest->as_double_reg(), src->as_register());
1119 break;
1120 }
1121 case Bytecodes::_l2d:
1122 {
1123 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1124 break;
1125 }
1126 case Bytecodes::_l2f:
1127 {
1128 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1129 break;
1130 }
1131 case Bytecodes::_f2d:
1132 {
1133 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1134 break;
1135 }
1136 case Bytecodes::_d2f:
1137 {
1138 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1139 break;
1140 }
1141 case Bytecodes::_i2c:
1142 {
1143 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1144 break;
1145 }
1146 case Bytecodes::_i2l:
1147 {
1148 __ sxtw(dest->as_register_lo(), src->as_register());
1149 break;
1150 }
1151 case Bytecodes::_i2s:
1152 {
1153 __ sxth(dest->as_register(), src->as_register());
1154 break;
1155 }
1156 case Bytecodes::_i2b:
1157 {
1158 __ sxtb(dest->as_register(), src->as_register());
1159 break;
1160 }
1161 case Bytecodes::_l2i:
1162 {
1163 _masm->block_comment("FIXME: This could be a no-op");
1164 __ uxtw(dest->as_register(), src->as_register_lo());
1165 break;
1166 }
1167 case Bytecodes::_d2l:
1168 {
1169 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1170 break;
1171 }
1172 case Bytecodes::_f2i:
1173 {
1174 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1175 break;
1176 }
1177 case Bytecodes::_f2l:
1178 {
1179 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1180 break;
1181 }
1182 case Bytecodes::_d2i:
1183 {
1184 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1185 break;
1186 }
1187 default: ShouldNotReachHere();
1188 }
1189 }
1190
emit_alloc_obj(LIR_OpAllocObj * op)1191 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1192 if (op->init_check()) {
1193 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1194 InstanceKlass::init_state_offset()));
1195 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1196 add_debug_info_for_null_check_here(op->stub()->info());
1197 __ br(Assembler::NE, *op->stub()->entry());
1198 }
1199 __ allocate_object(op->obj()->as_register(),
1200 op->tmp1()->as_register(),
1201 op->tmp2()->as_register(),
1202 op->header_size(),
1203 op->object_size(),
1204 op->klass()->as_register(),
1205 *op->stub()->entry());
1206 __ bind(*op->stub()->continuation());
1207 }
1208
emit_alloc_array(LIR_OpAllocArray * op)1209 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1210 Register len = op->len()->as_register();
1211 __ uxtw(len, len);
1212
1213 if (UseSlowPath ||
1214 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1215 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1216 __ b(*op->stub()->entry());
1217 } else {
1218 Register tmp1 = op->tmp1()->as_register();
1219 Register tmp2 = op->tmp2()->as_register();
1220 Register tmp3 = op->tmp3()->as_register();
1221 if (len == tmp1) {
1222 tmp1 = tmp3;
1223 } else if (len == tmp2) {
1224 tmp2 = tmp3;
1225 } else if (len == tmp3) {
1226 // everything is ok
1227 } else {
1228 __ mov(tmp3, len);
1229 }
1230 __ allocate_array(op->obj()->as_register(),
1231 len,
1232 tmp1,
1233 tmp2,
1234 arrayOopDesc::header_size(op->type()),
1235 array_element_size(op->type()),
1236 op->klass()->as_register(),
1237 *op->stub()->entry());
1238 }
1239 __ bind(*op->stub()->continuation());
1240 }
1241
type_profile_helper(Register mdo,ciMethodData * md,ciProfileData * data,Register recv,Label * update_done)1242 void LIR_Assembler::type_profile_helper(Register mdo,
1243 ciMethodData *md, ciProfileData *data,
1244 Register recv, Label* update_done) {
1245 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1246 Label next_test;
1247 // See if the receiver is receiver[n].
1248 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1249 __ ldr(rscratch1, Address(rscratch2));
1250 __ cmp(recv, rscratch1);
1251 __ br(Assembler::NE, next_test);
1252 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1253 __ addptr(data_addr, DataLayout::counter_increment);
1254 __ b(*update_done);
1255 __ bind(next_test);
1256 }
1257
1258 // Didn't find receiver; find next empty slot and fill it in
1259 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1260 Label next_test;
1261 __ lea(rscratch2,
1262 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1263 Address recv_addr(rscratch2);
1264 __ ldr(rscratch1, recv_addr);
1265 __ cbnz(rscratch1, next_test);
1266 __ str(recv, recv_addr);
1267 __ mov(rscratch1, DataLayout::counter_increment);
1268 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1269 __ str(rscratch1, Address(rscratch2));
1270 __ b(*update_done);
1271 __ bind(next_test);
1272 }
1273 }
1274
emit_typecheck_helper(LIR_OpTypeCheck * op,Label * success,Label * failure,Label * obj_is_null)1275 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1276 // we always need a stub for the failure case.
1277 CodeStub* stub = op->stub();
1278 Register obj = op->object()->as_register();
1279 Register k_RInfo = op->tmp1()->as_register();
1280 Register klass_RInfo = op->tmp2()->as_register();
1281 Register dst = op->result_opr()->as_register();
1282 ciKlass* k = op->klass();
1283 Register Rtmp1 = noreg;
1284
1285 // check if it needs to be profiled
1286 ciMethodData* md;
1287 ciProfileData* data;
1288
1289 const bool should_profile = op->should_profile();
1290
1291 if (should_profile) {
1292 ciMethod* method = op->profiled_method();
1293 assert(method != NULL, "Should have method");
1294 int bci = op->profiled_bci();
1295 md = method->method_data_or_null();
1296 assert(md != NULL, "Sanity");
1297 data = md->bci_to_data(bci);
1298 assert(data != NULL, "need data for type check");
1299 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1300 }
1301 Label profile_cast_success, profile_cast_failure;
1302 Label *success_target = should_profile ? &profile_cast_success : success;
1303 Label *failure_target = should_profile ? &profile_cast_failure : failure;
1304
1305 if (obj == k_RInfo) {
1306 k_RInfo = dst;
1307 } else if (obj == klass_RInfo) {
1308 klass_RInfo = dst;
1309 }
1310 if (k->is_loaded() && !UseCompressedClassPointers) {
1311 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1312 } else {
1313 Rtmp1 = op->tmp3()->as_register();
1314 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1315 }
1316
1317 assert_different_registers(obj, k_RInfo, klass_RInfo);
1318
1319 if (should_profile) {
1320 Label not_null;
1321 __ cbnz(obj, not_null);
1322 // Object is null; update MDO and exit
1323 Register mdo = klass_RInfo;
1324 __ mov_metadata(mdo, md->constant_encoding());
1325 Address data_addr
1326 = __ form_address(rscratch2, mdo,
1327 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1328 0);
1329 __ ldrb(rscratch1, data_addr);
1330 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1331 __ strb(rscratch1, data_addr);
1332 __ b(*obj_is_null);
1333 __ bind(not_null);
1334 } else {
1335 __ cbz(obj, *obj_is_null);
1336 }
1337
1338 if (!k->is_loaded()) {
1339 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1340 } else {
1341 __ mov_metadata(k_RInfo, k->constant_encoding());
1342 }
1343 __ verify_oop(obj);
1344
1345 if (op->fast_check()) {
1346 // get object class
1347 // not a safepoint as obj null check happens earlier
1348 __ load_klass(rscratch1, obj);
1349 __ cmp( rscratch1, k_RInfo);
1350
1351 __ br(Assembler::NE, *failure_target);
1352 // successful cast, fall through to profile or jump
1353 } else {
1354 // get object class
1355 // not a safepoint as obj null check happens earlier
1356 __ load_klass(klass_RInfo, obj);
1357 if (k->is_loaded()) {
1358 // See if we get an immediate positive hit
1359 __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
1360 __ cmp(k_RInfo, rscratch1);
1361 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1362 __ br(Assembler::NE, *failure_target);
1363 // successful cast, fall through to profile or jump
1364 } else {
1365 // See if we get an immediate positive hit
1366 __ br(Assembler::EQ, *success_target);
1367 // check for self
1368 __ cmp(klass_RInfo, k_RInfo);
1369 __ br(Assembler::EQ, *success_target);
1370
1371 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1372 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1373 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1374 // result is a boolean
1375 __ cbzw(klass_RInfo, *failure_target);
1376 // successful cast, fall through to profile or jump
1377 }
1378 } else {
1379 // perform the fast part of the checking logic
1380 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1381 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1382 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1383 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1384 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1385 // result is a boolean
1386 __ cbz(k_RInfo, *failure_target);
1387 // successful cast, fall through to profile or jump
1388 }
1389 }
1390 if (should_profile) {
1391 Register mdo = klass_RInfo, recv = k_RInfo;
1392 __ bind(profile_cast_success);
1393 __ mov_metadata(mdo, md->constant_encoding());
1394 __ load_klass(recv, obj);
1395 Label update_done;
1396 type_profile_helper(mdo, md, data, recv, success);
1397 __ b(*success);
1398
1399 __ bind(profile_cast_failure);
1400 __ mov_metadata(mdo, md->constant_encoding());
1401 Address counter_addr
1402 = __ form_address(rscratch2, mdo,
1403 md->byte_offset_of_slot(data, CounterData::count_offset()),
1404 0);
1405 __ ldr(rscratch1, counter_addr);
1406 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1407 __ str(rscratch1, counter_addr);
1408 __ b(*failure);
1409 }
1410 __ b(*success);
1411 }
1412
1413
emit_opTypeCheck(LIR_OpTypeCheck * op)1414 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1415 const bool should_profile = op->should_profile();
1416
1417 LIR_Code code = op->code();
1418 if (code == lir_store_check) {
1419 Register value = op->object()->as_register();
1420 Register array = op->array()->as_register();
1421 Register k_RInfo = op->tmp1()->as_register();
1422 Register klass_RInfo = op->tmp2()->as_register();
1423 Register Rtmp1 = op->tmp3()->as_register();
1424
1425 CodeStub* stub = op->stub();
1426
1427 // check if it needs to be profiled
1428 ciMethodData* md;
1429 ciProfileData* data;
1430
1431 if (should_profile) {
1432 ciMethod* method = op->profiled_method();
1433 assert(method != NULL, "Should have method");
1434 int bci = op->profiled_bci();
1435 md = method->method_data_or_null();
1436 assert(md != NULL, "Sanity");
1437 data = md->bci_to_data(bci);
1438 assert(data != NULL, "need data for type check");
1439 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1440 }
1441 Label profile_cast_success, profile_cast_failure, done;
1442 Label *success_target = should_profile ? &profile_cast_success : &done;
1443 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1444
1445 if (should_profile) {
1446 Label not_null;
1447 __ cbnz(value, not_null);
1448 // Object is null; update MDO and exit
1449 Register mdo = klass_RInfo;
1450 __ mov_metadata(mdo, md->constant_encoding());
1451 Address data_addr
1452 = __ form_address(rscratch2, mdo,
1453 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1454 0);
1455 __ ldrb(rscratch1, data_addr);
1456 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1457 __ strb(rscratch1, data_addr);
1458 __ b(done);
1459 __ bind(not_null);
1460 } else {
1461 __ cbz(value, done);
1462 }
1463
1464 add_debug_info_for_null_check_here(op->info_for_exception());
1465 __ load_klass(k_RInfo, array);
1466 __ load_klass(klass_RInfo, value);
1467
1468 // get instance klass (it's already uncompressed)
1469 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1470 // perform the fast part of the checking logic
1471 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1472 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1473 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1474 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1475 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1476 // result is a boolean
1477 __ cbzw(k_RInfo, *failure_target);
1478 // fall through to the success case
1479
1480 if (should_profile) {
1481 Register mdo = klass_RInfo, recv = k_RInfo;
1482 __ bind(profile_cast_success);
1483 __ mov_metadata(mdo, md->constant_encoding());
1484 __ load_klass(recv, value);
1485 Label update_done;
1486 type_profile_helper(mdo, md, data, recv, &done);
1487 __ b(done);
1488
1489 __ bind(profile_cast_failure);
1490 __ mov_metadata(mdo, md->constant_encoding());
1491 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1492 __ lea(rscratch2, counter_addr);
1493 __ ldr(rscratch1, Address(rscratch2));
1494 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1495 __ str(rscratch1, Address(rscratch2));
1496 __ b(*stub->entry());
1497 }
1498
1499 __ bind(done);
1500 } else if (code == lir_checkcast) {
1501 Register obj = op->object()->as_register();
1502 Register dst = op->result_opr()->as_register();
1503 Label success;
1504 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1505 __ bind(success);
1506 if (dst != obj) {
1507 __ mov(dst, obj);
1508 }
1509 } else if (code == lir_instanceof) {
1510 Register obj = op->object()->as_register();
1511 Register dst = op->result_opr()->as_register();
1512 Label success, failure, done;
1513 emit_typecheck_helper(op, &success, &failure, &failure);
1514 __ bind(failure);
1515 __ mov(dst, zr);
1516 __ b(done);
1517 __ bind(success);
1518 __ mov(dst, 1);
1519 __ bind(done);
1520 } else {
1521 ShouldNotReachHere();
1522 }
1523 }
1524
casw(Register addr,Register newval,Register cmpval)1525 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1526 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1527 __ cset(rscratch1, Assembler::NE);
1528 __ membar(__ AnyAny);
1529 }
1530
casl(Register addr,Register newval,Register cmpval)1531 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1532 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1533 __ cset(rscratch1, Assembler::NE);
1534 __ membar(__ AnyAny);
1535 }
1536
1537
emit_compare_and_swap(LIR_OpCompareAndSwap * op)1538 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1539 assert(VM_Version::supports_cx8(), "wrong machine");
1540 Register addr;
1541 if (op->addr()->is_register()) {
1542 addr = as_reg(op->addr());
1543 } else {
1544 assert(op->addr()->is_address(), "what else?");
1545 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1546 assert(addr_ptr->disp() == 0, "need 0 disp");
1547 assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1548 addr = as_reg(addr_ptr->base());
1549 }
1550 Register newval = as_reg(op->new_value());
1551 Register cmpval = as_reg(op->cmp_value());
1552
1553 if (op->code() == lir_cas_obj) {
1554 if (UseCompressedOops) {
1555 Register t1 = op->tmp1()->as_register();
1556 assert(op->tmp1()->is_valid(), "must be");
1557 __ encode_heap_oop(t1, cmpval);
1558 cmpval = t1;
1559 __ encode_heap_oop(rscratch2, newval);
1560 newval = rscratch2;
1561 casw(addr, newval, cmpval);
1562 } else {
1563 casl(addr, newval, cmpval);
1564 }
1565 } else if (op->code() == lir_cas_int) {
1566 casw(addr, newval, cmpval);
1567 } else {
1568 casl(addr, newval, cmpval);
1569 }
1570 }
1571
1572
cmove(LIR_Condition condition,LIR_Opr opr1,LIR_Opr opr2,LIR_Opr result,BasicType type)1573 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1574
1575 Assembler::Condition acond, ncond;
1576 switch (condition) {
1577 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1578 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1579 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1580 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1581 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1582 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1583 case lir_cond_belowEqual:
1584 case lir_cond_aboveEqual:
1585 default: ShouldNotReachHere();
1586 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1587 }
1588
1589 assert(result->is_single_cpu() || result->is_double_cpu(),
1590 "expect single register for result");
1591 if (opr1->is_constant() && opr2->is_constant()
1592 && opr1->type() == T_INT && opr2->type() == T_INT) {
1593 jint val1 = opr1->as_jint();
1594 jint val2 = opr2->as_jint();
1595 if (val1 == 0 && val2 == 1) {
1596 __ cset(result->as_register(), ncond);
1597 return;
1598 } else if (val1 == 1 && val2 == 0) {
1599 __ cset(result->as_register(), acond);
1600 return;
1601 }
1602 }
1603
1604 if (opr1->is_constant() && opr2->is_constant()
1605 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1606 jlong val1 = opr1->as_jlong();
1607 jlong val2 = opr2->as_jlong();
1608 if (val1 == 0 && val2 == 1) {
1609 __ cset(result->as_register_lo(), ncond);
1610 return;
1611 } else if (val1 == 1 && val2 == 0) {
1612 __ cset(result->as_register_lo(), acond);
1613 return;
1614 }
1615 }
1616
1617 if (opr1->is_stack()) {
1618 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1619 opr1 = FrameMap::rscratch1_opr;
1620 } else if (opr1->is_constant()) {
1621 LIR_Opr tmp
1622 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1623 const2reg(opr1, tmp, lir_patch_none, NULL);
1624 opr1 = tmp;
1625 }
1626
1627 if (opr2->is_stack()) {
1628 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1629 opr2 = FrameMap::rscratch2_opr;
1630 } else if (opr2->is_constant()) {
1631 LIR_Opr tmp
1632 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1633 const2reg(opr2, tmp, lir_patch_none, NULL);
1634 opr2 = tmp;
1635 }
1636
1637 if (result->type() == T_LONG)
1638 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1639 else
1640 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1641 }
1642
arith_op(LIR_Code code,LIR_Opr left,LIR_Opr right,LIR_Opr dest,CodeEmitInfo * info,bool pop_fpu_stack)1643 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1644 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1645
1646 if (left->is_single_cpu()) {
1647 Register lreg = left->as_register();
1648 Register dreg = as_reg(dest);
1649
1650 if (right->is_single_cpu()) {
1651 // cpu register - cpu register
1652
1653 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1654 "should be");
1655 Register rreg = right->as_register();
1656 switch (code) {
1657 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1658 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1659 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1660 default: ShouldNotReachHere();
1661 }
1662
1663 } else if (right->is_double_cpu()) {
1664 Register rreg = right->as_register_lo();
1665 // single_cpu + double_cpu: can happen with obj+long
1666 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1667 switch (code) {
1668 case lir_add: __ add(dreg, lreg, rreg); break;
1669 case lir_sub: __ sub(dreg, lreg, rreg); break;
1670 default: ShouldNotReachHere();
1671 }
1672 } else if (right->is_constant()) {
1673 // cpu register - constant
1674 jlong c;
1675
1676 // FIXME. This is fugly: we really need to factor all this logic.
1677 switch(right->type()) {
1678 case T_LONG:
1679 c = right->as_constant_ptr()->as_jlong();
1680 break;
1681 case T_INT:
1682 case T_ADDRESS:
1683 c = right->as_constant_ptr()->as_jint();
1684 break;
1685 default:
1686 ShouldNotReachHere();
1687 c = 0; // unreachable
1688 break;
1689 }
1690
1691 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1692 if (c == 0 && dreg == lreg) {
1693 COMMENT("effective nop elided");
1694 return;
1695 }
1696 switch(left->type()) {
1697 case T_INT:
1698 switch (code) {
1699 case lir_add: __ addw(dreg, lreg, c); break;
1700 case lir_sub: __ subw(dreg, lreg, c); break;
1701 default: ShouldNotReachHere();
1702 }
1703 break;
1704 case T_OBJECT:
1705 case T_ADDRESS:
1706 switch (code) {
1707 case lir_add: __ add(dreg, lreg, c); break;
1708 case lir_sub: __ sub(dreg, lreg, c); break;
1709 default: ShouldNotReachHere();
1710 }
1711 break;
1712 default:
1713 ShouldNotReachHere();
1714 }
1715 } else {
1716 ShouldNotReachHere();
1717 }
1718
1719 } else if (left->is_double_cpu()) {
1720 Register lreg_lo = left->as_register_lo();
1721
1722 if (right->is_double_cpu()) {
1723 // cpu register - cpu register
1724 Register rreg_lo = right->as_register_lo();
1725 switch (code) {
1726 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1727 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1728 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1729 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1730 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1731 default:
1732 ShouldNotReachHere();
1733 }
1734
1735 } else if (right->is_constant()) {
1736 jlong c = right->as_constant_ptr()->as_jlong();
1737 Register dreg = as_reg(dest);
1738 switch (code) {
1739 case lir_add:
1740 case lir_sub:
1741 if (c == 0 && dreg == lreg_lo) {
1742 COMMENT("effective nop elided");
1743 return;
1744 }
1745 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1746 break;
1747 case lir_div:
1748 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1749 if (c == 1) {
1750 // move lreg_lo to dreg if divisor is 1
1751 __ mov(dreg, lreg_lo);
1752 } else {
1753 unsigned int shift = exact_log2_long(c);
1754 // use rscratch1 as intermediate result register
1755 __ asr(rscratch1, lreg_lo, 63);
1756 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1757 __ asr(dreg, rscratch1, shift);
1758 }
1759 break;
1760 case lir_rem:
1761 assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1762 if (c == 1) {
1763 // move 0 to dreg if divisor is 1
1764 __ mov(dreg, zr);
1765 } else {
1766 // use rscratch1 as intermediate result register
1767 __ negs(rscratch1, lreg_lo);
1768 __ andr(dreg, lreg_lo, c - 1);
1769 __ andr(rscratch1, rscratch1, c - 1);
1770 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1771 }
1772 break;
1773 default:
1774 ShouldNotReachHere();
1775 }
1776 } else {
1777 ShouldNotReachHere();
1778 }
1779 } else if (left->is_single_fpu()) {
1780 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1781 switch (code) {
1782 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1783 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1784 case lir_mul_strictfp: // fall through
1785 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1786 case lir_div_strictfp: // fall through
1787 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1788 default:
1789 ShouldNotReachHere();
1790 }
1791 } else if (left->is_double_fpu()) {
1792 if (right->is_double_fpu()) {
1793 // fpu register - fpu register
1794 switch (code) {
1795 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1796 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1797 case lir_mul_strictfp: // fall through
1798 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1799 case lir_div_strictfp: // fall through
1800 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1801 default:
1802 ShouldNotReachHere();
1803 }
1804 } else {
1805 if (right->is_constant()) {
1806 ShouldNotReachHere();
1807 }
1808 ShouldNotReachHere();
1809 }
1810 } else if (left->is_single_stack() || left->is_address()) {
1811 assert(left == dest, "left and dest must be equal");
1812 ShouldNotReachHere();
1813 } else {
1814 ShouldNotReachHere();
1815 }
1816 }
1817
arith_fpu_implementation(LIR_Code code,int left_index,int right_index,int dest_index,bool pop_fpu_stack)1818 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1819
1820
intrinsic_op(LIR_Code code,LIR_Opr value,LIR_Opr unused,LIR_Opr dest,LIR_Op * op)1821 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1822 switch(code) {
1823 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1824 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1825 default : ShouldNotReachHere();
1826 }
1827 }
1828
logic_op(LIR_Code code,LIR_Opr left,LIR_Opr right,LIR_Opr dst)1829 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1830
1831 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1832 Register Rleft = left->is_single_cpu() ? left->as_register() :
1833 left->as_register_lo();
1834 if (dst->is_single_cpu()) {
1835 Register Rdst = dst->as_register();
1836 if (right->is_constant()) {
1837 switch (code) {
1838 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1839 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1840 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1841 default: ShouldNotReachHere(); break;
1842 }
1843 } else {
1844 Register Rright = right->is_single_cpu() ? right->as_register() :
1845 right->as_register_lo();
1846 switch (code) {
1847 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1848 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1849 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1850 default: ShouldNotReachHere(); break;
1851 }
1852 }
1853 } else {
1854 Register Rdst = dst->as_register_lo();
1855 if (right->is_constant()) {
1856 switch (code) {
1857 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1858 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1859 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1860 default: ShouldNotReachHere(); break;
1861 }
1862 } else {
1863 Register Rright = right->is_single_cpu() ? right->as_register() :
1864 right->as_register_lo();
1865 switch (code) {
1866 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1867 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1868 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1869 default: ShouldNotReachHere(); break;
1870 }
1871 }
1872 }
1873 }
1874
1875
1876
arithmetic_idiv(LIR_Code code,LIR_Opr left,LIR_Opr right,LIR_Opr illegal,LIR_Opr result,CodeEmitInfo * info)1877 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1878
1879 // opcode check
1880 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1881 bool is_irem = (code == lir_irem);
1882
1883 // operand check
1884 assert(left->is_single_cpu(), "left must be register");
1885 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1886 assert(result->is_single_cpu(), "result must be register");
1887 Register lreg = left->as_register();
1888 Register dreg = result->as_register();
1889
1890 // power-of-2 constant check and codegen
1891 if (right->is_constant()) {
1892 int c = right->as_constant_ptr()->as_jint();
1893 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1894 if (is_irem) {
1895 if (c == 1) {
1896 // move 0 to dreg if divisor is 1
1897 __ movw(dreg, zr);
1898 } else {
1899 // use rscratch1 as intermediate result register
1900 __ negsw(rscratch1, lreg);
1901 __ andw(dreg, lreg, c - 1);
1902 __ andw(rscratch1, rscratch1, c - 1);
1903 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1904 }
1905 } else {
1906 if (c == 1) {
1907 // move lreg to dreg if divisor is 1
1908 __ movw(dreg, lreg);
1909 } else {
1910 unsigned int shift = exact_log2(c);
1911 // use rscratch1 as intermediate result register
1912 __ asrw(rscratch1, lreg, 31);
1913 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1914 __ asrw(dreg, rscratch1, shift);
1915 }
1916 }
1917 } else {
1918 Register rreg = right->as_register();
1919 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1920 }
1921 }
1922
1923
comp_op(LIR_Condition condition,LIR_Opr opr1,LIR_Opr opr2,LIR_Op2 * op)1924 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1925 if (opr1->is_constant() && opr2->is_single_cpu()) {
1926 // tableswitch
1927 Register reg = as_reg(opr2);
1928 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1929 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1930 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1931 Register reg1 = as_reg(opr1);
1932 if (opr2->is_single_cpu()) {
1933 // cpu register - cpu register
1934 Register reg2 = opr2->as_register();
1935 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1936 __ cmpoop(reg1, reg2);
1937 } else {
1938 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1939 __ cmpw(reg1, reg2);
1940 }
1941 return;
1942 }
1943 if (opr2->is_double_cpu()) {
1944 // cpu register - cpu register
1945 Register reg2 = opr2->as_register_lo();
1946 __ cmp(reg1, reg2);
1947 return;
1948 }
1949
1950 if (opr2->is_constant()) {
1951 bool is_32bit = false; // width of register operand
1952 jlong imm;
1953
1954 switch(opr2->type()) {
1955 case T_INT:
1956 imm = opr2->as_constant_ptr()->as_jint();
1957 is_32bit = true;
1958 break;
1959 case T_LONG:
1960 imm = opr2->as_constant_ptr()->as_jlong();
1961 break;
1962 case T_ADDRESS:
1963 imm = opr2->as_constant_ptr()->as_jint();
1964 break;
1965 case T_OBJECT:
1966 case T_ARRAY:
1967 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1968 __ cmpoop(reg1, rscratch1);
1969 return;
1970 default:
1971 ShouldNotReachHere();
1972 imm = 0; // unreachable
1973 break;
1974 }
1975
1976 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1977 if (is_32bit)
1978 __ cmpw(reg1, imm);
1979 else
1980 __ subs(zr, reg1, imm);
1981 return;
1982 } else {
1983 __ mov(rscratch1, imm);
1984 if (is_32bit)
1985 __ cmpw(reg1, rscratch1);
1986 else
1987 __ cmp(reg1, rscratch1);
1988 return;
1989 }
1990 } else
1991 ShouldNotReachHere();
1992 } else if (opr1->is_single_fpu()) {
1993 FloatRegister reg1 = opr1->as_float_reg();
1994 assert(opr2->is_single_fpu(), "expect single float register");
1995 FloatRegister reg2 = opr2->as_float_reg();
1996 __ fcmps(reg1, reg2);
1997 } else if (opr1->is_double_fpu()) {
1998 FloatRegister reg1 = opr1->as_double_reg();
1999 assert(opr2->is_double_fpu(), "expect double float register");
2000 FloatRegister reg2 = opr2->as_double_reg();
2001 __ fcmpd(reg1, reg2);
2002 } else {
2003 ShouldNotReachHere();
2004 }
2005 }
2006
comp_fl2i(LIR_Code code,LIR_Opr left,LIR_Opr right,LIR_Opr dst,LIR_Op2 * op)2007 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2008 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2009 bool is_unordered_less = (code == lir_ucmp_fd2i);
2010 if (left->is_single_fpu()) {
2011 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2012 } else if (left->is_double_fpu()) {
2013 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2014 } else {
2015 ShouldNotReachHere();
2016 }
2017 } else if (code == lir_cmp_l2i) {
2018 Label done;
2019 __ cmp(left->as_register_lo(), right->as_register_lo());
2020 __ mov(dst->as_register(), (u_int64_t)-1L);
2021 __ br(Assembler::LT, done);
2022 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2023 __ bind(done);
2024 } else {
2025 ShouldNotReachHere();
2026 }
2027 }
2028
2029
align_call(LIR_Code code)2030 void LIR_Assembler::align_call(LIR_Code code) { }
2031
2032
call(LIR_OpJavaCall * op,relocInfo::relocType rtype)2033 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2034 address call = __ trampoline_call(Address(op->addr(), rtype));
2035 if (call == NULL) {
2036 bailout("trampoline stub overflow");
2037 return;
2038 }
2039 add_call_info(code_offset(), op->info());
2040 }
2041
2042
ic_call(LIR_OpJavaCall * op)2043 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2044 address call = __ ic_call(op->addr());
2045 if (call == NULL) {
2046 bailout("trampoline stub overflow");
2047 return;
2048 }
2049 add_call_info(code_offset(), op->info());
2050 }
2051
2052
2053 /* Currently, vtable-dispatch is only enabled for sparc platforms */
vtable_call(LIR_OpJavaCall * op)2054 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2055 ShouldNotReachHere();
2056 }
2057
2058
emit_static_call_stub()2059 void LIR_Assembler::emit_static_call_stub() {
2060 address call_pc = __ pc();
2061 address stub = __ start_a_stub(call_stub_size());
2062 if (stub == NULL) {
2063 bailout("static call stub overflow");
2064 return;
2065 }
2066
2067 int start = __ offset();
2068
2069 __ relocate(static_stub_Relocation::spec(call_pc));
2070 __ mov_metadata(rmethod, (Metadata*)NULL);
2071 __ movptr(rscratch1, 0);
2072 __ br(rscratch1);
2073
2074 assert(__ offset() - start <= call_stub_size(), "stub too big");
2075 __ end_a_stub();
2076 }
2077
2078
throw_op(LIR_Opr exceptionPC,LIR_Opr exceptionOop,CodeEmitInfo * info)2079 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2080 assert(exceptionOop->as_register() == r0, "must match");
2081 assert(exceptionPC->as_register() == r3, "must match");
2082
2083 // exception object is not added to oop map by LinearScan
2084 // (LinearScan assumes that no oops are in fixed registers)
2085 info->add_register_oop(exceptionOop);
2086 Runtime1::StubID unwind_id;
2087
2088 // get current pc information
2089 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2090 int pc_for_athrow_offset = __ offset();
2091 InternalAddress pc_for_athrow(__ pc());
2092 __ adr(exceptionPC->as_register(), pc_for_athrow);
2093 add_call_info(pc_for_athrow_offset, info); // for exception handler
2094
2095 __ verify_not_null_oop(r0);
2096 // search an exception handler (r0: exception oop, r3: throwing pc)
2097 if (compilation()->has_fpu_code()) {
2098 unwind_id = Runtime1::handle_exception_id;
2099 } else {
2100 unwind_id = Runtime1::handle_exception_nofpu_id;
2101 }
2102 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2103
2104 // FIXME: enough room for two byte trap ????
2105 __ nop();
2106 }
2107
2108
unwind_op(LIR_Opr exceptionOop)2109 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2110 assert(exceptionOop->as_register() == r0, "must match");
2111
2112 __ b(_unwind_handler_entry);
2113 }
2114
2115
shift_op(LIR_Code code,LIR_Opr left,LIR_Opr count,LIR_Opr dest,LIR_Opr tmp)2116 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2117 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2118 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2119
2120 switch (left->type()) {
2121 case T_INT: {
2122 switch (code) {
2123 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2124 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2125 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2126 default:
2127 ShouldNotReachHere();
2128 break;
2129 }
2130 break;
2131 case T_LONG:
2132 case T_ADDRESS:
2133 case T_OBJECT:
2134 switch (code) {
2135 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2136 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2137 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2138 default:
2139 ShouldNotReachHere();
2140 break;
2141 }
2142 break;
2143 default:
2144 ShouldNotReachHere();
2145 break;
2146 }
2147 }
2148 }
2149
2150
shift_op(LIR_Code code,LIR_Opr left,jint count,LIR_Opr dest)2151 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2152 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2153 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2154
2155 switch (left->type()) {
2156 case T_INT: {
2157 switch (code) {
2158 case lir_shl: __ lslw (dreg, lreg, count); break;
2159 case lir_shr: __ asrw (dreg, lreg, count); break;
2160 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2161 default:
2162 ShouldNotReachHere();
2163 break;
2164 }
2165 break;
2166 case T_LONG:
2167 case T_ADDRESS:
2168 case T_OBJECT:
2169 switch (code) {
2170 case lir_shl: __ lsl (dreg, lreg, count); break;
2171 case lir_shr: __ asr (dreg, lreg, count); break;
2172 case lir_ushr: __ lsr (dreg, lreg, count); break;
2173 default:
2174 ShouldNotReachHere();
2175 break;
2176 }
2177 break;
2178 default:
2179 ShouldNotReachHere();
2180 break;
2181 }
2182 }
2183 }
2184
2185
store_parameter(Register r,int offset_from_rsp_in_words)2186 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2187 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2188 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2189 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2190 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2191 }
2192
2193
store_parameter(jint c,int offset_from_rsp_in_words)2194 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2195 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2196 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2197 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2198 __ mov (rscratch1, c);
2199 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2200 }
2201
2202
store_parameter(jobject o,int offset_from_rsp_in_words)2203 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2204 ShouldNotReachHere();
2205 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2206 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2207 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2208 __ lea(rscratch1, __ constant_oop_address(o));
2209 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2210 }
2211
2212
2213 // This code replaces a call to arraycopy; no exception may
2214 // be thrown in this code, they must be thrown in the System.arraycopy
2215 // activation frame; we could save some checks if this would not be the case
emit_arraycopy(LIR_OpArrayCopy * op)2216 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2217 ciArrayKlass* default_type = op->expected_type();
2218 Register src = op->src()->as_register();
2219 Register dst = op->dst()->as_register();
2220 Register src_pos = op->src_pos()->as_register();
2221 Register dst_pos = op->dst_pos()->as_register();
2222 Register length = op->length()->as_register();
2223 Register tmp = op->tmp()->as_register();
2224
2225 __ resolve(ACCESS_READ, src);
2226 __ resolve(ACCESS_WRITE, dst);
2227
2228 CodeStub* stub = op->stub();
2229 int flags = op->flags();
2230 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2231 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2232
2233 // if we don't know anything, just go through the generic arraycopy
2234 if (default_type == NULL // || basic_type == T_OBJECT
2235 ) {
2236 Label done;
2237 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2238
2239 // Save the arguments in case the generic arraycopy fails and we
2240 // have to fall back to the JNI stub
2241 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2242 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2243 __ str(src, Address(sp, 4*BytesPerWord));
2244
2245 address copyfunc_addr = StubRoutines::generic_arraycopy();
2246 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2247
2248 // The arguments are in java calling convention so we shift them
2249 // to C convention
2250 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2251 __ mov(c_rarg0, j_rarg0);
2252 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2253 __ mov(c_rarg1, j_rarg1);
2254 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2255 __ mov(c_rarg2, j_rarg2);
2256 assert_different_registers(c_rarg3, j_rarg4);
2257 __ mov(c_rarg3, j_rarg3);
2258 __ mov(c_rarg4, j_rarg4);
2259 #ifndef PRODUCT
2260 if (PrintC1Statistics) {
2261 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2262 }
2263 #endif
2264 __ far_call(RuntimeAddress(copyfunc_addr));
2265
2266 __ cbz(r0, *stub->continuation());
2267
2268 // Reload values from the stack so they are where the stub
2269 // expects them.
2270 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2271 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2272 __ ldr(src, Address(sp, 4*BytesPerWord));
2273
2274 // r0 is -1^K where K == partial copied count
2275 __ eonw(rscratch1, r0, 0);
2276 // adjust length down and src/end pos up by partial copied count
2277 __ subw(length, length, rscratch1);
2278 __ addw(src_pos, src_pos, rscratch1);
2279 __ addw(dst_pos, dst_pos, rscratch1);
2280 __ b(*stub->entry());
2281
2282 __ bind(*stub->continuation());
2283 return;
2284 }
2285
2286 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2287
2288 int elem_size = type2aelembytes(basic_type);
2289 int shift_amount;
2290 int scale = exact_log2(elem_size);
2291
2292 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2293 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2294 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2295 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2296
2297 // test for NULL
2298 if (flags & LIR_OpArrayCopy::src_null_check) {
2299 __ cbz(src, *stub->entry());
2300 }
2301 if (flags & LIR_OpArrayCopy::dst_null_check) {
2302 __ cbz(dst, *stub->entry());
2303 }
2304
2305 // If the compiler was not able to prove that exact type of the source or the destination
2306 // of the arraycopy is an array type, check at runtime if the source or the destination is
2307 // an instance type.
2308 if (flags & LIR_OpArrayCopy::type_check) {
2309 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2310 __ load_klass(tmp, dst);
2311 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2312 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2313 __ br(Assembler::GE, *stub->entry());
2314 }
2315
2316 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2317 __ load_klass(tmp, src);
2318 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2319 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2320 __ br(Assembler::GE, *stub->entry());
2321 }
2322 }
2323
2324 // check if negative
2325 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2326 __ cmpw(src_pos, 0);
2327 __ br(Assembler::LT, *stub->entry());
2328 }
2329 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2330 __ cmpw(dst_pos, 0);
2331 __ br(Assembler::LT, *stub->entry());
2332 }
2333
2334 if (flags & LIR_OpArrayCopy::length_positive_check) {
2335 __ cmpw(length, 0);
2336 __ br(Assembler::LT, *stub->entry());
2337 }
2338
2339 if (flags & LIR_OpArrayCopy::src_range_check) {
2340 __ addw(tmp, src_pos, length);
2341 __ ldrw(rscratch1, src_length_addr);
2342 __ cmpw(tmp, rscratch1);
2343 __ br(Assembler::HI, *stub->entry());
2344 }
2345 if (flags & LIR_OpArrayCopy::dst_range_check) {
2346 __ addw(tmp, dst_pos, length);
2347 __ ldrw(rscratch1, dst_length_addr);
2348 __ cmpw(tmp, rscratch1);
2349 __ br(Assembler::HI, *stub->entry());
2350 }
2351
2352 if (flags & LIR_OpArrayCopy::type_check) {
2353 // We don't know the array types are compatible
2354 if (basic_type != T_OBJECT) {
2355 // Simple test for basic type arrays
2356 if (UseCompressedClassPointers) {
2357 __ ldrw(tmp, src_klass_addr);
2358 __ ldrw(rscratch1, dst_klass_addr);
2359 __ cmpw(tmp, rscratch1);
2360 } else {
2361 __ ldr(tmp, src_klass_addr);
2362 __ ldr(rscratch1, dst_klass_addr);
2363 __ cmp(tmp, rscratch1);
2364 }
2365 __ br(Assembler::NE, *stub->entry());
2366 } else {
2367 // For object arrays, if src is a sub class of dst then we can
2368 // safely do the copy.
2369 Label cont, slow;
2370
2371 #define PUSH(r1, r2) \
2372 stp(r1, r2, __ pre(sp, -2 * wordSize));
2373
2374 #define POP(r1, r2) \
2375 ldp(r1, r2, __ post(sp, 2 * wordSize));
2376
2377 __ PUSH(src, dst);
2378
2379 __ load_klass(src, src);
2380 __ load_klass(dst, dst);
2381
2382 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2383
2384 __ PUSH(src, dst);
2385 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2386 __ POP(src, dst);
2387
2388 __ cbnz(src, cont);
2389
2390 __ bind(slow);
2391 __ POP(src, dst);
2392
2393 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2394 if (copyfunc_addr != NULL) { // use stub if available
2395 // src is not a sub class of dst so we have to do a
2396 // per-element check.
2397
2398 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2399 if ((flags & mask) != mask) {
2400 // Check that at least both of them object arrays.
2401 assert(flags & mask, "one of the two should be known to be an object array");
2402
2403 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2404 __ load_klass(tmp, src);
2405 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2406 __ load_klass(tmp, dst);
2407 }
2408 int lh_offset = in_bytes(Klass::layout_helper_offset());
2409 Address klass_lh_addr(tmp, lh_offset);
2410 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2411 __ ldrw(rscratch1, klass_lh_addr);
2412 __ mov(rscratch2, objArray_lh);
2413 __ eorw(rscratch1, rscratch1, rscratch2);
2414 __ cbnzw(rscratch1, *stub->entry());
2415 }
2416
2417 // Spill because stubs can use any register they like and it's
2418 // easier to restore just those that we care about.
2419 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2420 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2421 __ str(src, Address(sp, 4*BytesPerWord));
2422
2423 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2424 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2425 assert_different_registers(c_rarg0, dst, dst_pos, length);
2426 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2427 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2428 assert_different_registers(c_rarg1, dst, length);
2429 __ uxtw(c_rarg2, length);
2430 assert_different_registers(c_rarg2, dst);
2431
2432 __ load_klass(c_rarg4, dst);
2433 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2434 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2435 __ far_call(RuntimeAddress(copyfunc_addr));
2436
2437 #ifndef PRODUCT
2438 if (PrintC1Statistics) {
2439 Label failed;
2440 __ cbnz(r0, failed);
2441 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2442 __ bind(failed);
2443 }
2444 #endif
2445
2446 __ cbz(r0, *stub->continuation());
2447
2448 #ifndef PRODUCT
2449 if (PrintC1Statistics) {
2450 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2451 }
2452 #endif
2453 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2454
2455 // Restore previously spilled arguments
2456 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2457 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2458 __ ldr(src, Address(sp, 4*BytesPerWord));
2459
2460 // return value is -1^K where K is partial copied count
2461 __ eonw(rscratch1, r0, zr);
2462 // adjust length down and src/end pos up by partial copied count
2463 __ subw(length, length, rscratch1);
2464 __ addw(src_pos, src_pos, rscratch1);
2465 __ addw(dst_pos, dst_pos, rscratch1);
2466 }
2467
2468 __ b(*stub->entry());
2469
2470 __ bind(cont);
2471 __ POP(src, dst);
2472 }
2473 }
2474
2475 #ifdef ASSERT
2476 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2477 // Sanity check the known type with the incoming class. For the
2478 // primitive case the types must match exactly with src.klass and
2479 // dst.klass each exactly matching the default type. For the
2480 // object array case, if no type check is needed then either the
2481 // dst type is exactly the expected type and the src type is a
2482 // subtype which we can't check or src is the same array as dst
2483 // but not necessarily exactly of type default_type.
2484 Label known_ok, halt;
2485 __ mov_metadata(tmp, default_type->constant_encoding());
2486 if (UseCompressedClassPointers) {
2487 __ encode_klass_not_null(tmp);
2488 }
2489
2490 if (basic_type != T_OBJECT) {
2491
2492 if (UseCompressedClassPointers) {
2493 __ ldrw(rscratch1, dst_klass_addr);
2494 __ cmpw(tmp, rscratch1);
2495 } else {
2496 __ ldr(rscratch1, dst_klass_addr);
2497 __ cmp(tmp, rscratch1);
2498 }
2499 __ br(Assembler::NE, halt);
2500 if (UseCompressedClassPointers) {
2501 __ ldrw(rscratch1, src_klass_addr);
2502 __ cmpw(tmp, rscratch1);
2503 } else {
2504 __ ldr(rscratch1, src_klass_addr);
2505 __ cmp(tmp, rscratch1);
2506 }
2507 __ br(Assembler::EQ, known_ok);
2508 } else {
2509 if (UseCompressedClassPointers) {
2510 __ ldrw(rscratch1, dst_klass_addr);
2511 __ cmpw(tmp, rscratch1);
2512 } else {
2513 __ ldr(rscratch1, dst_klass_addr);
2514 __ cmp(tmp, rscratch1);
2515 }
2516 __ br(Assembler::EQ, known_ok);
2517 __ cmp(src, dst);
2518 __ br(Assembler::EQ, known_ok);
2519 }
2520 __ bind(halt);
2521 __ stop("incorrect type information in arraycopy");
2522 __ bind(known_ok);
2523 }
2524 #endif
2525
2526 #ifndef PRODUCT
2527 if (PrintC1Statistics) {
2528 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2529 }
2530 #endif
2531
2532 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2533 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2534 assert_different_registers(c_rarg0, dst, dst_pos, length);
2535 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2536 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2537 assert_different_registers(c_rarg1, dst, length);
2538 __ uxtw(c_rarg2, length);
2539 assert_different_registers(c_rarg2, dst);
2540
2541 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2542 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2543 const char *name;
2544 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2545
2546 CodeBlob *cb = CodeCache::find_blob(entry);
2547 if (cb) {
2548 __ far_call(RuntimeAddress(entry));
2549 } else {
2550 __ call_VM_leaf(entry, 3);
2551 }
2552
2553 __ bind(*stub->continuation());
2554 }
2555
2556
2557
2558
emit_lock(LIR_OpLock * op)2559 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2560 Register obj = op->obj_opr()->as_register(); // may not be an oop
2561 Register hdr = op->hdr_opr()->as_register();
2562 Register lock = op->lock_opr()->as_register();
2563 if (!UseFastLocking) {
2564 __ b(*op->stub()->entry());
2565 } else if (op->code() == lir_lock) {
2566 Register scratch = noreg;
2567 if (UseBiasedLocking) {
2568 scratch = op->scratch_opr()->as_register();
2569 }
2570 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2571 __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
2572 // add debug info for NullPointerException only if one is possible
2573 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2574 if (op->info() != NULL) {
2575 add_debug_info_for_null_check(null_check_offset, op->info());
2576 }
2577 // done
2578 } else if (op->code() == lir_unlock) {
2579 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2580 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2581 } else {
2582 Unimplemented();
2583 }
2584 __ bind(*op->stub()->continuation());
2585 }
2586
2587
emit_profile_call(LIR_OpProfileCall * op)2588 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2589 ciMethod* method = op->profiled_method();
2590 int bci = op->profiled_bci();
2591 ciMethod* callee = op->profiled_callee();
2592
2593 // Update counter for all call types
2594 ciMethodData* md = method->method_data_or_null();
2595 assert(md != NULL, "Sanity");
2596 ciProfileData* data = md->bci_to_data(bci);
2597 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2598 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2599 Register mdo = op->mdo()->as_register();
2600 __ mov_metadata(mdo, md->constant_encoding());
2601 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2602 // Perform additional virtual call profiling for invokevirtual and
2603 // invokeinterface bytecodes
2604 if (op->should_profile_receiver_type()) {
2605 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2606 Register recv = op->recv()->as_register();
2607 assert_different_registers(mdo, recv);
2608 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2609 ciKlass* known_klass = op->known_holder();
2610 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2611 // We know the type that will be seen at this call site; we can
2612 // statically update the MethodData* rather than needing to do
2613 // dynamic tests on the receiver type
2614
2615 // NOTE: we should probably put a lock around this search to
2616 // avoid collisions by concurrent compilations
2617 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2618 uint i;
2619 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2620 ciKlass* receiver = vc_data->receiver(i);
2621 if (known_klass->equals(receiver)) {
2622 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2623 __ addptr(data_addr, DataLayout::counter_increment);
2624 return;
2625 }
2626 }
2627
2628 // Receiver type not found in profile data; select an empty slot
2629
2630 // Note that this is less efficient than it should be because it
2631 // always does a write to the receiver part of the
2632 // VirtualCallData rather than just the first time
2633 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2634 ciKlass* receiver = vc_data->receiver(i);
2635 if (receiver == NULL) {
2636 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2637 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2638 __ lea(rscratch2, recv_addr);
2639 __ str(rscratch1, Address(rscratch2));
2640 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2641 __ addptr(data_addr, DataLayout::counter_increment);
2642 return;
2643 }
2644 }
2645 } else {
2646 __ load_klass(recv, recv);
2647 Label update_done;
2648 type_profile_helper(mdo, md, data, recv, &update_done);
2649 // Receiver did not match any saved receiver and there is no empty row for it.
2650 // Increment total counter to indicate polymorphic case.
2651 __ addptr(counter_addr, DataLayout::counter_increment);
2652
2653 __ bind(update_done);
2654 }
2655 } else {
2656 // Static call
2657 __ addptr(counter_addr, DataLayout::counter_increment);
2658 }
2659 }
2660
2661
emit_delay(LIR_OpDelay *)2662 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2663 Unimplemented();
2664 }
2665
2666
monitor_address(int monitor_no,LIR_Opr dst)2667 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2668 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2669 }
2670
emit_updatecrc32(LIR_OpUpdateCRC32 * op)2671 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2672 assert(op->crc()->is_single_cpu(), "crc must be register");
2673 assert(op->val()->is_single_cpu(), "byte value must be register");
2674 assert(op->result_opr()->is_single_cpu(), "result must be register");
2675 Register crc = op->crc()->as_register();
2676 Register val = op->val()->as_register();
2677 Register res = op->result_opr()->as_register();
2678
2679 assert_different_registers(val, crc, res);
2680 unsigned long offset;
2681 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2682 if (offset) __ add(res, res, offset);
2683
2684 __ mvnw(crc, crc); // ~crc
2685 __ update_byte_crc32(crc, val, res);
2686 __ mvnw(res, crc); // ~crc
2687 }
2688
emit_profile_type(LIR_OpProfileType * op)2689 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2690 COMMENT("emit_profile_type {");
2691 Register obj = op->obj()->as_register();
2692 Register tmp = op->tmp()->as_pointer_register();
2693 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2694 ciKlass* exact_klass = op->exact_klass();
2695 intptr_t current_klass = op->current_klass();
2696 bool not_null = op->not_null();
2697 bool no_conflict = op->no_conflict();
2698
2699 Label update, next, none;
2700
2701 bool do_null = !not_null;
2702 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2703 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2704
2705 assert(do_null || do_update, "why are we here?");
2706 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2707 assert(mdo_addr.base() != rscratch1, "wrong register");
2708
2709 __ verify_oop(obj);
2710
2711 if (tmp != obj) {
2712 __ mov(tmp, obj);
2713 }
2714 if (do_null) {
2715 __ cbnz(tmp, update);
2716 if (!TypeEntries::was_null_seen(current_klass)) {
2717 __ ldr(rscratch2, mdo_addr);
2718 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2719 __ str(rscratch2, mdo_addr);
2720 }
2721 if (do_update) {
2722 #ifndef ASSERT
2723 __ b(next);
2724 }
2725 #else
2726 __ b(next);
2727 }
2728 } else {
2729 __ cbnz(tmp, update);
2730 __ stop("unexpected null obj");
2731 #endif
2732 }
2733
2734 __ bind(update);
2735
2736 if (do_update) {
2737 #ifdef ASSERT
2738 if (exact_klass != NULL) {
2739 Label ok;
2740 __ load_klass(tmp, tmp);
2741 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2742 __ eor(rscratch1, tmp, rscratch1);
2743 __ cbz(rscratch1, ok);
2744 __ stop("exact klass and actual klass differ");
2745 __ bind(ok);
2746 }
2747 #endif
2748 if (!no_conflict) {
2749 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2750 if (exact_klass != NULL) {
2751 __ mov_metadata(tmp, exact_klass->constant_encoding());
2752 } else {
2753 __ load_klass(tmp, tmp);
2754 }
2755
2756 __ ldr(rscratch2, mdo_addr);
2757 __ eor(tmp, tmp, rscratch2);
2758 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2759 // klass seen before, nothing to do. The unknown bit may have been
2760 // set already but no need to check.
2761 __ cbz(rscratch1, next);
2762
2763 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2764
2765 if (TypeEntries::is_type_none(current_klass)) {
2766 __ cbz(rscratch2, none);
2767 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2768 __ br(Assembler::EQ, none);
2769 // There is a chance that the checks above (re-reading profiling
2770 // data from memory) fail if another thread has just set the
2771 // profiling to this obj's klass
2772 __ dmb(Assembler::ISHLD);
2773 __ ldr(rscratch2, mdo_addr);
2774 __ eor(tmp, tmp, rscratch2);
2775 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2776 __ cbz(rscratch1, next);
2777 }
2778 } else {
2779 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2780 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2781
2782 __ ldr(tmp, mdo_addr);
2783 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2784 }
2785
2786 // different than before. Cannot keep accurate profile.
2787 __ ldr(rscratch2, mdo_addr);
2788 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2789 __ str(rscratch2, mdo_addr);
2790
2791 if (TypeEntries::is_type_none(current_klass)) {
2792 __ b(next);
2793
2794 __ bind(none);
2795 // first time here. Set profile type.
2796 __ str(tmp, mdo_addr);
2797 }
2798 } else {
2799 // There's a single possible klass at this profile point
2800 assert(exact_klass != NULL, "should be");
2801 if (TypeEntries::is_type_none(current_klass)) {
2802 __ mov_metadata(tmp, exact_klass->constant_encoding());
2803 __ ldr(rscratch2, mdo_addr);
2804 __ eor(tmp, tmp, rscratch2);
2805 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2806 __ cbz(rscratch1, next);
2807 #ifdef ASSERT
2808 {
2809 Label ok;
2810 __ ldr(rscratch1, mdo_addr);
2811 __ cbz(rscratch1, ok);
2812 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2813 __ br(Assembler::EQ, ok);
2814 // may have been set by another thread
2815 __ dmb(Assembler::ISHLD);
2816 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2817 __ ldr(rscratch2, mdo_addr);
2818 __ eor(rscratch2, rscratch1, rscratch2);
2819 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2820 __ cbz(rscratch2, ok);
2821
2822 __ stop("unexpected profiling mismatch");
2823 __ bind(ok);
2824 }
2825 #endif
2826 // first time here. Set profile type.
2827 __ ldr(tmp, mdo_addr);
2828 } else {
2829 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2830 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2831
2832 __ ldr(tmp, mdo_addr);
2833 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2834
2835 __ orr(tmp, tmp, TypeEntries::type_unknown);
2836 __ str(tmp, mdo_addr);
2837 // FIXME: Write barrier needed here?
2838 }
2839 }
2840
2841 __ bind(next);
2842 }
2843 COMMENT("} emit_profile_type");
2844 }
2845
2846
align_backward_branch_target()2847 void LIR_Assembler::align_backward_branch_target() {
2848 }
2849
2850
negate(LIR_Opr left,LIR_Opr dest,LIR_Opr tmp)2851 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2852 // tmp must be unused
2853 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2854
2855 if (left->is_single_cpu()) {
2856 assert(dest->is_single_cpu(), "expect single result reg");
2857 __ negw(dest->as_register(), left->as_register());
2858 } else if (left->is_double_cpu()) {
2859 assert(dest->is_double_cpu(), "expect double result reg");
2860 __ neg(dest->as_register_lo(), left->as_register_lo());
2861 } else if (left->is_single_fpu()) {
2862 assert(dest->is_single_fpu(), "expect single float result reg");
2863 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2864 } else {
2865 assert(left->is_double_fpu(), "expect double float operand reg");
2866 assert(dest->is_double_fpu(), "expect double float result reg");
2867 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2868 }
2869 }
2870
2871
leal(LIR_Opr addr,LIR_Opr dest,LIR_PatchCode patch_code,CodeEmitInfo * info)2872 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2873 assert(patch_code == lir_patch_none, "Patch code not supported");
2874 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2875 }
2876
2877
rt_call(LIR_Opr result,address dest,const LIR_OprList * args,LIR_Opr tmp,CodeEmitInfo * info)2878 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2879 assert(!tmp->is_valid(), "don't need temporary");
2880
2881 CodeBlob *cb = CodeCache::find_blob(dest);
2882 if (cb) {
2883 __ far_call(RuntimeAddress(dest));
2884 } else {
2885 __ mov(rscratch1, RuntimeAddress(dest));
2886 int len = args->length();
2887 int type = 0;
2888 if (! result->is_illegal()) {
2889 switch (result->type()) {
2890 case T_VOID:
2891 type = 0;
2892 break;
2893 case T_INT:
2894 case T_LONG:
2895 case T_OBJECT:
2896 type = 1;
2897 break;
2898 case T_FLOAT:
2899 type = 2;
2900 break;
2901 case T_DOUBLE:
2902 type = 3;
2903 break;
2904 default:
2905 ShouldNotReachHere();
2906 break;
2907 }
2908 }
2909 int num_gpargs = 0;
2910 int num_fpargs = 0;
2911 for (int i = 0; i < args->length(); i++) {
2912 LIR_Opr arg = args->at(i);
2913 if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) {
2914 num_fpargs++;
2915 } else {
2916 num_gpargs++;
2917 }
2918 }
2919 __ blrt(rscratch1, num_gpargs, num_fpargs, type);
2920 }
2921
2922 if (info != NULL) {
2923 add_call_info_here(info);
2924 }
2925 __ maybe_isb();
2926 }
2927
volatile_move_op(LIR_Opr src,LIR_Opr dest,BasicType type,CodeEmitInfo * info)2928 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2929 if (dest->is_address() || src->is_address()) {
2930 move_op(src, dest, type, lir_patch_none, info,
2931 /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
2932 } else {
2933 ShouldNotReachHere();
2934 }
2935 }
2936
2937 #ifdef ASSERT
2938 // emit run-time assertion
emit_assert(LIR_OpAssert * op)2939 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2940 assert(op->code() == lir_assert, "must be");
2941
2942 if (op->in_opr1()->is_valid()) {
2943 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2944 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2945 } else {
2946 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2947 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2948 }
2949
2950 Label ok;
2951 if (op->condition() != lir_cond_always) {
2952 Assembler::Condition acond = Assembler::AL;
2953 switch (op->condition()) {
2954 case lir_cond_equal: acond = Assembler::EQ; break;
2955 case lir_cond_notEqual: acond = Assembler::NE; break;
2956 case lir_cond_less: acond = Assembler::LT; break;
2957 case lir_cond_lessEqual: acond = Assembler::LE; break;
2958 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2959 case lir_cond_greater: acond = Assembler::GT; break;
2960 case lir_cond_belowEqual: acond = Assembler::LS; break;
2961 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2962 default: ShouldNotReachHere();
2963 }
2964 __ br(acond, ok);
2965 }
2966 if (op->halt()) {
2967 const char* str = __ code_string(op->msg());
2968 __ stop(str);
2969 } else {
2970 breakpoint();
2971 }
2972 __ bind(ok);
2973 }
2974 #endif
2975
2976 #ifndef PRODUCT
2977 #define COMMENT(x) do { __ block_comment(x); } while (0)
2978 #else
2979 #define COMMENT(x)
2980 #endif
2981
membar()2982 void LIR_Assembler::membar() {
2983 COMMENT("membar");
2984 __ membar(MacroAssembler::AnyAny);
2985 }
2986
membar_acquire()2987 void LIR_Assembler::membar_acquire() {
2988 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2989 }
2990
membar_release()2991 void LIR_Assembler::membar_release() {
2992 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2993 }
2994
membar_loadload()2995 void LIR_Assembler::membar_loadload() {
2996 __ membar(Assembler::LoadLoad);
2997 }
2998
membar_storestore()2999 void LIR_Assembler::membar_storestore() {
3000 __ membar(MacroAssembler::StoreStore);
3001 }
3002
membar_loadstore()3003 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3004
membar_storeload()3005 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3006
on_spin_wait()3007 void LIR_Assembler::on_spin_wait() {
3008 Unimplemented();
3009 }
3010
get_thread(LIR_Opr result_reg)3011 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3012 __ mov(result_reg->as_register(), rthread);
3013 }
3014
3015
peephole(LIR_List * lir)3016 void LIR_Assembler::peephole(LIR_List *lir) {
3017 #if 0
3018 if (tableswitch_count >= max_tableswitches)
3019 return;
3020
3021 /*
3022 This finite-state automaton recognizes sequences of compare-and-
3023 branch instructions. We will turn them into a tableswitch. You
3024 could argue that C1 really shouldn't be doing this sort of
3025 optimization, but without it the code is really horrible.
3026 */
3027
3028 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3029 int first_key, last_key = -2147483648;
3030 int next_key = 0;
3031 int start_insn = -1;
3032 int last_insn = -1;
3033 Register reg = noreg;
3034 LIR_Opr reg_opr;
3035 state = start_s;
3036
3037 LIR_OpList* inst = lir->instructions_list();
3038 for (int i = 0; i < inst->length(); i++) {
3039 LIR_Op* op = inst->at(i);
3040 switch (state) {
3041 case start_s:
3042 first_key = -1;
3043 start_insn = i;
3044 switch (op->code()) {
3045 case lir_cmp:
3046 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3047 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3048 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3049 && opr2->is_constant()
3050 && opr2->type() == T_INT) {
3051 reg_opr = opr1;
3052 reg = opr1->as_register();
3053 first_key = opr2->as_constant_ptr()->as_jint();
3054 next_key = first_key + 1;
3055 state = cmp_s;
3056 goto next_state;
3057 }
3058 break;
3059 }
3060 break;
3061 case cmp_s:
3062 switch (op->code()) {
3063 case lir_branch:
3064 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3065 state = beq_s;
3066 last_insn = i;
3067 goto next_state;
3068 }
3069 }
3070 state = start_s;
3071 break;
3072 case beq_s:
3073 switch (op->code()) {
3074 case lir_cmp: {
3075 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3076 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3077 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3078 && opr1->as_register() == reg
3079 && opr2->is_constant()
3080 && opr2->type() == T_INT
3081 && opr2->as_constant_ptr()->as_jint() == next_key) {
3082 last_key = next_key;
3083 next_key++;
3084 state = cmp_s;
3085 goto next_state;
3086 }
3087 }
3088 }
3089 last_key = next_key;
3090 state = start_s;
3091 break;
3092 default:
3093 assert(false, "impossible state");
3094 }
3095 if (state == start_s) {
3096 if (first_key < last_key - 5L && reg != noreg) {
3097 {
3098 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3099 // reg->encoding(),
3100 // start_insn, first_key, last_key);
3101 // for (int i = 0; i < inst->length(); i++) {
3102 // inst->at(i)->print();
3103 // tty->print("\n");
3104 // }
3105 // tty->print("\n");
3106 }
3107
3108 struct tableswitch *sw = &switches[tableswitch_count];
3109 sw->_insn_index = start_insn, sw->_first_key = first_key,
3110 sw->_last_key = last_key, sw->_reg = reg;
3111 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3112 {
3113 // Insert the new table of branches
3114 int offset = last_insn;
3115 for (int n = first_key; n < last_key; n++) {
3116 inst->insert_before
3117 (last_insn + 1,
3118 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3119 inst->at(offset)->as_OpBranch()->label()));
3120 offset -= 2, i++;
3121 }
3122 }
3123 // Delete all the old compare-and-branch instructions
3124 for (int n = first_key; n < last_key; n++) {
3125 inst->remove_at(start_insn);
3126 inst->remove_at(start_insn);
3127 }
3128 // Insert the tableswitch instruction
3129 inst->insert_before(start_insn,
3130 new LIR_Op2(lir_cmp, lir_cond_always,
3131 LIR_OprFact::intConst(tableswitch_count),
3132 reg_opr));
3133 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3134 tableswitch_count++;
3135 }
3136 reg = noreg;
3137 last_key = -2147483648;
3138 }
3139 next_state:
3140 ;
3141 }
3142 #endif
3143 }
3144
atomic_op(LIR_Code code,LIR_Opr src,LIR_Opr data,LIR_Opr dest,LIR_Opr tmp_op)3145 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3146 Address addr = as_Address(src->as_address_ptr());
3147 BasicType type = src->type();
3148 bool is_oop = type == T_OBJECT || type == T_ARRAY;
3149
3150 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3151 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3152
3153 switch(type) {
3154 case T_INT:
3155 xchg = &MacroAssembler::atomic_xchgalw;
3156 add = &MacroAssembler::atomic_addalw;
3157 break;
3158 case T_LONG:
3159 xchg = &MacroAssembler::atomic_xchgal;
3160 add = &MacroAssembler::atomic_addal;
3161 break;
3162 case T_OBJECT:
3163 case T_ARRAY:
3164 if (UseCompressedOops) {
3165 xchg = &MacroAssembler::atomic_xchgalw;
3166 add = &MacroAssembler::atomic_addalw;
3167 } else {
3168 xchg = &MacroAssembler::atomic_xchgal;
3169 add = &MacroAssembler::atomic_addal;
3170 }
3171 break;
3172 default:
3173 ShouldNotReachHere();
3174 xchg = &MacroAssembler::atomic_xchgal;
3175 add = &MacroAssembler::atomic_addal; // unreachable
3176 }
3177
3178 switch (code) {
3179 case lir_xadd:
3180 {
3181 RegisterOrConstant inc;
3182 Register tmp = as_reg(tmp_op);
3183 Register dst = as_reg(dest);
3184 if (data->is_constant()) {
3185 inc = RegisterOrConstant(as_long(data));
3186 assert_different_registers(dst, addr.base(), tmp,
3187 rscratch1, rscratch2);
3188 } else {
3189 inc = RegisterOrConstant(as_reg(data));
3190 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3191 rscratch1, rscratch2);
3192 }
3193 __ lea(tmp, addr);
3194 (_masm->*add)(dst, inc, tmp);
3195 break;
3196 }
3197 case lir_xchg:
3198 {
3199 Register tmp = tmp_op->as_register();
3200 Register obj = as_reg(data);
3201 Register dst = as_reg(dest);
3202 if (is_oop && UseCompressedOops) {
3203 __ encode_heap_oop(rscratch2, obj);
3204 obj = rscratch2;
3205 }
3206 assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3207 __ lea(tmp, addr);
3208 (_masm->*xchg)(dst, obj, tmp);
3209 if (is_oop && UseCompressedOops) {
3210 __ decode_heap_oop(dst);
3211 }
3212 }
3213 break;
3214 default:
3215 ShouldNotReachHere();
3216 }
3217 __ membar(__ AnyAny);
3218 }
3219
3220 #undef __
3221