1 /*
2 * Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2020 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_ASSEMBLER_PPC_INLINE_HPP
27 #define CPU_PPC_ASSEMBLER_PPC_INLINE_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "asm/codeBuffer.hpp"
31 #include "code/codeCache.hpp"
32
emit_int32(int x)33 inline void Assembler::emit_int32(int x) {
34 AbstractAssembler::emit_int32(x);
35 }
36
emit_data(int x)37 inline void Assembler::emit_data(int x) {
38 emit_int32(x);
39 }
40
emit_data(int x,relocInfo::relocType rtype)41 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
42 relocate(rtype);
43 emit_int32(x);
44 }
45
emit_data(int x,RelocationHolder const & rspec)46 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
47 relocate(rspec);
48 emit_int32(x);
49 }
50
51 // Emit an address
emit_addr(const address addr)52 inline address Assembler::emit_addr(const address addr) {
53 address start = pc();
54 emit_address(addr);
55 return start;
56 }
57
58 #if !defined(ABI_ELFv2)
59 // Emit a function descriptor with the specified entry point, TOC, and
60 // ENV. If the entry point is NULL, the descriptor will point just
61 // past the descriptor.
emit_fd(address entry,address toc,address env)62 inline address Assembler::emit_fd(address entry, address toc, address env) {
63 FunctionDescriptor* fd = (FunctionDescriptor*)pc();
64
65 assert(sizeof(FunctionDescriptor) == 3*sizeof(address), "function descriptor size");
66
67 (void)emit_addr();
68 (void)emit_addr();
69 (void)emit_addr();
70
71 fd->set_entry(entry == NULL ? pc() : entry);
72 fd->set_toc(toc);
73 fd->set_env(env);
74
75 return (address)fd;
76 }
77 #endif
78
79 // Issue an illegal instruction. 0 is guaranteed to be an illegal instruction.
illtrap()80 inline void Assembler::illtrap() { Assembler::emit_int32(0); }
is_illtrap(int x)81 inline bool Assembler::is_illtrap(int x) { return x == 0; }
82
83 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
addi(Register d,Register a,int si16)84 inline void Assembler::addi( Register d, Register a, int si16) { assert(a != R0, "r0 not allowed"); addi_r0ok( d, a, si16); }
addis(Register d,Register a,int si16)85 inline void Assembler::addis( Register d, Register a, int si16) { assert(a != R0, "r0 not allowed"); addis_r0ok(d, a, si16); }
addi_r0ok(Register d,Register a,int si16)86 inline void Assembler::addi_r0ok(Register d,Register a,int si16) { emit_int32(ADDI_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
addis_r0ok(Register d,Register a,int si16)87 inline void Assembler::addis_r0ok(Register d,Register a,int si16) { emit_int32(ADDIS_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
addic_(Register d,Register a,int si16)88 inline void Assembler::addic_( Register d, Register a, int si16) { emit_int32(ADDIC__OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
subfic(Register d,Register a,int si16)89 inline void Assembler::subfic( Register d, Register a, int si16) { emit_int32(SUBFIC_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
add(Register d,Register a,Register b)90 inline void Assembler::add( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
add_(Register d,Register a,Register b)91 inline void Assembler::add_( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
subf(Register d,Register a,Register b)92 inline void Assembler::subf( Register d, Register a, Register b) { emit_int32(SUBF_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
sub(Register d,Register a,Register b)93 inline void Assembler::sub( Register d, Register a, Register b) { subf(d, b, a); }
subf_(Register d,Register a,Register b)94 inline void Assembler::subf_( Register d, Register a, Register b) { emit_int32(SUBF_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
addc(Register d,Register a,Register b)95 inline void Assembler::addc( Register d, Register a, Register b) { emit_int32(ADDC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
addc_(Register d,Register a,Register b)96 inline void Assembler::addc_( Register d, Register a, Register b) { emit_int32(ADDC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
subfc(Register d,Register a,Register b)97 inline void Assembler::subfc( Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
subfc_(Register d,Register a,Register b)98 inline void Assembler::subfc_( Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
adde(Register d,Register a,Register b)99 inline void Assembler::adde( Register d, Register a, Register b) { emit_int32(ADDE_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
adde_(Register d,Register a,Register b)100 inline void Assembler::adde_( Register d, Register a, Register b) { emit_int32(ADDE_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
subfe(Register d,Register a,Register b)101 inline void Assembler::subfe( Register d, Register a, Register b) { emit_int32(SUBFE_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
subfe_(Register d,Register a,Register b)102 inline void Assembler::subfe_( Register d, Register a, Register b) { emit_int32(SUBFE_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
addme(Register d,Register a)103 inline void Assembler::addme( Register d, Register a) { emit_int32(ADDME_OPCODE | rt(d) | ra(a) | oe(0) | rc(0)); }
addme_(Register d,Register a)104 inline void Assembler::addme_( Register d, Register a) { emit_int32(ADDME_OPCODE | rt(d) | ra(a) | oe(0) | rc(1)); }
subfme(Register d,Register a)105 inline void Assembler::subfme( Register d, Register a) { emit_int32(SUBFME_OPCODE | rt(d) | ra(a) | oe(0) | rc(0)); }
subfme_(Register d,Register a)106 inline void Assembler::subfme_(Register d, Register a) { emit_int32(SUBFME_OPCODE | rt(d) | ra(a) | oe(0) | rc(1)); }
addze(Register d,Register a)107 inline void Assembler::addze( Register d, Register a) { emit_int32(ADDZE_OPCODE | rt(d) | ra(a) | oe(0) | rc(0)); }
addze_(Register d,Register a)108 inline void Assembler::addze_( Register d, Register a) { emit_int32(ADDZE_OPCODE | rt(d) | ra(a) | oe(0) | rc(1)); }
subfze(Register d,Register a)109 inline void Assembler::subfze( Register d, Register a) { emit_int32(SUBFZE_OPCODE | rt(d) | ra(a) | oe(0) | rc(0)); }
subfze_(Register d,Register a)110 inline void Assembler::subfze_(Register d, Register a) { emit_int32(SUBFZE_OPCODE | rt(d) | ra(a) | oe(0) | rc(1)); }
neg(Register d,Register a)111 inline void Assembler::neg( Register d, Register a) { emit_int32(NEG_OPCODE | rt(d) | ra(a) | oe(0) | rc(0)); }
neg_(Register d,Register a)112 inline void Assembler::neg_( Register d, Register a) { emit_int32(NEG_OPCODE | rt(d) | ra(a) | oe(0) | rc(1)); }
mulli(Register d,Register a,int si16)113 inline void Assembler::mulli( Register d, Register a, int si16) { emit_int32(MULLI_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
mulld(Register d,Register a,Register b)114 inline void Assembler::mulld( Register d, Register a, Register b) { emit_int32(MULLD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
mulld_(Register d,Register a,Register b)115 inline void Assembler::mulld_( Register d, Register a, Register b) { emit_int32(MULLD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
mullw(Register d,Register a,Register b)116 inline void Assembler::mullw( Register d, Register a, Register b) { emit_int32(MULLW_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
mullw_(Register d,Register a,Register b)117 inline void Assembler::mullw_( Register d, Register a, Register b) { emit_int32(MULLW_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
mulhw(Register d,Register a,Register b)118 inline void Assembler::mulhw( Register d, Register a, Register b) { emit_int32(MULHW_OPCODE | rt(d) | ra(a) | rb(b) | rc(0)); }
mulhw_(Register d,Register a,Register b)119 inline void Assembler::mulhw_( Register d, Register a, Register b) { emit_int32(MULHW_OPCODE | rt(d) | ra(a) | rb(b) | rc(1)); }
mulhwu(Register d,Register a,Register b)120 inline void Assembler::mulhwu( Register d, Register a, Register b) { emit_int32(MULHWU_OPCODE | rt(d) | ra(a) | rb(b) | rc(0)); }
mulhwu_(Register d,Register a,Register b)121 inline void Assembler::mulhwu_(Register d, Register a, Register b) { emit_int32(MULHWU_OPCODE | rt(d) | ra(a) | rb(b) | rc(1)); }
mulhd(Register d,Register a,Register b)122 inline void Assembler::mulhd( Register d, Register a, Register b) { emit_int32(MULHD_OPCODE | rt(d) | ra(a) | rb(b) | rc(0)); }
mulhd_(Register d,Register a,Register b)123 inline void Assembler::mulhd_( Register d, Register a, Register b) { emit_int32(MULHD_OPCODE | rt(d) | ra(a) | rb(b) | rc(1)); }
mulhdu(Register d,Register a,Register b)124 inline void Assembler::mulhdu( Register d, Register a, Register b) { emit_int32(MULHDU_OPCODE | rt(d) | ra(a) | rb(b) | rc(0)); }
mulhdu_(Register d,Register a,Register b)125 inline void Assembler::mulhdu_(Register d, Register a, Register b) { emit_int32(MULHDU_OPCODE | rt(d) | ra(a) | rb(b) | rc(1)); }
divd(Register d,Register a,Register b)126 inline void Assembler::divd( Register d, Register a, Register b) { emit_int32(DIVD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
divd_(Register d,Register a,Register b)127 inline void Assembler::divd_( Register d, Register a, Register b) { emit_int32(DIVD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
divw(Register d,Register a,Register b)128 inline void Assembler::divw( Register d, Register a, Register b) { emit_int32(DIVW_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
divw_(Register d,Register a,Register b)129 inline void Assembler::divw_( Register d, Register a, Register b) { emit_int32(DIVW_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
130
131 // Fixed-Point Arithmetic Instructions with Overflow detection
addo(Register d,Register a,Register b)132 inline void Assembler::addo( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
addo_(Register d,Register a,Register b)133 inline void Assembler::addo_( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
subfo(Register d,Register a,Register b)134 inline void Assembler::subfo( Register d, Register a, Register b) { emit_int32(SUBF_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
subfo_(Register d,Register a,Register b)135 inline void Assembler::subfo_( Register d, Register a, Register b) { emit_int32(SUBF_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
addco(Register d,Register a,Register b)136 inline void Assembler::addco( Register d, Register a, Register b) { emit_int32(ADDC_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
addco_(Register d,Register a,Register b)137 inline void Assembler::addco_( Register d, Register a, Register b) { emit_int32(ADDC_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
subfco(Register d,Register a,Register b)138 inline void Assembler::subfco( Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
subfco_(Register d,Register a,Register b)139 inline void Assembler::subfco_( Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
addeo(Register d,Register a,Register b)140 inline void Assembler::addeo( Register d, Register a, Register b) { emit_int32(ADDE_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
addeo_(Register d,Register a,Register b)141 inline void Assembler::addeo_( Register d, Register a, Register b) { emit_int32(ADDE_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
subfeo(Register d,Register a,Register b)142 inline void Assembler::subfeo( Register d, Register a, Register b) { emit_int32(SUBFE_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
subfeo_(Register d,Register a,Register b)143 inline void Assembler::subfeo_( Register d, Register a, Register b) { emit_int32(SUBFE_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
addmeo(Register d,Register a)144 inline void Assembler::addmeo( Register d, Register a) { emit_int32(ADDME_OPCODE | rt(d) | ra(a) | oe(1) | rc(0)); }
addmeo_(Register d,Register a)145 inline void Assembler::addmeo_( Register d, Register a) { emit_int32(ADDME_OPCODE | rt(d) | ra(a) | oe(1) | rc(1)); }
subfmeo(Register d,Register a)146 inline void Assembler::subfmeo( Register d, Register a) { emit_int32(SUBFME_OPCODE | rt(d) | ra(a) | oe(1) | rc(0)); }
subfmeo_(Register d,Register a)147 inline void Assembler::subfmeo_(Register d, Register a) { emit_int32(SUBFME_OPCODE | rt(d) | ra(a) | oe(1) | rc(1)); }
addzeo(Register d,Register a)148 inline void Assembler::addzeo( Register d, Register a) { emit_int32(ADDZE_OPCODE | rt(d) | ra(a) | oe(1) | rc(0)); }
addzeo_(Register d,Register a)149 inline void Assembler::addzeo_( Register d, Register a) { emit_int32(ADDZE_OPCODE | rt(d) | ra(a) | oe(1) | rc(1)); }
subfzeo(Register d,Register a)150 inline void Assembler::subfzeo( Register d, Register a) { emit_int32(SUBFZE_OPCODE | rt(d) | ra(a) | oe(1) | rc(0)); }
subfzeo_(Register d,Register a)151 inline void Assembler::subfzeo_(Register d, Register a) { emit_int32(SUBFZE_OPCODE | rt(d) | ra(a) | oe(1) | rc(1)); }
nego(Register d,Register a)152 inline void Assembler::nego( Register d, Register a) { emit_int32(NEG_OPCODE | rt(d) | ra(a) | oe(1) | rc(0)); }
nego_(Register d,Register a)153 inline void Assembler::nego_( Register d, Register a) { emit_int32(NEG_OPCODE | rt(d) | ra(a) | oe(1) | rc(1)); }
mulldo(Register d,Register a,Register b)154 inline void Assembler::mulldo( Register d, Register a, Register b) { emit_int32(MULLD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
mulldo_(Register d,Register a,Register b)155 inline void Assembler::mulldo_( Register d, Register a, Register b) { emit_int32(MULLD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
mullwo(Register d,Register a,Register b)156 inline void Assembler::mullwo( Register d, Register a, Register b) { emit_int32(MULLW_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
mullwo_(Register d,Register a,Register b)157 inline void Assembler::mullwo_( Register d, Register a, Register b) { emit_int32(MULLW_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
divdo(Register d,Register a,Register b)158 inline void Assembler::divdo( Register d, Register a, Register b) { emit_int32(DIVD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
divdo_(Register d,Register a,Register b)159 inline void Assembler::divdo_( Register d, Register a, Register b) { emit_int32(DIVD_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
divwo(Register d,Register a,Register b)160 inline void Assembler::divwo( Register d, Register a, Register b) { emit_int32(DIVW_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(0)); }
divwo_(Register d,Register a,Register b)161 inline void Assembler::divwo_( Register d, Register a, Register b) { emit_int32(DIVW_OPCODE | rt(d) | ra(a) | rb(b) | oe(1) | rc(1)); }
162
163 // extended mnemonics
li(Register d,int si16)164 inline void Assembler::li( Register d, int si16) { Assembler::addi_r0ok( d, R0, si16); }
lis(Register d,int si16)165 inline void Assembler::lis( Register d, int si16) { Assembler::addis_r0ok(d, R0, si16); }
addir(Register d,int si16,Register a)166 inline void Assembler::addir(Register d, int si16, Register a) { Assembler::addi(d, a, si16); }
subi(Register d,Register a,int si16)167 inline void Assembler::subi( Register d, Register a, int si16) { Assembler::addi(d, a, -si16); }
168
169 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
cmpi(ConditionRegister f,int l,Register a,int si16)170 inline void Assembler::cmpi( ConditionRegister f, int l, Register a, int si16) { emit_int32( CMPI_OPCODE | bf(f) | l10(l) | ra(a) | simm(si16,16)); }
cmp(ConditionRegister f,int l,Register a,Register b)171 inline void Assembler::cmp( ConditionRegister f, int l, Register a, Register b) { emit_int32( CMP_OPCODE | bf(f) | l10(l) | ra(a) | rb(b)); }
cmpli(ConditionRegister f,int l,Register a,int ui16)172 inline void Assembler::cmpli( ConditionRegister f, int l, Register a, int ui16) { emit_int32( CMPLI_OPCODE | bf(f) | l10(l) | ra(a) | uimm(ui16,16)); }
cmpl(ConditionRegister f,int l,Register a,Register b)173 inline void Assembler::cmpl( ConditionRegister f, int l, Register a, Register b) { emit_int32( CMPL_OPCODE | bf(f) | l10(l) | ra(a) | rb(b)); }
cmprb(ConditionRegister f,int l,Register a,Register b)174 inline void Assembler::cmprb( ConditionRegister f, int l, Register a, Register b) { emit_int32( CMPRB_OPCODE | bf(f) | l10(l) | ra(a) | rb(b)); }
cmpeqb(ConditionRegister f,Register a,Register b)175 inline void Assembler::cmpeqb(ConditionRegister f, Register a, Register b) { emit_int32( CMPEQB_OPCODE| bf(f) | ra(a) | rb(b)); }
176
177 // extended mnemonics of Compare Instructions
cmpwi(ConditionRegister crx,Register a,int si16)178 inline void Assembler::cmpwi( ConditionRegister crx, Register a, int si16) { Assembler::cmpi( crx, 0, a, si16); }
cmpdi(ConditionRegister crx,Register a,int si16)179 inline void Assembler::cmpdi( ConditionRegister crx, Register a, int si16) { Assembler::cmpi( crx, 1, a, si16); }
cmpw(ConditionRegister crx,Register a,Register b)180 inline void Assembler::cmpw( ConditionRegister crx, Register a, Register b) { Assembler::cmp( crx, 0, a, b); }
cmpd(ConditionRegister crx,Register a,Register b)181 inline void Assembler::cmpd( ConditionRegister crx, Register a, Register b) { Assembler::cmp( crx, 1, a, b); }
cmplwi(ConditionRegister crx,Register a,int ui16)182 inline void Assembler::cmplwi(ConditionRegister crx, Register a, int ui16) { Assembler::cmpli(crx, 0, a, ui16); }
cmpldi(ConditionRegister crx,Register a,int ui16)183 inline void Assembler::cmpldi(ConditionRegister crx, Register a, int ui16) { Assembler::cmpli(crx, 1, a, ui16); }
cmplw(ConditionRegister crx,Register a,Register b)184 inline void Assembler::cmplw( ConditionRegister crx, Register a, Register b) { Assembler::cmpl( crx, 0, a, b); }
cmpld(ConditionRegister crx,Register a,Register b)185 inline void Assembler::cmpld( ConditionRegister crx, Register a, Register b) { Assembler::cmpl( crx, 1, a, b); }
186
isel(Register d,Register a,Register b,int c)187 inline void Assembler::isel(Register d, Register a, Register b, int c) { guarantee(VM_Version::has_isel(), "opcode not supported on this hardware");
188 emit_int32(ISEL_OPCODE | rt(d) | ra(a) | rb(b) | bc(c)); }
189
190 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
andi_(Register a,Register s,int ui16)191 inline void Assembler::andi_( Register a, Register s, int ui16) { emit_int32(ANDI_OPCODE | rta(a) | rs(s) | uimm(ui16, 16)); }
andis_(Register a,Register s,int ui16)192 inline void Assembler::andis_( Register a, Register s, int ui16) { emit_int32(ANDIS_OPCODE | rta(a) | rs(s) | uimm(ui16, 16)); }
ori(Register a,Register s,int ui16)193 inline void Assembler::ori( Register a, Register s, int ui16) { emit_int32(ORI_OPCODE | rta(a) | rs(s) | uimm(ui16, 16)); }
oris(Register a,Register s,int ui16)194 inline void Assembler::oris( Register a, Register s, int ui16) { emit_int32(ORIS_OPCODE | rta(a) | rs(s) | uimm(ui16, 16)); }
xori(Register a,Register s,int ui16)195 inline void Assembler::xori( Register a, Register s, int ui16) { emit_int32(XORI_OPCODE | rta(a) | rs(s) | uimm(ui16, 16)); }
xoris(Register a,Register s,int ui16)196 inline void Assembler::xoris( Register a, Register s, int ui16) { emit_int32(XORIS_OPCODE | rta(a) | rs(s) | uimm(ui16, 16)); }
andr(Register a,Register s,Register b)197 inline void Assembler::andr( Register a, Register s, Register b) { emit_int32(AND_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
and_(Register a,Register s,Register b)198 inline void Assembler::and_( Register a, Register s, Register b) { emit_int32(AND_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
199
or_unchecked(Register a,Register s,Register b)200 inline void Assembler::or_unchecked(Register a, Register s, Register b){ emit_int32(OR_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
orr(Register a,Register s,Register b)201 inline void Assembler::orr( Register a, Register s, Register b) { if (a==s && s==b) { Assembler::nop(); } else { Assembler::or_unchecked(a,s,b); } }
or_(Register a,Register s,Register b)202 inline void Assembler::or_( Register a, Register s, Register b) { emit_int32(OR_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
xorr(Register a,Register s,Register b)203 inline void Assembler::xorr( Register a, Register s, Register b) { emit_int32(XOR_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
xor_(Register a,Register s,Register b)204 inline void Assembler::xor_( Register a, Register s, Register b) { emit_int32(XOR_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
nand(Register a,Register s,Register b)205 inline void Assembler::nand( Register a, Register s, Register b) { emit_int32(NAND_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
nand_(Register a,Register s,Register b)206 inline void Assembler::nand_( Register a, Register s, Register b) { emit_int32(NAND_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
nor(Register a,Register s,Register b)207 inline void Assembler::nor( Register a, Register s, Register b) { emit_int32(NOR_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
nor_(Register a,Register s,Register b)208 inline void Assembler::nor_( Register a, Register s, Register b) { emit_int32(NOR_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
andc(Register a,Register s,Register b)209 inline void Assembler::andc( Register a, Register s, Register b) { emit_int32(ANDC_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
andc_(Register a,Register s,Register b)210 inline void Assembler::andc_( Register a, Register s, Register b) { emit_int32(ANDC_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
orc(Register a,Register s,Register b)211 inline void Assembler::orc( Register a, Register s, Register b) { emit_int32(ORC_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
orc_(Register a,Register s,Register b)212 inline void Assembler::orc_( Register a, Register s, Register b) { emit_int32(ORC_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
extsb(Register a,Register s)213 inline void Assembler::extsb( Register a, Register s) { emit_int32(EXTSB_OPCODE | rta(a) | rs(s) | rc(0)); }
extsb_(Register a,Register s)214 inline void Assembler::extsb_( Register a, Register s) { emit_int32(EXTSB_OPCODE | rta(a) | rs(s) | rc(1)); }
extsh(Register a,Register s)215 inline void Assembler::extsh( Register a, Register s) { emit_int32(EXTSH_OPCODE | rta(a) | rs(s) | rc(0)); }
extsh_(Register a,Register s)216 inline void Assembler::extsh_( Register a, Register s) { emit_int32(EXTSH_OPCODE | rta(a) | rs(s) | rc(1)); }
extsw(Register a,Register s)217 inline void Assembler::extsw( Register a, Register s) { emit_int32(EXTSW_OPCODE | rta(a) | rs(s) | rc(0)); }
extsw_(Register a,Register s)218 inline void Assembler::extsw_( Register a, Register s) { emit_int32(EXTSW_OPCODE | rta(a) | rs(s) | rc(1)); }
219
220 // extended mnemonics
nop()221 inline void Assembler::nop() { Assembler::ori(R0, R0, 0); }
222 // NOP for FP and BR units (different versions to allow them to be in one group)
fpnop0()223 inline void Assembler::fpnop0() { Assembler::fmr(F30, F30); }
fpnop1()224 inline void Assembler::fpnop1() { Assembler::fmr(F31, F31); }
brnop0()225 inline void Assembler::brnop0() { Assembler::mcrf(CCR2, CCR2); }
brnop1()226 inline void Assembler::brnop1() { Assembler::mcrf(CCR3, CCR3); }
brnop2()227 inline void Assembler::brnop2() { Assembler::mcrf(CCR4, CCR4); }
228
mr(Register d,Register s)229 inline void Assembler::mr( Register d, Register s) { Assembler::orr(d, s, s); }
ori_opt(Register d,int ui16)230 inline void Assembler::ori_opt( Register d, int ui16) { if (ui16!=0) Assembler::ori( d, d, ui16); }
oris_opt(Register d,int ui16)231 inline void Assembler::oris_opt(Register d, int ui16) { if (ui16!=0) Assembler::oris(d, d, ui16); }
232
endgroup()233 inline void Assembler::endgroup() { Assembler::ori(R1, R1, 0); }
234
235 // count instructions
cntlzw(Register a,Register s)236 inline void Assembler::cntlzw( Register a, Register s) { emit_int32(CNTLZW_OPCODE | rta(a) | rs(s) | rc(0)); }
cntlzw_(Register a,Register s)237 inline void Assembler::cntlzw_( Register a, Register s) { emit_int32(CNTLZW_OPCODE | rta(a) | rs(s) | rc(1)); }
cntlzd(Register a,Register s)238 inline void Assembler::cntlzd( Register a, Register s) { emit_int32(CNTLZD_OPCODE | rta(a) | rs(s) | rc(0)); }
cntlzd_(Register a,Register s)239 inline void Assembler::cntlzd_( Register a, Register s) { emit_int32(CNTLZD_OPCODE | rta(a) | rs(s) | rc(1)); }
cnttzw(Register a,Register s)240 inline void Assembler::cnttzw( Register a, Register s) { emit_int32(CNTTZW_OPCODE | rta(a) | rs(s) | rc(0)); }
cnttzw_(Register a,Register s)241 inline void Assembler::cnttzw_( Register a, Register s) { emit_int32(CNTTZW_OPCODE | rta(a) | rs(s) | rc(1)); }
cnttzd(Register a,Register s)242 inline void Assembler::cnttzd( Register a, Register s) { emit_int32(CNTTZD_OPCODE | rta(a) | rs(s) | rc(0)); }
cnttzd_(Register a,Register s)243 inline void Assembler::cnttzd_( Register a, Register s) { emit_int32(CNTTZD_OPCODE | rta(a) | rs(s) | rc(1)); }
244
245 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
sld(Register a,Register s,Register b)246 inline void Assembler::sld( Register a, Register s, Register b) { emit_int32(SLD_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
sld_(Register a,Register s,Register b)247 inline void Assembler::sld_( Register a, Register s, Register b) { emit_int32(SLD_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
slw(Register a,Register s,Register b)248 inline void Assembler::slw( Register a, Register s, Register b) { emit_int32(SLW_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
slw_(Register a,Register s,Register b)249 inline void Assembler::slw_( Register a, Register s, Register b) { emit_int32(SLW_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
srd(Register a,Register s,Register b)250 inline void Assembler::srd( Register a, Register s, Register b) { emit_int32(SRD_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
srd_(Register a,Register s,Register b)251 inline void Assembler::srd_( Register a, Register s, Register b) { emit_int32(SRD_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
srw(Register a,Register s,Register b)252 inline void Assembler::srw( Register a, Register s, Register b) { emit_int32(SRW_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
srw_(Register a,Register s,Register b)253 inline void Assembler::srw_( Register a, Register s, Register b) { emit_int32(SRW_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
srad(Register a,Register s,Register b)254 inline void Assembler::srad( Register a, Register s, Register b) { emit_int32(SRAD_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
srad_(Register a,Register s,Register b)255 inline void Assembler::srad_( Register a, Register s, Register b) { emit_int32(SRAD_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
sraw(Register a,Register s,Register b)256 inline void Assembler::sraw( Register a, Register s, Register b) { emit_int32(SRAW_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
sraw_(Register a,Register s,Register b)257 inline void Assembler::sraw_( Register a, Register s, Register b) { emit_int32(SRAW_OPCODE | rta(a) | rs(s) | rb(b) | rc(1)); }
sradi(Register a,Register s,int sh6)258 inline void Assembler::sradi( Register a, Register s, int sh6) { emit_int32(SRADI_OPCODE | rta(a) | rs(s) | sh162030(sh6) | rc(0)); }
sradi_(Register a,Register s,int sh6)259 inline void Assembler::sradi_( Register a, Register s, int sh6) { emit_int32(SRADI_OPCODE | rta(a) | rs(s) | sh162030(sh6) | rc(1)); }
srawi(Register a,Register s,int sh5)260 inline void Assembler::srawi( Register a, Register s, int sh5) { emit_int32(SRAWI_OPCODE | rta(a) | rs(s) | sh1620(sh5) | rc(0)); }
srawi_(Register a,Register s,int sh5)261 inline void Assembler::srawi_( Register a, Register s, int sh5) { emit_int32(SRAWI_OPCODE | rta(a) | rs(s) | sh1620(sh5) | rc(1)); }
262
263 // extended mnemonics for Shift Instructions
sldi(Register a,Register s,int sh6)264 inline void Assembler::sldi( Register a, Register s, int sh6) { Assembler::rldicr(a, s, sh6, 63-sh6); }
sldi_(Register a,Register s,int sh6)265 inline void Assembler::sldi_( Register a, Register s, int sh6) { Assembler::rldicr_(a, s, sh6, 63-sh6); }
slwi(Register a,Register s,int sh5)266 inline void Assembler::slwi( Register a, Register s, int sh5) { Assembler::rlwinm(a, s, sh5, 0, 31-sh5); }
slwi_(Register a,Register s,int sh5)267 inline void Assembler::slwi_( Register a, Register s, int sh5) { Assembler::rlwinm_(a, s, sh5, 0, 31-sh5); }
srdi(Register a,Register s,int sh6)268 inline void Assembler::srdi( Register a, Register s, int sh6) { Assembler::rldicl(a, s, 64-sh6, sh6); }
srdi_(Register a,Register s,int sh6)269 inline void Assembler::srdi_( Register a, Register s, int sh6) { Assembler::rldicl_(a, s, 64-sh6, sh6); }
srwi(Register a,Register s,int sh5)270 inline void Assembler::srwi( Register a, Register s, int sh5) { Assembler::rlwinm(a, s, 32-sh5, sh5, 31); }
srwi_(Register a,Register s,int sh5)271 inline void Assembler::srwi_( Register a, Register s, int sh5) { Assembler::rlwinm_(a, s, 32-sh5, sh5, 31); }
272
clrrdi(Register a,Register s,int ui6)273 inline void Assembler::clrrdi( Register a, Register s, int ui6) { Assembler::rldicr(a, s, 0, 63-ui6); }
clrrdi_(Register a,Register s,int ui6)274 inline void Assembler::clrrdi_( Register a, Register s, int ui6) { Assembler::rldicr_(a, s, 0, 63-ui6); }
clrldi(Register a,Register s,int ui6)275 inline void Assembler::clrldi( Register a, Register s, int ui6) { Assembler::rldicl(a, s, 0, ui6); }
clrldi_(Register a,Register s,int ui6)276 inline void Assembler::clrldi_( Register a, Register s, int ui6) { Assembler::rldicl_(a, s, 0, ui6); }
clrlsldi(Register a,Register s,int clrl6,int shl6)277 inline void Assembler::clrlsldi( Register a, Register s, int clrl6, int shl6) { Assembler::rldic( a, s, shl6, clrl6-shl6); }
clrlsldi_(Register a,Register s,int clrl6,int shl6)278 inline void Assembler::clrlsldi_(Register a, Register s, int clrl6, int shl6) { Assembler::rldic_(a, s, shl6, clrl6-shl6); }
extrdi(Register a,Register s,int n,int b)279 inline void Assembler::extrdi( Register a, Register s, int n, int b){ Assembler::rldicl(a, s, b+n, 64-n); }
280 // testbit with condition register.
testbitdi(ConditionRegister cr,Register a,Register s,int ui6)281 inline void Assembler::testbitdi(ConditionRegister cr, Register a, Register s, int ui6) {
282 if (cr == CCR0) {
283 Assembler::rldicr_(a, s, 63-ui6, 0);
284 } else {
285 Assembler::rldicr(a, s, 63-ui6, 0);
286 Assembler::cmpdi(cr, a, 0);
287 }
288 }
289
290 // rotate instructions
rotldi(Register a,Register s,int n)291 inline void Assembler::rotldi( Register a, Register s, int n) { Assembler::rldicl(a, s, n, 0); }
rotrdi(Register a,Register s,int n)292 inline void Assembler::rotrdi( Register a, Register s, int n) { Assembler::rldicl(a, s, 64-n, 0); }
rotlwi(Register a,Register s,int n)293 inline void Assembler::rotlwi( Register a, Register s, int n) { Assembler::rlwinm(a, s, n, 0, 31); }
rotrwi(Register a,Register s,int n)294 inline void Assembler::rotrwi( Register a, Register s, int n) { Assembler::rlwinm(a, s, 32-n, 0, 31); }
295
rldic(Register a,Register s,int sh6,int mb6)296 inline void Assembler::rldic( Register a, Register s, int sh6, int mb6) { emit_int32(RLDIC_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(0)); }
rldic_(Register a,Register s,int sh6,int mb6)297 inline void Assembler::rldic_( Register a, Register s, int sh6, int mb6) { emit_int32(RLDIC_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(1)); }
rldicr(Register a,Register s,int sh6,int mb6)298 inline void Assembler::rldicr( Register a, Register s, int sh6, int mb6) { emit_int32(RLDICR_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(0)); }
rldicr_(Register a,Register s,int sh6,int mb6)299 inline void Assembler::rldicr_( Register a, Register s, int sh6, int mb6) { emit_int32(RLDICR_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(1)); }
rldicl(Register a,Register s,int sh6,int me6)300 inline void Assembler::rldicl( Register a, Register s, int sh6, int me6) { emit_int32(RLDICL_OPCODE | rta(a) | rs(s) | sh162030(sh6) | me2126(me6) | rc(0)); }
rldicl_(Register a,Register s,int sh6,int me6)301 inline void Assembler::rldicl_( Register a, Register s, int sh6, int me6) { emit_int32(RLDICL_OPCODE | rta(a) | rs(s) | sh162030(sh6) | me2126(me6) | rc(1)); }
rlwinm(Register a,Register s,int sh5,int mb5,int me5)302 inline void Assembler::rlwinm( Register a, Register s, int sh5, int mb5, int me5){ emit_int32(RLWINM_OPCODE | rta(a) | rs(s) | sh1620(sh5) | mb2125(mb5) | me2630(me5) | rc(0)); }
rlwinm_(Register a,Register s,int sh5,int mb5,int me5)303 inline void Assembler::rlwinm_( Register a, Register s, int sh5, int mb5, int me5){ emit_int32(RLWINM_OPCODE | rta(a) | rs(s) | sh1620(sh5) | mb2125(mb5) | me2630(me5) | rc(1)); }
rldimi(Register a,Register s,int sh6,int mb6)304 inline void Assembler::rldimi( Register a, Register s, int sh6, int mb6) { emit_int32(RLDIMI_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(0)); }
rlwimi(Register a,Register s,int sh5,int mb5,int me5)305 inline void Assembler::rlwimi( Register a, Register s, int sh5, int mb5, int me5){ emit_int32(RLWIMI_OPCODE | rta(a) | rs(s) | sh1620(sh5) | mb2125(mb5) | me2630(me5) | rc(0)); }
rldimi_(Register a,Register s,int sh6,int mb6)306 inline void Assembler::rldimi_( Register a, Register s, int sh6, int mb6) { emit_int32(RLDIMI_OPCODE | rta(a) | rs(s) | sh162030(sh6) | mb2126(mb6) | rc(1)); }
insrdi(Register a,Register s,int n,int b)307 inline void Assembler::insrdi( Register a, Register s, int n, int b) { Assembler::rldimi(a, s, 64-(b+n), b); }
insrwi(Register a,Register s,int n,int b)308 inline void Assembler::insrwi( Register a, Register s, int n, int b) { Assembler::rlwimi(a, s, 32-(b+n), b, b+n-1); }
309
310 // PPC 1, section 3.3.2 Fixed-Point Load Instructions
lwzx(Register d,Register s1,Register s2)311 inline void Assembler::lwzx( Register d, Register s1, Register s2) { emit_int32(LWZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lwz(Register d,int si16,Register s1)312 inline void Assembler::lwz( Register d, int si16, Register s1) { emit_int32(LWZ_OPCODE | rt(d) | d1(si16) | ra0mem(s1));}
lwzu(Register d,int si16,Register s1)313 inline void Assembler::lwzu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LWZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));}
314
lwax(Register d,Register s1,Register s2)315 inline void Assembler::lwax( Register d, Register s1, Register s2) { emit_int32(LWAX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lwa(Register d,int si16,Register s1)316 inline void Assembler::lwa( Register d, int si16, Register s1) { emit_int32(LWA_OPCODE | rt(d) | ds(si16) | ra0mem(s1));}
317
lwbrx(Register d,Register s1,Register s2)318 inline void Assembler::lwbrx( Register d, Register s1, Register s2) { emit_int32(LWBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
319
lhzx(Register d,Register s1,Register s2)320 inline void Assembler::lhzx( Register d, Register s1, Register s2) { emit_int32(LHZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lhz(Register d,int si16,Register s1)321 inline void Assembler::lhz( Register d, int si16, Register s1) { emit_int32(LHZ_OPCODE | rt(d) | d1(si16) | ra0mem(s1));}
lhzu(Register d,int si16,Register s1)322 inline void Assembler::lhzu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LHZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));}
323
lhbrx(Register d,Register s1,Register s2)324 inline void Assembler::lhbrx( Register d, Register s1, Register s2) { emit_int32(LHBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
325
lhax(Register d,Register s1,Register s2)326 inline void Assembler::lhax( Register d, Register s1, Register s2) { emit_int32(LHAX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lha(Register d,int si16,Register s1)327 inline void Assembler::lha( Register d, int si16, Register s1) { emit_int32(LHA_OPCODE | rt(d) | d1(si16) | ra0mem(s1));}
lhau(Register d,int si16,Register s1)328 inline void Assembler::lhau( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LHAU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));}
329
lbzx(Register d,Register s1,Register s2)330 inline void Assembler::lbzx( Register d, Register s1, Register s2) { emit_int32(LBZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
lbz(Register d,int si16,Register s1)331 inline void Assembler::lbz( Register d, int si16, Register s1) { emit_int32(LBZ_OPCODE | rt(d) | d1(si16) | ra0mem(s1));}
lbzu(Register d,int si16,Register s1)332 inline void Assembler::lbzu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LBZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));}
333
ld(Register d,int si16,Register s1)334 inline void Assembler::ld( Register d, int si16, Register s1) { emit_int32(LD_OPCODE | rt(d) | ds(si16) | ra0mem(s1));}
ldx(Register d,Register s1,Register s2)335 inline void Assembler::ldx( Register d, Register s1, Register s2) { emit_int32(LDX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
ldu(Register d,int si16,Register s1)336 inline void Assembler::ldu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LDU_OPCODE | rt(d) | ds(si16) | rta0mem(s1));}
ldbrx(Register d,Register s1,Register s2)337 inline void Assembler::ldbrx( Register d, Register s1, Register s2) { emit_int32(LDBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
338
ld_ptr(Register d,int b,Register s1)339 inline void Assembler::ld_ptr(Register d, int b, Register s1) { ld(d, b, s1); }
DEBUG_ONLY(inline void Assembler::ld_ptr (Register d,ByteSize b,Register s1){ ld(d, in_bytes(b), s1); })340 DEBUG_ONLY(inline void Assembler::ld_ptr(Register d, ByteSize b, Register s1) { ld(d, in_bytes(b), s1); })
341
342 // PPC 1, section 3.3.3 Fixed-Point Store Instructions
343 inline void Assembler::stwx( Register d, Register s1, Register s2) { emit_int32(STWX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
stw(Register d,int si16,Register s1)344 inline void Assembler::stw( Register d, int si16, Register s1) { emit_int32(STW_OPCODE | rs(d) | d1(si16) | ra0mem(s1));}
stwu(Register d,int si16,Register s1)345 inline void Assembler::stwu( Register d, int si16, Register s1) { emit_int32(STWU_OPCODE | rs(d) | d1(si16) | rta0mem(s1));}
stwbrx(Register d,Register s1,Register s2)346 inline void Assembler::stwbrx( Register d, Register s1, Register s2) { emit_int32(STWBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
347
sthx(Register d,Register s1,Register s2)348 inline void Assembler::sthx( Register d, Register s1, Register s2) { emit_int32(STHX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
sth(Register d,int si16,Register s1)349 inline void Assembler::sth( Register d, int si16, Register s1) { emit_int32(STH_OPCODE | rs(d) | d1(si16) | ra0mem(s1));}
sthu(Register d,int si16,Register s1)350 inline void Assembler::sthu( Register d, int si16, Register s1) { emit_int32(STHU_OPCODE | rs(d) | d1(si16) | rta0mem(s1));}
sthbrx(Register d,Register s1,Register s2)351 inline void Assembler::sthbrx( Register d, Register s1, Register s2) { emit_int32(STHBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
352
stbx(Register d,Register s1,Register s2)353 inline void Assembler::stbx( Register d, Register s1, Register s2) { emit_int32(STBX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
stb(Register d,int si16,Register s1)354 inline void Assembler::stb( Register d, int si16, Register s1) { emit_int32(STB_OPCODE | rs(d) | d1(si16) | ra0mem(s1));}
stbu(Register d,int si16,Register s1)355 inline void Assembler::stbu( Register d, int si16, Register s1) { emit_int32(STBU_OPCODE | rs(d) | d1(si16) | rta0mem(s1));}
356
std(Register d,int si16,Register s1)357 inline void Assembler::std( Register d, int si16, Register s1) { emit_int32(STD_OPCODE | rs(d) | ds(si16) | ra0mem(s1));}
stdx(Register d,Register s1,Register s2)358 inline void Assembler::stdx( Register d, Register s1, Register s2) { emit_int32(STDX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
stdu(Register d,int si16,Register s1)359 inline void Assembler::stdu( Register d, int si16, Register s1) { emit_int32(STDU_OPCODE | rs(d) | ds(si16) | rta0mem(s1));}
stdux(Register s,Register a,Register b)360 inline void Assembler::stdux(Register s, Register a, Register b) { emit_int32(STDUX_OPCODE| rs(s) | rta0mem(a) | rb(b));}
stdbrx(Register d,Register s1,Register s2)361 inline void Assembler::stdbrx( Register d, Register s1, Register s2) { emit_int32(STDBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
362
st_ptr(Register d,int b,Register s1)363 inline void Assembler::st_ptr(Register d, int b, Register s1) { std(d, b, s1); }
DEBUG_ONLY(inline void Assembler::st_ptr (Register d,ByteSize b,Register s1){ std(d, in_bytes(b), s1); })364 DEBUG_ONLY(inline void Assembler::st_ptr(Register d, ByteSize b, Register s1) { std(d, in_bytes(b), s1); })
365
366 // PPC 1, section 3.3.13 Move To/From System Register Instructions
367 inline void Assembler::mtlr( Register s1) { emit_int32(MTLR_OPCODE | rs(s1)); }
mflr(Register d)368 inline void Assembler::mflr( Register d ) { emit_int32(MFLR_OPCODE | rt(d)); }
mtctr(Register s1)369 inline void Assembler::mtctr(Register s1) { emit_int32(MTCTR_OPCODE | rs(s1)); }
mfctr(Register d)370 inline void Assembler::mfctr(Register d ) { emit_int32(MFCTR_OPCODE | rt(d)); }
mtcrf(int afxm,Register s)371 inline void Assembler::mtcrf(int afxm, Register s){ emit_int32(MTCRF_OPCODE | fxm(afxm) | rs(s)); }
mfcr(Register d)372 inline void Assembler::mfcr( Register d ) { emit_int32(MFCR_OPCODE | rt(d)); }
mcrf(ConditionRegister crd,ConditionRegister cra)373 inline void Assembler::mcrf( ConditionRegister crd, ConditionRegister cra)
374 { emit_int32(MCRF_OPCODE | bf(crd) | bfa(cra)); }
mtcr(Register s)375 inline void Assembler::mtcr( Register s) { Assembler::mtcrf(0xff, s); }
setb(Register d,ConditionRegister cra)376 inline void Assembler::setb(Register d, ConditionRegister cra)
377 { emit_int32(SETB_OPCODE | rt(d) | bfa(cra)); }
378
379 // Special purpose registers
380 // Exception Register
mtxer(Register s1)381 inline void Assembler::mtxer(Register s1) { emit_int32(MTXER_OPCODE | rs(s1)); }
mfxer(Register d)382 inline void Assembler::mfxer(Register d ) { emit_int32(MFXER_OPCODE | rt(d)); }
383 // Vector Register Save Register
mtvrsave(Register s1)384 inline void Assembler::mtvrsave(Register s1) { emit_int32(MTVRSAVE_OPCODE | rs(s1)); }
mfvrsave(Register d)385 inline void Assembler::mfvrsave(Register d ) { emit_int32(MFVRSAVE_OPCODE | rt(d)); }
386 // Timebase
mftb(Register d)387 inline void Assembler::mftb(Register d ) { emit_int32(MFTB_OPCODE | rt(d)); }
388 // Introduced with Power 8:
389 // Data Stream Control Register
mtdscr(Register s1)390 inline void Assembler::mtdscr(Register s1) { emit_int32(MTDSCR_OPCODE | rs(s1)); }
mfdscr(Register d)391 inline void Assembler::mfdscr(Register d ) { emit_int32(MFDSCR_OPCODE | rt(d)); }
392 // Transactional Memory Registers
mftfhar(Register d)393 inline void Assembler::mftfhar(Register d ) { emit_int32(MFTFHAR_OPCODE | rt(d)); }
mftfiar(Register d)394 inline void Assembler::mftfiar(Register d ) { emit_int32(MFTFIAR_OPCODE | rt(d)); }
mftexasr(Register d)395 inline void Assembler::mftexasr(Register d ) { emit_int32(MFTEXASR_OPCODE | rt(d)); }
mftexasru(Register d)396 inline void Assembler::mftexasru(Register d ) { emit_int32(MFTEXASRU_OPCODE | rt(d)); }
397
398 // SAP JVM 2006-02-13 PPC branch instruction.
399 // PPC 1, section 2.4.1 Branch Instructions
b(address a,relocInfo::relocType rt)400 inline void Assembler::b( address a, relocInfo::relocType rt) { emit_data(BXX_OPCODE| li(disp( intptr_t(a), intptr_t(pc()))) |aa(0)|lk(0), rt); }
b(Label & L)401 inline void Assembler::b( Label& L) { b( target(L)); }
bl(address a,relocInfo::relocType rt)402 inline void Assembler::bl(address a, relocInfo::relocType rt) { emit_data(BXX_OPCODE| li(disp( intptr_t(a), intptr_t(pc()))) |aa(0)|lk(1), rt); }
bl(Label & L)403 inline void Assembler::bl(Label& L) { bl(target(L)); }
bc(int boint,int biint,address a,relocInfo::relocType rt)404 inline void Assembler::bc( int boint, int biint, address a, relocInfo::relocType rt) { emit_data(BCXX_OPCODE| bo(boint) | bi(biint) | bd(disp( intptr_t(a), intptr_t(pc()))) | aa(0) | lk(0), rt); }
bc(int boint,int biint,Label & L)405 inline void Assembler::bc( int boint, int biint, Label& L) { bc(boint, biint, target(L)); }
bcl(int boint,int biint,address a,relocInfo::relocType rt)406 inline void Assembler::bcl(int boint, int biint, address a, relocInfo::relocType rt) { emit_data(BCXX_OPCODE| bo(boint) | bi(biint) | bd(disp( intptr_t(a), intptr_t(pc()))) | aa(0)|lk(1)); }
bcl(int boint,int biint,Label & L)407 inline void Assembler::bcl(int boint, int biint, Label& L) { bcl(boint, biint, target(L)); }
408
bclr(int boint,int biint,int bhint,relocInfo::relocType rt)409 inline void Assembler::bclr( int boint, int biint, int bhint, relocInfo::relocType rt) { emit_data(BCLR_OPCODE | bo(boint) | bi(biint) | bh(bhint) | aa(0) | lk(0), rt); }
bclrl(int boint,int biint,int bhint,relocInfo::relocType rt)410 inline void Assembler::bclrl( int boint, int biint, int bhint, relocInfo::relocType rt) { emit_data(BCLR_OPCODE | bo(boint) | bi(biint) | bh(bhint) | aa(0) | lk(1), rt); }
bcctr(int boint,int biint,int bhint,relocInfo::relocType rt)411 inline void Assembler::bcctr( int boint, int biint, int bhint, relocInfo::relocType rt) { emit_data(BCCTR_OPCODE| bo(boint) | bi(biint) | bh(bhint) | aa(0) | lk(0), rt); }
bcctrl(int boint,int biint,int bhint,relocInfo::relocType rt)412 inline void Assembler::bcctrl(int boint, int biint, int bhint, relocInfo::relocType rt) { emit_data(BCCTR_OPCODE| bo(boint) | bi(biint) | bh(bhint) | aa(0) | lk(1), rt); }
413
414 // helper function for b
is_within_range_of_b(address a,address pc)415 inline bool Assembler::is_within_range_of_b(address a, address pc) {
416 // Guard against illegal branch targets, e.g. -1 (see CompiledStaticCall and ad-file).
417 if ((((uint64_t)a) & 0x3) != 0) return false;
418
419 const int range = 1 << (29-6); // li field is from bit 6 to bit 29.
420 int value = disp(intptr_t(a), intptr_t(pc));
421 bool result = -range <= value && value < range-1;
422 #ifdef ASSERT
423 if (result) li(value); // Assert that value is in correct range.
424 #endif
425 return result;
426 }
427
428 // helper functions for bcxx.
is_within_range_of_bcxx(address a,address pc)429 inline bool Assembler::is_within_range_of_bcxx(address a, address pc) {
430 // Guard against illegal branch targets, e.g. -1 (see CompiledStaticCall and ad-file).
431 if ((((uint64_t)a) & 0x3) != 0) return false;
432
433 const int range = 1 << (29-16); // bd field is from bit 16 to bit 29.
434 int value = disp(intptr_t(a), intptr_t(pc));
435 bool result = -range <= value && value < range-1;
436 #ifdef ASSERT
437 if (result) bd(value); // Assert that value is in correct range.
438 #endif
439 return result;
440 }
441
442 // Get the destination of a bxx branch (b, bl, ba, bla).
bxx_destination(address baddr)443 address Assembler::bxx_destination(address baddr) { return bxx_destination(*(int*)baddr, baddr); }
bxx_destination(int instr,address pc)444 address Assembler::bxx_destination(int instr, address pc) { return (address)bxx_destination_offset(instr, (intptr_t)pc); }
bxx_destination_offset(int instr,intptr_t bxx_pos)445 intptr_t Assembler::bxx_destination_offset(int instr, intptr_t bxx_pos) {
446 intptr_t displ = inv_li_field(instr);
447 return bxx_pos + displ;
448 }
449
450 // Extended mnemonics for Branch Instructions
blt(ConditionRegister crx,Label & L)451 inline void Assembler::blt(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs1, bi0(crx, less), L); }
bgt(ConditionRegister crx,Label & L)452 inline void Assembler::bgt(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs1, bi0(crx, greater), L); }
beq(ConditionRegister crx,Label & L)453 inline void Assembler::beq(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs1, bi0(crx, equal), L); }
bso(ConditionRegister crx,Label & L)454 inline void Assembler::bso(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs1, bi0(crx, summary_overflow), L); }
bge(ConditionRegister crx,Label & L)455 inline void Assembler::bge(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs0, bi0(crx, less), L); }
ble(ConditionRegister crx,Label & L)456 inline void Assembler::ble(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs0, bi0(crx, greater), L); }
bne(ConditionRegister crx,Label & L)457 inline void Assembler::bne(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs0, bi0(crx, equal), L); }
bns(ConditionRegister crx,Label & L)458 inline void Assembler::bns(ConditionRegister crx, Label& L) { Assembler::bc(bcondCRbiIs0, bi0(crx, summary_overflow), L); }
459
460 // Branch instructions with static prediction hints.
blt_predict_taken(ConditionRegister crx,Label & L)461 inline void Assembler::blt_predict_taken (ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsTaken, bi0(crx, less), L); }
bgt_predict_taken(ConditionRegister crx,Label & L)462 inline void Assembler::bgt_predict_taken (ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsTaken, bi0(crx, greater), L); }
beq_predict_taken(ConditionRegister crx,Label & L)463 inline void Assembler::beq_predict_taken (ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsTaken, bi0(crx, equal), L); }
bso_predict_taken(ConditionRegister crx,Label & L)464 inline void Assembler::bso_predict_taken (ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsTaken, bi0(crx, summary_overflow), L); }
bge_predict_taken(ConditionRegister crx,Label & L)465 inline void Assembler::bge_predict_taken (ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsTaken, bi0(crx, less), L); }
ble_predict_taken(ConditionRegister crx,Label & L)466 inline void Assembler::ble_predict_taken (ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsTaken, bi0(crx, greater), L); }
bne_predict_taken(ConditionRegister crx,Label & L)467 inline void Assembler::bne_predict_taken (ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsTaken, bi0(crx, equal), L); }
bns_predict_taken(ConditionRegister crx,Label & L)468 inline void Assembler::bns_predict_taken (ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsTaken, bi0(crx, summary_overflow), L); }
blt_predict_not_taken(ConditionRegister crx,Label & L)469 inline void Assembler::blt_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsNotTaken, bi0(crx, less), L); }
bgt_predict_not_taken(ConditionRegister crx,Label & L)470 inline void Assembler::bgt_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsNotTaken, bi0(crx, greater), L); }
beq_predict_not_taken(ConditionRegister crx,Label & L)471 inline void Assembler::beq_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsNotTaken, bi0(crx, equal), L); }
bso_predict_not_taken(ConditionRegister crx,Label & L)472 inline void Assembler::bso_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs1_bhintIsNotTaken, bi0(crx, summary_overflow), L); }
bge_predict_not_taken(ConditionRegister crx,Label & L)473 inline void Assembler::bge_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsNotTaken, bi0(crx, less), L); }
ble_predict_not_taken(ConditionRegister crx,Label & L)474 inline void Assembler::ble_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsNotTaken, bi0(crx, greater), L); }
bne_predict_not_taken(ConditionRegister crx,Label & L)475 inline void Assembler::bne_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsNotTaken, bi0(crx, equal), L); }
bns_predict_not_taken(ConditionRegister crx,Label & L)476 inline void Assembler::bns_predict_not_taken(ConditionRegister crx, Label& L) { bc(bcondCRbiIs0_bhintIsNotTaken, bi0(crx, summary_overflow), L); }
477
478 // For use in conjunction with testbitdi:
btrue(ConditionRegister crx,Label & L)479 inline void Assembler::btrue( ConditionRegister crx, Label& L) { Assembler::bne(crx, L); }
bfalse(ConditionRegister crx,Label & L)480 inline void Assembler::bfalse(ConditionRegister crx, Label& L) { Assembler::beq(crx, L); }
481
bltl(ConditionRegister crx,Label & L)482 inline void Assembler::bltl(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs1, bi0(crx, less), L); }
bgtl(ConditionRegister crx,Label & L)483 inline void Assembler::bgtl(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs1, bi0(crx, greater), L); }
beql(ConditionRegister crx,Label & L)484 inline void Assembler::beql(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs1, bi0(crx, equal), L); }
bsol(ConditionRegister crx,Label & L)485 inline void Assembler::bsol(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs1, bi0(crx, summary_overflow), L); }
bgel(ConditionRegister crx,Label & L)486 inline void Assembler::bgel(ConditionRegister crx, Label& L) { Assembler::bcl(bcondCRbiIs0, bi0(crx, less), L); }
blel(ConditionRegister crx,Label & L)487