1 /*
2  * Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved.
3  * Copyright (c) 2019 SAP SE. All rights reserved.
4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5  *
6  * This code is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 only, as
8  * published by the Free Software Foundation.
9  *
10  * This code is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * version 2 for more details (a copy is included in the LICENSE file that
14  * accompanied this code).
15  *
16  * You should have received a copy of the GNU General Public License version
17  * 2 along with this work; if not, write to the Free Software Foundation,
18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19  *
20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21  * or visit www.oracle.com if you need additional information or have any
22  * questions.
23  *
24  */
25 
26 #include "asm/macroAssembler.inline.hpp"
27 #include "code/codeCache.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "depChecker_ppc.hpp"
30 #include "gc/shared/collectedHeap.hpp"
31 #include "gc/shared/cardTableBarrierSet.hpp"
32 #include "gc/shared/genOopClosures.inline.hpp"
33 #include "oops/oop.inline.hpp"
34 #include "runtime/handles.inline.hpp"
35 #include "runtime/stubCodeGenerator.hpp"
36 #include "runtime/stubRoutines.hpp"
37 
38 // Macro to print instruction bits.
39 // numbering of instruction bits on ppc64 is (highest) 0 1 ... 30 31 (lowest).
40 #define print_instruction_bits(st, instruction, start_bit, end_bit) \
41   { assert((start_bit) <= (end_bit), "sanity check"); \
42     for (int i=(31-(start_bit));i>=(31-(end_bit));i--) { \
43       (st)->print("%d", ((instruction) >> i) & 0x1); \
44     } \
45   }
46 
47 // Macro to decode "bo" instruction bits.
48 #define print_decoded_bo_bits(env, instruction, end_bit) \
49   { int bo_bits = (instruction >> (31 - (end_bit))) & 0x1f; \
50     if ( ((bo_bits & 0x1c) == 0x4) || ((bo_bits & 0x1c) == 0xc) ) { \
51       switch (bo_bits & 0x3) { \
52         case (0 << 1) | (0 << 0): env->print("[no_hint]"); break; \
53         case (0 << 1) | (1 << 0): env->print("[reserved]"); break; \
54         case (1 << 1) | (0 << 0): env->print("[not_taken]"); break; \
55         case (1 << 1) | (1 << 0): env->print("[taken]"); break; \
56         default: break; \
57       } \
58     } else if ( ((bo_bits & 0x14) == 0x10) ) { \
59       switch (bo_bits & 0x9) { \
60         case (0 << 3) | (0 << 0): env->print("[no_hint]"); break; \
61         case (0 << 3) | (1 << 0): env->print("[reserved]"); break; \
62         case (1 << 3) | (0 << 0): env->print("[not_taken]"); break; \
63         case (1 << 3) | (1 << 0): env->print("[taken]"); break; \
64         default: break; \
65       } \
66     } \
67   }
68 
69 // Macro to decode "bh" instruction bits.
70 #define print_decoded_bh_bits(env, instruction, end_bit, is_bclr) \
71   { int bh_bits = (instruction >> (31 - (end_bit))) & 0x3; \
72     if (is_bclr) { \
73       switch (bh_bits) { \
74         case (0 << 1) | (0 << 0): env->print("[subroutine_return]"); break; \
75         case (0 << 1) | (1 << 0): env->print("[not_return_but_same]"); break; \
76         case (1 << 1) | (0 << 0): env->print("[reserved]"); break; \
77         case (1 << 1) | (1 << 0): env->print("[not_predictable]"); break; \
78         default: break; \
79       } \
80     } else { \
81       switch (bh_bits) { \
82         case (0 << 1) | (0 << 0): env->print("[not_return_but_same]"); break; \
83         case (0 << 1) | (1 << 0): env->print("[reserved]"); break; \
84         case (1 << 1) | (0 << 0): env->print("[reserved]"); break; \
85         case (1 << 1) | (1 << 0): env->print("[not_predictable]"); break; \
86         default: break; \
87       } \
88     } \
89   }
90 
find_prev_instr(address here,int n_instr)91 address Disassembler::find_prev_instr(address here, int n_instr) {
92   if (!os::is_readable_pointer(here)) return NULL;    // obviously a bad location to decode
93 
94   // Find most distant possible starting point.
95   // Narrow down because we don't want to SEGV while printing.
96   address start = here - n_instr*Assembler::instr_maxlen(); // starting point can't be further away.
97   while ((start < here) && !os::is_readable_range(start, here)) {
98     start = align_down(start, os::min_page_size()) + os::min_page_size();
99   }
100   if (start >= here) {
101     // Strange. Can only happen with here on page boundary.
102     return NULL;
103   }
104   return start;
105 }
106 
decode_instruction0(address here,outputStream * st,address virtual_begin)107 address Disassembler::decode_instruction0(address here, outputStream * st, address virtual_begin ) {
108   if (is_abstract()) {
109     // The disassembler library was not loaded (yet),
110     // use AbstractDisassembler's decode method.
111     return decode_instruction_abstract(here, st, Assembler::instr_len(here), Assembler::instr_maxlen());
112   }
113 
114   // Currently, "special decoding" doesn't work when decoding error files.
115   // When decoding an instruction from a hs_err file, the given
116   // instruction address 'start' points to the instruction's virtual address
117   // which is not equal to the address where the instruction is located.
118   // Therefore, we will either crash or decode garbage.
119   if (is_decode_error_file()) {
120     return here;
121   }
122 
123   //---<  Decode some well-known "instructions"  >---
124 
125   address  next;
126   uint32_t instruction = *(uint32_t*)here;
127 
128   // Align at next tab position.
129   const uint tabspacing  = 8;
130   const uint pos         = st->position();
131   const uint aligned_pos = ((pos+tabspacing-1)/tabspacing)*tabspacing;
132   st->fill_to(aligned_pos);
133 
134   if (instruction == 0x0) {
135     st->print("illtrap .data 0x0");
136     next = here + Assembler::instr_len(here);
137   } else if (instruction == 0xbadbabe) {
138     st->print(".data 0xbadbabe");
139     next = here + Assembler::instr_len(here);
140   } else if (Assembler::is_endgroup(instruction)) {
141     st->print("endgroup");
142     next = here + Assembler::instr_len(here);
143   } else {
144     next = here;
145   }
146   return next;
147 }
148 
149 // print annotations (instruction control bits)
annotate(address here,outputStream * st)150 void Disassembler::annotate(address here, outputStream* st) {
151   // Currently, annotation doesn't work when decoding error files.
152   // When decoding an instruction from a hs_err file, the given
153   // instruction address 'start' points to the instruction's virtual address
154   // which is not equal to the address where the instruction is located.
155   // Therefore, we will either crash or decode garbage.
156   if (is_decode_error_file()) {
157     return;
158   }
159 
160   uint32_t   instruction = *(uint32_t*)here;
161 
162   // Align at next tab position.
163   const uint tabspacing  = 8;
164   const uint pos         = st->position();
165   const uint aligned_pos = ((pos+tabspacing-1)/tabspacing)*tabspacing;
166 
167   int stop_type = -1;
168 
169   if (MacroAssembler::is_bcxx(instruction)) {
170     st->print(",bo=0b");
171     print_instruction_bits(st, instruction, 6, 10);
172     print_decoded_bo_bits(st, instruction, 10);
173   } else if (MacroAssembler::is_bctr(instruction) ||
174              MacroAssembler::is_bctrl(instruction) ||
175              MacroAssembler::is_bclr(instruction)) {
176     st->fill_to(aligned_pos);
177     st->print("bo=0b");
178     print_instruction_bits(st, instruction, 6, 10);
179     print_decoded_bo_bits(st, instruction, 10);
180     st->print(",bh=0b");
181     print_instruction_bits(st, instruction, 19, 20);
182     print_decoded_bh_bits(st, instruction, 20,
183                           !(MacroAssembler::is_bctr(instruction) ||
184                             MacroAssembler::is_bctrl(instruction)));
185   } else if (MacroAssembler::is_trap_null_check(instruction)) {
186     st->fill_to(aligned_pos + tabspacing);
187     st->print(";trap: null check");
188   } else if (MacroAssembler::is_trap_range_check(instruction)) {
189     st->fill_to(aligned_pos + tabspacing);
190     st->print(";trap: range check");
191   } else if (MacroAssembler::is_trap_ic_miss_check(instruction)) {
192     st->fill_to(aligned_pos + tabspacing);
193     st->print(";trap: ic miss check");
194   } else if ((stop_type = MacroAssembler::tdi_get_si16(instruction, Assembler::traptoUnconditional, 0)) != -1) {
195     bool msg_present = (stop_type & MacroAssembler::stop_msg_present);
196     stop_type = (stop_type &~ MacroAssembler::stop_msg_present);
197     const char **detail_msg_ptr = (const char**)(here + 4);
198     st->fill_to(aligned_pos + tabspacing);
199     st->print(";trap: stop type %d: %s", stop_type, msg_present ? *detail_msg_ptr : "no details provided");
200   }
201 }
202