1// 2// Copyright (c) 2008, 2013, Oracle and/or its affiliates. All rights reserved. 3// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4// 5// This code is free software; you can redistribute it and/or modify it 6// under the terms of the GNU General Public License version 2 only, as 7// published by the Free Software Foundation. 8// 9// This code is distributed in the hope that it will be useful, but WITHOUT 10// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12// version 2 for more details (a copy is included in the LICENSE file that 13// accompanied this code). 14// 15// You should have received a copy of the GNU General Public License version 16// 2 along with this work; if not, write to the Free Software Foundation, 17// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18// 19// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20// or visit www.oracle.com if you need additional information or have any 21// questions. 22// 23 24// ARM Architecture Description File 25 26//----------REGISTER DEFINITION BLOCK------------------------------------------ 27// This information is used by the matcher and the register allocator to 28// describe individual registers and classes of registers within the target 29// archtecture. 30register %{ 31//----------Architecture Description Register Definitions---------------------- 32// General Registers 33// "reg_def" name ( register save type, C convention save type, 34// ideal register type, encoding, vm name ); 35// Register Save Types: 36// 37// NS = No-Save: The register allocator assumes that these registers 38// can be used without saving upon entry to the method, & 39// that they do not need to be saved at call sites. 40// 41// SOC = Save-On-Call: The register allocator assumes that these registers 42// can be used without saving upon entry to the method, 43// but that they must be saved at call sites. 44// 45// SOE = Save-On-Entry: The register allocator assumes that these registers 46// must be saved before using them upon entry to the 47// method, but they do not need to be saved at call 48// sites. 49// 50// AS = Always-Save: The register allocator assumes that these registers 51// must be saved before using them upon entry to the 52// method, & that they must be saved at call sites. 53// 54// Ideal Register Type is used to determine how to save & restore a 55// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 56// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 57// 58// The encoding number is the actual bit-pattern placed into the opcodes. 59 60 61// ---------------------------- 62// Integer/Long Registers 63// ---------------------------- 64 65reg_def R_R0 (SOC, SOC, Op_RegI, 0, R(0)->as_VMReg()); 66reg_def R_R1 (SOC, SOC, Op_RegI, 1, R(1)->as_VMReg()); 67reg_def R_R2 (SOC, SOC, Op_RegI, 2, R(2)->as_VMReg()); 68reg_def R_R3 (SOC, SOC, Op_RegI, 3, R(3)->as_VMReg()); 69reg_def R_R4 (SOC, SOE, Op_RegI, 4, R(4)->as_VMReg()); 70reg_def R_R5 (SOC, SOE, Op_RegI, 5, R(5)->as_VMReg()); 71reg_def R_R6 (SOC, SOE, Op_RegI, 6, R(6)->as_VMReg()); 72reg_def R_R7 (SOC, SOE, Op_RegI, 7, R(7)->as_VMReg()); 73reg_def R_R8 (SOC, SOE, Op_RegI, 8, R(8)->as_VMReg()); 74reg_def R_R9 (SOC, SOE, Op_RegI, 9, R(9)->as_VMReg()); 75reg_def R_R10(NS, SOE, Op_RegI, 10, R(10)->as_VMReg()); 76reg_def R_R11(NS, SOE, Op_RegI, 11, R(11)->as_VMReg()); 77reg_def R_R12(SOC, SOC, Op_RegI, 12, R(12)->as_VMReg()); 78reg_def R_R13(NS, NS, Op_RegI, 13, R(13)->as_VMReg()); 79reg_def R_R14(SOC, SOC, Op_RegI, 14, R(14)->as_VMReg()); 80reg_def R_R15(NS, NS, Op_RegI, 15, R(15)->as_VMReg()); 81 82// ---------------------------- 83// Float/Double Registers 84// ---------------------------- 85 86// Float Registers 87 88reg_def R_S0 ( SOC, SOC, Op_RegF, 0, S0->as_VMReg()); 89reg_def R_S1 ( SOC, SOC, Op_RegF, 1, S1_reg->as_VMReg()); 90reg_def R_S2 ( SOC, SOC, Op_RegF, 2, S2_reg->as_VMReg()); 91reg_def R_S3 ( SOC, SOC, Op_RegF, 3, S3_reg->as_VMReg()); 92reg_def R_S4 ( SOC, SOC, Op_RegF, 4, S4_reg->as_VMReg()); 93reg_def R_S5 ( SOC, SOC, Op_RegF, 5, S5_reg->as_VMReg()); 94reg_def R_S6 ( SOC, SOC, Op_RegF, 6, S6_reg->as_VMReg()); 95reg_def R_S7 ( SOC, SOC, Op_RegF, 7, S7->as_VMReg()); 96reg_def R_S8 ( SOC, SOC, Op_RegF, 8, S8->as_VMReg()); 97reg_def R_S9 ( SOC, SOC, Op_RegF, 9, S9->as_VMReg()); 98reg_def R_S10( SOC, SOC, Op_RegF, 10,S10->as_VMReg()); 99reg_def R_S11( SOC, SOC, Op_RegF, 11,S11->as_VMReg()); 100reg_def R_S12( SOC, SOC, Op_RegF, 12,S12->as_VMReg()); 101reg_def R_S13( SOC, SOC, Op_RegF, 13,S13->as_VMReg()); 102reg_def R_S14( SOC, SOC, Op_RegF, 14,S14->as_VMReg()); 103reg_def R_S15( SOC, SOC, Op_RegF, 15,S15->as_VMReg()); 104reg_def R_S16( SOC, SOE, Op_RegF, 16,S16->as_VMReg()); 105reg_def R_S17( SOC, SOE, Op_RegF, 17,S17->as_VMReg()); 106reg_def R_S18( SOC, SOE, Op_RegF, 18,S18->as_VMReg()); 107reg_def R_S19( SOC, SOE, Op_RegF, 19,S19->as_VMReg()); 108reg_def R_S20( SOC, SOE, Op_RegF, 20,S20->as_VMReg()); 109reg_def R_S21( SOC, SOE, Op_RegF, 21,S21->as_VMReg()); 110reg_def R_S22( SOC, SOE, Op_RegF, 22,S22->as_VMReg()); 111reg_def R_S23( SOC, SOE, Op_RegF, 23,S23->as_VMReg()); 112reg_def R_S24( SOC, SOE, Op_RegF, 24,S24->as_VMReg()); 113reg_def R_S25( SOC, SOE, Op_RegF, 25,S25->as_VMReg()); 114reg_def R_S26( SOC, SOE, Op_RegF, 26,S26->as_VMReg()); 115reg_def R_S27( SOC, SOE, Op_RegF, 27,S27->as_VMReg()); 116reg_def R_S28( SOC, SOE, Op_RegF, 28,S28->as_VMReg()); 117reg_def R_S29( SOC, SOE, Op_RegF, 29,S29->as_VMReg()); 118reg_def R_S30( SOC, SOE, Op_RegF, 30,S30->as_VMReg()); 119reg_def R_S31( SOC, SOE, Op_RegF, 31,S31->as_VMReg()); 120 121// Double Registers 122// The rules of ADL require that double registers be defined in pairs. 123// Each pair must be two 32-bit values, but not necessarily a pair of 124// single float registers. In each pair, ADLC-assigned register numbers 125// must be adjacent, with the lower number even. Finally, when the 126// CPU stores such a register pair to memory, the word associated with 127// the lower ADLC-assigned number must be stored to the lower address. 128 129reg_def R_D16 (SOC, SOC, Op_RegD, 32, D16->as_VMReg()); 130reg_def R_D16x(SOC, SOC, Op_RegD,255, D16->as_VMReg()->next()); 131reg_def R_D17 (SOC, SOC, Op_RegD, 34, D17->as_VMReg()); 132reg_def R_D17x(SOC, SOC, Op_RegD,255, D17->as_VMReg()->next()); 133reg_def R_D18 (SOC, SOC, Op_RegD, 36, D18->as_VMReg()); 134reg_def R_D18x(SOC, SOC, Op_RegD,255, D18->as_VMReg()->next()); 135reg_def R_D19 (SOC, SOC, Op_RegD, 38, D19->as_VMReg()); 136reg_def R_D19x(SOC, SOC, Op_RegD,255, D19->as_VMReg()->next()); 137reg_def R_D20 (SOC, SOC, Op_RegD, 40, D20->as_VMReg()); 138reg_def R_D20x(SOC, SOC, Op_RegD,255, D20->as_VMReg()->next()); 139reg_def R_D21 (SOC, SOC, Op_RegD, 42, D21->as_VMReg()); 140reg_def R_D21x(SOC, SOC, Op_RegD,255, D21->as_VMReg()->next()); 141reg_def R_D22 (SOC, SOC, Op_RegD, 44, D22->as_VMReg()); 142reg_def R_D22x(SOC, SOC, Op_RegD,255, D22->as_VMReg()->next()); 143reg_def R_D23 (SOC, SOC, Op_RegD, 46, D23->as_VMReg()); 144reg_def R_D23x(SOC, SOC, Op_RegD,255, D23->as_VMReg()->next()); 145reg_def R_D24 (SOC, SOC, Op_RegD, 48, D24->as_VMReg()); 146reg_def R_D24x(SOC, SOC, Op_RegD,255, D24->as_VMReg()->next()); 147reg_def R_D25 (SOC, SOC, Op_RegD, 50, D25->as_VMReg()); 148reg_def R_D25x(SOC, SOC, Op_RegD,255, D25->as_VMReg()->next()); 149reg_def R_D26 (SOC, SOC, Op_RegD, 52, D26->as_VMReg()); 150reg_def R_D26x(SOC, SOC, Op_RegD,255, D26->as_VMReg()->next()); 151reg_def R_D27 (SOC, SOC, Op_RegD, 54, D27->as_VMReg()); 152reg_def R_D27x(SOC, SOC, Op_RegD,255, D27->as_VMReg()->next()); 153reg_def R_D28 (SOC, SOC, Op_RegD, 56, D28->as_VMReg()); 154reg_def R_D28x(SOC, SOC, Op_RegD,255, D28->as_VMReg()->next()); 155reg_def R_D29 (SOC, SOC, Op_RegD, 58, D29->as_VMReg()); 156reg_def R_D29x(SOC, SOC, Op_RegD,255, D29->as_VMReg()->next()); 157reg_def R_D30 (SOC, SOC, Op_RegD, 60, D30->as_VMReg()); 158reg_def R_D30x(SOC, SOC, Op_RegD,255, D30->as_VMReg()->next()); 159reg_def R_D31 (SOC, SOC, Op_RegD, 62, D31->as_VMReg()); 160reg_def R_D31x(SOC, SOC, Op_RegD,255, D31->as_VMReg()->next()); 161 162// ---------------------------- 163// Special Registers 164// Condition Codes Flag Registers 165reg_def APSR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 166reg_def FPSCR(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 167 168// ---------------------------- 169// Specify the enum values for the registers. These enums are only used by the 170// OptoReg "class". We can convert these enum values at will to VMReg when needed 171// for visibility to the rest of the vm. The order of this enum influences the 172// register allocator so having the freedom to set this order and not be stuck 173// with the order that is natural for the rest of the vm is worth it. 174 175// registers in that order so that R11/R12 is an aligned pair that can be used for longs 176alloc_class chunk0( 177 R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R11, R_R12, R_R10, R_R13, R_R14, R_R15, R_R0, R_R1, R_R2, R_R3); 178 179// Note that a register is not allocatable unless it is also mentioned 180// in a widely-used reg_class below. 181 182alloc_class chunk1( 183 R_S16, R_S17, R_S18, R_S19, R_S20, R_S21, R_S22, R_S23, 184 R_S24, R_S25, R_S26, R_S27, R_S28, R_S29, R_S30, R_S31, 185 R_S0, R_S1, R_S2, R_S3, R_S4, R_S5, R_S6, R_S7, 186 R_S8, R_S9, R_S10, R_S11, R_S12, R_S13, R_S14, R_S15, 187 R_D16, R_D16x,R_D17, R_D17x,R_D18, R_D18x,R_D19, R_D19x, 188 R_D20, R_D20x,R_D21, R_D21x,R_D22, R_D22x,R_D23, R_D23x, 189 R_D24, R_D24x,R_D25, R_D25x,R_D26, R_D26x,R_D27, R_D27x, 190 R_D28, R_D28x,R_D29, R_D29x,R_D30, R_D30x,R_D31, R_D31x 191); 192 193alloc_class chunk2(APSR, FPSCR); 194 195//----------Architecture Description Register Classes-------------------------- 196// Several register classes are automatically defined based upon information in 197// this architecture description. 198// 1) reg_class inline_cache_reg ( as defined in frame section ) 199// 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 200// 201 202// ---------------------------- 203// Integer Register Classes 204// ---------------------------- 205// Exclusions from i_reg: 206// SP (R13), PC (R15) 207// R10: reserved by HotSpot to the TLS register (invariant within Java) 208reg_class int_reg(R_R0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R11, R_R12, R_R14); 209 210reg_class R0_regI(R_R0); 211reg_class R1_regI(R_R1); 212reg_class R2_regI(R_R2); 213reg_class R3_regI(R_R3); 214reg_class R12_regI(R_R12); 215 216// ---------------------------- 217// Pointer Register Classes 218// ---------------------------- 219reg_class ptr_reg(R_R0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R11, R_R12, R_R14); 220// Special class for storeP instructions, which can store SP or RPC to TLS. 221// It is also used for memory addressing, allowing direct TLS addressing. 222reg_class sp_ptr_reg(R_R0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R11, R_R12, R_R14, R_R10 /* TLS*/, R_R13 /* SP*/); 223 224#define R_Ricklass R_R8 225#define R_Rthread R_R10 226#define R_Rexception_obj R_R4 227 228// Other special pointer regs 229reg_class R0_regP(R_R0); 230reg_class R1_regP(R_R1); 231reg_class R2_regP(R_R2); 232reg_class R4_regP(R_R4); 233reg_class R8_regP(R_R8); 234reg_class R9_regP(R_R9); 235reg_class R12_regP(R_R12); 236reg_class Rexception_regP(R_Rexception_obj); 237reg_class Ricklass_regP(R_Ricklass); 238reg_class Rthread_regP(R_Rthread); 239reg_class IP_regP(R_R12); 240reg_class SP_regP(R_R13); 241reg_class LR_regP(R_R14); 242 243reg_class FP_regP(R_R11); 244 245// ---------------------------- 246// Long Register Classes 247// ---------------------------- 248reg_class long_reg ( R_R0,R_R1, R_R2,R_R3, R_R4,R_R5, R_R6,R_R7, R_R8,R_R9, R_R11,R_R12); 249// for ldrexd, strexd: first reg of pair must be even 250reg_class long_reg_align ( R_R0,R_R1, R_R2,R_R3, R_R4,R_R5, R_R6,R_R7, R_R8,R_R9); 251 252reg_class R0R1_regL(R_R0,R_R1); 253reg_class R2R3_regL(R_R2,R_R3); 254 255// ---------------------------- 256// Special Class for Condition Code Flags Register 257reg_class int_flags(APSR); 258reg_class float_flags(FPSCR); 259 260 261// ---------------------------- 262// Float Point Register Classes 263// ---------------------------- 264// Skip S14/S15, they are reserved for mem-mem copies 265reg_class sflt_reg(R_S0, R_S1, R_S2, R_S3, R_S4, R_S5, R_S6, R_S7, R_S8, R_S9, R_S10, R_S11, R_S12, R_S13, 266 R_S16, R_S17, R_S18, R_S19, R_S20, R_S21, R_S22, R_S23, R_S24, R_S25, R_S26, R_S27, R_S28, R_S29, R_S30, R_S31); 267 268// Paired floating point registers--they show up in the same order as the floats, 269// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 270reg_class dflt_reg(R_S0,R_S1, R_S2,R_S3, R_S4,R_S5, R_S6,R_S7, R_S8,R_S9, R_S10,R_S11, R_S12,R_S13, 271 R_S16,R_S17, R_S18,R_S19, R_S20,R_S21, R_S22,R_S23, R_S24,R_S25, R_S26,R_S27, R_S28,R_S29, R_S30,R_S31, 272 R_D16,R_D16x, R_D17,R_D17x, R_D18,R_D18x, R_D19,R_D19x, R_D20,R_D20x, R_D21,R_D21x, R_D22,R_D22x, 273 R_D23,R_D23x, R_D24,R_D24x, R_D25,R_D25x, R_D26,R_D26x, R_D27,R_D27x, R_D28,R_D28x, R_D29,R_D29x, 274 R_D30,R_D30x, R_D31,R_D31x); 275 276reg_class dflt_low_reg(R_S0,R_S1, R_S2,R_S3, R_S4,R_S5, R_S6,R_S7, R_S8,R_S9, R_S10,R_S11, R_S12,R_S13, 277 R_S16,R_S17, R_S18,R_S19, R_S20,R_S21, R_S22,R_S23, R_S24,R_S25, R_S26,R_S27, R_S28,R_S29, R_S30,R_S31); 278 279 280reg_class actual_dflt_reg %{ 281 if (VM_Version::has_vfp3_32()) { 282 return DFLT_REG_mask(); 283 } else { 284 return DFLT_LOW_REG_mask(); 285 } 286%} 287 288reg_class S0_regF(R_S0); 289reg_class D0_regD(R_S0,R_S1); 290reg_class D1_regD(R_S2,R_S3); 291reg_class D2_regD(R_S4,R_S5); 292reg_class D3_regD(R_S6,R_S7); 293reg_class D4_regD(R_S8,R_S9); 294reg_class D5_regD(R_S10,R_S11); 295reg_class D6_regD(R_S12,R_S13); 296reg_class D7_regD(R_S14,R_S15); 297 298reg_class D16_regD(R_D16,R_D16x); 299reg_class D17_regD(R_D17,R_D17x); 300reg_class D18_regD(R_D18,R_D18x); 301reg_class D19_regD(R_D19,R_D19x); 302reg_class D20_regD(R_D20,R_D20x); 303reg_class D21_regD(R_D21,R_D21x); 304reg_class D22_regD(R_D22,R_D22x); 305reg_class D23_regD(R_D23,R_D23x); 306reg_class D24_regD(R_D24,R_D24x); 307reg_class D25_regD(R_D25,R_D25x); 308reg_class D26_regD(R_D26,R_D26x); 309reg_class D27_regD(R_D27,R_D27x); 310reg_class D28_regD(R_D28,R_D28x); 311reg_class D29_regD(R_D29,R_D29x); 312reg_class D30_regD(R_D30,R_D30x); 313reg_class D31_regD(R_D31,R_D31x); 314 315reg_class vectorx_reg(R_S0,R_S1,R_S2,R_S3, R_S4,R_S5,R_S6,R_S7, 316 R_S8,R_S9,R_S10,R_S11, /* skip S14/S15 */ 317 R_S16,R_S17,R_S18,R_S19, R_S20,R_S21,R_S22,R_S23, 318 R_S24,R_S25,R_S26,R_S27, R_S28,R_S29,R_S30,R_S31, 319 R_D16,R_D16x,R_D17,R_D17x, R_D18,R_D18x,R_D19,R_D19x, 320 R_D20,R_D20x,R_D21,R_D21x, R_D22,R_D22x,R_D23,R_D23x, 321 R_D24,R_D24x,R_D25,R_D25x, R_D26,R_D26x,R_D27,R_D27x, 322 R_D28,R_D28x,R_D29,R_D29x, R_D30,R_D30x,R_D31,R_D31x); 323 324%} 325 326source_hpp %{ 327// FIXME 328const MachRegisterNumbers R_mem_copy_lo_num = R_S14_num; 329const MachRegisterNumbers R_mem_copy_hi_num = R_S15_num; 330const FloatRegister Rmemcopy = S14; 331const MachRegisterNumbers R_hf_ret_lo_num = R_S0_num; 332const MachRegisterNumbers R_hf_ret_hi_num = R_S1_num; 333 334const MachRegisterNumbers R_Ricklass_num = R_R8_num; 335const MachRegisterNumbers R_Rmethod_num = R_R9_num; 336 337#define LDR_DOUBLE "FLDD" 338#define LDR_FLOAT "FLDS" 339#define STR_DOUBLE "FSTD" 340#define STR_FLOAT "FSTS" 341#define LDR_64 "LDRD" 342#define STR_64 "STRD" 343#define LDR_32 "LDR" 344#define STR_32 "STR" 345#define MOV_DOUBLE "FCPYD" 346#define MOV_FLOAT "FCPYS" 347#define FMSR "FMSR" 348#define FMRS "FMRS" 349#define LDREX "ldrex " 350#define STREX "strex " 351 352#define str_64 strd 353#define ldr_64 ldrd 354#define ldr_32 ldr 355#define ldrex ldrex 356#define strex strex 357 358static inline bool is_memoryD(int offset) { 359 return offset < 1024 && offset > -1024; 360} 361 362static inline bool is_memoryfp(int offset) { 363 return offset < 1024 && offset > -1024; 364} 365 366static inline bool is_memoryI(int offset) { 367 return offset < 4096 && offset > -4096; 368} 369 370static inline bool is_memoryP(int offset) { 371 return offset < 4096 && offset > -4096; 372} 373 374static inline bool is_memoryHD(int offset) { 375 return offset < 256 && offset > -256; 376} 377 378static inline bool is_aimm(int imm) { 379 return AsmOperand::is_rotated_imm(imm); 380} 381 382static inline bool is_limmI(jint imm) { 383 return AsmOperand::is_rotated_imm(imm); 384} 385 386static inline bool is_limmI_low(jint imm, int n) { 387 int imml = imm & right_n_bits(n); 388 return is_limmI(imml) || is_limmI(imm); 389} 390 391static inline int limmI_low(jint imm, int n) { 392 int imml = imm & right_n_bits(n); 393 return is_limmI(imml) ? imml : imm; 394} 395 396%} 397 398source %{ 399 400// Given a register encoding, produce a Integer Register object 401static Register reg_to_register_object(int register_encoding) { 402 assert(R0->encoding() == R_R0_enc && R15->encoding() == R_R15_enc, "right coding"); 403 return as_Register(register_encoding); 404} 405 406// Given a register encoding, produce a single-precision Float Register object 407static FloatRegister reg_to_FloatRegister_object(int register_encoding) { 408 assert(S0->encoding() == R_S0_enc && S31->encoding() == R_S31_enc, "right coding"); 409 return as_FloatRegister(register_encoding); 410} 411 412void Compile::pd_compiler2_init() { 413 // Umimplemented 414} 415 416// Location of compiled Java return values. Same as C 417OptoRegPair c2::return_value(int ideal_reg) { 418 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 419#ifndef __ABI_HARD__ 420 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, R_R0_num, R_R0_num, R_R0_num, R_R0_num, R_R0_num }; 421 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_R1_num, R_R1_num }; 422#else 423 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, R_R0_num, R_R0_num, R_hf_ret_lo_num, R_hf_ret_lo_num, R_R0_num }; 424 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_hf_ret_hi_num, R_R1_num }; 425#endif 426 return OptoRegPair( hi[ideal_reg], lo[ideal_reg]); 427} 428 429// !!!!! Special hack to get all type of calls to specify the byte offset 430// from the start of the call to the point where the return address 431// will point. 432 433int MachCallStaticJavaNode::ret_addr_offset() { 434 bool far = (_method == NULL) ? maybe_far_call(this) : !cache_reachable(); 435 return ((far ? 3 : 1) + (_method_handle_invoke ? 1 : 0)) * 436 NativeInstruction::instruction_size; 437} 438 439int MachCallDynamicJavaNode::ret_addr_offset() { 440 bool far = !cache_reachable(); 441 // mov_oop is always 2 words 442 return (2 + (far ? 3 : 1)) * NativeInstruction::instruction_size; 443} 444 445int MachCallRuntimeNode::ret_addr_offset() { 446 // bl or movw; movt; blx 447 bool far = maybe_far_call(this); 448 return (far ? 3 : 1) * NativeInstruction::instruction_size; 449} 450 451int MachCallNativeNode::ret_addr_offset() { 452 Unimplemented(); 453 return -1; 454} 455%} 456 457// The intptr_t operand types, defined by textual substitution. 458// (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 459#define immX immI 460#define immXRot immIRot 461#define iRegX iRegI 462#define aimmX aimmI 463#define limmX limmI 464#define immX10x2 immI10x2 465#define LShiftX LShiftI 466#define shimmX immU5 467 468// Compatibility interface 469#define aimmP immPRot 470#define immIMov immIRot 471 472#define store_RegL iRegL 473#define store_RegLd iRegLd 474#define store_RegI iRegI 475#define store_ptr_RegP iRegP 476 477//----------ATTRIBUTES--------------------------------------------------------- 478//----------Operand Attributes------------------------------------------------- 479op_attrib op_cost(1); // Required cost attribute 480 481//----------OPERANDS----------------------------------------------------------- 482// Operand definitions must precede instruction definitions for correct parsing 483// in the ADLC because operands constitute user defined types which are used in 484// instruction definitions. 485 486//----------Simple Operands---------------------------------------------------- 487// Immediate Operands 488 489operand immIRot() %{ 490 predicate(AsmOperand::is_rotated_imm(n->get_int())); 491 match(ConI); 492 493 op_cost(0); 494 // formats are generated automatically for constants and base registers 495 format %{ %} 496 interface(CONST_INTER); 497%} 498 499operand immIRotn() %{ 500 predicate(n->get_int() != 0 && AsmOperand::is_rotated_imm(~n->get_int())); 501 match(ConI); 502 503 op_cost(0); 504 // formats are generated automatically for constants and base registers 505 format %{ %} 506 interface(CONST_INTER); 507%} 508 509operand immIRotneg() %{ 510 // if AsmOperand::is_rotated_imm() is true for this constant, it is 511 // a immIRot and an optimal instruction combination exists to handle the 512 // constant as an immIRot 513 predicate(!AsmOperand::is_rotated_imm(n->get_int()) && AsmOperand::is_rotated_imm(-n->get_int())); 514 match(ConI); 515 516 op_cost(0); 517 // formats are generated automatically for constants and base registers 518 format %{ %} 519 interface(CONST_INTER); 520%} 521 522// Non-negative integer immediate that is encodable using the rotation scheme, 523// and that when expanded fits in 31 bits. 524operand immU31Rot() %{ 525 predicate((0 <= n->get_int()) && AsmOperand::is_rotated_imm(n->get_int())); 526 match(ConI); 527 528 op_cost(0); 529 // formats are generated automatically for constants and base registers 530 format %{ %} 531 interface(CONST_INTER); 532%} 533 534operand immPRot() %{ 535 predicate(n->get_ptr() == 0 || (AsmOperand::is_rotated_imm(n->get_ptr()) && ((ConPNode*)n)->type()->reloc() == relocInfo::none)); 536 537 match(ConP); 538 539 op_cost(0); 540 // formats are generated automatically for constants and base registers 541 format %{ %} 542 interface(CONST_INTER); 543%} 544 545operand immLlowRot() %{ 546 predicate(n->get_long() >> 32 == 0 && AsmOperand::is_rotated_imm((int)n->get_long())); 547 match(ConL); 548 op_cost(0); 549 550 format %{ %} 551 interface(CONST_INTER); 552%} 553 554operand immLRot2() %{ 555 predicate(AsmOperand::is_rotated_imm((int)(n->get_long() >> 32)) && 556 AsmOperand::is_rotated_imm((int)(n->get_long()))); 557 match(ConL); 558 op_cost(0); 559 560 format %{ %} 561 interface(CONST_INTER); 562%} 563 564// Integer Immediate: 12-bit - for addressing mode 565operand immI12() %{ 566 predicate((-4096 < n->get_int()) && (n->get_int() < 4096)); 567 match(ConI); 568 op_cost(0); 569 570 format %{ %} 571 interface(CONST_INTER); 572%} 573 574// Integer Immediate: 10-bit disp and disp+4 - for addressing float pair 575operand immI10x2() %{ 576 predicate((-1024 < n->get_int()) && (n->get_int() < 1024 - 4)); 577 match(ConI); 578 op_cost(0); 579 580 format %{ %} 581 interface(CONST_INTER); 582%} 583 584// Integer Immediate: 12-bit disp and disp+4 - for addressing word pair 585operand immI12x2() %{ 586 predicate((-4096 < n->get_int()) && (n->get_int() < 4096 - 4)); 587 match(ConI); 588 op_cost(0); 589 590 format %{ %} 591 interface(CONST_INTER); 592%} 593