1// 2// Copyright (c) 2017, 2021, Oracle and/or its affiliates. All rights reserved. 3// Copyright (c) 2017, 2020 SAP SE. All rights reserved. 4// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5// 6// This code is free software; you can redistribute it and/or modify it 7// under the terms of the GNU General Public License version 2 only, as 8// published by the Free Software Foundation. 9// 10// This code is distributed in the hope that it will be useful, but WITHOUT 11// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13// version 2 for more details (a copy is included in the LICENSE file that 14// accompanied this code). 15// 16// You should have received a copy of the GNU General Public License version 17// 2 along with this work; if not, write to the Free Software Foundation, 18// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19// 20// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21// or visit www.oracle.com if you need additional information or have any 22// questions. 23// 24 25// z/Architecture Architecture Description File 26 27// Major contributions by AS, JL, LS. 28 29// 30// Following information is derived from private mail communication 31// (Oct. 2011). 32// 33// General branch target alignment considerations 34// 35// z/Architecture does not imply a general branch target alignment requirement. 36// There are side effects and side considerations, though, which may 37// provide some performance benefit. These are: 38// - Align branch target on octoword (32-byte) boundary 39// On more recent models (from z9 on), I-fetch is done on a Octoword 40// (32 bytes at a time) basis. To avoid I-fetching unnecessary 41// instructions, branch targets should be 32-byte aligend. If this 42// exact alingment cannot be achieved, having the branch target in 43// the first doubleword still provides some benefit. 44// - Avoid branch targets at the end of cache lines (> 64 bytes distance). 45// Sequential instruction prefetching after the branch target starts 46// immediately after having fetched the octoword containing the 47// branch target. When I-fetching crosses a cache line, there may be 48// a small stall. The worst case: the branch target (at the end of 49// a cache line) is a L1 I-cache miss and the next line as well. 50// Then, the entire target line must be filled first (to contine at the 51// branch target). Only then can the next sequential line be filled. 52// - Avoid multiple poorly predicted branches in a row. 53// 54 55//----------REGISTER DEFINITION BLOCK------------------------------------------ 56// This information is used by the matcher and the register allocator to 57// describe individual registers and classes of registers within the target 58// architecture. 59 60register %{ 61 62//----------Architecture Description Register Definitions---------------------- 63// General Registers 64// "reg_def" name (register save type, C convention save type, 65// ideal register type, encoding); 66// 67// Register Save Types: 68// 69// NS = No-Save: The register allocator assumes that these registers 70// can be used without saving upon entry to the method, & 71// that they do not need to be saved at call sites. 72// 73// SOC = Save-On-Call: The register allocator assumes that these registers 74// can be used without saving upon entry to the method, 75// but that they must be saved at call sites. 76// 77// SOE = Save-On-Entry: The register allocator assumes that these registers 78// must be saved before using them upon entry to the 79// method, but they do not need to be saved at call sites. 80// 81// AS = Always-Save: The register allocator assumes that these registers 82// must be saved before using them upon entry to the 83// method, & that they must be saved at call sites. 84// 85// Ideal Register Type is used to determine how to save & restore a 86// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 87// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 88// 89// The encoding number is the actual bit-pattern placed into the opcodes. 90 91// z/Architecture register definitions, based on the z/Architecture Principles 92// of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement, 93// 5th Edition, March 2001. 94// 95// For each 64-bit register we must define two registers: the register 96// itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half', 97// e.g. Z_R3_H, which is needed by the allocator, but is not used 98// for stores, loads, etc. 99 100 // Integer/Long Registers 101 // ---------------------------- 102 103 // z/Architecture has 16 64-bit integer registers. 104 105 // types: v = volatile, nv = non-volatile, s = system 106 reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1 107 reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next()); 108 reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2 109 reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next()); 110 reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret 111 reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next()); 112 reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2 113 reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next()); 114 reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3 115 reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next()); 116 reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4 117 reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next()); 118 reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5 119 reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next()); 120 reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg()); 121 reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next()); 122 reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg()); 123 reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next()); 124 reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg()); 125 reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next()); 126 reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg()); 127 reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next()); 128 reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg()); 129 reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next()); 130 reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg()); 131 reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next()); 132 reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg()); 133 reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next()); 134 reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc 135 reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next()); 136 reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP 137 reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next()); 138 139 // Float/Double Registers 140 141 // The rules of ADL require that double registers be defined in pairs. 142 // Each pair must be two 32-bit values, but not necessarily a pair of 143 // single float registers. In each pair, ADLC-assigned register numbers 144 // must be adjacent, with the lower number even. Finally, when the 145 // CPU stores such a register pair to memory, the word associated with 146 // the lower ADLC-assigned number must be stored to the lower address. 147 148 // z/Architecture has 16 64-bit floating-point registers. Each can store a single 149 // or double precision floating-point value. 150 151 // types: v = volatile, nv = non-volatile, s = system 152 reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret 153 reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next()); 154 reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg()); 155 reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next()); 156 reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2 157 reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next()); 158 reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg()); 159 reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next()); 160 reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3 161 reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next()); 162 reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg()); 163 reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next()); 164 reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg()); 165 reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next()); 166 reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg()); 167 reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next()); 168 reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg()); 169 reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next()); 170 reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg()); 171 reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next()); 172 reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg()); 173 reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next()); 174 reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg()); 175 reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next()); 176 reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg()); 177 reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next()); 178 reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg()); 179 reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next()); 180 reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg()); 181 reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next()); 182 reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg()); 183 reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next()); 184 185 186 // Special Registers 187 188 // Condition Codes Flag Registers 189 190 // z/Architecture has the PSW (program status word) that contains 191 // (among other information) the condition code. We treat this 192 // part of the PSW as a condition register CR. It consists of 4 193 // bits. Floating point instructions influence the same condition register CR. 194 195 reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile 196 197 198// Specify priority of register selection within phases of register 199// allocation. Highest priority is first. A useful heuristic is to 200// give registers a low priority when they are required by machine 201// instructions, and choose no-save registers before save-on-call, and 202// save-on-call before save-on-entry. Registers which participate in 203// fix calling sequences should come last. Registers which are used 204// as pairs must fall on an even boundary. 205 206// It's worth about 1% on SPEC geomean to get this right. 207 208// Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 209// in adGlobals_s390.hpp which defines the <register>_num values, e.g. 210// Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not) 211// the same as Z_R3->encoding()! Furthermore, we cannot make any 212// assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num. 213// Additionally, the function 214// static enum RC rc_class(OptoReg::Name reg) 215// maps a given <register>_num value to its chunk type (except for flags) 216// and its current implementation relies on chunk0 and chunk1 having a 217// size of 64 each. 218 219alloc_class chunk0( 220 // chunk0 contains *all* 32 integer registers halves. 221 222 // potential SOE regs 223 Z_R13,Z_R13_H, 224 Z_R12,Z_R12_H, 225 Z_R11,Z_R11_H, 226 Z_R10,Z_R10_H, 227 228 Z_R9,Z_R9_H, 229 Z_R8,Z_R8_H, 230 Z_R7,Z_R7_H, 231 232 Z_R1,Z_R1_H, 233 Z_R0,Z_R0_H, 234 235 // argument registers 236 Z_R6,Z_R6_H, 237 Z_R5,Z_R5_H, 238 Z_R4,Z_R4_H, 239 Z_R3,Z_R3_H, 240 Z_R2,Z_R2_H, 241 242 // special registers 243 Z_R14,Z_R14_H, 244 Z_R15,Z_R15_H 245); 246 247alloc_class chunk1( 248 // Chunk1 contains *all* 64 floating-point registers halves. 249 250 Z_F15,Z_F15_H, 251 Z_F14,Z_F14_H, 252 Z_F13,Z_F13_H, 253 Z_F12,Z_F12_H, 254 Z_F11,Z_F11_H, 255 Z_F10,Z_F10_H, 256 Z_F9,Z_F9_H, 257 Z_F8,Z_F8_H, 258 // scratch register 259 Z_F7,Z_F7_H, 260 Z_F5,Z_F5_H, 261 Z_F3,Z_F3_H, 262 Z_F1,Z_F1_H, 263 // argument registers 264 Z_F6,Z_F6_H, 265 Z_F4,Z_F4_H, 266 Z_F2,Z_F2_H, 267 Z_F0,Z_F0_H 268); 269 270alloc_class chunk2( 271 Z_CR 272); 273 274 275//-------Architecture Description Register Classes----------------------- 276 277// Several register classes are automatically defined based upon 278// information in this architecture description. 279 280// 1) reg_class inline_cache_reg (as defined in frame section) 281// 2) reg_class stack_slots(/* one chunk of stack-based "registers" */) 282 283// Integer Register Classes 284reg_class z_int_reg( 285/*Z_R0*/ // R0 286/*Z_R1*/ 287 Z_R2, 288 Z_R3, 289 Z_R4, 290 Z_R5, 291 Z_R6, 292 Z_R7, 293/*Z_R8,*/ // Z_thread 294 Z_R9, 295 Z_R10, 296 Z_R11, 297 Z_R12, 298 Z_R13 299/*Z_R14*/ // return_pc 300/*Z_R15*/ // SP 301); 302 303reg_class z_no_odd_int_reg( 304/*Z_R0*/ // R0 305/*Z_R1*/ 306 Z_R2, 307 Z_R3, 308 Z_R4, 309/*Z_R5,*/ // odd part of fix register pair 310 Z_R6, 311 Z_R7, 312/*Z_R8,*/ // Z_thread 313 Z_R9, 314 Z_R10, 315 Z_R11, 316 Z_R12, 317 Z_R13 318/*Z_R14*/ // return_pc 319/*Z_R15*/ // SP 320); 321 322reg_class z_no_arg_int_reg( 323/*Z_R0*/ // R0 324/*Z_R1*/ // scratch 325/*Z_R2*/ 326/*Z_R3*/ 327/*Z_R4*/ 328/*Z_R5*/ 329/*Z_R6*/ 330 Z_R7, 331/*Z_R8*/ // Z_thread 332 Z_R9, 333 Z_R10, 334 Z_R11, 335 Z_R12, 336 Z_R13 337/*Z_R14*/ // return_pc 338/*Z_R15*/ // SP 339); 340 341reg_class z_rarg1_int_reg(Z_R2); 342reg_class z_rarg2_int_reg(Z_R3); 343reg_class z_rarg3_int_reg(Z_R4); 344reg_class z_rarg4_int_reg(Z_R5); 345reg_class z_rarg5_int_reg(Z_R6); 346 347// Pointer Register Classes 348 349// 64-bit build means 64-bit pointers means hi/lo pairs. 350 351reg_class z_rarg5_ptrN_reg(Z_R6); 352 353reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2); 354reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3); 355reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4); 356reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5); 357reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6); 358reg_class z_thread_ptr_reg(Z_R8_H,Z_R8); 359 360reg_class z_ptr_reg( 361/*Z_R0_H,Z_R0*/ // R0 362/*Z_R1_H,Z_R1*/ 363 Z_R2_H,Z_R2, 364 Z_R3_H,Z_R3, 365 Z_R4_H,Z_R4, 366 Z_R5_H,Z_R5, 367 Z_R6_H,Z_R6, 368 Z_R7_H,Z_R7, 369/*Z_R8_H,Z_R8,*/ // Z_thread 370 Z_R9_H,Z_R9, 371 Z_R10_H,Z_R10, 372 Z_R11_H,Z_R11, 373 Z_R12_H,Z_R12, 374 Z_R13_H,Z_R13 375/*Z_R14_H,Z_R14*/ // return_pc 376/*Z_R15_H,Z_R15*/ // SP 377); 378 379reg_class z_lock_ptr_reg( 380/*Z_R0_H,Z_R0*/ // R0 381/*Z_R1_H,Z_R1*/ 382 Z_R2_H,Z_R2, 383 Z_R3_H,Z_R3, 384 Z_R4_H,Z_R4, 385/*Z_R5_H,Z_R5,*/ 386/*Z_R6_H,Z_R6,*/ 387 Z_R7_H,Z_R7, 388/*Z_R8_H,Z_R8,*/ // Z_thread 389 Z_R9_H,Z_R9, 390 Z_R10_H,Z_R10, 391 Z_R11_H,Z_R11, 392 Z_R12_H,Z_R12, 393 Z_R13_H,Z_R13 394/*Z_R14_H,Z_R14*/ // return_pc 395/*Z_R15_H,Z_R15*/ // SP 396); 397 398reg_class z_no_arg_ptr_reg( 399/*Z_R0_H,Z_R0*/ // R0 400/*Z_R1_H,Z_R1*/ // scratch 401/*Z_R2_H,Z_R2*/ 402/*Z_R3_H,Z_R3*/ 403/*Z_R4_H,Z_R4*/ 404/*Z_R5_H,Z_R5*/ 405/*Z_R6_H,Z_R6*/ 406 Z_R7_H, Z_R7, 407/*Z_R8_H,Z_R8*/ // Z_thread 408 Z_R9_H,Z_R9, 409 Z_R10_H,Z_R10, 410 Z_R11_H,Z_R11, 411 Z_R12_H,Z_R12, 412 Z_R13_H,Z_R13 413/*Z_R14_H,Z_R14*/ // return_pc 414/*Z_R15_H,Z_R15*/ // SP 415); 416 417// Special class for storeP instructions, which can store SP or RPC to 418// TLS. (Note: Do not generalize this to "any_reg". If you add 419// another register, such as FP, to this mask, the allocator may try 420// to put a temp in it.) 421// Register class for memory access base registers, 422// This class is a superset of z_ptr_reg including Z_thread. 423reg_class z_memory_ptr_reg( 424/*Z_R0_H,Z_R0*/ // R0 425/*Z_R1_H,Z_R1*/ 426 Z_R2_H,Z_R2, 427 Z_R3_H,Z_R3, 428 Z_R4_H,Z_R4, 429 Z_R5_H,Z_R5, 430 Z_R6_H,Z_R6, 431 Z_R7_H,Z_R7, 432 Z_R8_H,Z_R8, // Z_thread 433 Z_R9_H,Z_R9, 434 Z_R10_H,Z_R10, 435 Z_R11_H,Z_R11, 436 Z_R12_H,Z_R12, 437 Z_R13_H,Z_R13 438/*Z_R14_H,Z_R14*/ // return_pc 439/*Z_R15_H,Z_R15*/ // SP 440); 441 442// Other special pointer regs. 443reg_class z_r1_regP(Z_R1_H,Z_R1); 444reg_class z_r9_regP(Z_R9_H,Z_R9); 445 446 447// Long Register Classes 448 449reg_class z_rarg1_long_reg(Z_R2_H,Z_R2); 450reg_class z_rarg2_long_reg(Z_R3_H,Z_R3); 451reg_class z_rarg3_long_reg(Z_R4_H,Z_R4); 452reg_class z_rarg4_long_reg(Z_R5_H,Z_R5); 453reg_class z_rarg5_long_reg(Z_R6_H,Z_R6); 454 455// Longs in 1 register. Aligned adjacent hi/lo pairs. 456reg_class z_long_reg( 457/*Z_R0_H,Z_R0*/ // R0 458/*Z_R1_H,Z_R1*/ 459 Z_R2_H,Z_R2, 460 Z_R3_H,Z_R3, 461 Z_R4_H,Z_R4, 462 Z_R5_H,Z_R5, 463 Z_R6_H,Z_R6, 464 Z_R7_H,Z_R7, 465/*Z_R8_H,Z_R8,*/ // Z_thread 466 Z_R9_H,Z_R9, 467 Z_R10_H,Z_R10, 468 Z_R11_H,Z_R11, 469 Z_R12_H,Z_R12, 470 Z_R13_H,Z_R13 471/*Z_R14_H,Z_R14,*/ // return_pc 472/*Z_R15_H,Z_R15*/ // SP 473); 474 475// z_long_reg without even registers 476reg_class z_long_odd_reg( 477/*Z_R0_H,Z_R0*/ // R0 478/*Z_R1_H,Z_R1*/ 479 Z_R3_H,Z_R3, 480 Z_R5_H,Z_R5, 481 Z_R7_H,Z_R7, 482 Z_R9_H,Z_R9, 483 Z_R11_H,Z_R11, 484 Z_R13_H,Z_R13 485/*Z_R14_H,Z_R14,*/ // return_pc 486/*Z_R15_H,Z_R15*/ // SP 487); 488 489// Special Class for Condition Code Flags Register 490 491reg_class z_condition_reg( 492 Z_CR 493); 494 495// Scratch register for late profiling. Callee saved. 496reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2); 497 498 499// Float Register Classes 500 501reg_class z_flt_reg( 502 Z_F0, 503/*Z_F1,*/ // scratch 504 Z_F2, 505 Z_F3, 506 Z_F4, 507 Z_F5, 508 Z_F6, 509 Z_F7, 510 Z_F8, 511 Z_F9, 512 Z_F10, 513 Z_F11, 514 Z_F12, 515 Z_F13, 516 Z_F14, 517 Z_F15 518); 519reg_class z_rscratch1_flt_reg(Z_F1); 520 521// Double precision float registers have virtual `high halves' that 522// are needed by the allocator. 523reg_class z_dbl_reg( 524 Z_F0,Z_F0_H, 525/*Z_F1,Z_F1_H,*/ // scratch 526 Z_F2,Z_F2_H, 527 Z_F3,Z_F3_H, 528 Z_F4,Z_F4_H, 529 Z_F5,Z_F5_H, 530 Z_F6,Z_F6_H, 531 Z_F7,Z_F7_H, 532 Z_F8,Z_F8_H, 533 Z_F9,Z_F9_H, 534 Z_F10,Z_F10_H, 535 Z_F11,Z_F11_H, 536 Z_F12,Z_F12_H, 537 Z_F13,Z_F13_H, 538 Z_F14,Z_F14_H, 539 Z_F15,Z_F15_H 540); 541reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H); 542 543%} 544 545//----------DEFINITION BLOCK--------------------------------------------------- 546// Define 'name --> value' mappings to inform the ADLC of an integer valued name. 547// Current support includes integer values in the range [0, 0x7FFFFFFF]. 548// Format: 549// int_def <name> (<int_value>, <expression>); 550// Generated Code in ad_<arch>.hpp 551// #define <name> (<expression>) 552// // value == <int_value> 553// Generated code in ad_<arch>.cpp adlc_verification() 554// assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 555// 556definitions %{ 557 // The default cost (of an ALU instruction). 558 int_def DEFAULT_COST ( 100, 100); 559 int_def DEFAULT_COST_LOW ( 80, 80); 560 int_def DEFAULT_COST_HIGH ( 120, 120); 561 int_def HUGE_COST (1000000, 1000000); 562 563 // Put an advantage on REG_MEM vs. MEM+REG_REG operations. 564 int_def ALU_REG_COST ( 100, DEFAULT_COST); 565 int_def ALU_MEMORY_COST ( 150, 150); 566 567 // Memory refs are twice as expensive as run-of-the-mill. 568 int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20); 569 int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST); 570 int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20); 571 572 // Branches are even more expensive. 573 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 574 int_def CALL_COST ( 300, DEFAULT_COST * 3); 575%} 576 577source %{ 578 579#ifdef PRODUCT 580#define BLOCK_COMMENT(str) 581#define BIND(label) __ bind(label) 582#else 583#define BLOCK_COMMENT(str) __ block_comment(str) 584#define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":") 585#endif 586 587#define __ _masm. 588 589#define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6 590#define Z_DISP3_SIZE 6 591 592// Tertiary op of a LoadP or StoreP encoding. 593#define REGP_OP true 594 595// Given a register encoding, produce an Integer Register object. 596static Register reg_to_register_object(int register_encoding); 597 598// **************************************************************************** 599 600// REQUIRED FUNCTIONALITY 601 602// !!!!! Special hack to get all type of calls to specify the byte offset 603// from the start of the call to the point where the return address 604// will point. 605 606void PhaseOutput::pd_perform_mach_node_analysis() { 607} 608 609int MachNode::pd_alignment_required() const { 610 return 1; 611} 612 613int MachNode::compute_padding(int current_offset) const { 614 return 0; 615} 616 617int MachCallStaticJavaNode::ret_addr_offset() { 618 if (_method) { 619 return 8; 620 } else { 621 return MacroAssembler::call_far_patchable_ret_addr_offset(); 622 } 623} 624 625int MachCallDynamicJavaNode::ret_addr_offset() { 626 // Consider size of receiver type profiling (C2 tiers). 627 int profile_receiver_type_size = 0; 628 629 int vtable_index = this->_vtable_index; 630 if (vtable_index == -4) { 631 return 14 + profile_receiver_type_size; 632 } else { 633 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 634 return 36 + profile_receiver_type_size; 635 } 636} 637 638int MachCallRuntimeNode::ret_addr_offset() { 639 return 12 + MacroAssembler::call_far_patchable_ret_addr_offset(); 640} 641 642int MachCallNativeNode::ret_addr_offset() { 643 Unimplemented(); 644 return -1; 645} 646 647// Compute padding required for nodes which need alignment 648// 649// The addresses of the call instructions needs to be 4-byte aligned to 650// ensure that they don't span a cache line so that they are atomically patchable. 651// The actual calls get emitted at different offsets within the node emitters. 652// ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted. 653 654int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const { 655 return (0 - current_offset) & 2; 656} 657 658int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const { 659 return (6 - current_offset) & 2; 660} 661 662int CallRuntimeDirectNode::compute_padding(int current_offset) const { 663 return (12 - current_offset) & 2; 664} 665 666int CallLeafDirectNode::compute_padding(int current_offset) const { 667 return (12 - current_offset) & 2; 668} 669 670int CallLeafNoFPDirectNode::compute_padding(int current_offset) const { 671 return (12 - current_offset) & 2; 672} 673 674void emit_nop(CodeBuffer &cbuf) { 675 C2_MacroAssembler _masm(&cbuf); 676 __ z_nop(); 677} 678 679// Emit an interrupt that is caught by the debugger (for debugging compiler). 680void emit_break(CodeBuffer &cbuf) { 681 C2_MacroAssembler _masm(&cbuf); 682 __ z_illtrap(); 683} 684 685#if !defined(PRODUCT) 686void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const { 687 os->print("TA"); 688} 689#endif 690 691void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 692 emit_break(cbuf); 693} 694 695uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 696 return MachNode::size(ra_); 697} 698 699static inline void z_emit16(CodeBuffer &cbuf, long value) { 700 // 32bit instructions may become sign extended. 701 assert(value >= 0, "unintended sign extension (int->long)"); 702 assert(value < (1L << 16), "instruction too large"); 703 *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value; 704 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short)); 705} 706 707static inline void z_emit32(CodeBuffer &cbuf, long value) { 708 // 32bit instructions may become sign extended. 709 assert(value < (1L << 32), "instruction too large"); 710 *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value; 711 cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int)); 712} 713 714static inline void z_emit48(CodeBuffer &cbuf, long value) { 715 // 32bit instructions may become sign extended. 716 assert(value >= 0, "unintended sign extension (int->long)"); 717 assert(value < (1L << 48), "instruction too large"); 718 value = value<<16; 719 memcpy(cbuf.insts_end(), (unsigned char*)&value, 6); 720 cbuf.set_insts_end(cbuf.insts_end() + 6); 721} 722 723static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) { 724 if (value < 0) { 725 // There obviously has been an unintended sign extension (int->long). Revert it. 726 value = (long)((unsigned long)((unsigned int)value)); 727 } 728 729 if (value < (1L << 16)) { // 2-byte instruction 730 z_emit16(cbuf, value); 731 return 2; 732 } 733 734 if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store 735 z_emit32(cbuf, value); 736 return 4; 737 } 738 739 // 6-byte instruction, probably unaligned store. 740 z_emit48(cbuf, value); 741 return 6; 742} 743 744// Check effective address (at runtime) for required alignment. 745static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) { 746 C2_MacroAssembler _masm(&cbuf); 747 748 __ z_lay(Z_R0, disp, index, base); 749 __ z_nill(Z_R0, alignment-1); 750 __ z_brc(Assembler::bcondEqual, +3); 751 __ z_illtrap(); 752} 753 754int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype, 755 PhaseRegAlloc* ra_, bool is_native_call = false) { 756 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). 757 address old_mark = __ inst_mark(); 758 unsigned int start_off = __ offset(); 759 760 if (is_native_call) { 761 ShouldNotReachHere(); 762 } 763 764 if (rtype == relocInfo::runtime_call_w_cp_type) { 765 assert((__ offset() & 2) == 0, "misaligned emit_call_reloc"); 766 address call_addr = __ call_c_opt((address)entry_point); 767 if (call_addr == NULL) { 768 Compile::current()->env()->record_out_of_memory_failure(); 769 return -1; 770 } 771 } else { 772 assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type || 773 rtype == relocInfo::static_call_type, "unexpected rtype"); 774 __ relocate(rtype); 775 // BRASL must be prepended with a nop to identify it in the instruction stream. 776 __ z_nop(); 777 __ z_brasl(Z_R14, (address)entry_point); 778 } 779 780 unsigned int ret_off = __ offset(); 781 782 return (ret_off - start_off); 783} 784 785static int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) { 786 __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp(). 787 address old_mark = __ inst_mark(); 788 unsigned int start_off = __ offset(); 789 790 relocInfo::relocType rtype = rspec.type(); 791 assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type, 792 "unexpected rtype"); 793 794 __ relocate(rspec); 795 __ z_nop(); 796 __ z_brasl(Z_R14, (address)entry_point); 797 798 unsigned int ret_off = __ offset(); 799 800 return (ret_off - start_off); 801} 802 803//============================================================================= 804 805const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask; 806int ConstantTable::calculate_table_base_offset() const { 807 return 0; // absolute addressing, no offset 808} 809 810bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 811void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 812 ShouldNotReachHere(); 813} 814 815// Even with PC-relative TOC addressing, we still need this node. 816// Float loads/stores do not support PC-relative addresses. 817void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 818 C2_MacroAssembler _masm(&cbuf); 819 Register Rtoc = as_Register(ra_->get_encode(this)); 820 __ load_toc(Rtoc); 821} 822 823uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 824 // PCrelative TOC access. 825 return 6; // sizeof(LARL) 826} 827 828#if !defined(PRODUCT) 829void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 830 Register r = as_Register(ra_->get_encode(this)); 831 st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name()); 832} 833#endif 834 835//============================================================================= 836 837#if !defined(PRODUCT) 838void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 839 Compile* C = ra_->C; 840 st->print_cr("--- MachPrologNode ---"); 841 st->print("\t"); 842 for (int i = 0; i < OptoPrologueNops; i++) { 843 st->print_cr("NOP"); st->print("\t"); 844 } 845 846 if (VerifyThread) { 847 st->print_cr("Verify_Thread"); 848 st->print("\t"); 849 } 850 851 long framesize = C->output()->frame_size_in_bytes(); 852 int bangsize = C->output()->bang_size_in_bytes(); 853 854 // Calls to C2R adapters often do not accept exceptional returns. 855 // We require that their callers must bang for them. But be 856 // careful, because some VM calls (such as call site linkage) can 857 // use several kilobytes of stack. But the stack safety zone should 858 // account for that. See bugs 4446381, 4468289, 4497237. 859 if (C->output()->need_stack_bang(bangsize)) { 860 st->print_cr("# stack bang"); st->print("\t"); 861 } 862 st->print_cr("push_frame %d", (int)-framesize); 863 st->print("\t"); 864} 865#endif 866 867void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 868 Compile* C = ra_->C; 869 C2_MacroAssembler _masm(&cbuf); 870 871 __ verify_thread(); 872 873 size_t framesize = C->output()->frame_size_in_bytes(); 874 size_t bangsize = C->output()->bang_size_in_bytes(); 875 876 assert(framesize % wordSize == 0, "must preserve wordSize alignment"); 877 878 if (C->clinit_barrier_on_entry()) { 879 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started"); 880 881 Label L_skip_barrier; 882 Register klass = Z_R1_scratch; 883 884 // Notify OOP recorder (don't need the relocation) 885 AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding()); 886 __ load_const_optimized(klass, md.value()); 887 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/); 888 889 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub()); 890 __ z_br(klass); 891 892 __ bind(L_skip_barrier); 893 } 894 895 // Calls to C2R adapters often do not accept exceptional returns. 896 // We require that their callers must bang for them. But be 897 // careful, because some VM calls (such as call site linkage) can 898 // use several kilobytes of stack. But the stack safety zone should 899 // account for that. See bugs 4446381, 4468289, 4497237. 900 if (C->output()->need_stack_bang(bangsize)) { 901 __ generate_stack_overflow_check(bangsize); 902 } 903 904 assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!"); 905 __ save_return_pc(); 906 907 // The z/Architecture abi is already accounted for in `framesize' via the 908 // 'out_preserve_stack_slots' declaration. 909 __ push_frame((unsigned int)framesize/*includes JIT ABI*/); 910 911 if (C->has_mach_constant_base_node()) { 912 // NOTE: We set the table base offset here because users might be 913 // emitted before MachConstantBaseNode. 914 ConstantTable& constant_table = C->output()->constant_table(); 915 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 916 } 917} 918 919uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 920 // Variable size. Determine dynamically. 921 return MachNode::size(ra_); 922} 923 924int MachPrologNode::reloc() const { 925 // Return number of relocatable values contained in this instruction. 926 return 1; // One reloc entry for load_const(toc). 927} 928 929//============================================================================= 930 931#if !defined(PRODUCT) 932void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 933 os->print_cr("epilog"); 934 os->print("\t"); 935 if (do_polling() && ra_->C->is_method_compilation()) { 936 os->print_cr("load_from_polling_page Z_R1_scratch"); 937 os->print("\t"); 938 } 939} 940#endif 941 942void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 943 C2_MacroAssembler _masm(&cbuf); 944 Compile* C = ra_->C; 945 __ verify_thread(); 946 947 // If this does safepoint polling, then do it here. 948 bool need_polling = do_polling() && C->is_method_compilation(); 949 950 // Pop frame, restore return_pc, and all stuff needed by interpreter. 951 int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes); 952 __ pop_frame_restore_retPC(frame_size_in_bytes); 953 954 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 955 __ reserved_stack_check(Z_R14); 956 } 957 958 // Touch the polling page. 959 if (need_polling) { 960 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset())); 961 // We need to mark the code position where the load from the safepoint 962 // polling page was emitted as relocInfo::poll_return_type here. 963 __ relocate(relocInfo::poll_return_type); 964 __ load_from_polling_page(Z_R1_scratch); 965 } 966} 967 968uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 969 // Variable size. determine dynamically. 970 return MachNode::size(ra_); 971} 972 973int MachEpilogNode::reloc() const { 974 // Return number of relocatable values contained in this instruction. 975 return 1; // One for load_from_polling_page. 976} 977 978const Pipeline * MachEpilogNode::pipeline() const { 979 return MachNode::pipeline_class(); 980} 981 982//============================================================================= 983 984// Figure out which register class each belongs in: rc_int, rc_float, rc_stack. 985enum RC { rc_bad, rc_int, rc_float, rc_stack }; 986 987static enum RC rc_class(OptoReg::Name reg) { 988 // Return the register class for the given register. The given register 989 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 990 // enumeration in adGlobals_s390.hpp. 991 992 if (reg == OptoReg::Bad) { 993 return rc_bad; 994 } 995 996 // We have 32 integer register halves, starting at index 0. 997 if (reg < 32) { 998 return rc_int; 999 } 1000 1001 // We have 32 floating-point register halves, starting at index 32. 1002 if (reg < 32+32) { 1003 return rc_float; 1004 } 1005 1006 // Between float regs & stack are the flags regs. 1007 assert(reg >= OptoReg::stack0(), "blow up if spilling flags"); 1008 return rc_stack; 1009} 1010 1011// Returns size as obtained from z_emit_instr. 1012static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode, 1013 int reg, int offset, bool do_print, outputStream *os) { 1014 1015 if (cbuf) { 1016 if (opcode > (1L<<32)) { 1017 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) | 1018 Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48)); 1019 } else { 1020 return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) | 1021 Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32)); 1022 } 1023 } 1024 1025#if !defined(PRODUCT) 1026 if (do_print) { 1027 os->print("%s %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset); 1028 } 1029#endif 1030 return (opcode > (1L << 32)) ? 6 : 4; 1031} 1032 1033static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) { 1034 if (cbuf) { 1035 C2_MacroAssembler _masm(cbuf); 1036 __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP); 1037 } 1038 1039#if !defined(PRODUCT) 1040 else if (do_print) { 1041 os->print("MVC %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off); 1042 } 1043#endif 1044 1045 return 6; 1046} 1047 1048uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const { 1049 // Get registers to move. 1050 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1051 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1052 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1053 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1054 1055 enum RC src_hi_rc = rc_class(src_hi); 1056 enum RC src_lo_rc = rc_class(src_lo); 1057 enum RC dst_hi_rc = rc_class(dst_hi); 1058 enum RC dst_lo_rc = rc_class(dst_lo); 1059 1060 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1061 bool is64 = (src_hi_rc != rc_bad); 1062 assert(!is64 || 1063 ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi), 1064 "expected aligned-adjacent pairs"); 1065 1066 // Generate spill code! 1067 1068 if (src_lo == dst_lo && src_hi == dst_hi) { 1069 return 0; // Self copy, no move. 1070 } 1071 1072 int src_offset = ra_->reg2offset(src_lo); 1073 int dst_offset = ra_->reg2offset(dst_lo); 1074 bool print = !do_size; 1075 bool src12 = Immediate::is_uimm12(src_offset); 1076 bool dst12 = Immediate::is_uimm12(dst_offset); 1077 1078 const char *mnemo = NULL; 1079 unsigned long opc = 0; 1080 1081 // Memory->Memory Spill. Use Z_R0 to hold the value. 1082 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1083 1084 assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack), 1085 "expected same type of move for high parts"); 1086 1087 if (src12 && dst12) { 1088 return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os); 1089 } 1090 1091 int r0 = Z_R0_num; 1092 if (is64) { 1093 return z_ld_st_helper(cbuf, "LG ", LG_ZOPC, r0, src_offset, print, os) + 1094 z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os); 1095 } 1096 1097 return z_ld_st_helper(cbuf, "LY ", LY_ZOPC, r0, src_offset, print, os) + 1098 z_ld_st_helper(cbuf, "STY ", STY_ZOPC, r0, dst_offset, print, os); 1099 } 1100 1101 // Check for float->int copy. Requires a trip through memory. 1102 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1103 Unimplemented(); // Unsafe, do not remove! 1104 } 1105 1106 // Check for integer reg-reg copy. 1107 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1108 if (cbuf) { 1109 C2_MacroAssembler _masm(cbuf); 1110 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1111 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1112 __ z_lgr(Rdst, Rsrc); 1113 return 4; 1114 } 1115#if !defined(PRODUCT) 1116 // else 1117 if (print) { 1118 os->print("LGR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1119 } 1120#endif 1121 return 4; 1122 } 1123 1124 // Check for integer store. 1125 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1126 assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack), 1127 "expected same type of move for high parts"); 1128 1129 if (is64) { 1130 return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os); 1131 } 1132 1133 // else 1134 mnemo = dst12 ? "ST " : "STY "; 1135 opc = dst12 ? ST_ZOPC : STY_ZOPC; 1136 1137 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1138 } 1139 1140 // Check for integer load 1141 // Always load cOops zero-extended. That doesn't hurt int loads. 1142 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1143 1144 assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack), 1145 "expected same type of move for high parts"); 1146 1147 mnemo = is64 ? "LG " : "LLGF"; 1148 opc = is64 ? LG_ZOPC : LLGF_ZOPC; 1149 1150 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1151 } 1152 1153 // Check for float reg-reg copy. 1154 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1155 if (cbuf) { 1156 C2_MacroAssembler _masm(cbuf); 1157 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1158 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1159 __ z_ldr(Rdst, Rsrc); 1160 return 2; 1161 } 1162#if !defined(PRODUCT) 1163 // else 1164 if (print) { 1165 os->print("LDR %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1166 } 1167#endif 1168 return 2; 1169 } 1170 1171 // Check for float store. 1172 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1173 assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack), 1174 "expected same type of move for high parts"); 1175 1176 if (is64) { 1177 mnemo = dst12 ? "STD " : "STDY "; 1178 opc = dst12 ? STD_ZOPC : STDY_ZOPC; 1179 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1180 } 1181 // else 1182 1183 mnemo = dst12 ? "STE " : "STEY "; 1184 opc = dst12 ? STE_ZOPC : STEY_ZOPC; 1185 return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os); 1186 } 1187 1188 // Check for float load. 1189 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1190 assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack), 1191 "expected same type of move for high parts"); 1192 1193 if (is64) { 1194 mnemo = src12 ? "LD " : "LDY "; 1195 opc = src12 ? LD_ZOPC : LDY_ZOPC; 1196 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1197 } 1198 // else 1199 1200 mnemo = src12 ? "LE " : "LEY "; 1201 opc = src12 ? LE_ZOPC : LEY_ZOPC; 1202 return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os); 1203 } 1204 1205 // -------------------------------------------------------------------- 1206 // Check for hi bits still needing moving. Only happens for misaligned 1207 // arguments to native calls. 1208 if (src_hi == dst_hi) { 1209 return 0; // Self copy, no move. 1210 } 1211 1212 assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1213 Unimplemented(); // Unsafe, do not remove! 1214 1215 return 0; // never reached, but make the compiler shut up! 1216} 1217 1218#if !defined(PRODUCT) 1219void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1220 if (ra_ && ra_->node_regs_max_index() > 0) { 1221 implementation(NULL, ra_, false, os); 1222 } else { 1223 if (req() == 2 && in(1)) { 1224 os->print("N%d = N%d\n", _idx, in(1)->_idx); 1225 } else { 1226 const char *c = "("; 1227 os->print("N%d = ", _idx); 1228 for (uint i = 1; i < req(); ++i) { 1229 os->print("%sN%d", c, in(i)->_idx); 1230 c = ", "; 1231 } 1232 os->print(")"); 1233 } 1234 } 1235} 1236#endif 1237 1238void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1239 implementation(&cbuf, ra_, false, NULL); 1240} 1241 1242uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1243 return implementation(NULL, ra_, true, NULL); 1244} 1245 1246//============================================================================= 1247 1248#if !defined(PRODUCT) 1249void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const { 1250 os->print("NOP # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size()); 1251} 1252#endif 1253 1254void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const { 1255 C2_MacroAssembler _masm(&cbuf); 1256 1257 int rem_space = 0; 1258 if (!(ra_->C->output()->in_scratch_emit_size())) { 1259 rem_space = cbuf.insts()->remaining(); 1260 if (rem_space <= _count*2 + 8) { 1261 tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space); 1262 } 1263 } 1264 1265 for (int i = 0; i < _count; i++) { 1266 __ z_nop(); 1267 } 1268 1269 if (!(ra_->C->output()->in_scratch_emit_size())) { 1270 if (rem_space <= _count*2 + 8) { 1271 int rem_space2 = cbuf.insts()->remaining(); 1272 tty->print_cr(", after = %d", rem_space2); 1273 } 1274 } 1275} 1276 1277uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1278 return 2 * _count; 1279} 1280 1281#if !defined(PRODUCT) 1282void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1283 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1284 if (ra_ && ra_->node_regs_max_index() > 0) { 1285 int reg = ra_->get_reg_first(this); 1286 os->print("ADDHI %s, SP, %d\t//box node", Matcher::regName[reg], offset); 1287 } else { 1288 os->print("ADDHI N%d = SP + %d\t// box node", _idx, offset); 1289 } 1290} 1291#endif 1292 1293// Take care of the size function, if you make changes here! 1294void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1295 C2_MacroAssembler _masm(&cbuf); 1296 1297 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1298 int reg = ra_->get_encode(this); 1299 __ z_lay(as_Register(reg), offset, Z_SP); 1300} 1301 1302uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1303 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1304 return 6; 1305} 1306 1307 %} // end source section 1308 1309//----------SOURCE BLOCK------------------------------------------------------- 1310// This is a block of C++ code which provides values, functions, and 1311// definitions necessary in the rest of the architecture description 1312 1313source_hpp %{ 1314 1315// Header information of the source block. 1316// Method declarations/definitions which are used outside 1317// the ad-scope can conveniently be defined here. 1318// 1319// To keep related declarations/definitions/uses close together, 1320// we switch between source %{ }% and source_hpp %{ }% freely as needed. 1321 1322#include "oops/klass.inline.hpp" 1323 1324//-------------------------------------------------------------- 1325// Used for optimization in Compile::Shorten_branches 1326//-------------------------------------------------------------- 1327 1328class CallStubImpl { 1329 public: 1330 1331 // call trampolines 1332 // Size of call trampoline stub. For add'l comments, see size_java_to_interp(). 1333 static uint size_call_trampoline() { 1334 return 0; // no call trampolines on this platform 1335 } 1336 1337 // call trampolines 1338 // Number of relocations needed by a call trampoline stub. 1339 static uint reloc_call_trampoline() { 1340 return 0; // No call trampolines on this platform. 1341 } 1342}; 1343 1344%} // end source_hpp section 1345 1346source %{ 1347 1348#if !defined(PRODUCT) 1349void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const { 1350 os->print_cr("---- MachUEPNode ----"); 1351 os->print_cr("\tTA"); 1352 os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()"); 1353 os->print_cr("\tBR(Z_R1)"); 1354 os->print_cr("\tTA # pad with illtraps"); 1355 os->print_cr("\t..."); 1356 os->print_cr("\tTA"); 1357 os->print_cr("\tLTGR Z_R2, Z_R2"); 1358 os->print_cr("\tBRU ic_miss"); 1359} 1360#endif 1361 1362void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1363 C2_MacroAssembler _masm(&cbuf); 1364 const int ic_miss_offset = 2; 1365 1366 // Inline_cache contains a klass. 1367 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 1368 // ARG1 is the receiver oop. 1369 Register R2_receiver = Z_ARG1; 1370 int klass_offset = oopDesc::klass_offset_in_bytes(); 1371 AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub()); 1372 Register R1_ic_miss_stub_addr = Z_R1_scratch; 1373 1374 // Null check of receiver. 1375 // This is the null check of the receiver that actually should be 1376 // done in the caller. It's here because in case of implicit null 1377 // checks we get it for free. 1378 assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), 1379 "second word in oop should not require explicit null check."); 1380 if (!ImplicitNullChecks) { 1381 Label valid; 1382 if (VM_Version::has_CompareBranch()) { 1383 __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid); 1384 } else { 1385 __ z_ltgr(R2_receiver, R2_receiver); 1386 __ z_bre(valid); 1387 } 1388 // The ic_miss_stub will handle the null pointer exception. 1389 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); 1390 __ z_br(R1_ic_miss_stub_addr); 1391 __ bind(valid); 1392 } 1393 1394 // Check whether this method is the proper implementation for the class of 1395 // the receiver (ic miss check). 1396 { 1397 Label valid; 1398 // Compare cached class against klass from receiver. 1399 // This also does an implicit null check! 1400 __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false); 1401 __ z_bre(valid); 1402 // The inline cache points to the wrong method. Call the 1403 // ic_miss_stub to find the proper method. 1404 __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); 1405 __ z_br(R1_ic_miss_stub_addr); 1406 __ bind(valid); 1407 } 1408} 1409 1410uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1411 // Determine size dynamically. 1412 return MachNode::size(ra_); 1413} 1414 1415//============================================================================= 1416 1417%} // interrupt source section 1418 1419source_hpp %{ // Header information of the source block. 1420 1421class HandlerImpl { 1422 public: 1423 1424 static int emit_exception_handler(CodeBuffer &cbuf); 1425 static int emit_deopt_handler(CodeBuffer& cbuf); 1426 1427 static uint size_exception_handler() { 1428 return NativeJump::max_instruction_size(); 1429 } 1430 1431 static uint size_deopt_handler() { 1432 return NativeCall::max_instruction_size(); 1433 } 1434}; 1435 1436class Node::PD { 1437public: 1438 enum NodeFlags { 1439 _last_flag = Node::_last_flag 1440 }; 1441}; 1442 1443%} // end source_hpp section 1444 1445source %{ 1446 1447// This exception handler code snippet is placed after the method's 1448// code. It is the return point if an exception occurred. it jumps to 1449// the exception blob. 1450// 1451// If the method gets deoptimized, the method and this code snippet 1452// get patched. 1453// 1454// 1) Trampoline code gets patched into the end of this exception 1455// handler. the trampoline code jumps to the deoptimization blob. 1456// 1457// 2) The return address in the method's code will get patched such 1458// that it jumps to the trampoline. 1459// 1460// 3) The handler will get patched such that it does not jump to the 1461// exception blob, but to an entry in the deoptimization blob being 1462// aware of the exception. 1463int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 1464 Register temp_reg = Z_R1; 1465 C2_MacroAssembler _masm(&cbuf); 1466 1467 address base = __ start_a_stub(size_exception_handler()); 1468 if (base == NULL) { 1469 return 0; // CodeBuffer::expand failed 1470 } 1471 1472 int offset = __ offset(); 1473 // Use unconditional pc-relative jump with 32-bit range here. 1474 __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin()); 1475 __ z_br(temp_reg); 1476 1477 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1478 1479 __ end_a_stub(); 1480 1481 return offset; 1482} 1483 1484// Emit deopt handler code. 1485int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1486 C2_MacroAssembler _masm(&cbuf); 1487 address base = __ start_a_stub(size_deopt_handler()); 1488 1489 if (base == NULL) { 1490 return 0; // CodeBuffer::expand failed 1491 } 1492 1493 int offset = __ offset(); 1494 1495 // Size_deopt_handler() must be exact on zarch, so for simplicity 1496 // we do not use load_const_opt here. 1497 __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack()); 1498 __ call(Z_R1); 1499 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 1500 1501 __ end_a_stub(); 1502 return offset; 1503} 1504 1505//============================================================================= 1506 1507 1508// Given a register encoding, produce an Integer Register object. 1509static Register reg_to_register_object(int register_encoding) { 1510 assert(Z_R12->encoding() == Z_R12_enc, "wrong coding"); 1511 return as_Register(register_encoding); 1512} 1513 1514const bool Matcher::match_rule_supported(int opcode) { 1515 if (!has_match_rule(opcode)) { 1516 return false; // no match rule present 1517 } 1518 1519 switch (opcode) { 1520 case Op_ReverseBytesI: 1521 case Op_ReverseBytesL: 1522 return UseByteReverseInstruction; 1523 case Op_PopCountI: 1524 case Op_PopCountL: 1525 // PopCount supported by H/W from z/Architecture G5 (z196) on. 1526 return (UsePopCountInstruction && VM_Version::has_PopCount()); 1527 } 1528 1529 return true; // Per default match rules are supported. 1530} 1531 1532const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) { 1533 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) { 1534 return false; 1535 } 1536 return true; // Per default match rules are supported. 1537} 1538 1539const RegMask* Matcher::predicate_reg_mask(void) { 1540 return NULL; 1541} 1542 1543const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) { 1544 return NULL; 1545} 1546 1547// Vector calling convention not yet implemented. 1548const bool Matcher::supports_vector_calling_convention(void) { 1549 return false; 1550} 1551 1552OptoRegPair Matcher::vector_return_value(uint ideal_reg) { 1553 Unimplemented(); 1554 return OptoRegPair(0, 0); 1555} 1556 1557const int Matcher::float_pressure(int default_pressure_threshold) { 1558 return default_pressure_threshold; 1559} 1560 1561//----------SUPERWORD HELPERS---------------------------------------- 1562 1563// Vector width in bytes. 1564const int Matcher::vector_width_in_bytes(BasicType bt) { 1565 assert(MaxVectorSize == 8, ""); 1566 return 8; 1567} 1568 1569// Vector ideal reg. 1570const uint Matcher::vector_ideal_reg(int size) { 1571 assert(MaxVectorSize == 8 && size == 8, ""); 1572 return Op_RegL; 1573} 1574 1575// Limits on vector size (number of elements) loaded into vector. 1576const int Matcher::max_vector_size(const BasicType bt) { 1577 assert(is_java_primitive(bt), "only primitive type vectors"); 1578 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1579} 1580 1581const int Matcher::min_vector_size(const BasicType bt) { 1582 return max_vector_size(bt); // Same as max. 1583} 1584 1585const int Matcher::scalable_vector_reg_size(const BasicType bt) { 1586 return -1; 1587} 1588 1589// RETURNS: whether this branch offset is short enough that a short 1590// branch can be used. 1591// 1592// If the platform does not provide any short branch variants, then 1593// this method should return `false' for offset 0. 1594// 1595// `Compile::Fill_buffer' will decide on basis of this information 1596// whether to do the pass `Compile::Shorten_branches' at all. 1597// 1598// And `Compile::Shorten_branches' will decide on basis of this 1599// information whether to replace particular branch sites by short 1600// ones. 1601bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1602 // On zarch short branches use a 16 bit signed immediate that 1603 // is the pc-relative offset in halfword (= 2 bytes) units. 1604 return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0); 1605} 1606 1607MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) { 1608 ShouldNotReachHere(); // generic vector operands not supported 1609 return NULL; 1610} 1611 1612bool Matcher::is_generic_reg2reg_move(MachNode* m) { 1613 ShouldNotReachHere(); // generic vector operands not supported 1614 return false; 1615} 1616 1617bool Matcher::is_generic_vector(MachOper* opnd) { 1618 ShouldNotReachHere(); // generic vector operands not supported 1619 return false; 1620} 1621 1622// Constants for c2c and c calling conventions. 1623 1624const MachRegisterNumbers z_iarg_reg[5] = { 1625 Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num 1626}; 1627 1628const MachRegisterNumbers z_farg_reg[4] = { 1629 Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num 1630}; 1631 1632const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]); 1633 1634const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]); 1635 1636// Return whether or not this register is ever used as an argument. This 1637// function is used on startup to build the trampoline stubs in generateOptoStub. 1638// Registers not mentioned will be killed by the VM call in the trampoline, and 1639// arguments in those registers not be available to the callee. 1640bool Matcher::can_be_java_arg(int reg) { 1641 // We return true for all registers contained in z_iarg_reg[] and 1642 // z_farg_reg[] and their virtual halves. 1643 // We must include the virtual halves in order to get STDs and LDs 1644 // instead of STWs and LWs in the trampoline stubs. 1645 1646 if (reg == Z_R2_num || reg == Z_R2_H_num || 1647 reg == Z_R3_num || reg == Z_R3_H_num || 1648 reg == Z_R4_num || reg == Z_R4_H_num || 1649 reg == Z_R5_num || reg == Z_R5_H_num || 1650 reg == Z_R6_num || reg == Z_R6_H_num) { 1651 return true; 1652 } 1653 1654 if (reg == Z_F0_num || reg == Z_F0_H_num || 1655 reg == Z_F2_num || reg == Z_F2_H_num || 1656 reg == Z_F4_num || reg == Z_F4_H_num || 1657 reg == Z_F6_num || reg == Z_F6_H_num) { 1658 return true; 1659 } 1660 1661 return false; 1662} 1663 1664bool Matcher::is_spillable_arg(int reg) { 1665 return can_be_java_arg(reg); 1666} 1667 1668bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 1669 return false; 1670} 1671 1672// Register for DIVI projection of divmodI 1673RegMask Matcher::divI_proj_mask() { 1674 return _Z_RARG4_INT_REG_mask; 1675} 1676 1677// Register for MODI projection of divmodI 1678RegMask Matcher::modI_proj_mask() { 1679 return _Z_RARG3_INT_REG_mask; 1680} 1681 1682// Register for DIVL projection of divmodL 1683RegMask Matcher::divL_proj_mask() { 1684 return _Z_RARG4_LONG_REG_mask; 1685} 1686 1687// Register for MODL projection of divmodL 1688RegMask Matcher::modL_proj_mask() { 1689 return _Z_RARG3_LONG_REG_mask; 1690} 1691 1692// Copied from sparc. 1693const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1694 return RegMask(); 1695} 1696 1697// Should the matcher clone input 'm' of node 'n'? 1698bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) { 1699 return false; 1700} 1701 1702// Should the Matcher clone shifts on addressing modes, expecting them 1703// to be subsumed into complex addressing expressions or compute them 1704// into registers? 1705bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 1706 return clone_base_plus_offset_address(m, mstack, address_visited); 1707} 1708 1709%} // source 1710 1711//----------ENCODING BLOCK----------------------------------------------------- 1712// This block specifies the encoding classes used by the compiler to output 1713// byte streams. Encoding classes are parameterized macros used by 1714// Machine Instruction Nodes in order to generate the bit encoding of the 1715// instruction. Operands specify their base encoding interface with the 1716// interface keyword. There are currently supported four interfaces, 1717// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1718// operand to generate a function which returns its register number when 1719// queried. CONST_INTER causes an operand to generate a function which 1720// returns the value of the constant when queried. MEMORY_INTER causes an 1721// operand to generate four functions which return the Base Register, the 1722// Index Register, the Scale Value, and the Offset Value of the operand when 1723// queried. COND_INTER causes an operand to generate six functions which 1724// return the encoding code (ie - encoding bits for the instruction) 1725// associated with each basic boolean condition for a conditional instruction. 1726// 1727// Instructions specify two basic values for encoding. Again, a function 1728// is available to check if the constant displacement is an oop. They use the 1729// ins_encode keyword to specify their encoding classes (which must be 1730// a sequence of enc_class names, and their parameters, specified in 1731// the encoding block), and they use the 1732// opcode keyword to specify, in order, their primary, secondary, and 1733// tertiary opcode. Only the opcode sections which a particular instruction 1734// needs for encoding need to be specified. 1735encode %{ 1736 enc_class enc_unimplemented %{ 1737 C2_MacroAssembler _masm(&cbuf); 1738 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 1739 %} 1740 1741 enc_class enc_untested %{ 1742#ifdef ASSERT 1743 C2_MacroAssembler _masm(&cbuf); 1744 __ untested("Untested mach node encoding in AD file."); 1745#endif 1746 %} 1747 1748 enc_class z_rrform(iRegI dst, iRegI src) %{ 1749 assert((($primary >> 14) & 0x03) == 0, "Instruction format error"); 1750 assert( ($primary >> 16) == 0, "Instruction format error"); 1751 z_emit16(cbuf, $primary | 1752 Assembler::reg($dst$$reg,8,16) | 1753 Assembler::reg($src$$reg,12,16)); 1754 %} 1755 1756 enc_class z_rreform(iRegI dst1, iRegI src2) %{ 1757 assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); 1758 z_emit32(cbuf, $primary | 1759 Assembler::reg($dst1$$reg,24,32) | 1760 Assembler::reg($src2$$reg,28,32)); 1761 %} 1762 1763 enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{ 1764 assert((($primary >> 30) & 0x03) == 2, "Instruction format error"); 1765 z_emit32(cbuf, $primary | 1766 Assembler::reg($dst1$$reg,24,32) | 1767 Assembler::reg($src2$$reg,28,32) | 1768 Assembler::reg($src3$$reg,16,32)); 1769 %} 1770 1771 enc_class z_riform_signed(iRegI dst, immI16 src) %{ 1772 assert((($primary>>30) & 0x03) == 2, "Instruction format error"); 1773 z_emit32(cbuf, $primary | 1774 Assembler::reg($dst$$reg,8,32) | 1775 Assembler::simm16($src$$constant,16,32)); 1776 %} 1777 1778 enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{ 1779 assert((($primary>>30) & 0x03) == 2, "Instruction format error"); 1780 z_emit32(cbuf, $primary | 1781 Assembler::reg($dst$$reg,8,32) | 1782 Assembler::uimm16($src$$constant,16,32)); 1783 %} 1784 1785 enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{ 1786 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1787 z_emit48(cbuf, $primary | 1788 Assembler::reg($dst1$$reg,8,48) | 1789 Assembler::reg($src3$$reg,12,48) | 1790 Assembler::simm16($src2$$constant,16,48)); 1791 %} 1792 1793 enc_class z_rilform_signed(iRegI dst, immL32 src) %{ 1794 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1795 z_emit48(cbuf, $primary | 1796 Assembler::reg($dst$$reg,8,48) | 1797 Assembler::simm32($src$$constant,16,48)); 1798 %} 1799 1800 enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{ 1801 assert((($primary>>46) & 0x03) == 3, "Instruction format error"); 1802 z_emit48(cbuf, $primary | 1803 Assembler::reg($dst$$reg,8,48) | 1804 Assembler::uimm32($src$$constant,16,48)); 1805 %} 1806 1807 enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{ 1808 z_emit48(cbuf, $primary | 1809 Assembler::reg($dst$$reg,8,48) | 1810 Assembler::reg($src1$$reg,12,48) | 1811 Assembler::simm20($src2$$constant)); 1812 %} 1813 1814 enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{ 1815 z_emit48(cbuf, $primary | 1816 Assembler::reg($dst$$reg,8,48) | 1817 Assembler::reg($src$$reg,12,48) | 1818 Assembler::reg($shft$$reg,16,48) | 1819 Assembler::simm20(0)); 1820 %} 1821 1822 enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{ 1823 assert((($primary>>30) & 0x03) == 1, "Instruction format error"); 1824 z_emit32(cbuf, $primary | 1825 Assembler::reg($dst$$reg,8,32) | 1826 Assembler::reg($src1$$reg,12,32) | 1827 Assembler::reg($src2$$reg,16,32) | 1828 Assembler::uimm12($con$$constant,20,32)); 1829 %} 1830 1831 enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{ 1832 assert((($primary>>30) & 0x03) == 1, "Instruction format error"); 1833 z_emit32(cbuf, $primary | 1834 Assembler::reg($dst$$reg,8,32) | 1835 Assembler::reg($src$$reg,16,32) | 1836 Assembler::uimm12($con$$constant,20,32)); 1837 %} 1838 1839 enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{ 1840 z_emit48(cbuf, $primary | 1841 Assembler::reg($dst$$reg,8,48) | 1842 Assembler::reg($src1$$reg,12,48) | 1843 Assembler::reg($src2$$reg,16,48) | 1844 Assembler::simm20($con$$constant)); 1845 %} 1846 1847 enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{ 1848 z_emit48(cbuf, $primary | 1849 Assembler::reg($dst$$reg,8,48) | 1850 Assembler::reg($src$$reg,16,48) | 1851 Assembler::simm20($con$$constant)); 1852 %} 1853 1854 // Direct memory arithmetic. 1855 enc_class z_siyform(memoryRSY mem, immI8 src) %{ 1856 int disp = $mem$$disp; 1857 Register base = reg_to_register_object($mem$$base); 1858 int con = $src$$constant; 1859 1860 assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU"); 1861 z_emit_inst(cbuf, $primary | 1862 Assembler::regz(base,16,48) | 1863 Assembler::simm20(disp) | 1864 Assembler::simm8(con,8,48)); 1865 %} 1866 1867 enc_class z_silform(memoryRS mem, immI16 src) %{ 1868 z_emit_inst(cbuf, $primary | 1869 Assembler::regz(reg_to_register_object($mem$$base),16,48) | 1870 Assembler::uimm12($mem$$disp,20,48) | 1871 Assembler::simm16($src$$constant,32,48)); 1872 %} 1873 1874 // Encoder for FP ALU reg/mem instructions (support only short displacements). 1875 enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{ 1876 Register Ridx = $mem$$index$$Register; 1877 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1878 if ($primary > (1L << 32)) { 1879 z_emit_inst(cbuf, $primary | 1880 Assembler::reg($dst$$reg, 8, 48) | 1881 Assembler::uimm12($mem$$disp, 20, 48) | 1882 Assembler::reg(Ridx, 12, 48) | 1883 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1884 } else { 1885 z_emit_inst(cbuf, $primary | 1886 Assembler::reg($dst$$reg, 8, 32) | 1887 Assembler::uimm12($mem$$disp, 20, 32) | 1888 Assembler::reg(Ridx, 12, 32) | 1889 Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); 1890 } 1891 %} 1892 1893 enc_class z_form_rt_mem(iRegI dst, memory mem) %{ 1894 Register Ridx = $mem$$index$$Register; 1895 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1896 if ($primary > (1L<<32)) { 1897 z_emit_inst(cbuf, $primary | 1898 Assembler::reg($dst$$reg, 8, 48) | 1899 Assembler::simm20($mem$$disp) | 1900 Assembler::reg(Ridx, 12, 48) | 1901 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1902 } else { 1903 z_emit_inst(cbuf, $primary | 1904 Assembler::reg($dst$$reg, 8, 32) | 1905 Assembler::uimm12($mem$$disp, 20, 32) | 1906 Assembler::reg(Ridx, 12, 32) | 1907 Assembler::regz(reg_to_register_object($mem$$base), 16, 32)); 1908 } 1909 %} 1910 1911 enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{ 1912 int isize = $secondary > 1L << 32 ? 48 : 32; 1913 Register Ridx = $mem$$index$$Register; 1914 if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0. 1915 1916 if (Displacement::is_shortDisp((long)$mem$$disp)) { 1917 z_emit_inst(cbuf, $secondary | 1918 Assembler::reg($dst$$reg, 8, isize) | 1919 Assembler::uimm12($mem$$disp, 20, isize) | 1920 Assembler::reg(Ridx, 12, isize) | 1921 Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); 1922 } else if (Displacement::is_validDisp((long)$mem$$disp)) { 1923 z_emit_inst(cbuf, $primary | 1924 Assembler::reg($dst$$reg, 8, 48) | 1925 Assembler::simm20($mem$$disp) | 1926 Assembler::reg(Ridx, 12, 48) | 1927 Assembler::regz(reg_to_register_object($mem$$base), 16, 48)); 1928 } else { 1929 C2_MacroAssembler _masm(&cbuf); 1930 __ load_const_optimized(Z_R1_scratch, $mem$$disp); 1931 if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); } 1932 z_emit_inst(cbuf, $secondary | 1933 Assembler::reg($dst$$reg, 8, isize) | 1934 Assembler::uimm12(0, 20, isize) | 1935 Assembler::reg(Z_R1_scratch, 12, isize) | 1936 Assembler::regz(reg_to_register_object($mem$$base), 16, isize)); 1937 } 1938 %} 1939 1940 enc_class z_enc_brul(Label lbl) %{ 1941 C2_MacroAssembler _masm(&cbuf); 1942 Label* p = $lbl$$label; 1943 1944 // 'p' is `NULL' when this encoding class is used only to 1945 // determine the size of the encoded instruction. 1946 // Use a bound dummy label in that case. 1947 Label d; 1948 __ bind(d); 1949 Label& l = (NULL == p) ? d : *(p); 1950 __ z_brul(l); 1951 %} 1952 1953 enc_class z_enc_bru(Label lbl) %{ 1954 C2_MacroAssembler _masm(&cbuf); 1955 Label* p = $lbl$$label; 1956 1957 // 'p' is `NULL' when this encoding class is used only to 1958 // determine the size of the encoded instruction. 1959 // Use a bound dummy label in that case. 1960 Label d; 1961 __ bind(d); 1962 Label& l = (NULL == p) ? d : *(p); 1963 __ z_bru(l); 1964 %} 1965 1966 enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{ 1967 C2_MacroAssembler _masm(&cbuf); 1968 Label* p = $lbl$$label; 1969 1970 // 'p' is `NULL' when this encoding class is used only to 1971 // determine the size of the encoded instruction. 1972 // Use a bound dummy label in that case. 1973 Label d; 1974 __ bind(d); 1975 Label& l = (NULL == p) ? d : *(p); 1976 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 1977 %} 1978 1979 enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{ 1980 C2_MacroAssembler _masm(&cbuf); 1981 Label* p = $lbl$$label; 1982 1983 // 'p' is `NULL' when this encoding class is used only to 1984 // determine the size of the encoded instruction. 1985 // Use a bound dummy label in that case. 1986 Label d; 1987 __ bind(d); 1988 Label& l = (NULL == p) ? d : *(p); 1989 __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l); 1990 %} 1991 1992 enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{ 1993 C2_MacroAssembler _masm(&cbuf); 1994 Label* p = $lbl$$label; 1995 1996 // 'p' is `NULL' when this encoding class is used only to 1997 // determine the size of the encoded instruction. 1998 // Use a bound dummy label in that case. 1999 Label d; 2000 __ bind(d); 2001 Label& l = (NULL == p) ? d : *(p); 2002 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2003 unsigned long instr = $primary; 2004 if (instr == CRJ_ZOPC) { 2005 __ z_crj($src1$$Register, $src2$$Register, cc, l); 2006 } else if (instr == CLRJ_ZOPC) { 2007 __ z_clrj($src1$$Register, $src2$$Register, cc, l); 2008 } else if (instr == CGRJ_ZOPC) { 2009 __ z_cgrj($src1$$Register, $src2$$Register, cc, l); 2010 } else { 2011 guarantee(instr == CLGRJ_ZOPC, "opcode not implemented"); 2012 __ z_clgrj($src1$$Register, $src2$$Register, cc, l); 2013 } 2014 %} 2015 2016 enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{ 2017 C2_MacroAssembler _masm(&cbuf); 2018 Label* p = $lbl$$label; 2019 2020 // 'p' is `NULL' when this encoding class is used only to 2021 // determine the size of the encoded instruction. 2022 // Use a bound dummy label in that case. 2023 Label d; 2024 __ bind(d); 2025 Label& l = (NULL == p) ? d : *(p); 2026 2027 unsigned long instr = $primary; 2028 if (instr == CR_ZOPC) { 2029 __ z_cr($src1$$Register, $src2$$Register); 2030 } else if (instr == CLR_ZOPC) { 2031 __ z_clr($src1$$Register, $src2$$Register); 2032 } else if (instr == CGR_ZOPC) { 2033 __ z_cgr($src1$$Register, $src2$$Register); 2034 } else { 2035 guarantee(instr == CLGR_ZOPC, "opcode not implemented"); 2036 __ z_clgr($src1$$Register, $src2$$Register); 2037 } 2038 2039 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2040 %} 2041 2042 enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{ 2043 C2_MacroAssembler _masm(&cbuf); 2044 Label* p = $lbl$$label; 2045 2046 // 'p' is `NULL' when this encoding class is used only to 2047 // determine the size of the encoded instruction. 2048 // Use a bound dummy label in that case. 2049 Label d; 2050 __ bind(d); 2051 Label& l = (NULL == p) ? d : *(p); 2052 2053 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2054 unsigned long instr = $primary; 2055 if (instr == CIJ_ZOPC) { 2056 __ z_cij($src1$$Register, $src2$$constant, cc, l); 2057 } else if (instr == CLIJ_ZOPC) { 2058 __ z_clij($src1$$Register, $src2$$constant, cc, l); 2059 } else if (instr == CGIJ_ZOPC) { 2060 __ z_cgij($src1$$Register, $src2$$constant, cc, l); 2061 } else { 2062 guarantee(instr == CLGIJ_ZOPC, "opcode not implemented"); 2063 __ z_clgij($src1$$Register, $src2$$constant, cc, l); 2064 } 2065 %} 2066 2067 enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{ 2068 C2_MacroAssembler _masm(&cbuf); 2069 Label* p = $lbl$$label; 2070 2071 // 'p' is `NULL' when this encoding class is used only to 2072 // determine the size of the encoded instruction. 2073 // Use a bound dummy label in that case. 2074 Label d; 2075 __ bind(d); 2076 Label& l = (NULL == p) ? d : *(p); 2077 2078 unsigned long instr = $primary; 2079 if (instr == CHI_ZOPC) { 2080 __ z_chi($src1$$Register, $src2$$constant); 2081 } else if (instr == CLFI_ZOPC) { 2082 __ z_clfi($src1$$Register, $src2$$constant); 2083 } else if (instr == CGHI_ZOPC) { 2084 __ z_cghi($src1$$Register, $src2$$constant); 2085 } else { 2086 guarantee(instr == CLGFI_ZOPC, "opcode not implemented"); 2087 __ z_clgfi($src1$$Register, $src2$$constant); 2088 } 2089 2090 __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l); 2091 %} 2092 2093 // Call from Java to runtime. 2094 enc_class z_enc_java_to_runtime_call(method meth) %{ 2095 C2_MacroAssembler _masm(&cbuf); 2096 2097 // Save return pc before call to the place where we need it, since 2098 // callee doesn't. 2099 unsigned int start_off = __ offset(); 2100 // Compute size of "larl + stg + call_c_opt". 2101 const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size(); 2102 __ get_PC(Z_R14, size_of_code); 2103 __ save_return_pc(); 2104 assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off); 2105 2106 assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call"); 2107 address call_addr = __ call_c_opt((address)$meth$$method); 2108 if (call_addr == NULL) { 2109 Compile::current()->env()->record_out_of_memory_failure(); 2110 return; 2111 } 2112 2113#ifdef ASSERT 2114 // Plausibility check for size_of_code assumptions. 2115 unsigned int actual_ret_off = __ offset(); 2116 assert(start_off + size_of_code == actual_ret_off, "wrong return_pc"); 2117#endif 2118 %} 2119 2120 enc_class z_enc_java_static_call(method meth) %{ 2121 // Call to fixup routine. Fixup routine uses ScopeDesc info to determine 2122 // whom we intended to call. 2123 C2_MacroAssembler _masm(&cbuf); 2124 int ret_offset = 0; 2125 2126 if (!_method) { 2127 ret_offset = emit_call_reloc(_masm, $meth$$method, 2128 relocInfo::runtime_call_w_cp_type, ra_); 2129 } else { 2130 int method_index = resolved_method_index(cbuf); 2131 if (_optimized_virtual) { 2132 ret_offset = emit_call_reloc(_masm, $meth$$method, 2133 opt_virtual_call_Relocation::spec(method_index)); 2134 } else { 2135 ret_offset = emit_call_reloc(_masm, $meth$$method, 2136 static_call_Relocation::spec(method_index)); 2137 } 2138 } 2139 assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()"); 2140 2141 if (_method) { // Emit stub for static call. 2142 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2143 if (stub == NULL) { 2144 ciEnv::current()->record_failure("CodeCache is full"); 2145 return; 2146 } 2147 } 2148 %} 2149 2150 // Java dynamic call 2151 enc_class z_enc_java_dynamic_call(method meth) %{ 2152 C2_MacroAssembler _masm(&cbuf); 2153 unsigned int start_off = __ offset(); 2154 2155 int vtable_index = this->_vtable_index; 2156 if (vtable_index == -4) { 2157 Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2158 address virtual_call_oop_addr = NULL; 2159 2160 AddressLiteral empty_ic((address) Universe::non_oop_word()); 2161 virtual_call_oop_addr = __ pc(); 2162 bool success = __ load_const_from_toc(ic_reg, empty_ic); 2163 if (!success) { 2164 Compile::current()->env()->record_out_of_memory_failure(); 2165 return; 2166 } 2167 2168 // Call to fixup routine. Fixup routine uses ScopeDesc info 2169 // to determine who we intended to call. 2170 int method_index = resolved_method_index(cbuf); 2171 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index)); 2172 unsigned int ret_off = __ offset(); 2173 assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off); 2174 ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_); 2175 assert(_method, "lazy_constant may be wrong when _method==null"); 2176 } else { 2177 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2178 // Go through the vtable. Get receiver klass. Receiver already 2179 // checked for non-null. If we'll go thru a C2I adapter, the 2180 // interpreter expects method in Z_method. 2181 // Use Z_method to temporarily hold the klass oop. 2182 // Z_R1_scratch is destroyed. 2183 __ load_klass(Z_method, Z_R2); 2184 2185 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes(); 2186 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2187 2188 if (Displacement::is_validDisp(v_off) ) { 2189 // Can use load instruction with large offset. 2190 __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/)); 2191 } else { 2192 // Worse case, must load offset into register. 2193 __ load_const(Z_R1_scratch, v_off); 2194 __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/)); 2195 } 2196 // NOTE: for vtable dispatches, the vtable entry will never be 2197 // null. However it may very well end up in handle_wrong_method 2198 // if the method is abstract for the particular class. 2199 __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset())); 2200 // Call target. Either compiled code or C2I adapter. 2201 __ z_basr(Z_R14, Z_R1_scratch); 2202 unsigned int ret_off = __ offset(); 2203 } 2204 %} 2205 2206 enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{ 2207 C2_MacroAssembler _masm(&cbuf); 2208 Register Rdst = reg_to_register_object($dst$$reg); 2209 Register Rsrc = reg_to_register_object($src$$reg); 2210 2211 // Don't emit code if operands are identical (same register). 2212 if (Rsrc != Rdst) { 2213 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2214 2215 if (VM_Version::has_LoadStoreConditional()) { 2216 __ z_locgr(Rdst, Rsrc, cc); 2217 } else { 2218 // Branch if not (cmp cr). 2219 Label done; 2220 __ z_brc(Assembler::inverse_condition(cc), done); 2221 __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr. 2222 __ bind(done); 2223 } 2224 } 2225 %} 2226 2227 enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{ 2228 C2_MacroAssembler _masm(&cbuf); 2229 Register Rdst = reg_to_register_object($dst$$reg); 2230 int Csrc = $src$$constant; 2231 Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode; 2232 Label done; 2233 // Branch if not (cmp cr). 2234 __ z_brc(Assembler::inverse_condition(cc), done); 2235 if (Csrc == 0) { 2236 // Don't set CC. 2237 __ clear_reg(Rdst, true, false); // Use for int, long & ptr. 2238 } else { 2239 __ z_lghi(Rdst, Csrc); // Use for int, long & ptr. 2240 } 2241 __ bind(done); 2242 %} 2243 2244 enc_class z_enc_cctobool(iRegI res) %{ 2245 C2_MacroAssembler _masm(&cbuf); 2246 Register Rres = reg_to_register_object($res$$reg); 2247 2248 if (VM_Version::has_LoadStoreConditional()) { 2249 __ load_const_optimized(Z_R0_scratch, 0L); // false (failed) 2250 __ load_const_optimized(Rres, 1L); // true (succeed) 2251 __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual); 2252 } else { 2253 Label done; 2254 __ load_const_optimized(Rres, 0L); // false (failed) 2255 __ z_brne(done); // Assume true to be the common case. 2256 __ load_const_optimized(Rres, 1L); // true (succeed) 2257 __ bind(done); 2258 } 2259 %} 2260 2261 enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{ 2262 C2_MacroAssembler _masm(&cbuf); 2263 Register Rcomp = reg_to_register_object($compare_value$$reg); 2264 Register Rnew = reg_to_register_object($exchange_value$$reg); 2265 Register Raddr = reg_to_register_object($addr_ptr$$reg); 2266 2267 __ z_cs(Rcomp, Rnew, 0, Raddr); 2268 %} 2269 2270 enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{ 2271 C2_MacroAssembler _masm(&cbuf); 2272 Register Rcomp = reg_to_register_object($compare_value$$reg); 2273 Register Rnew = reg_to_register_object($exchange_value$$reg); 2274 Register Raddr = reg_to_register_object($addr_ptr$$reg); 2275 2276 __ z_csg(Rcomp, Rnew, 0, Raddr); 2277 %} 2278 2279 enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{ 2280 C2_MacroAssembler _masm(&cbuf); 2281 Register Rdst = reg_to_register_object($dst$$reg); 2282 Register Rtmp = reg_to_register_object($tmp$$reg); 2283 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); 2284 Label retry; 2285 2286 // Iterate until swap succeeds. 2287 __ z_llgf(Rtmp, $mem$$Address); // current contents 2288 __ bind(retry); 2289 // Calculate incremented value. 2290 __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value. 2291 __ z_brne(retry); // Yikes, concurrent update, need to retry. 2292 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. 2293 %} 2294 2295 enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{ 2296 C2_MacroAssembler _masm(&cbuf); 2297 Register Rdst = reg_to_register_object($dst$$reg); 2298 Register Rtmp = reg_to_register_object($tmp$$reg); 2299 guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF"); 2300 Label retry; 2301 2302 // Iterate until swap succeeds. 2303 __ z_lg(Rtmp, $mem$$Address); // current contents 2304 __ bind(retry); 2305 // Calculate incremented value. 2306 __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value. 2307 __ z_brne(retry); // Yikes, concurrent update, need to retry. 2308 __ z_lgr(Rdst, Rtmp); // Exchanged value from memory is return value. 2309 %} 2310 2311%} // encode 2312 2313source %{ 2314 2315 // Check whether outs are all Stores. If so, we can omit clearing the upper 2316 // 32 bits after encoding. 2317 static bool all_outs_are_Stores(const Node *n) { 2318 for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) { 2319 Node *out = n->fast_out(k); 2320 if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) { 2321 // Most other outs are SpillCopy, but there are various other. 2322 // jvm98 has arond 9% Encodes where we return false. 2323 return false; 2324 } 2325 } 2326 return true; 2327 } 2328 2329%} // source 2330 2331 2332//----------FRAME-------------------------------------------------------------- 2333// Definition of frame structure and management information. 2334 2335frame %{ 2336 // These two registers define part of the calling convention between 2337 // compiled code and the interpreter. 2338 2339 // Inline Cache Register 2340 inline_cache_reg(Z_R9); // Z_inline_cache 2341 2342 // Argument pointer for I2C adapters 2343 // 2344 // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6. 2345 // interpreter_arg_ptr_reg(Z_R6); 2346 2347 // Optional: name the operand used by cisc-spilling to access 2348 // [stack_pointer + offset]. 2349 cisc_spilling_operand_name(indOffset12); 2350 2351 // Number of stack slots consumed by a Monitor enter. 2352 sync_stack_slots(frame::jit_monitor_size_in_4_byte_units); 2353 2354 // Compiled code's Frame Pointer 2355 // 2356 // z/Architecture stack pointer 2357 frame_pointer(Z_R15); // Z_SP 2358 2359 // Interpreter stores its frame pointer in a register which is 2360 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 2361 // interpreted java to compiled java. 2362 // 2363 // Z_state holds pointer to caller's cInterpreter. 2364 interpreter_frame_pointer(Z_R7); // Z_state 2365 2366 // Use alignment_in_bytes instead of log_2_of_alignment_in_bits. 2367 stack_alignment(frame::alignment_in_bytes); 2368 2369 // A `slot' is assumed 4 bytes here! 2370 // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units); 2371 2372 // Number of outgoing stack slots killed above the 2373 // out_preserve_stack_slots for calls to C. Supports the var-args 2374 // backing area for register parms. 2375 varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 2376 2377 // The after-PROLOG location of the return address. Location of 2378 // return address specifies a type (REG or STACK) and a number 2379 // representing the register number (i.e. - use a register name) or 2380 // stack slot. 2381 return_addr(REG Z_R14); 2382 2383 // Location of native (C/C++) and interpreter return values. This 2384 // is specified to be the same as Java. In the 32-bit VM, long 2385 // values are actually returned from native calls in O0:O1 and 2386 // returned to the interpreter in I0:I1. The copying to and from 2387 // the register pairs is done by the appropriate call and epilog 2388 // opcodes. This simplifies the register allocator. 2389 // 2390 // Use register pair for c return value. 2391 c_return_value %{ 2392 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); 2393 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num }; 2394 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num }; 2395 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 2396 %} 2397 2398 // Use register pair for return value. 2399 // Location of compiled Java return values. Same as C 2400 return_value %{ 2401 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values"); 2402 static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num }; 2403 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num }; 2404 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 2405 %} 2406%} 2407 2408 2409//----------ATTRIBUTES--------------------------------------------------------- 2410 2411//----------Operand Attributes------------------------------------------------- 2412op_attrib op_cost(1); // Required cost attribute 2413 2414//----------Instruction Attributes--------------------------------------------- 2415 2416// Cost attribute. required. 2417ins_attrib ins_cost(DEFAULT_COST); 2418 2419// Is this instruction a non-matching short branch variant of some 2420// long branch? Not required. 2421ins_attrib ins_short_branch(0); 2422 2423// Indicates this is a trap based check node and final control-flow fixup 2424// must generate a proper fall through. 2425ins_attrib ins_is_TrapBasedCheckNode(true); 2426 2427// Attribute of instruction to tell how many constants the instruction will generate. 2428// (optional attribute). Default: 0. 2429ins_attrib ins_num_consts(0); 2430 2431// Required alignment attribute (must be a power of 2) 2432// specifies the alignment that some part of the instruction (not 2433// necessarily the start) requires. If > 1, a compute_padding() 2434// function must be provided for the instruction. 2435// 2436// WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in 2437// instructions which depend on the proper alignment, because the 2438// desired alignment isn't guaranteed for the call to "emit()" during 2439// the size computation. 2440ins_attrib ins_alignment(1); 2441 2442// Enforce/prohibit rematerializations. 2443// - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 2444// then rematerialization of that instruction is prohibited and the 2445// instruction's value will be spilled if necessary. 2446// - If an instruction is attributed with 'ins_should_rematerialize(true)' 2447// then rematerialization is enforced and the instruction's value will 2448// never get spilled. a copy of the instruction will be inserted if 2449// necessary. 2450// Note: this may result in rematerializations in front of every use. 2451// (optional attribute) 2452ins_attrib ins_cannot_rematerialize(false); 2453ins_attrib ins_should_rematerialize(false); 2454 2455//----------OPERANDS----------------------------------------------------------- 2456// Operand definitions must precede instruction definitions for correct 2457// parsing in the ADLC because operands constitute user defined types 2458// which are used in instruction definitions. 2459 2460//----------Simple Operands---------------------------------------------------- 2461// Immediate Operands 2462// Please note: 2463// Formats are generated automatically for constants and base registers. 2464 2465//---------------------------------------------- 2466// SIGNED (shorter than INT) immediate operands 2467//---------------------------------------------- 2468 2469// Byte Immediate: constant 'int -1' 2470operand immB_minus1() %{ 2471 // sign-ext constant zero-ext constant 2472 predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff)); 2473 match(ConI); 2474 op_cost(1); 2475 format %{ %} 2476 interface(CONST_INTER); 2477%} 2478 2479// Byte Immediate: constant, but not 'int 0' nor 'int -1'. 2480operand immB_n0m1() %{ 2481 // sign-ext constant zero-ext constant 2482 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff); 2483 match(ConI); 2484 op_cost(1); 2485 format %{ %} 2486 interface(CONST_INTER); 2487%} 2488 2489// Short Immediate: constant 'int -1' 2490operand immS_minus1() %{ 2491 // sign-ext constant zero-ext constant 2492 predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff)); 2493 match(ConI); 2494 op_cost(1); 2495 format %{ %} 2496 interface(CONST_INTER); 2497%} 2498 2499// Short Immediate: constant, but not 'int 0' nor 'int -1'. 2500operand immS_n0m1() %{ 2501 // sign-ext constant zero-ext constant 2502 predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff); 2503 match(ConI); 2504 op_cost(1); 2505 format %{ %} 2506 interface(CONST_INTER); 2507%} 2508 2509//----------------------------------------- 2510// SIGNED INT immediate operands 2511//----------------------------------------- 2512 2513// Integer Immediate: 32-bit 2514operand immI() %{ 2515 match(ConI); 2516 op_cost(1); 2517 format %{ %} 2518 interface(CONST_INTER); 2519%} 2520 2521// Int Immediate: 20-bit 2522operand immI20() %{ 2523 predicate(Immediate::is_simm20(n->get_int())); 2524 match(ConI); 2525 op_cost(1); 2526 format %{ %} 2527 interface(CONST_INTER); 2528%} 2529 2530// Integer Immediate: 16-bit 2531operand immI16() %{ 2532 predicate(Immediate::is_simm16(n->get_int())); 2533 match(ConI); 2534 op_cost(1); 2535 format %{ %} 2536 interface(CONST_INTER); 2537%} 2538 2539// Integer Immediate: 8-bit 2540operand immI8() %{ 2541 predicate(Immediate::is_simm8(n->get_int())); 2542 match(ConI); 2543 op_cost(1); 2544 format %{ %} 2545 interface(CONST_INTER); 2546%} 2547 2548// Integer Immediate: constant 'int 0' 2549operand immI_0() %{ 2550 predicate(n->get_int() == 0); 2551 match(ConI); 2552 op_cost(1); 2553 format %{ %} 2554 interface(CONST_INTER); 2555%} 2556 2557// Integer Immediate: constant 'int -1' 2558operand immI_minus1() %{ 2559 predicate(n->get_int() == -1); 2560 match(ConI); 2561 op_cost(1); 2562 format %{ %} 2563 interface(CONST_INTER); 2564%} 2565 2566// Integer Immediate: constant, but not 'int 0' nor 'int -1'. 2567operand immI_n0m1() %{ 2568 predicate(n->get_int() != 0 && n->get_int() != -1); 2569 match(ConI); 2570 op_cost(1); 2571 format %{ %} 2572 interface(CONST_INTER); 2573%} 2574 2575//------------------------------------------- 2576// UNSIGNED INT immediate operands 2577//------------------------------------------- 2578 2579// Unsigned Integer Immediate: 32-bit 2580operand uimmI() %{ 2581 match(ConI); 2582 op_cost(1); 2583 format %{ %} 2584 interface(CONST_INTER); 2585%} 2586 2587// Unsigned Integer Immediate: 16-bit 2588operand uimmI16() %{ 2589 predicate(Immediate::is_uimm16(n->get_int())); 2590 match(ConI); 2591 op_cost(1); 2592 format %{ %} 2593 interface(CONST_INTER); 2594%} 2595 2596// Unsigned Integer Immediate: 12-bit 2597operand uimmI12() %{ 2598 predicate(Immediate::is_uimm12(n->get_int())); 2599 match(ConI); 2600 op_cost(1); 2601 format %{ %} 2602 interface(CONST_INTER); 2603%} 2604 2605// Unsigned Integer Immediate: 12-bit 2606operand uimmI8() %{ 2607 predicate(Immediate::is_uimm8(n->get_int())); 2608 match(ConI); 2609 op_cost(1); 2610 format %{ %} 2611 interface(CONST_INTER); 2612%} 2613 2614// Integer Immediate: 6-bit 2615operand uimmI6() %{ 2616 predicate(Immediate::is_uimm(n->get_int(), 6)); 2617 match(ConI); 2618 op_cost(1); 2619 format %{ %} 2620 interface(CONST_INTER); 2621%} 2622 2623// Integer Immediate: 5-bit 2624operand uimmI5() %{ 2625 predicate(Immediate::is_uimm(n->get_int(), 5)); 2626 match(ConI); 2627 op_cost(1); 2628 format %{ %} 2629 interface(CONST_INTER); 2630%} 2631 2632// Length for SS instructions, given in DWs, 2633// possible range [1..512], i.e. [8..4096] Bytes 2634// used range [1..256], i.e. [8..2048] Bytes 2635// operand type int 2636// Unsigned Integer Immediate: 9-bit 2637operand SSlenDW() %{ 2638 predicate(Immediate::is_uimm8(n->get_long()-1)); 2639 match(ConL); 2640 op_cost(1); 2641 format %{ %} 2642 interface(CONST_INTER); 2643%} 2644 2645//------------------------------------------ 2646// (UN)SIGNED INT specific values 2647//------------------------------------------ 2648 2649// Integer Immediate: the value 1 2650operand immI_1() %{ 2651 predicate(n->get_int() == 1); 2652 match(ConI); 2653 op_cost(1); 2654 format %{ %} 2655 interface(CONST_INTER); 2656%} 2657 2658// Integer Immediate: the value 16. 2659operand immI_16() %{ 2660 predicate(n->get_int() == 16); 2661 match(ConI); 2662 op_cost(1); 2663 format %{ %} 2664 interface(CONST_INTER); 2665%} 2666 2667// Integer Immediate: the value 24. 2668operand immI_24() %{ 2669 predicate(n->get_int() == 24); 2670 match(ConI); 2671 op_cost(1); 2672 format %{ %} 2673 interface(CONST_INTER); 2674%} 2675 2676// Integer Immediate: the value 255 2677operand immI_255() %{ 2678 predicate(n->get_int() == 255); 2679 match(ConI); 2680 op_cost(1); 2681 format %{ %} 2682 interface(CONST_INTER); 2683%} 2684 2685// Integer Immediate: the values 32-63 2686operand immI_32_63() %{ 2687 predicate(n->get_int() >= 32 && n->get_int() <= 63); 2688 match(ConI); 2689 op_cost(1); 2690 format %{ %} 2691 interface(CONST_INTER); 2692%} 2693 2694// Unsigned Integer Immediate: LL-part, extended by 1s. 2695operand uimmI_LL1() %{ 2696 predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000); 2697 match(ConI); 2698 op_cost(1); 2699 format %{ %} 2700 interface(CONST_INTER); 2701%} 2702 2703// Unsigned Integer Immediate: LH-part, extended by 1s. 2704operand uimmI_LH1() %{ 2705 predicate((n->get_int() & 0xFFFF) == 0xFFFF); 2706 match(ConI); 2707 op_cost(1); 2708 format %{ %} 2709 interface(CONST_INTER); 2710%} 2711 2712//------------------------------------------ 2713// SIGNED LONG immediate operands 2714//------------------------------------------ 2715 2716operand immL() %{ 2717 match(ConL); 2718 op_cost(1); 2719 format %{ %} 2720 interface(CONST_INTER); 2721%} 2722 2723// Long Immediate: 32-bit 2724operand immL32() %{ 2725 predicate(Immediate::is_simm32(n->get_long())); 2726 match(ConL); 2727 op_cost(1); 2728 format %{ %} 2729 interface(CONST_INTER); 2730%} 2731 2732// Long Immediate: 20-bit 2733operand immL20() %{ 2734 predicate(Immediate::is_simm20(n->get_long())); 2735 match(ConL); 2736 op_cost(1); 2737 format %{ %} 2738 interface(CONST_INTER); 2739%} 2740 2741// Long Immediate: 16-bit 2742operand immL16() %{ 2743 predicate(Immediate::is_simm16(n->get_long())); 2744 match(ConL); 2745 op_cost(1); 2746 format %{ %} 2747 interface(CONST_INTER); 2748%} 2749 2750// Long Immediate: 8-bit 2751operand immL8() %{ 2752 predicate(Immediate::is_simm8(n->get_long())); 2753 match(ConL); 2754 op_cost(1); 2755 format %{ %} 2756 interface(CONST_INTER); 2757%} 2758 2759//-------------------------------------------- 2760// UNSIGNED LONG immediate operands 2761//-------------------------------------------- 2762 2763operand uimmL32() %{ 2764 predicate(Immediate::is_uimm32(n->get_long())); 2765 match(ConL); 2766 op_cost(1); 2767 format %{ %} 2768 interface(CONST_INTER); 2769%} 2770 2771// Unsigned Long Immediate: 16-bit 2772operand uimmL16() %{ 2773 predicate(Immediate::is_uimm16(n->get_long())); 2774 match(ConL); 2775 op_cost(1); 2776 format %{ %} 2777 interface(CONST_INTER); 2778%} 2779 2780// Unsigned Long Immediate: 12-bit 2781operand uimmL12() %{ 2782 predicate(Immediate::is_uimm12(n->get_long())); 2783 match(ConL); 2784 op_cost(1); 2785 format %{ %} 2786 interface(CONST_INTER); 2787%} 2788 2789// Unsigned Long Immediate: 8-bit 2790operand uimmL8() %{ 2791 predicate(Immediate::is_uimm8(n->get_long())); 2792 match(ConL); 2793 op_cost(1); 2794 format %{ %} 2795 interface(CONST_INTER); 2796%} 2797 2798//------------------------------------------- 2799// (UN)SIGNED LONG specific values 2800//------------------------------------------- 2801 2802// Long Immediate: the value FF 2803operand immL_FF() %{ 2804 predicate(n->get_long() == 0xFFL); 2805 match(ConL); 2806 op_cost(1); 2807 format %{ %} 2808 interface(CONST_INTER); 2809%} 2810 2811// Long Immediate: the value FFFF 2812operand immL_FFFF() %{ 2813 predicate(n->get_long() == 0xFFFFL); 2814 match(ConL); 2815 op_cost(1); 2816 format %{ %} 2817 interface(CONST_INTER); 2818%} 2819 2820// Long Immediate: the value FFFFFFFF 2821operand immL_FFFFFFFF() %{ 2822 predicate(n->get_long() == 0xFFFFFFFFL); 2823 match(ConL); 2824 op_cost(1); 2825 format %{ %} 2826 interface(CONST_INTER); 2827%} 2828 2829operand immL_0() %{ 2830 predicate(n->get_long() == 0L); 2831 match(ConL); 2832 op_cost(1); 2833 format %{ %} 2834 interface(CONST_INTER); 2835%} 2836 2837// Unsigned Long Immediate: LL-part, extended by 1s. 2838operand uimmL_LL1() %{ 2839 predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L); 2840 match(ConL); 2841 op_cost(1); 2842 format %{ %} 2843 interface(CONST_INTER); 2844%} 2845 2846// Unsigned Long Immediate: LH-part, extended by 1s. 2847operand uimmL_LH1() %{ 2848 predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL); 2849 match(ConL); 2850 op_cost(1); 2851 format %{ %} 2852 interface(CONST_INTER); 2853%} 2854 2855// Unsigned Long Immediate: HL-part, extended by 1s. 2856operand uimmL_HL1() %{ 2857 predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL); 2858 match(ConL); 2859 op_cost(1); 2860 format %{ %} 2861 interface(CONST_INTER); 2862%} 2863 2864// Unsigned Long Immediate: HH-part, extended by 1s. 2865operand uimmL_HH1() %{ 2866 predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL); 2867 match(ConL); 2868 op_cost(1); 2869 format %{ %} 2870 interface(CONST_INTER); 2871%} 2872 2873// Long Immediate: low 32-bit mask 2874operand immL_32bits() %{ 2875 predicate(n->get_long() == 0xFFFFFFFFL); 2876 match(ConL); 2877 op_cost(1); 2878 format %{ %} 2879 interface(CONST_INTER); 2880%} 2881 2882//-------------------------------------- 2883// POINTER immediate operands 2884//-------------------------------------- 2885 2886// Pointer Immediate: 64-bit 2887operand immP() %{ 2888 match(ConP); 2889 op_cost(1); 2890 format %{ %} 2891 interface(CONST_INTER); 2892%} 2893 2894// Pointer Immediate: 32-bit 2895operand immP32() %{ 2896 predicate(Immediate::is_uimm32(n->get_ptr())); 2897 match(ConP); 2898 op_cost(1); 2899 format %{ %} 2900 interface(CONST_INTER); 2901%} 2902 2903// Pointer Immediate: 16-bit 2904operand immP16() %{ 2905 predicate(Immediate::is_uimm16(n->get_ptr())); 2906 match(ConP); 2907 op_cost(1); 2908 format %{ %} 2909 interface(CONST_INTER); 2910%} 2911 2912// Pointer Immediate: 8-bit 2913operand immP8() %{ 2914 predicate(Immediate::is_uimm8(n->get_ptr())); 2915 match(ConP); 2916 op_cost(1); 2917 format %{ %} 2918 interface(CONST_INTER); 2919%} 2920 2921//----------------------------------- 2922// POINTER specific values 2923//----------------------------------- 2924 2925// Pointer Immediate: NULL 2926operand immP0() %{ 2927 predicate(n->get_ptr() == 0); 2928 match(ConP); 2929 op_cost(1); 2930 format %{ %} 2931 interface(CONST_INTER); 2932%} 2933 2934//--------------------------------------------- 2935// NARROW POINTER immediate operands 2936//--------------------------------------------- 2937 2938// Narrow Pointer Immediate 2939operand immN() %{ 2940 match(ConN); 2941 op_cost(1); 2942 format %{ %} 2943 interface(CONST_INTER); 2944%} 2945 2946operand immNKlass() %{ 2947 match(ConNKlass); 2948 op_cost(1); 2949 format %{ %} 2950 interface(CONST_INTER); 2951%} 2952 2953// Narrow Pointer Immediate 2954operand immN8() %{ 2955 predicate(Immediate::is_uimm8(n->get_narrowcon())); 2956 match(ConN); 2957 op_cost(1); 2958 format %{ %} 2959 interface(CONST_INTER); 2960%} 2961 2962// Narrow NULL Pointer Immediate 2963operand immN0() %{ 2964 predicate(n->get_narrowcon() == 0); 2965 match(ConN); 2966 op_cost(1); 2967 format %{ %} 2968 interface(CONST_INTER); 2969%} 2970 2971// FLOAT and DOUBLE immediate operands 2972 2973// Double Immediate 2974operand immD() %{ 2975 match(ConD); 2976 op_cost(1); 2977 format %{ %} 2978 interface(CONST_INTER); 2979%} 2980 2981// Double Immediate: +-0 2982operand immDpm0() %{ 2983 predicate(n->getd() == 0); 2984 match(ConD); 2985 op_cost(1); 2986 format %{ %} 2987 interface(CONST_INTER); 2988%} 2989 2990// Double Immediate: +0 2991operand immDp0() %{ 2992 predicate(jlong_cast(n->getd()) == 0); 2993 match(ConD); 2994 op_cost(1); 2995 format %{ %} 2996 interface(CONST_INTER); 2997%} 2998 2999// Float Immediate 3000operand immF() %{ 3001 match(ConF); 3002 op_cost(1); 3003 format %{ %} 3004 interface(CONST_INTER); 3005%} 3006 3007// Float Immediate: +-0 3008operand immFpm0() %{ 3009 predicate(n->getf() == 0); 3010 match(ConF); 3011 op_cost(1); 3012 format %{ %} 3013 interface(CONST_INTER); 3014%} 3015 3016// Float Immediate: +0 3017operand immFp0() %{ 3018 predicate(jint_cast(n->getf()) == 0); 3019 match(ConF); 3020 op_cost(1); 3021 format %{ %} 3022 interface(CONST_INTER); 3023%} 3024 3025// End of Immediate Operands 3026 3027// Integer Register Operands 3028// Integer Register 3029operand iRegI() %{ 3030 constraint(ALLOC_IN_RC(z_int_reg)); 3031 match(RegI); 3032 match(noArg_iRegI); 3033 match(rarg1RegI); 3034 match(rarg2RegI); 3035 match(rarg3RegI); 3036 match(rarg4RegI); 3037 match(rarg5RegI); 3038 match(noOdd_iRegI); 3039 match(revenRegI); 3040 match(roddRegI); 3041 format %{ %} 3042 interface(REG_INTER); 3043%} 3044 3045operand noArg_iRegI() %{ 3046 constraint(ALLOC_IN_RC(z_no_arg_int_reg)); 3047 match(RegI); 3048 format %{ %} 3049 interface(REG_INTER); 3050%} 3051 3052// revenRegI and roddRegI constitute and even-odd-pair. 3053operand revenRegI() %{ 3054 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3055 match(iRegI); 3056 format %{ %} 3057 interface(REG_INTER); 3058%} 3059 3060// revenRegI and roddRegI constitute and even-odd-pair. 3061operand roddRegI() %{ 3062 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3063 match(iRegI); 3064 format %{ %} 3065 interface(REG_INTER); 3066%} 3067 3068operand rarg1RegI() %{ 3069 constraint(ALLOC_IN_RC(z_rarg1_int_reg)); 3070 match(iRegI); 3071 format %{ %} 3072 interface(REG_INTER); 3073%} 3074 3075operand rarg2RegI() %{ 3076 constraint(ALLOC_IN_RC(z_rarg2_int_reg)); 3077 match(iRegI); 3078 format %{ %} 3079 interface(REG_INTER); 3080%} 3081 3082operand rarg3RegI() %{ 3083 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3084 match(iRegI); 3085 format %{ %} 3086 interface(REG_INTER); 3087%} 3088 3089operand rarg4RegI() %{ 3090 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3091 match(iRegI); 3092 format %{ %} 3093 interface(REG_INTER); 3094%} 3095 3096operand rarg5RegI() %{ 3097 constraint(ALLOC_IN_RC(z_rarg5_int_reg)); 3098 match(iRegI); 3099 format %{ %} 3100 interface(REG_INTER); 3101%} 3102 3103operand noOdd_iRegI() %{ 3104 constraint(ALLOC_IN_RC(z_no_odd_int_reg)); 3105 match(RegI); 3106 match(revenRegI); 3107 format %{ %} 3108 interface(REG_INTER); 3109%} 3110 3111// Pointer Register 3112operand iRegP() %{ 3113 constraint(ALLOC_IN_RC(z_ptr_reg)); 3114 match(RegP); 3115 match(noArg_iRegP); 3116 match(rarg1RegP); 3117 match(rarg2RegP); 3118 match(rarg3RegP); 3119 match(rarg4RegP); 3120 match(rarg5RegP); 3121 match(revenRegP); 3122 match(roddRegP); 3123 format %{ %} 3124 interface(REG_INTER); 3125%} 3126 3127// thread operand 3128operand threadRegP() %{ 3129 constraint(ALLOC_IN_RC(z_thread_ptr_reg)); 3130 match(RegP); 3131 format %{ "Z_THREAD" %} 3132 interface(REG_INTER); 3133%} 3134 3135operand noArg_iRegP() %{ 3136 constraint(ALLOC_IN_RC(z_no_arg_ptr_reg)); 3137 match(iRegP); 3138 format %{ %} 3139 interface(REG_INTER); 3140%} 3141 3142operand rarg1RegP() %{ 3143 constraint(ALLOC_IN_RC(z_rarg1_ptr_reg)); 3144 match(iRegP); 3145 format %{ %} 3146 interface(REG_INTER); 3147%} 3148 3149operand rarg2RegP() %{ 3150 constraint(ALLOC_IN_RC(z_rarg2_ptr_reg)); 3151 match(iRegP); 3152 format %{ %} 3153 interface(REG_INTER); 3154%} 3155 3156operand rarg3RegP() %{ 3157 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); 3158 match(iRegP); 3159 format %{ %} 3160 interface(REG_INTER); 3161%} 3162 3163operand rarg4RegP() %{ 3164 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); 3165 match(iRegP); 3166 format %{ %} 3167 interface(REG_INTER); 3168%} 3169 3170operand rarg5RegP() %{ 3171 constraint(ALLOC_IN_RC(z_rarg5_ptr_reg)); 3172 match(iRegP); 3173 format %{ %} 3174 interface(REG_INTER); 3175%} 3176 3177operand memoryRegP() %{ 3178 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3179 match(RegP); 3180 match(iRegP); 3181 match(threadRegP); 3182 format %{ %} 3183 interface(REG_INTER); 3184%} 3185 3186// revenRegP and roddRegP constitute and even-odd-pair. 3187operand revenRegP() %{ 3188 constraint(ALLOC_IN_RC(z_rarg3_ptr_reg)); 3189 match(iRegP); 3190 format %{ %} 3191 interface(REG_INTER); 3192%} 3193 3194// revenRegP and roddRegP constitute and even-odd-pair. 3195operand roddRegP() %{ 3196 constraint(ALLOC_IN_RC(z_rarg4_ptr_reg)); 3197 match(iRegP); 3198 format %{ %} 3199 interface(REG_INTER); 3200%} 3201 3202operand lock_ptr_RegP() %{ 3203 constraint(ALLOC_IN_RC(z_lock_ptr_reg)); 3204 match(RegP); 3205 format %{ %} 3206 interface(REG_INTER); 3207%} 3208 3209operand rscratch2RegP() %{ 3210 constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg)); 3211 match(RegP); 3212 format %{ %} 3213 interface(REG_INTER); 3214%} 3215 3216operand iRegN() %{ 3217 constraint(ALLOC_IN_RC(z_int_reg)); 3218 match(RegN); 3219 match(noArg_iRegN); 3220 match(rarg1RegN); 3221 match(rarg2RegN); 3222 match(rarg3RegN); 3223 match(rarg4RegN); 3224 match(rarg5RegN); 3225 format %{ %} 3226 interface(REG_INTER); 3227%} 3228 3229operand noArg_iRegN() %{ 3230 constraint(ALLOC_IN_RC(z_no_arg_int_reg)); 3231 match(iRegN); 3232 format %{ %} 3233 interface(REG_INTER); 3234%} 3235 3236operand rarg1RegN() %{ 3237 constraint(ALLOC_IN_RC(z_rarg1_int_reg)); 3238 match(iRegN); 3239 format %{ %} 3240 interface(REG_INTER); 3241%} 3242 3243operand rarg2RegN() %{ 3244 constraint(ALLOC_IN_RC(z_rarg2_int_reg)); 3245 match(iRegN); 3246 format %{ %} 3247 interface(REG_INTER); 3248%} 3249 3250operand rarg3RegN() %{ 3251 constraint(ALLOC_IN_RC(z_rarg3_int_reg)); 3252 match(iRegN); 3253 format %{ %} 3254 interface(REG_INTER); 3255%} 3256 3257operand rarg4RegN() %{ 3258 constraint(ALLOC_IN_RC(z_rarg4_int_reg)); 3259 match(iRegN); 3260 format %{ %} 3261 interface(REG_INTER); 3262%} 3263 3264operand rarg5RegN() %{ 3265 constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg)); 3266 match(iRegN); 3267 format %{ %} 3268 interface(REG_INTER); 3269%} 3270 3271// Long Register 3272operand iRegL() %{ 3273 constraint(ALLOC_IN_RC(z_long_reg)); 3274 match(RegL); 3275 match(revenRegL); 3276 match(roddRegL); 3277 match(allRoddRegL); 3278 match(rarg1RegL); 3279 match(rarg5RegL); 3280 format %{ %} 3281 interface(REG_INTER); 3282%} 3283 3284// revenRegL and roddRegL constitute and even-odd-pair. 3285operand revenRegL() %{ 3286 constraint(ALLOC_IN_RC(z_rarg3_long_reg)); 3287 match(iRegL); 3288 format %{ %} 3289 interface(REG_INTER); 3290%} 3291 3292// revenRegL and roddRegL constitute and even-odd-pair. 3293operand roddRegL() %{ 3294 constraint(ALLOC_IN_RC(z_rarg4_long_reg)); 3295 match(iRegL); 3296 format %{ %} 3297 interface(REG_INTER); 3298%} 3299 3300// available odd registers for iRegL 3301operand allRoddRegL() %{ 3302 constraint(ALLOC_IN_RC(z_long_odd_reg)); 3303 match(iRegL); 3304 format %{ %} 3305 interface(REG_INTER); 3306%} 3307 3308operand rarg1RegL() %{ 3309 constraint(ALLOC_IN_RC(z_rarg1_long_reg)); 3310 match(iRegL); 3311 format %{ %} 3312 interface(REG_INTER); 3313%} 3314 3315operand rarg5RegL() %{ 3316 constraint(ALLOC_IN_RC(z_rarg5_long_reg)); 3317 match(iRegL); 3318 format %{ %} 3319 interface(REG_INTER); 3320%} 3321 3322// Condition Code Flag Registers 3323operand flagsReg() %{ 3324 constraint(ALLOC_IN_RC(z_condition_reg)); 3325 match(RegFlags); 3326 format %{ "CR" %} 3327 interface(REG_INTER); 3328%} 3329 3330// Condition Code Flag Registers for rules with result tuples 3331operand TD_flagsReg() %{ 3332 constraint(ALLOC_IN_RC(z_condition_reg)); 3333 match(RegFlags); 3334 format %{ "CR" %} 3335 interface(REG_TUPLE_DEST_INTER); 3336%} 3337 3338operand regD() %{ 3339 constraint(ALLOC_IN_RC(z_dbl_reg)); 3340 match(RegD); 3341 format %{ %} 3342 interface(REG_INTER); 3343%} 3344 3345operand rscratchRegD() %{ 3346 constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg)); 3347 match(RegD); 3348 format %{ %} 3349 interface(REG_INTER); 3350%} 3351 3352operand regF() %{ 3353 constraint(ALLOC_IN_RC(z_flt_reg)); 3354 match(RegF); 3355 format %{ %} 3356 interface(REG_INTER); 3357%} 3358 3359operand rscratchRegF() %{ 3360 constraint(ALLOC_IN_RC(z_rscratch1_flt_reg)); 3361 match(RegF); 3362 format %{ %} 3363 interface(REG_INTER); 3364%} 3365 3366// Special Registers 3367 3368// Method Register 3369operand inline_cache_regP(iRegP reg) %{ 3370 constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg 3371 match(reg); 3372 format %{ %} 3373 interface(REG_INTER); 3374%} 3375 3376// Operands to remove register moves in unscaled mode. 3377// Match read/write registers with an EncodeP node if neither shift nor add are required. 3378operand iRegP2N(iRegP reg) %{ 3379 predicate(CompressedOops::shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL); 3380 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3381 match(EncodeP reg); 3382 format %{ "$reg" %} 3383 interface(REG_INTER) 3384%} 3385 3386operand iRegN2P(iRegN reg) %{ 3387 predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0 && 3388 _leaf->as_DecodeN()->in(0) == NULL); 3389 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3390 match(DecodeN reg); 3391 format %{ "$reg" %} 3392 interface(REG_INTER) 3393%} 3394 3395 3396//----------Complex Operands--------------------------------------------------- 3397 3398// Indirect Memory Reference 3399operand indirect(memoryRegP base) %{ 3400 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3401 match(base); 3402 op_cost(1); 3403 format %{ "#0[,$base]" %} 3404 interface(MEMORY_INTER) %{ 3405 base($base); 3406 index(0xffffFFFF); // noreg 3407 scale(0x0); 3408 disp(0x0); 3409 %} 3410%} 3411 3412// Indirect with Offset (long) 3413operand indOffset20(memoryRegP base, immL20 offset) %{ 3414 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3415 match(AddP base offset); 3416 op_cost(1); 3417 format %{ "$offset[,$base]" %} 3418 interface(MEMORY_INTER) %{ 3419 base($base); 3420 index(0xffffFFFF); // noreg 3421 scale(0x0); 3422 disp($offset); 3423 %} 3424%} 3425 3426operand indOffset20Narrow(iRegN base, immL20 offset) %{ 3427 predicate(Matcher::narrow_oop_use_complex_address()); 3428 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3429 match(AddP (DecodeN base) offset); 3430 op_cost(1); 3431 format %{ "$offset[,$base]" %} 3432 interface(MEMORY_INTER) %{ 3433 base($base); 3434 index(0xffffFFFF); // noreg 3435 scale(0x0); 3436 disp($offset); 3437 %} 3438%} 3439 3440// Indirect with Offset (short) 3441operand indOffset12(memoryRegP base, uimmL12 offset) %{ 3442 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3443 match(AddP base offset); 3444 op_cost(1); 3445 format %{ "$offset[[,$base]]" %} 3446 interface(MEMORY_INTER) %{ 3447 base($base); 3448 index(0xffffFFFF); // noreg 3449 scale(0x0); 3450 disp($offset); 3451 %} 3452%} 3453 3454operand indOffset12Narrow(iRegN base, uimmL12 offset) %{ 3455 predicate(Matcher::narrow_oop_use_complex_address()); 3456 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3457 match(AddP (DecodeN base) offset); 3458 op_cost(1); 3459 format %{ "$offset[[,$base]]" %} 3460 interface(MEMORY_INTER) %{ 3461 base($base); 3462 index(0xffffFFFF); // noreg 3463 scale(0x0); 3464 disp($offset); 3465 %} 3466%} 3467 3468// Indirect with Register Index 3469operand indIndex(memoryRegP base, iRegL index) %{ 3470 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3471 match(AddP base index); 3472 op_cost(1); 3473 format %{ "#0[($index,$base)]" %} 3474 interface(MEMORY_INTER) %{ 3475 base($base); 3476 index($index); 3477 scale(0x0); 3478 disp(0x0); 3479 %} 3480%} 3481 3482// Indirect with Offset (long) and index 3483operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{ 3484 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3485 match(AddP (AddP base index) offset); 3486 op_cost(1); 3487 format %{ "$offset[($index,$base)]" %} 3488 interface(MEMORY_INTER) %{ 3489 base($base); 3490 index($index); 3491 scale(0x0); 3492 disp($offset); 3493 %} 3494%} 3495 3496operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{ 3497 predicate(Matcher::narrow_oop_use_complex_address()); 3498 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3499 match(AddP (AddP (DecodeN base) index) offset); 3500 op_cost(1); 3501 format %{ "$offset[($index,$base)]" %} 3502 interface(MEMORY_INTER) %{ 3503 base($base); 3504 index($index); 3505 scale(0x0); 3506 disp($offset); 3507 %} 3508%} 3509 3510// Indirect with Offset (short) and index 3511operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{ 3512 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3513 match(AddP (AddP base index) offset); 3514 op_cost(1); 3515 format %{ "$offset[[($index,$base)]]" %} 3516 interface(MEMORY_INTER) %{ 3517 base($base); 3518 index($index); 3519 scale(0x0); 3520 disp($offset); 3521 %} 3522%} 3523 3524operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{ 3525 predicate(Matcher::narrow_oop_use_complex_address()); 3526 constraint(ALLOC_IN_RC(z_memory_ptr_reg)); 3527 match(AddP (AddP (DecodeN base) index) offset); 3528 op_cost(1); 3529 format %{ "$offset[[($index,$base)]]" %} 3530 interface(MEMORY_INTER) %{ 3531 base($base); 3532 index($index); 3533 scale(0x0); 3534 disp($offset); 3535 %} 3536%} 3537 3538//----------Special Memory Operands-------------------------------------------- 3539 3540// Stack Slot Operand 3541// This operand is used for loading and storing temporary values on 3542// the stack where a match requires a value to flow through memory. 3543operand stackSlotI(sRegI reg) %{ 3544 constraint(ALLOC_IN_RC(stack_slots)); 3545 op_cost(1); 3546 format %{ "[$reg(stackSlotI)]" %} 3547 interface(MEMORY_INTER) %{ 3548 base(0xf); // Z_SP 3549 index(0xffffFFFF); // noreg 3550 scale(0x0); 3551 disp($reg); // stack offset 3552 %} 3553%} 3554 3555operand stackSlotP(sRegP reg) %{ 3556 constraint(ALLOC_IN_RC(stack_slots)); 3557 op_cost(1); 3558 format %{ "[$reg(stackSlotP)]" %} 3559 interface(MEMORY_INTER) %{ 3560 base(0xf); // Z_SP 3561 index(0xffffFFFF); // noreg 3562 scale(0x0); 3563 disp($reg); // Stack Offset 3564 %} 3565%} 3566 3567operand stackSlotF(sRegF reg) %{ 3568 constraint(ALLOC_IN_RC(stack_slots)); 3569 op_cost(1); 3570 format %{ "[$reg(stackSlotF)]" %} 3571 interface(MEMORY_INTER) %{ 3572 base(0xf); // Z_SP 3573 index(0xffffFFFF); // noreg 3574 scale(0x0); 3575 disp($reg); // Stack Offset 3576 %} 3577%} 3578 3579operand stackSlotD(sRegD reg) %{ 3580 constraint(ALLOC_IN_RC(stack_slots)); 3581 op_cost(1); 3582 //match(RegD); 3583 format %{ "[$reg(stackSlotD)]" %} 3584 interface(MEMORY_INTER) %{ 3585 base(0xf); // Z_SP 3586 index(0xffffFFFF); // noreg 3587 scale(0x0); 3588 disp($reg); // Stack Offset 3589 %} 3590%} 3591 3592operand stackSlotL(sRegL reg) %{ 3593 constraint(ALLOC_IN_RC(stack_slots)); 3594 op_cost(1); //match(RegL); 3595 format %{ "[$reg(stackSlotL)]" %} 3596 interface(MEMORY_INTER) %{ 3597 base(0xf); // Z_SP 3598 index(0xffffFFFF); // noreg 3599 scale(0x0); 3600 disp($reg); // Stack Offset 3601 %} 3602%} 3603 3604// Operands for expressing Control Flow 3605// NOTE: Label is a predefined operand which should not be redefined in 3606// the AD file. It is generically handled within the ADLC. 3607 3608//----------Conditional Branch Operands---------------------------------------- 3609// Comparison Op - This is the operation of the comparison, and is limited to 3610// the following set of codes: 3611// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 3612// 3613// Other attributes of the comparison, such as unsignedness, are specified 3614// by the comparison instruction that sets a condition code flags register. 3615// That result is represented by a flags operand whose subtype is appropriate 3616// to the unsignedness (etc.) of the comparison. 3617// 3618// Later, the instruction which matches both the Comparison Op (a Bool) and 3619// the flags (produced by the Cmp) specifies the coding of the comparison op 3620// by matching a specific subtype of Bool operand below. 3621 3622// INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not 3623// have mask bit #3 set. 3624operand cmpOpT() %{ 3625 match(Bool); 3626 format %{ "" %} 3627 interface(COND_INTER) %{ 3628 equal(0x8); // Assembler::bcondEqual 3629 not_equal(0x6); // Assembler::bcondNotEqual 3630 less(0x4); // Assembler::bcondLow 3631 greater_equal(0xa); // Assembler::bcondNotLow 3632 less_equal(0xc); // Assembler::bcondNotHigh 3633 greater(0x2); // Assembler::bcondHigh 3634 overflow(0x1); // Assembler::bcondOverflow 3635 no_overflow(0xe); // Assembler::bcondNotOverflow 3636 %} 3637%} 3638 3639// When used for floating point comparisons: unordered is treated as less. 3640operand cmpOpF() %{ 3641 match(Bool); 3642 format %{ "" %} 3643 interface(COND_INTER) %{ 3644 equal(0x8); 3645 not_equal(0x7); // Includes 'unordered'. 3646 less(0x5); // Includes 'unordered'. 3647 greater_equal(0xa); 3648 less_equal(0xd); // Includes 'unordered'. 3649 greater(0x2); 3650 overflow(0x0); // Not meaningful on z/Architecture. 3651 no_overflow(0x0); // leave unchanged (zero) therefore 3652 %} 3653%} 3654 3655// "Regular" cmpOp for int comparisons, includes bit #3 (overflow). 3656operand cmpOp() %{ 3657 match(Bool); 3658 format %{ "" %} 3659 interface(COND_INTER) %{ 3660 equal(0x8); 3661 not_equal(0x7); // Includes 'unordered'. 3662 less(0x5); // Includes 'unordered'. 3663 greater_equal(0xa); 3664 less_equal(0xd); // Includes 'unordered'. 3665 greater(0x2); 3666 overflow(0x1); // Assembler::bcondOverflow 3667 no_overflow(0xe); // Assembler::bcondNotOverflow 3668 %} 3669%} 3670 3671//----------OPERAND CLASSES---------------------------------------------------- 3672// Operand Classes are groups of operands that are used to simplify 3673// instruction definitions by not requiring the AD writer to specify 3674// seperate instructions for every form of operand when the 3675// instruction accepts multiple operand types with the same basic 3676// encoding and format. The classic case of this is memory operands. 3677// Indirect is not included since its use is limited to Compare & Swap 3678 3679// Most general memory operand, allows base, index, and long displacement. 3680opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); 3681opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow); 3682 3683// General memory operand, allows base, index, and short displacement. 3684opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow); 3685 3686// Memory operand, allows only base and long displacement. 3687opclass memoryRSY(indirect, indOffset20, indOffset20Narrow); 3688 3689// Memory operand, allows only base and short displacement. 3690opclass memoryRS(indirect, indOffset12, indOffset12Narrow); 3691 3692// Operand classes to match encode and decode. 3693opclass iRegN_P2N(iRegN); 3694opclass iRegP_N2P(iRegP); 3695 3696 3697//----------PIPELINE----------------------------------------------------------- 3698pipeline %{ 3699 3700//----------ATTRIBUTES--------------------------------------------------------- 3701attributes %{ 3702 // z/Architecture instructions are of length 2, 4, or 6 bytes. 3703 variable_size_instructions; 3704 instruction_unit_size = 2; 3705 3706 // Meaningless on z/Architecture. 3707 max_instructions_per_bundle = 1; 3708 3709 // The z/Architecture processor fetches 64 bytes... 3710 instruction_fetch_unit_size = 64; 3711 3712 // ...in one line. 3713 instruction_fetch_units = 1 3714%} 3715 3716//----------RESOURCES---------------------------------------------------------- 3717// Resources are the functional units available to the machine. 3718resources( 3719 Z_BR, // branch unit 3720 Z_CR, // condition unit 3721 Z_FX1, // integer arithmetic unit 1 3722 Z_FX2, // integer arithmetic unit 2 3723 Z_LDST1, // load/store unit 1 3724 Z_LDST2, // load/store unit 2 3725 Z_FP1, // float arithmetic unit 1 3726 Z_FP2, // float arithmetic unit 2 3727 Z_LDST = Z_LDST1 | Z_LDST2, 3728 Z_FX = Z_FX1 | Z_FX2, 3729 Z_FP = Z_FP1 | Z_FP2 3730 ); 3731 3732//----------PIPELINE DESCRIPTION----------------------------------------------- 3733// Pipeline Description specifies the stages in the machine's pipeline. 3734pipe_desc( 3735 // TODO: adapt 3736 Z_IF, // instruction fetch 3737 Z_IC, 3738 Z_D0, // decode 3739 Z_D1, // decode 3740 Z_D2, // decode 3741 Z_D3, // decode 3742 Z_Xfer1, 3743 Z_GD, // group definition 3744 Z_MP, // map 3745 Z_ISS, // issue 3746 Z_RF, // resource fetch 3747 Z_EX1, // execute (all units) 3748 Z_EX2, // execute (FP, LDST) 3749 Z_EX3, // execute (FP, LDST) 3750 Z_EX4, // execute (FP) 3751 Z_EX5, // execute (FP) 3752 Z_EX6, // execute (FP) 3753 Z_WB, // write back 3754 Z_Xfer2, 3755 Z_CP 3756 ); 3757 3758//----------PIPELINE CLASSES--------------------------------------------------- 3759// Pipeline Classes describe the stages in which input and output are 3760// referenced by the hardware pipeline. 3761 3762// Providing the `ins_pipe' declarations in the instruction 3763// specifications seems to be of little use. So we use 3764// `pipe_class_dummy' for all our instructions at present. 3765pipe_class pipe_class_dummy() %{ 3766 single_instruction; 3767 fixed_latency(4); 3768%} 3769 3770// SIGTRAP based implicit range checks in compiled code. 3771// Currently, no pipe classes are used on z/Architecture. 3772pipe_class pipe_class_trap() %{ 3773 single_instruction; 3774%} 3775 3776pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 3777 single_instruction; 3778 dst : Z_EX1(write); 3779 src1 : Z_RF(read); 3780 src2 : Z_RF(read); 3781 Z_FX : Z_RF; 3782%} 3783 3784pipe_class pipe_class_ldst(iRegP dst, memory mem) %{ 3785 single_instruction; 3786 mem : Z_RF(read); 3787 dst : Z_WB(write); 3788 Z_LDST : Z_RF; 3789%} 3790 3791define %{ 3792 MachNop = pipe_class_dummy; 3793%} 3794 3795%} 3796 3797//----------INSTRUCTIONS------------------------------------------------------- 3798 3799//---------- Chain stack slots between similar types -------- 3800 3801// Load integer from stack slot. 3802instruct stkI_to_regI(iRegI dst, stackSlotI src) %{ 3803 match(Set dst src); 3804 ins_cost(MEMORY_REF_COST); 3805 // TODO: s390 port size(FIXED_SIZE); 3806 format %{ "L $dst,$src\t # stk reload int" %} 3807 opcode(L_ZOPC); 3808 ins_encode(z_form_rt_mem(dst, src)); 3809 ins_pipe(pipe_class_dummy); 3810%} 3811 3812// Store integer to stack slot. 3813instruct regI_to_stkI(stackSlotI dst, iRegI src) %{ 3814 match(Set dst src); 3815 ins_cost(MEMORY_REF_COST); 3816 // TODO: s390 port size(FIXED_SIZE); 3817 format %{ "ST $src,$dst\t # stk spill int" %} 3818 opcode(ST_ZOPC); 3819 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3820 ins_pipe(pipe_class_dummy); 3821%} 3822 3823// Load long from stack slot. 3824instruct stkL_to_regL(iRegL dst, stackSlotL src) %{ 3825 match(Set dst src); 3826 ins_cost(MEMORY_REF_COST); 3827 // TODO: s390 port size(FIXED_SIZE); 3828 format %{ "LG $dst,$src\t # stk reload long" %} 3829 opcode(LG_ZOPC); 3830 ins_encode(z_form_rt_mem(dst, src)); 3831 ins_pipe(pipe_class_dummy); 3832%} 3833 3834// Store long to stack slot. 3835instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 3836 match(Set dst src); 3837 ins_cost(MEMORY_REF_COST); 3838 size(6); 3839 format %{ "STG $src,$dst\t # stk spill long" %} 3840 opcode(STG_ZOPC); 3841 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3842 ins_pipe(pipe_class_dummy); 3843%} 3844 3845// Load pointer from stack slot, 64-bit encoding. 3846instruct stkP_to_regP(iRegP dst, stackSlotP src) %{ 3847 match(Set dst src); 3848 ins_cost(MEMORY_REF_COST); 3849 // TODO: s390 port size(FIXED_SIZE); 3850 format %{ "LG $dst,$src\t # stk reload ptr" %} 3851 opcode(LG_ZOPC); 3852 ins_encode(z_form_rt_mem(dst, src)); 3853 ins_pipe(pipe_class_dummy); 3854%} 3855 3856// Store pointer to stack slot. 3857instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 3858 match(Set dst src); 3859 ins_cost(MEMORY_REF_COST); 3860 // TODO: s390 port size(FIXED_SIZE); 3861 format %{ "STG $src,$dst\t # stk spill ptr" %} 3862 opcode(STG_ZOPC); 3863 ins_encode(z_form_rt_mem(src, dst)); // rs=rt 3864 ins_pipe(pipe_class_dummy); 3865%} 3866 3867// Float types 3868 3869// Load float value from stack slot. 3870instruct stkF_to_regF(regF dst, stackSlotF src) %{ 3871 match(Set dst src); 3872 ins_cost(MEMORY_REF_COST); 3873 size(4); 3874 format %{ "LE(Y) $dst,$src\t # stk reload float" %} 3875 opcode(LE_ZOPC); 3876 ins_encode(z_form_rt_mem(dst, src)); 3877 ins_pipe(pipe_class_dummy); 3878%} 3879 3880// Store float value to stack slot. 3881instruct regF_to_stkF(stackSlotF dst, regF src) %{ 3882 match(Set dst src); 3883 ins_cost(MEMORY_REF_COST); 3884 size(4); 3885 format %{ "STE(Y) $src,$dst\t # stk spill float" %} 3886 opcode(STE_ZOPC); 3887 ins_encode(z_form_rt_mem(src, dst)); 3888 ins_pipe(pipe_class_dummy); 3889%} 3890 3891// Load double value from stack slot. 3892instruct stkD_to_regD(regD dst, stackSlotD src) %{ 3893 match(Set dst src); 3894 ins_cost(MEMORY_REF_COST); 3895 // TODO: s390 port size(FIXED_SIZE); 3896 format %{ "LD(Y) $dst,$src\t # stk reload double" %} 3897 opcode(LD_ZOPC); 3898 ins_encode(z_form_rt_mem(dst, src)); 3899 ins_pipe(pipe_class_dummy); 3900%} 3901 3902// Store double value to stack slot. 3903instruct regD_to_stkD(stackSlotD dst, regD src) %{ 3904 match(Set dst src); 3905 ins_cost(MEMORY_REF_COST); 3906 size(4); 3907 format %{ "STD(Y) $src,$dst\t # stk spill double" %} 3908 opcode(STD_ZOPC); 3909 ins_encode(z_form_rt_mem(src, dst)); 3910 ins_pipe(pipe_class_dummy); 3911%} 3912 3913//----------Load/Store/Move Instructions--------------------------------------- 3914 3915//----------Load Instructions-------------------------------------------------- 3916 3917//------------------ 3918// MEMORY 3919//------------------ 3920 3921// BYTE 3922// Load Byte (8bit signed) 3923instruct loadB(iRegI dst, memory mem) %{ 3924 match(Set dst (LoadB mem)); 3925 ins_cost(MEMORY_REF_COST); 3926 size(Z_DISP3_SIZE); 3927 format %{ "LB $dst, $mem\t # sign-extend byte to int" %} 3928 opcode(LB_ZOPC, LB_ZOPC); 3929 ins_encode(z_form_rt_mem_opt(dst, mem)); 3930 ins_pipe(pipe_class_dummy); 3931%} 3932 3933// Load Byte (8bit signed) 3934instruct loadB2L(iRegL dst, memory mem) %{ 3935 match(Set dst (ConvI2L (LoadB mem))); 3936 ins_cost(MEMORY_REF_COST); 3937 size(Z_DISP3_SIZE); 3938 format %{ "LGB $dst, $mem\t # sign-extend byte to long" %} 3939 opcode(LGB_ZOPC, LGB_ZOPC); 3940 ins_encode(z_form_rt_mem_opt(dst, mem)); 3941 ins_pipe(pipe_class_dummy); 3942%} 3943 3944// Load Unsigned Byte (8bit UNsigned) into an int reg. 3945instruct loadUB(iRegI dst, memory mem) %{ 3946 match(Set dst (LoadUB mem)); 3947 ins_cost(MEMORY_REF_COST); 3948 size(Z_DISP3_SIZE); 3949 format %{ "LLGC $dst,$mem\t # zero-extend byte to int" %} 3950 opcode(LLGC_ZOPC, LLGC_ZOPC); 3951 ins_encode(z_form_rt_mem_opt(dst, mem)); 3952 ins_pipe(pipe_class_dummy); 3953%} 3954 3955// Load Unsigned Byte (8bit UNsigned) into a Long Register. 3956instruct loadUB2L(iRegL dst, memory mem) %{ 3957 match(Set dst (ConvI2L (LoadUB mem))); 3958 ins_cost(MEMORY_REF_COST); 3959 size(Z_DISP3_SIZE); 3960 format %{ "LLGC $dst,$mem\t # zero-extend byte to long" %} 3961 opcode(LLGC_ZOPC, LLGC_ZOPC); 3962 ins_encode(z_form_rt_mem_opt(dst, mem)); 3963 ins_pipe(pipe_class_dummy); 3964%} 3965 3966// CHAR/SHORT 3967 3968// Load Short (16bit signed) 3969instruct loadS(iRegI dst, memory mem) %{ 3970 match(Set dst (LoadS mem)); 3971 ins_cost(MEMORY_REF_COST); 3972 size(Z_DISP_SIZE); 3973 format %{ "LH(Y) $dst,$mem\t # sign-extend short to int" %} 3974 opcode(LHY_ZOPC, LH_ZOPC); 3975 ins_encode(z_form_rt_mem_opt(dst, mem)); 3976 ins_pipe(pipe_class_dummy); 3977%} 3978 3979// Load Short (16bit signed) 3980instruct loadS2L(iRegL dst, memory mem) %{ 3981 match(Set dst (ConvI2L (LoadS mem))); 3982 ins_cost(MEMORY_REF_COST); 3983 size(Z_DISP3_SIZE); 3984 format %{ "LGH $dst,$mem\t # sign-extend short to long" %} 3985 opcode(LGH_ZOPC, LGH_ZOPC); 3986 ins_encode(z_form_rt_mem_opt(dst, mem)); 3987 ins_pipe(pipe_class_dummy); 3988%} 3989 3990// Load Char (16bit Unsigned) 3991instruct loadUS(iRegI dst, memory mem) %{ 3992 match(Set dst (LoadUS mem)); 3993 ins_cost(MEMORY_REF_COST); 3994 size(Z_DISP3_SIZE); 3995 format %{ "LLGH $dst,$mem\t # zero-extend short to int" %} 3996 opcode(LLGH_ZOPC, LLGH_ZOPC); 3997 ins_encode(z_form_rt_mem_opt(dst, mem)); 3998 ins_pipe(pipe_class_dummy); 3999%} 4000 4001// Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 4002instruct loadUS2L(iRegL dst, memory mem) %{ 4003 match(Set dst (ConvI2L (LoadUS mem))); 4004 ins_cost(MEMORY_REF_COST); 4005 size(Z_DISP3_SIZE); 4006 format %{ "LLGH $dst,$mem\t # zero-extend short to long" %} 4007 opcode(LLGH_ZOPC, LLGH_ZOPC); 4008 ins_encode(z_form_rt_mem_opt(dst, mem)); 4009 ins_pipe(pipe_class_dummy); 4010%} 4011 4012// INT 4013 4014// Load Integer 4015instruct loadI(iRegI dst, memory mem) %{ 4016 match(Set dst (LoadI mem)); 4017 ins_cost(MEMORY_REF_COST); 4018 size(Z_DISP_SIZE); 4019 format %{ "L(Y) $dst,$mem\t #" %} 4020 opcode(LY_ZOPC, L_ZOPC); 4021 ins_encode(z_form_rt_mem_opt(dst, mem)); 4022 ins_pipe(pipe_class_dummy); 4023%} 4024 4025// Load and convert to long. 4026instruct loadI2L(iRegL dst, memory mem) %{ 4027 match(Set dst (ConvI2L (LoadI mem))); 4028 ins_cost(MEMORY_REF_COST); 4029 size(Z_DISP3_SIZE); 4030 format %{ "LGF $dst,$mem\t #" %} 4031 opcode(LGF_ZOPC, LGF_ZOPC); 4032 ins_encode(z_form_rt_mem_opt(dst, mem)); 4033 ins_pipe(pipe_class_dummy); 4034%} 4035 4036// Load Unsigned Integer into a Long Register 4037instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{ 4038 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 4039 ins_cost(MEMORY_REF_COST); 4040 size(Z_DISP3_SIZE); 4041 format %{ "LLGF $dst,$mem\t # zero-extend int to long" %} 4042 opcode(LLGF_ZOPC, LLGF_ZOPC); 4043 ins_encode(z_form_rt_mem_opt(dst, mem)); 4044 ins_pipe(pipe_class_dummy); 4045%} 4046 4047// range = array length (=jint) 4048// Load Range 4049instruct loadRange(iRegI dst, memory mem) %{ 4050 match(Set dst (LoadRange mem)); 4051 ins_cost(MEMORY_REF_COST); 4052 size(Z_DISP_SIZE); 4053 format %{ "L(Y) $dst,$mem\t # range" %} 4054 opcode(LY_ZOPC, L_ZOPC); 4055 ins_encode(z_form_rt_mem_opt(dst, mem)); 4056 ins_pipe(pipe_class_dummy); 4057%} 4058 4059// LONG 4060 4061// Load Long - aligned 4062instruct loadL(iRegL dst, memory mem) %{ 4063 match(Set dst (LoadL mem)); 4064 ins_cost(MEMORY_REF_COST); 4065 size(Z_DISP3_SIZE); 4066 format %{ "LG $dst,$mem\t # long" %} 4067 opcode(LG_ZOPC, LG_ZOPC); 4068 ins_encode(z_form_rt_mem_opt(dst, mem)); 4069 ins_pipe(pipe_class_dummy); 4070%} 4071 4072// Load Long - UNaligned 4073instruct loadL_unaligned(iRegL dst, memory mem) %{ 4074 match(Set dst (LoadL_unaligned mem)); 4075 ins_cost(MEMORY_REF_COST); 4076 size(Z_DISP3_SIZE); 4077 format %{ "LG $dst,$mem\t # unaligned long" %} 4078 opcode(LG_ZOPC, LG_ZOPC); 4079 ins_encode(z_form_rt_mem_opt(dst, mem)); 4080 ins_pipe(pipe_class_dummy); 4081%} 4082 4083 4084// PTR 4085 4086// Load Pointer 4087instruct loadP(iRegP dst, memory mem) %{ 4088 match(Set dst (LoadP mem)); 4089 ins_cost(MEMORY_REF_COST); 4090 size(Z_DISP3_SIZE); 4091 format %{ "LG $dst,$mem\t # ptr" %} 4092 opcode(LG_ZOPC, LG_ZOPC); 4093 ins_encode(z_form_rt_mem_opt(dst, mem)); 4094 ins_pipe(pipe_class_dummy); 4095%} 4096 4097// LoadP + CastP2L 4098instruct castP2X_loadP(iRegL dst, memory mem) %{ 4099 match(Set dst (CastP2X (LoadP mem))); 4100 ins_cost(MEMORY_REF_COST); 4101 size(Z_DISP3_SIZE); 4102 format %{ "LG $dst,$mem\t # ptr + p2x" %} 4103 opcode(LG_ZOPC, LG_ZOPC); 4104 ins_encode(z_form_rt_mem_opt(dst, mem)); 4105 ins_pipe(pipe_class_dummy); 4106%} 4107 4108// Load Klass Pointer 4109instruct loadKlass(iRegP dst, memory mem) %{ 4110 match(Set dst (LoadKlass mem)); 4111 ins_cost(MEMORY_REF_COST); 4112 size(Z_DISP3_SIZE); 4113 format %{ "LG $dst,$mem\t # klass ptr" %} 4114 opcode(LG_ZOPC, LG_ZOPC); 4115 ins_encode(z_form_rt_mem_opt(dst, mem)); 4116 ins_pipe(pipe_class_dummy); 4117%} 4118 4119instruct loadTOC(iRegL dst) %{ 4120 effect(DEF dst); 4121 ins_cost(DEFAULT_COST); 4122 // TODO: s390 port size(FIXED_SIZE); 4123 // TODO: check why this attribute causes many unnecessary rematerializations. 4124 // 4125 // The graphs I saw just had high register pressure. Further the 4126 // register TOC is loaded to is overwritten by the constant short 4127 // after. Here something as round robin register allocation might 4128 // help. But rematerializing seems not to hurt, jack even seems to 4129 // improve slightly. 4130 // 4131 // Without this flag we get spill-split recycle sanity check 4132 // failures in 4133 // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in 4134 // a block with three loadConP_dynTOC nodes and a tlsLoadP. The 4135 // tlsLoadP has a huge amount of outs and forces the TOC down to the 4136 // stack. Later tlsLoadP is rematerialized, leaving the register 4137 // allocator with TOC on the stack and a badly placed reload. 4138 ins_should_rematerialize(true); 4139 format %{ "LARL $dst, &constant_pool\t; load dynTOC" %} 4140 ins_encode %{ __ load_toc($dst$$Register); %} 4141 ins_pipe(pipe_class_dummy); 4142%} 4143 4144// FLOAT 4145 4146// Load Float 4147instruct loadF(regF dst, memory mem) %{ 4148 match(Set dst (LoadF mem)); 4149 ins_cost(MEMORY_REF_COST); 4150 size(Z_DISP_SIZE); 4151 format %{ "LE(Y) $dst,$mem" %} 4152 opcode(LEY_ZOPC, LE_ZOPC); 4153 ins_encode(z_form_rt_mem_opt(dst, mem)); 4154 ins_pipe(pipe_class_dummy); 4155%} 4156 4157// DOUBLE 4158 4159// Load Double 4160instruct loadD(regD dst, memory mem) %{ 4161 match(Set dst (LoadD mem)); 4162 ins_cost(MEMORY_REF_COST); 4163 size(Z_DISP_SIZE); 4164 format %{ "LD(Y) $dst,$mem" %} 4165 opcode(LDY_ZOPC, LD_ZOPC); 4166 ins_encode(z_form_rt_mem_opt(dst, mem)); 4167 ins_pipe(pipe_class_dummy); 4168%} 4169 4170// Load Double - UNaligned 4171instruct loadD_unaligned(regD dst, memory mem) %{ 4172 match(Set dst (LoadD_unaligned mem)); 4173 ins_cost(MEMORY_REF_COST); 4174 size(Z_DISP_SIZE); 4175 format %{ "LD(Y) $dst,$mem" %} 4176 opcode(LDY_ZOPC, LD_ZOPC); 4177 ins_encode(z_form_rt_mem_opt(dst, mem)); 4178 ins_pipe(pipe_class_dummy); 4179%} 4180 4181 4182//---------------------- 4183// IMMEDIATES 4184//---------------------- 4185 4186instruct loadConI(iRegI dst, immI src) %{ 4187 match(Set dst src); 4188 ins_cost(DEFAULT_COST); 4189 size(6); 4190 format %{ "LGFI $dst,$src\t # (int)" %} 4191 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4192 ins_pipe(pipe_class_dummy); 4193%} 4194 4195instruct loadConI16(iRegI dst, immI16 src) %{ 4196 match(Set dst src); 4197 ins_cost(DEFAULT_COST_LOW); 4198 size(4); 4199 format %{ "LGHI $dst,$src\t # (int)" %} 4200 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4201 ins_pipe(pipe_class_dummy); 4202%} 4203 4204instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{ 4205 match(Set dst src); 4206 effect(KILL cr); 4207 ins_cost(DEFAULT_COST_LOW); 4208 size(4); 4209 format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %} 4210 opcode(XGR_ZOPC); 4211 ins_encode(z_rreform(dst, dst)); 4212 ins_pipe(pipe_class_dummy); 4213%} 4214 4215instruct loadConUI16(iRegI dst, uimmI16 src) %{ 4216 match(Set dst src); 4217 // TODO: s390 port size(FIXED_SIZE); 4218 format %{ "LLILL $dst,$src" %} 4219 opcode(LLILL_ZOPC); 4220 ins_encode(z_riform_unsigned(dst, src) ); 4221 ins_pipe(pipe_class_dummy); 4222%} 4223 4224// Load long constant from TOC with pcrelative address. 4225instruct loadConL_pcrelTOC(iRegL dst, immL src) %{ 4226 match(Set dst src); 4227 ins_cost(MEMORY_REF_COST_LO); 4228 size(6); 4229 format %{ "LGRL $dst,[pcrelTOC]\t # load long $src from table" %} 4230 ins_encode %{ 4231 address long_address = __ long_constant($src$$constant); 4232 if (long_address == NULL) { 4233 Compile::current()->env()->record_out_of_memory_failure(); 4234 return; 4235 } 4236 __ load_long_pcrelative($dst$$Register, long_address); 4237 %} 4238 ins_pipe(pipe_class_dummy); 4239%} 4240 4241instruct loadConL32(iRegL dst, immL32 src) %{ 4242 match(Set dst src); 4243 ins_cost(DEFAULT_COST); 4244 size(6); 4245 format %{ "LGFI $dst,$src\t # (long)" %} 4246 ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4247 ins_pipe(pipe_class_dummy); 4248%} 4249 4250instruct loadConL16(iRegL dst, immL16 src) %{ 4251 match(Set dst src); 4252 ins_cost(DEFAULT_COST_LOW); 4253 size(4); 4254 format %{ "LGHI $dst,$src\t # (long)" %} 4255 ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. 4256 ins_pipe(pipe_class_dummy); 4257%} 4258 4259instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{ 4260 match(Set dst src); 4261 effect(KILL cr); 4262 ins_cost(DEFAULT_COST_LOW); 4263 format %{ "LoadConL $dst,$src\t # (long) XGR because ZERO is loaded" %} 4264 opcode(XGR_ZOPC); 4265 ins_encode(z_rreform(dst, dst)); 4266 ins_pipe(pipe_class_dummy); 4267%} 4268 4269// Load ptr constant from TOC with pc relative address. 4270// Special handling for oop constants required. 4271instruct loadConP_pcrelTOC(iRegP dst, immP src) %{ 4272 match(Set dst src); 4273 ins_cost(MEMORY_REF_COST_LO); 4274 size(6); 4275 format %{ "LGRL $dst,[pcrelTOC]\t # load ptr $src from table" %} 4276 ins_encode %{ 4277 relocInfo::relocType constant_reloc = $src->constant_reloc(); 4278 if (constant_reloc == relocInfo::oop_type) { 4279 AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant); 4280 bool success = __ load_oop_from_toc($dst$$Register, a); 4281 if (!success) { 4282 Compile::current()->env()->record_out_of_memory_failure(); 4283 return; 4284 } 4285 } else if (constant_reloc == relocInfo::metadata_type) { 4286 AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant); 4287 address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 4288 if (const_toc_addr == NULL) { 4289 Compile::current()->env()->record_out_of_memory_failure(); 4290 return; 4291 } 4292 __ load_long_pcrelative($dst$$Register, const_toc_addr); 4293 } else { // Non-oop pointers, e.g. card mark base, heap top. 4294 address long_address = __ long_constant((jlong)$src$$constant); 4295 if (long_address == NULL) { 4296 Compile::current()->env()->record_out_of_memory_failure(); 4297 return; 4298 } 4299 __ load_long_pcrelative($dst$$Register, long_address); 4300 } 4301 %} 4302 ins_pipe(pipe_class_dummy); 4303%} 4304 4305// We don't use immP16 to avoid problems with oops. 4306instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{ 4307 match(Set dst src); 4308 effect(KILL cr); 4309 size(4); 4310 format %{ "XGR $dst,$dst\t # NULL ptr" %} 4311 opcode(XGR_ZOPC); 4312 ins_encode(z_rreform(dst, dst)); 4313 ins_pipe(pipe_class_dummy); 4314%} 4315 4316//----------Load Float Constant Instructions------------------------------------------------- 4317 4318// We may not specify this instruction via an `expand' rule. If we do, 4319// code selection will forget that this instruction needs a floating 4320// point constant inserted into the code buffer. So `Shorten_branches' 4321// will fail. 4322instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{ 4323 match(Set dst src); 4324 effect(KILL cr); 4325 ins_cost(MEMORY_REF_COST); 4326 size(6); 4327 // If this instruction rematerializes, it prolongs the live range 4328 // of the toc node, causing illegal graphs. 4329 ins_cannot_rematerialize(true); 4330 format %{ "LE(Y) $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %} 4331 ins_encode %{ 4332 __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); 4333 %} 4334 ins_pipe(pipe_class_dummy); 4335%} 4336 4337// E may not specify this instruction via an `expand' rule. If we do, 4338// code selection will forget that this instruction needs a floating 4339// point constant inserted into the code buffer. So `Shorten_branches' 4340// will fail. 4341instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{ 4342 match(Set dst src); 4343 effect(KILL cr); 4344 ins_cost(MEMORY_REF_COST); 4345 size(6); 4346 // If this instruction rematerializes, it prolongs the live range 4347 // of the toc node, causing illegal graphs. 4348 ins_cannot_rematerialize(true); 4349 format %{ "LD(Y) $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %} 4350 ins_encode %{ 4351 __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch); 4352 %} 4353 ins_pipe(pipe_class_dummy); 4354%} 4355 4356// Special case: Load Const 0.0F 4357 4358// There's a special instr to clear a FP register. 4359instruct loadConF0(regF dst, immFp0 src) %{ 4360 match(Set dst src); 4361 ins_cost(DEFAULT_COST_LOW); 4362 size(4); 4363 format %{ "LZER $dst,$src\t # clear to zero" %} 4364 opcode(LZER_ZOPC); 4365 ins_encode(z_rreform(dst, Z_F0)); 4366 ins_pipe(pipe_class_dummy); 4367%} 4368 4369// There's a special instr to clear a FP register. 4370instruct loadConD0(regD dst, immDp0 src) %{ 4371 match(Set dst src); 4372 ins_cost(DEFAULT_COST_LOW); 4373 size(4); 4374 format %{ "LZDR $dst,$src\t # clear to zero" %} 4375 opcode(LZDR_ZOPC); 4376 ins_encode(z_rreform(dst, Z_F0)); 4377 ins_pipe(pipe_class_dummy); 4378%} 4379 4380 4381//----------Store Instructions------------------------------------------------- 4382 4383// BYTE 4384 4385// Store Byte 4386instruct storeB(memory mem, iRegI src) %{ 4387 match(Set mem (StoreB mem src)); 4388 ins_cost(MEMORY_REF_COST); 4389 size(Z_DISP_SIZE); 4390 format %{ "STC(Y) $src,$mem\t # byte" %} 4391 opcode(STCY_ZOPC, STC_ZOPC); 4392 ins_encode(z_form_rt_mem_opt(src, mem)); 4393 ins_pipe(pipe_class_dummy); 4394%} 4395 4396instruct storeCM(memory mem, immI_0 src) %{ 4397 match(Set mem (StoreCM mem src)); 4398 ins_cost(MEMORY_REF_COST); 4399 // TODO: s390 port size(VARIABLE_SIZE); 4400 format %{ "STC(Y) $src,$mem\t # CMS card-mark byte (must be 0!)" %} 4401 ins_encode %{ 4402 guarantee($mem$$index$$Register != Z_R0, "content will not be used."); 4403 if ($mem$$index$$Register != noreg) { 4404 // Can't use clear_mem --> load const zero and store character. 4405 __ load_const_optimized(Z_R0_scratch, (long)0); 4406 if (Immediate::is_uimm12($mem$$disp)) { 4407 __ z_stc(Z_R0_scratch, $mem$$Address); 4408 } else { 4409 __ z_stcy(Z_R0_scratch, $mem$$Address); 4410 } 4411 } else { 4412 __ clear_mem(Address($mem$$Address), 1); 4413 } 4414 %} 4415 ins_pipe(pipe_class_dummy); 4416%} 4417 4418// CHAR/SHORT 4419 4420// Store Char/Short 4421instruct storeC(memory mem, iRegI src) %{ 4422 match(Set mem (StoreC mem src)); 4423 ins_cost(MEMORY_REF_COST); 4424 size(Z_DISP_SIZE); 4425 format %{ "STH(Y) $src,$mem\t # short" %} 4426 opcode(STHY_ZOPC, STH_ZOPC); 4427 ins_encode(z_form_rt_mem_opt(src, mem)); 4428 ins_pipe(pipe_class_dummy); 4429%} 4430 4431// INT 4432 4433// Store Integer 4434instruct storeI(memory mem, iRegI src) %{ 4435 match(Set mem (StoreI mem src)); 4436 ins_cost(MEMORY_REF_COST); 4437 size(Z_DISP_SIZE); 4438 format %{ "ST(Y) $src,$mem\t # int" %} 4439 opcode(STY_ZOPC, ST_ZOPC); 4440 ins_encode(z_form_rt_mem_opt(src, mem)); 4441 ins_pipe(pipe_class_dummy); 4442%} 4443 4444// LONG 4445 4446// Store Long 4447instruct storeL(memory mem, iRegL src) %{ 4448 match(Set mem (StoreL mem src)); 4449 ins_cost(MEMORY_REF_COST); 4450 size(Z_DISP3_SIZE); 4451 format %{ "STG $src,$mem\t # long" %} 4452 opcode(STG_ZOPC, STG_ZOPC); 4453 ins_encode(z_form_rt_mem_opt(src, mem)); 4454 ins_pipe(pipe_class_dummy); 4455%} 4456 4457// PTR 4458 4459// Store Pointer 4460instruct storeP(memory dst, memoryRegP src) %{ 4461 match(Set dst (StoreP dst src)); 4462 ins_cost(MEMORY_REF_COST); 4463 size(Z_DISP3_SIZE); 4464 format %{ "STG $src,$dst\t # ptr" %} 4465 opcode(STG_ZOPC, STG_ZOPC); 4466 ins_encode(z_form_rt_mem_opt(src, dst)); 4467 ins_pipe(pipe_class_dummy); 4468%} 4469 4470// FLOAT 4471 4472// Store Float 4473instruct storeF(memory mem, regF src) %{ 4474 match(Set mem (StoreF mem src)); 4475 ins_cost(MEMORY_REF_COST); 4476 size(Z_DISP_SIZE); 4477 format %{ "STE(Y) $src,$mem\t # float" %} 4478 opcode(STEY_ZOPC, STE_ZOPC); 4479 ins_encode(z_form_rt_mem_opt(src, mem)); 4480 ins_pipe(pipe_class_dummy); 4481%} 4482 4483// DOUBLE 4484 4485// Store Double 4486instruct storeD(memory mem, regD src) %{ 4487 match(Set mem (StoreD mem src)); 4488 ins_cost(MEMORY_REF_COST); 4489 size(Z_DISP_SIZE); 4490 format %{ "STD(Y) $src,$mem\t # double" %} 4491 opcode(STDY_ZOPC, STD_ZOPC); 4492 ins_encode(z_form_rt_mem_opt(src, mem)); 4493 ins_pipe(pipe_class_dummy); 4494%} 4495 4496// Prefetch instructions. Must be safe to execute with invalid address (cannot fault). 4497 4498// Should support match rule for PrefetchAllocation. 4499// Still needed after 8068977 for PrefetchAllocate. 4500instruct prefetchAlloc(memory mem) %{ 4501 match(PrefetchAllocation mem); 4502 predicate(VM_Version::has_Prefetch()); 4503 ins_cost(DEFAULT_COST); 4504 format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %} 4505 ins_encode %{ __ z_pfd(0x02, $mem$$Address); %} 4506 ins_pipe(pipe_class_dummy); 4507%} 4508 4509//----------Memory init instructions------------------------------------------ 4510 4511// Move Immediate to 1-byte memory. 4512instruct memInitB(memoryRSY mem, immI8 src) %{ 4513 match(Set mem (StoreB mem src)); 4514 ins_cost(MEMORY_REF_COST); 4515 // TODO: s390 port size(VARIABLE_SIZE); 4516 format %{ "MVI $mem,$src\t # direct mem init 1" %} 4517 ins_encode %{ 4518 if (Immediate::is_uimm12((long)$mem$$disp)) { 4519 __ z_mvi($mem$$Address, $src$$constant); 4520 } else { 4521 __ z_mviy($mem$$Address, $src$$constant); 4522 } 4523 %} 4524 ins_pipe(pipe_class_dummy); 4525%} 4526 4527// Move Immediate to 2-byte memory. 4528instruct memInitC(memoryRS mem, immI16 src) %{ 4529 match(Set mem (StoreC mem src)); 4530 ins_cost(MEMORY_REF_COST); 4531 size(6); 4532 format %{ "MVHHI $mem,$src\t # direct mem init 2" %} 4533 opcode(MVHHI_ZOPC); 4534 ins_encode(z_silform(mem, src)); 4535 ins_pipe(pipe_class_dummy); 4536%} 4537 4538// Move Immediate to 4-byte memory. 4539instruct memInitI(memoryRS mem, immI16 src) %{ 4540 match(Set mem (StoreI mem src)); 4541 ins_cost(MEMORY_REF_COST); 4542 size(6); 4543 format %{ "MVHI $mem,$src\t # direct mem init 4" %} 4544 opcode(MVHI_ZOPC); 4545 ins_encode(z_silform(mem, src)); 4546 ins_pipe(pipe_class_dummy); 4547%} 4548 4549 4550// Move Immediate to 8-byte memory. 4551instruct memInitL(memoryRS mem, immL16 src) %{ 4552 match(Set mem (StoreL mem src)); 4553 ins_cost(MEMORY_REF_COST); 4554 size(6); 4555 format %{ "MVGHI $mem,$src\t # direct mem init 8" %} 4556 opcode(MVGHI_ZOPC); 4557 ins_encode(z_silform(mem, src)); 4558 ins_pipe(pipe_class_dummy); 4559%} 4560 4561// Move Immediate to 8-byte memory. 4562instruct memInitP(memoryRS mem, immP16 src) %{ 4563 match(Set mem (StoreP mem src)); 4564 ins_cost(MEMORY_REF_COST); 4565 size(6); 4566 format %{ "MVGHI $mem,$src\t # direct mem init 8" %} 4567 opcode(MVGHI_ZOPC); 4568 ins_encode(z_silform(mem, src)); 4569 ins_pipe(pipe_class_dummy); 4570%} 4571 4572 4573//----------Instructions for compressed pointers (cOop and NKlass)------------- 4574 4575// See cOop encoding classes for elaborate comment. 4576 4577// Moved here because it is needed in expand rules for encode. 4578// Long negation. 4579instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{ 4580 match(Set dst (SubL zero src)); 4581 effect(KILL cr); 4582 size(4); 4583 format %{ "NEG $dst, $src\t # long" %} 4584 ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %} 4585 ins_pipe(pipe_class_dummy); 4586%} 4587 4588// Load Compressed Pointer 4589 4590// Load narrow oop 4591instruct loadN(iRegN dst, memory mem) %{ 4592 match(Set dst (LoadN mem)); 4593 ins_cost(MEMORY_REF_COST); 4594 size(Z_DISP3_SIZE); 4595 format %{ "LoadN $dst,$mem\t # (cOop)" %} 4596 opcode(LLGF_ZOPC, LLGF_ZOPC); 4597 ins_encode(z_form_rt_mem_opt(dst, mem)); 4598 ins_pipe(pipe_class_dummy); 4599%} 4600 4601// Load narrow Klass Pointer 4602instruct loadNKlass(iRegN dst, memory mem) %{ 4603 match(Set dst (LoadNKlass mem)); 4604 ins_cost(MEMORY_REF_COST); 4605 size(Z_DISP3_SIZE); 4606 format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %} 4607 opcode(LLGF_ZOPC, LLGF_ZOPC); 4608 ins_encode(z_form_rt_mem_opt(dst, mem)); 4609 ins_pipe(pipe_class_dummy); 4610%} 4611 4612// Load constant Compressed Pointer 4613 4614instruct loadConN(iRegN dst, immN src) %{ 4615 match(Set dst src); 4616 ins_cost(DEFAULT_COST); 4617 size(6); 4618 format %{ "loadConN $dst,$src\t # (cOop)" %} 4619 ins_encode %{ 4620 AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant); 4621 __ relocate(cOop.rspec(), 1); 4622 __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value()); 4623 %} 4624 ins_pipe(pipe_class_dummy); 4625%} 4626 4627instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{ 4628 match(Set dst src); 4629 effect(KILL cr); 4630 ins_cost(DEFAULT_COST_LOW); 4631 size(4); 4632 format %{ "loadConN $dst,$src\t # (cOop) XGR because ZERO is loaded" %} 4633 opcode(XGR_ZOPC); 4634 ins_encode(z_rreform(dst, dst)); 4635 ins_pipe(pipe_class_dummy); 4636%} 4637 4638instruct loadConNKlass(iRegN dst, immNKlass src) %{ 4639 match(Set dst src); 4640 ins_cost(DEFAULT_COST); 4641 size(6); 4642 format %{ "loadConNKlass $dst,$src\t # (cKlass)" %} 4643 ins_encode %{ 4644 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); 4645 __ relocate(NKlass.rspec(), 1); 4646 __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value()); 4647 %} 4648 ins_pipe(pipe_class_dummy); 4649%} 4650 4651// Load and Decode Compressed Pointer 4652// optimized variants for Unscaled cOops 4653 4654instruct decodeLoadN(iRegP dst, memory mem) %{ 4655 match(Set dst (DecodeN (LoadN mem))); 4656 predicate(false && (CompressedOops::base()==NULL)&&(CompressedOops::shift()==0)); 4657 ins_cost(MEMORY_REF_COST); 4658 size(Z_DISP3_SIZE); 4659 format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %} 4660 opcode(LLGF_ZOPC, LLGF_ZOPC); 4661 ins_encode(z_form_rt_mem_opt(dst, mem)); 4662 ins_pipe(pipe_class_dummy); 4663%} 4664 4665instruct decodeLoadNKlass(iRegP dst, memory mem) %{ 4666 match(Set dst (DecodeNKlass (LoadNKlass mem))); 4667 predicate(false && (CompressedKlassPointers::base()==NULL)&&(CompressedKlassPointers::shift()==0)); 4668 ins_cost(MEMORY_REF_COST); 4669 size(Z_DISP3_SIZE); 4670 format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %} 4671 opcode(LLGF_ZOPC, LLGF_ZOPC); 4672 ins_encode(z_form_rt_mem_opt(dst, mem)); 4673 ins_pipe(pipe_class_dummy); 4674%} 4675 4676instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{ 4677 match(Set dst (DecodeNKlass src)); 4678 ins_cost(3 * DEFAULT_COST); 4679 size(12); 4680 format %{ "DecodeLoadConNKlass $dst,$src\t # decode(cKlass)" %} 4681 ins_encode %{ 4682 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant); 4683 __ relocate(NKlass.rspec(), 1); 4684 __ load_const($dst$$Register, (Klass*)NKlass.value()); 4685 %} 4686 ins_pipe(pipe_class_dummy); 4687%} 4688 4689// Decode Compressed Pointer 4690 4691// General decoder 4692instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{ 4693 match(Set dst (DecodeN src)); 4694 effect(KILL cr); 4695 predicate(CompressedOops::base() == NULL || !ExpandLoadingBaseDecode); 4696 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); 4697 // TODO: s390 port size(VARIABLE_SIZE); 4698 format %{ "decodeN $dst,$src\t # (decode cOop)" %} 4699 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %} 4700 ins_pipe(pipe_class_dummy); 4701%} 4702 4703// General Klass decoder 4704instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{ 4705 match(Set dst (DecodeNKlass src)); 4706 effect(KILL cr); 4707 ins_cost(3 * DEFAULT_COST); 4708 format %{ "decode_klass $dst,$src" %} 4709 ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %} 4710 ins_pipe(pipe_class_dummy); 4711%} 4712 4713// General decoder 4714instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{ 4715 match(Set dst (DecodeN src)); 4716 effect(KILL cr); 4717 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || 4718 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 4719 (CompressedOops::base()== NULL || !ExpandLoadingBaseDecode_NN)); 4720 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4721 // TODO: s390 port size(VARIABLE_SIZE); 4722 format %{ "decodeN $dst,$src\t # (decode cOop NN)" %} 4723 ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %} 4724 ins_pipe(pipe_class_dummy); 4725%} 4726 4727 instruct loadBase(iRegL dst, immL baseImm) %{ 4728 effect(DEF dst, USE baseImm); 4729 predicate(false); 4730 format %{ "llihl $dst=$baseImm \t// load heap base" %} 4731 ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %} 4732 ins_pipe(pipe_class_dummy); 4733 %} 4734 4735 // Decoder for heapbased mode peeling off loading the base. 4736 instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ 4737 match(Set dst (DecodeN src base)); 4738 // Note: Effect TEMP dst was used with the intention to get 4739 // different regs for dst and base, but this has caused ADLC to 4740 // generate wrong code. Oop_decoder generates additional lgr when 4741 // dst==base. 4742 effect(KILL cr); 4743 predicate(false); 4744 // TODO: s390 port size(VARIABLE_SIZE); 4745 format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %} 4746 ins_encode %{ 4747 __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register, 4748 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base())); 4749 %} 4750 ins_pipe(pipe_class_dummy); 4751 %} 4752 4753 // Decoder for heapbased mode peeling off loading the base. 4754 instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ 4755 match(Set dst (DecodeN src base)); 4756 effect(KILL cr); 4757 predicate(false); 4758 // TODO: s390 port size(VARIABLE_SIZE); 4759 format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %} 4760 ins_encode %{ 4761 __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register, 4762 (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base())); 4763 %} 4764 ins_pipe(pipe_class_dummy); 4765 %} 4766 4767// Decoder for heapbased mode peeling off loading the base. 4768instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ 4769 match(Set dst (DecodeN src)); 4770 predicate(CompressedOops::base() != NULL && ExpandLoadingBaseDecode); 4771 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); 4772 // TODO: s390 port size(VARIABLE_SIZE); 4773 expand %{ 4774 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} 4775 iRegL base; 4776 loadBase(base, baseImm); 4777 decodeN_base(dst, src, base, cr); 4778 %} 4779%} 4780 4781// Decoder for heapbased mode peeling off loading the base. 4782instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ 4783 match(Set dst (DecodeN src)); 4784 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || 4785 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 4786 CompressedOops::base() != NULL && ExpandLoadingBaseDecode_NN); 4787 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4788 // TODO: s390 port size(VARIABLE_SIZE); 4789 expand %{ 4790 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} 4791 iRegL base; 4792 loadBase(base, baseImm); 4793 decodeN_NN_base(dst, src, base, cr); 4794 %} 4795%} 4796 4797// Encode Compressed Pointer 4798 4799// General encoder 4800instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{ 4801 match(Set dst (EncodeP src)); 4802 effect(KILL cr); 4803 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && 4804 (CompressedOops::base() == 0 || 4805 CompressedOops::base_disjoint() || 4806 !ExpandLoadingBaseEncode)); 4807 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4808 // TODO: s390 port size(VARIABLE_SIZE); 4809 format %{ "encodeP $dst,$src\t # (encode cOop)" %} 4810 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} 4811 ins_pipe(pipe_class_dummy); 4812%} 4813 4814// General class encoder 4815instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{ 4816 match(Set dst (EncodePKlass src)); 4817 effect(KILL cr); 4818 format %{ "encode_klass $dst,$src" %} 4819 ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %} 4820 ins_pipe(pipe_class_dummy); 4821%} 4822 4823instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{ 4824 match(Set dst (EncodeP src)); 4825 effect(KILL cr); 4826 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && 4827 (CompressedOops::base() == 0 || 4828 CompressedOops::base_disjoint() || 4829 !ExpandLoadingBaseEncode_NN)); 4830 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4831 // TODO: s390 port size(VARIABLE_SIZE); 4832 format %{ "encodeP $dst,$src\t # (encode cOop)" %} 4833 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} 4834 ins_pipe(pipe_class_dummy); 4835%} 4836 4837 // Encoder for heapbased mode peeling off loading the base. 4838 instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{ 4839 match(Set dst (EncodeP src (Binary base dst))); 4840 effect(TEMP_DEF dst); 4841 predicate(false); 4842 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4843 // TODO: s390 port size(VARIABLE_SIZE); 4844 format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %} 4845 ins_encode %{ 4846 jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset 4847 (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift()); 4848 __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset); 4849 %} 4850 ins_pipe(pipe_class_dummy); 4851 %} 4852 4853 // Encoder for heapbased mode peeling off loading the base. 4854 instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{ 4855 match(Set dst (EncodeP src base)); 4856 effect(USE pow2_offset); 4857 predicate(false); 4858 ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); 4859 // TODO: s390 port size(VARIABLE_SIZE); 4860 format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %} 4861 ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %} 4862 ins_pipe(pipe_class_dummy); 4863 %} 4864 4865// Encoder for heapbased mode peeling off loading the base. 4866instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{ 4867 match(Set dst (EncodeP src)); 4868 effect(KILL cr); 4869 predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && 4870 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode)); 4871 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4872 // TODO: s390 port size(VARIABLE_SIZE); 4873 expand %{ 4874 immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %} 4875 immL_0 zero %{ (0) %} 4876 flagsReg ccr; 4877 iRegL base; 4878 iRegL negBase; 4879 loadBase(base, baseImm); 4880 negL_reg_reg(negBase, zero, base, ccr); 4881 encodeP_base(dst, src, negBase); 4882 %} 4883%} 4884 4885// Encoder for heapbased mode peeling off loading the base. 4886instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{ 4887 match(Set dst (EncodeP src)); 4888 effect(KILL cr); 4889 predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && 4890 (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN)); 4891 ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); 4892 // TODO: s390 port size(VARIABLE_SIZE); 4893 expand %{ 4894 immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} 4895 immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %} 4896 immL_0 zero %{ 0 %} 4897 flagsReg ccr; 4898 iRegL base; 4899 iRegL negBase; 4900 loadBase(base, baseImm); 4901 negL_reg_reg(negBase, zero, base, ccr); 4902 encodeP_NN_base(dst, src, negBase, pow2_offset); 4903 %} 4904%} 4905 4906// Store Compressed Pointer 4907 4908// Store Compressed Pointer 4909instruct storeN(memory mem, iRegN_P2N src) %{ 4910 match(Set mem (StoreN mem src)); 4911 ins_cost(MEMORY_REF_COST); 4912 size(Z_DISP_SIZE); 4913 format %{ "ST $src,$mem\t # (cOop)" %} 4914 opcode(STY_ZOPC, ST_ZOPC); 4915 ins_encode(z_form_rt_mem_opt(src, mem)); 4916 ins_pipe(pipe_class_dummy); 4917%} 4918 4919// Store Compressed Klass pointer 4920instruct storeNKlass(memory mem, iRegN src) %{ 4921 match(Set mem (StoreNKlass mem src)); 4922 ins_cost(MEMORY_REF_COST); 4923 size(Z_DISP_SIZE); 4924 format %{ "ST $src,$mem\t # (cKlass)" %} 4925 opcode(STY_ZOPC, ST_ZOPC); 4926 ins_encode(z_form_rt_mem_opt(src, mem)); 4927 ins_pipe(pipe_class_dummy); 4928%} 4929 4930// Compare Compressed Pointers 4931 4932instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{ 4933 match(Set cr (CmpN src1 src2)); 4934 ins_cost(DEFAULT_COST); 4935 size(2); 4936 format %{ "CLR $src1,$src2\t # (cOop)" %} 4937 opcode(CLR_ZOPC); 4938 ins_encode(z_rrform(src1, src2)); 4939 ins_pipe(pipe_class_dummy); 4940%} 4941 4942instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{ 4943 match(Set cr (CmpN src1 src2)); 4944 ins_cost(DEFAULT_COST); 4945 size(6); 4946 format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %} 4947 ins_encode %{ 4948 AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant); 4949 __ relocate(cOop.rspec(), 1); 4950 __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value()); 4951 %} 4952 ins_pipe(pipe_class_dummy); 4953%} 4954 4955instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{ 4956 match(Set cr (CmpN src1 src2)); 4957 ins_cost(DEFAULT_COST); 4958 size(6); 4959 format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %} 4960 ins_encode %{ 4961 AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant); 4962 __ relocate(NKlass.rspec(), 1); 4963 __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value()); 4964 %} 4965 ins_pipe(pipe_class_dummy); 4966%} 4967 4968instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{ 4969 match(Set cr (CmpN src1 src2)); 4970 ins_cost(DEFAULT_COST); 4971 size(2); 4972 format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %} 4973 opcode(LTR_ZOPC); 4974 ins_encode(z_rrform(src1, src1)); 4975 ins_pipe(pipe_class_dummy); 4976%} 4977 4978 4979//----------MemBar Instructions----------------------------------------------- 4980 4981// Memory barrier flavors 4982 4983instruct membar_acquire() %{ 4984 match(MemBarAcquire); 4985 match(LoadFence); 4986 ins_cost(4*MEMORY_REF_COST); 4987 size(0); 4988 format %{ "MEMBAR-acquire" %} 4989 ins_encode %{ __ z_acquire(); %} 4990 ins_pipe(pipe_class_dummy); 4991%} 4992 4993instruct membar_acquire_lock() %{ 4994 match(MemBarAcquireLock); 4995 ins_cost(0); 4996 size(0); 4997 format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 4998 ins_encode(/*empty*/); 4999 ins_pipe(pipe_class_dummy); 5000%} 5001 5002instruct membar_release() %{ 5003 match(MemBarRelease); 5004 match(StoreFence); 5005 ins_cost(4 * MEMORY_REF_COST); 5006 size(0); 5007 format %{ "MEMBAR-release" %} 5008 ins_encode %{ __ z_release(); %} 5009 ins_pipe(pipe_class_dummy); 5010%} 5011 5012instruct membar_release_lock() %{ 5013 match(MemBarReleaseLock); 5014 ins_cost(0); 5015 size(0); 5016 format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 5017 ins_encode(/*empty*/); 5018 ins_pipe(pipe_class_dummy); 5019%} 5020 5021instruct membar_volatile() %{ 5022 match(MemBarVolatile); 5023 ins_cost(4 * MEMORY_REF_COST); 5024 size(2); 5025 format %{ "MEMBAR-volatile" %} 5026 ins_encode %{ __ z_fence(); %} 5027 ins_pipe(pipe_class_dummy); 5028%} 5029 5030instruct unnecessary_membar_volatile() %{ 5031 match(MemBarVolatile); 5032 predicate(Matcher::post_store_load_barrier(n)); 5033 ins_cost(0); 5034 size(0); 5035 format %{ "# MEMBAR-volatile (empty)" %} 5036 ins_encode(/*empty*/); 5037 ins_pipe(pipe_class_dummy); 5038%} 5039 5040instruct membar_CPUOrder() %{ 5041 match(MemBarCPUOrder); 5042 ins_cost(0); 5043 // TODO: s390 port size(FIXED_SIZE); 5044 format %{ "MEMBAR-CPUOrder (empty)" %} 5045 ins_encode(/*empty*/); 5046 ins_pipe(pipe_class_dummy); 5047%} 5048 5049instruct membar_storestore() %{ 5050 match(MemBarStoreStore); 5051 ins_cost(0); 5052 size(0); 5053 format %{ "MEMBAR-storestore (empty)" %} 5054 ins_encode(); 5055 ins_pipe(pipe_class_dummy); 5056%} 5057 5058 5059//----------Register Move Instructions----------------------------------------- 5060instruct roundDouble_nop(regD dst) %{ 5061 match(Set dst (RoundDouble dst)); 5062 ins_cost(0); 5063 // TODO: s390 port size(FIXED_SIZE); 5064 // z/Architecture results are already "rounded" (i.e., normal-format IEEE). 5065 ins_encode(); 5066 ins_pipe(pipe_class_dummy); 5067%} 5068 5069instruct roundFloat_nop(regF dst) %{ 5070 match(Set dst (RoundFloat dst)); 5071 ins_cost(0); 5072 // TODO: s390 port size(FIXED_SIZE); 5073 // z/Architecture results are already "rounded" (i.e., normal-format IEEE). 5074 ins_encode(); 5075 ins_pipe(pipe_class_dummy); 5076%} 5077 5078// Cast Long to Pointer for unsafe natives. 5079instruct castX2P(iRegP dst, iRegL src) %{ 5080 match(Set dst (CastX2P src)); 5081 // TODO: s390 port size(VARIABLE_SIZE); 5082 format %{ "LGR $dst,$src\t # CastX2P" %} 5083 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %} 5084 ins_pipe(pipe_class_dummy); 5085%} 5086 5087// Cast Pointer to Long for unsafe natives. 5088instruct castP2X(iRegL dst, iRegP_N2P src) %{ 5089 match(Set dst (CastP2X src)); 5090 // TODO: s390 port size(VARIABLE_SIZE); 5091 format %{ "LGR $dst,$src\t # CastP2X" %} 5092 ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %} 5093 ins_pipe(pipe_class_dummy); 5094%} 5095 5096instruct stfSSD(stackSlotD stkSlot, regD src) %{ 5097 // %%%% TODO: Tell the coalescer that this kind of node is a copy! 5098 match(Set stkSlot src); // chain rule 5099 ins_cost(MEMORY_REF_COST); 5100 // TODO: s390 port size(FIXED_SIZE); 5101 format %{ " STD $src,$stkSlot\t # stk" %} 5102 opcode(STD_ZOPC); 5103 ins_encode(z_form_rt_mem(src, stkSlot)); 5104 ins_pipe(pipe_class_dummy); 5105%} 5106 5107instruct stfSSF(stackSlotF stkSlot, regF src) %{ 5108 // %%%% TODO: Tell the coalescer that this kind of node is a copy! 5109 match(Set stkSlot src); // chain rule 5110 ins_cost(MEMORY_REF_COST); 5111 // TODO: s390 port size(FIXED_SIZE); 5112 format %{ "STE $src,$stkSlot\t # stk" %} 5113 opcode(STE_ZOPC); 5114 ins_encode(z_form_rt_mem(src, stkSlot)); 5115 ins_pipe(pipe_class_dummy); 5116%} 5117 5118//----------Conditional Move--------------------------------------------------- 5119 5120instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{ 5121 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); 5122 ins_cost(DEFAULT_COST + BRANCH_COST); 5123 // TODO: s390 port size(VARIABLE_SIZE); 5124 format %{ "CMoveN,$cmp $dst,$src" %} 5125 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5126 ins_pipe(pipe_class_dummy); 5127%} 5128 5129instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{ 5130 match(Set dst (CMoveN (Binary cmp cr) (Binary dst src))); 5131 ins_cost(DEFAULT_COST + BRANCH_COST); 5132 // TODO: s390 port size(VARIABLE_SIZE); 5133 format %{ "CMoveN,$cmp $dst,$src" %} 5134 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5135 ins_pipe(pipe_class_dummy); 5136%} 5137 5138instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{ 5139 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); 5140 ins_cost(DEFAULT_COST + BRANCH_COST); 5141 // TODO: s390 port size(VARIABLE_SIZE); 5142 format %{ "CMoveI,$cmp $dst,$src" %} 5143 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5144 ins_pipe(pipe_class_dummy); 5145%} 5146 5147instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{ 5148 match(Set dst (CMoveI (Binary cmp cr) (Binary dst src))); 5149 ins_cost(DEFAULT_COST + BRANCH_COST); 5150 // TODO: s390 port size(VARIABLE_SIZE); 5151 format %{ "CMoveI,$cmp $dst,$src" %} 5152 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5153 ins_pipe(pipe_class_dummy); 5154%} 5155 5156instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{ 5157 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); 5158 ins_cost(DEFAULT_COST + BRANCH_COST); 5159 // TODO: s390 port size(VARIABLE_SIZE); 5160 format %{ "CMoveP,$cmp $dst,$src" %} 5161 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5162 ins_pipe(pipe_class_dummy); 5163%} 5164 5165instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{ 5166 match(Set dst (CMoveP (Binary cmp cr) (Binary dst src))); 5167 ins_cost(DEFAULT_COST + BRANCH_COST); 5168 // TODO: s390 port size(VARIABLE_SIZE); 5169 format %{ "CMoveP,$cmp $dst,$src" %} 5170 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5171 ins_pipe(pipe_class_dummy); 5172%} 5173 5174instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{ 5175 match(Set dst (CMoveF (Binary cmp cr) (Binary dst src))); 5176 ins_cost(DEFAULT_COST + BRANCH_COST); 5177 // TODO: s390 port size(VARIABLE_SIZE); 5178 format %{ "CMoveF,$cmp $dst,$src" %} 5179 ins_encode %{ 5180 // Don't emit code if operands are identical (same register). 5181 if ($dst$$FloatRegister != $src$$FloatRegister) { 5182 Label done; 5183 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); 5184 __ z_ler($dst$$FloatRegister, $src$$FloatRegister); 5185 __ bind(done); 5186 } 5187 %} 5188 ins_pipe(pipe_class_dummy); 5189%} 5190 5191instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{ 5192 match(Set dst (CMoveD (Binary cmp cr) (Binary dst src))); 5193 ins_cost(DEFAULT_COST + BRANCH_COST); 5194 // TODO: s390 port size(VARIABLE_SIZE); 5195 format %{ "CMoveD,$cmp $dst,$src" %} 5196 ins_encode %{ 5197 // Don't emit code if operands are identical (same register). 5198 if ($dst$$FloatRegister != $src$$FloatRegister) { 5199 Label done; 5200 __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done); 5201 __ z_ldr($dst$$FloatRegister, $src$$FloatRegister); 5202 __ bind(done); 5203 } 5204 %} 5205 ins_pipe(pipe_class_dummy); 5206%} 5207 5208instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{ 5209 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); 5210 ins_cost(DEFAULT_COST + BRANCH_COST); 5211 // TODO: s390 port size(VARIABLE_SIZE); 5212 format %{ "CMoveL,$cmp $dst,$src" %} 5213 ins_encode(z_enc_cmov_reg(cmp,dst,src)); 5214 ins_pipe(pipe_class_dummy); 5215%} 5216 5217instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{ 5218 match(Set dst (CMoveL (Binary cmp cr) (Binary dst src))); 5219 ins_cost(DEFAULT_COST + BRANCH_COST); 5220 // TODO: s390 port size(VARIABLE_SIZE); 5221 format %{ "CMoveL,$cmp $dst,$src" %} 5222 ins_encode(z_enc_cmov_imm(cmp,dst,src)); 5223 ins_pipe(pipe_class_dummy); 5224%} 5225 5226//----------OS and Locking Instructions---------------------------------------- 5227 5228// This name is KNOWN by the ADLC and cannot be changed. 5229// The ADLC forces a 'TypeRawPtr::BOTTOM' output type 5230// for this guy. 5231instruct tlsLoadP(threadRegP dst) %{ 5232 match(Set dst (ThreadLocal)); 5233 ins_cost(0); 5234 size(0); 5235 ins_should_rematerialize(true); 5236 format %{ "# $dst=ThreadLocal" %} 5237 ins_encode(/* empty */); 5238 ins_pipe(pipe_class_dummy); 5239%} 5240 5241instruct checkCastPP(iRegP dst) %{ 5242 match(Set dst (CheckCastPP dst)); 5243 size(0); 5244 format %{ "# checkcastPP of $dst" %} 5245 ins_encode(/*empty*/); 5246 ins_pipe(pipe_class_dummy); 5247%} 5248 5249instruct castPP(iRegP dst) %{ 5250 match(Set dst (CastPP dst)); 5251 size(0); 5252 format %{ "# castPP of $dst" %} 5253 ins_encode(/*empty*/); 5254 ins_pipe(pipe_class_dummy); 5255%} 5256 5257instruct castII(iRegI dst) %{ 5258 match(Set dst (CastII dst)); 5259 size(0); 5260 format %{ "# castII of $dst" %} 5261 ins_encode(/*empty*/); 5262 ins_pipe(pipe_class_dummy); 5263%} 5264 5265instruct castLL(iRegL dst) %{ 5266 match(Set dst (CastLL dst)); 5267 size(0); 5268 format %{ "# castLL of $dst" %} 5269 ins_encode(/*empty*/); 5270 ins_pipe(pipe_class_dummy); 5271%} 5272 5273instruct castFF(regF dst) %{ 5274 match(Set dst (CastFF dst)); 5275 size(0); 5276 format %{ "# castFF of $dst" %} 5277 ins_encode(/*empty*/); 5278 ins_pipe(pipe_class_dummy); 5279%} 5280 5281instruct castDD(regD dst) %{ 5282 match(Set dst (CastDD dst)); 5283 size(0); 5284 format %{ "# castDD of $dst" %} 5285 ins_encode(/*empty*/); 5286 ins_pipe(pipe_class_dummy); 5287%} 5288 5289instruct castVV(iRegL dst) %{ 5290 match(Set dst (CastVV dst)); 5291 size(0); 5292 format %{ "# castVV of $dst" %} 5293 ins_encode(/*empty*/); 5294 ins_pipe(pipe_class_dummy); 5295%} 5296 5297//----------Conditional_store-------------------------------------------------- 5298// Conditional-store of the updated heap-top. 5299// Used during allocation of the shared heap. 5300// Sets flags (EQ) on success. 5301 5302// Implement LoadPLocked. Must be ordered against changes of the memory location 5303// by storePConditional. 5304// Don't know whether this is ever used. 5305instruct loadPLocked(iRegP dst, memory mem) %{ 5306 match(Set dst (LoadPLocked mem)); 5307 ins_cost(MEMORY_REF_COST); 5308 size(Z_DISP3_SIZE); 5309 format %{ "LG $dst,$mem\t # LoadPLocked" %} 5310 opcode(LG_ZOPC, LG_ZOPC); 5311 ins_encode(z_form_rt_mem_opt(dst, mem)); 5312 ins_pipe(pipe_class_dummy); 5313%} 5314 5315// As compareAndSwapP, but return flag register instead of boolean value in 5316// int register. 5317// This instruction is matched if UseTLAB is off. Needed to pass 5318// option tests. Mem_ptr must be a memory operand, else this node 5319// does not get Flag_needs_anti_dependence_check set by adlc. If this 5320// is not set this node can be rematerialized which leads to errors. 5321instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{ 5322 match(Set cr (StorePConditional mem_ptr (Binary oldval newval))); 5323 effect(KILL oldval); 5324 // TODO: s390 port size(FIXED_SIZE); 5325 format %{ "storePConditional $oldval,$newval,$mem_ptr" %} 5326 ins_encode(z_enc_casL(oldval, newval, mem_ptr)); 5327 ins_pipe(pipe_class_dummy); 5328%} 5329 5330// As compareAndSwapL, but return flag register instead of boolean value in 5331// int register. 5332// Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory 5333// operand, else this node does not get 5334// Flag_needs_anti_dependence_check set by adlc. If this is not set 5335// this node can be rematerialized which leads to errors. 5336instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{ 5337 match(Set cr (StoreLConditional mem_ptr (Binary oldval newval))); 5338 effect(KILL oldval); 5339 // TODO: s390 port size(FIXED_SIZE); 5340 format %{ "storePConditional $oldval,$newval,$mem_ptr" %} 5341 ins_encode(z_enc_casL(oldval, newval, mem_ptr)); 5342 ins_pipe(pipe_class_dummy); 5343%} 5344 5345// No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them. 5346 5347instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{ 5348 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 5349 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5350 size(16); 5351 format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %} 5352 ins_encode(z_enc_casI(oldval, newval, mem_ptr), 5353 z_enc_cctobool(res)); 5354 ins_pipe(pipe_class_dummy); 5355%} 5356 5357instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{ 5358 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 5359 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5360 size(18); 5361 format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %} 5362 ins_encode(z_enc_casL(oldval, newval, mem_ptr), 5363 z_enc_cctobool(res)); 5364 ins_pipe(pipe_class_dummy); 5365%} 5366 5367instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{ 5368 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 5369 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5370 size(18); 5371 format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %} 5372 ins_encode(z_enc_casL(oldval, newval, mem_ptr), 5373 z_enc_cctobool(res)); 5374 ins_pipe(pipe_class_dummy); 5375%} 5376 5377instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{ 5378 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 5379 effect(USE mem_ptr, USE_KILL oldval, KILL cr); 5380 size(16); 5381 format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %} 5382 ins_encode(z_enc_casI(oldval, newval, mem_ptr), 5383 z_enc_cctobool(res)); 5384 ins_pipe(pipe_class_dummy); 5385%} 5386 5387//----------Atomic operations on memory (GetAndSet*, GetAndAdd*)--------------- 5388 5389// Exploit: direct memory arithmetic 5390// Prereqs: - instructions available 5391// - instructions guarantee atomicity 5392// - immediate operand to be added 5393// - immediate operand is small enough (8-bit signed). 5394// - result of instruction is not used 5395instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{ 5396 match(Set dummy (GetAndAddI mem src)); 5397 effect(KILL cr); 5398 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); 5399 ins_cost(MEMORY_REF_COST); 5400 size(6); 5401 format %{ "ASI [$mem],$src\t # GetAndAddI (atomic)" %} 5402 opcode(ASI_ZOPC); 5403 ins_encode(z_siyform(mem, src)); 5404 ins_pipe(pipe_class_dummy); 5405%} 5406 5407// Fallback: direct memory arithmetic not available 5408// Disadvantages: - CS-Loop required, very expensive. 5409// - more code generated (26 to xx bytes vs. 6 bytes) 5410instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{ 5411 match(Set dst (GetAndAddI mem src)); 5412 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5413 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5414 format %{ "BEGIN ATOMIC {\n\t" 5415 " LGF $dst,[$mem]\n\t" 5416 " AHIK $tmp,$dst,$src\n\t" 5417 " CSY $dst,$tmp,$mem\n\t" 5418 " retry if failed\n\t" 5419 "} END ATOMIC" 5420 %} 5421 ins_encode %{ 5422 Register Rdst = $dst$$Register; 5423 Register Rtmp = $tmp$$Register; 5424 int Isrc = $src$$constant; 5425 Label retry; 5426 5427 // Iterate until update with incremented value succeeds. 5428 __ z_lgf(Rdst, $mem$$Address); // current contents 5429 __ bind(retry); 5430 // Calculate incremented value. 5431 if (VM_Version::has_DistinctOpnds()) { 5432 __ z_ahik(Rtmp, Rdst, Isrc); 5433 } else { 5434 __ z_lr(Rtmp, Rdst); 5435 __ z_ahi(Rtmp, Isrc); 5436 } 5437 // Swap into memory location. 5438 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5439 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5440 %} 5441 ins_pipe(pipe_class_dummy); 5442%} 5443 5444instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{ 5445 match(Set dst (GetAndAddI mem src)); 5446 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5447 ins_cost(MEMORY_REF_COST+200*DEFAULT_COST); 5448 format %{ "BEGIN ATOMIC {\n\t" 5449 " LGF $dst,[$mem]\n\t" 5450 " LGR $tmp,$dst\n\t" 5451 " AFI $tmp,$src\n\t" 5452 " CSY $dst,$tmp,$mem\n\t" 5453 " retry if failed\n\t" 5454 "} END ATOMIC" 5455 %} 5456 ins_encode %{ 5457 Register Rdst = $dst$$Register; 5458 Register Rtmp = $tmp$$Register; 5459 int Isrc = $src$$constant; 5460 Label retry; 5461 5462 // Iterate until update with incremented value succeeds. 5463 __ z_lgf(Rdst, $mem$$Address); // current contents 5464 __ bind(retry); 5465 // Calculate incremented value. 5466 __ z_lr(Rtmp, Rdst); 5467 __ z_afi(Rtmp, Isrc); 5468 // Swap into memory location. 5469 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5470 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5471 %} 5472 ins_pipe(pipe_class_dummy); 5473%} 5474 5475instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 5476 match(Set dst (GetAndAddI mem src)); 5477 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5478 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5479 format %{ "BEGIN ATOMIC {\n\t" 5480 " LGF $dst,[$mem]\n\t" 5481 " ARK $tmp,$dst,$src\n\t" 5482 " CSY $dst,$tmp,$mem\n\t" 5483 " retry if failed\n\t" 5484 "} END ATOMIC" 5485 %} 5486 ins_encode %{ 5487 Register Rsrc = $src$$Register; 5488 Register Rdst = $dst$$Register; 5489 Register Rtmp = $tmp$$Register; 5490 Label retry; 5491 5492 // Iterate until update with incremented value succeeds. 5493 __ z_lgf(Rdst, $mem$$Address); // current contents 5494 __ bind(retry); 5495 // Calculate incremented value. 5496 if (VM_Version::has_DistinctOpnds()) { 5497 __ z_ark(Rtmp, Rdst, Rsrc); 5498 } else { 5499 __ z_lr(Rtmp, Rdst); 5500 __ z_ar(Rtmp, Rsrc); 5501 } 5502 __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5503 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5504 %} 5505 ins_pipe(pipe_class_dummy); 5506%} 5507 5508 5509// Exploit: direct memory arithmetic 5510// Prereqs: - instructions available 5511// - instructions guarantee atomicity 5512// - immediate operand to be added 5513// - immediate operand is small enough (8-bit signed). 5514// - result of instruction is not used 5515instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{ 5516 match(Set dummy (GetAndAddL mem src)); 5517 effect(KILL cr); 5518 predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used()); 5519 ins_cost(MEMORY_REF_COST); 5520 size(6); 5521 format %{ "AGSI [$mem],$src\t # GetAndAddL (atomic)" %} 5522 opcode(AGSI_ZOPC); 5523 ins_encode(z_siyform(mem, src)); 5524 ins_pipe(pipe_class_dummy); 5525%} 5526 5527// Fallback: direct memory arithmetic not available 5528// Disadvantages: - CS-Loop required, very expensive. 5529// - more code generated (26 to xx bytes vs. 6 bytes) 5530instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{ 5531 match(Set dst (GetAndAddL mem src)); 5532 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5533 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5534 format %{ "BEGIN ATOMIC {\n\t" 5535 " LG $dst,[$mem]\n\t" 5536 " AGHIK $tmp,$dst,$src\n\t" 5537 " CSG $dst,$tmp,$mem\n\t" 5538 " retry if failed\n\t" 5539 "} END ATOMIC" 5540 %} 5541 ins_encode %{ 5542 Register Rdst = $dst$$Register; 5543 Register Rtmp = $tmp$$Register; 5544 int Isrc = $src$$constant; 5545 Label retry; 5546 5547 // Iterate until update with incremented value succeeds. 5548 __ z_lg(Rdst, $mem$$Address); // current contents 5549 __ bind(retry); 5550 // Calculate incremented value. 5551 if (VM_Version::has_DistinctOpnds()) { 5552 __ z_aghik(Rtmp, Rdst, Isrc); 5553 } else { 5554 __ z_lgr(Rtmp, Rdst); 5555 __ z_aghi(Rtmp, Isrc); 5556 } 5557 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5558 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5559 %} 5560 ins_pipe(pipe_class_dummy); 5561%} 5562 5563instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{ 5564 match(Set dst (GetAndAddL mem src)); 5565 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5566 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5567 format %{ "BEGIN ATOMIC {\n\t" 5568 " LG $dst,[$mem]\n\t" 5569 " LGR $tmp,$dst\n\t" 5570 " AGFI $tmp,$src\n\t" 5571 " CSG $dst,$tmp,$mem\n\t" 5572 " retry if failed\n\t" 5573 "} END ATOMIC" 5574 %} 5575 ins_encode %{ 5576 Register Rdst = $dst$$Register; 5577 Register Rtmp = $tmp$$Register; 5578 int Isrc = $src$$constant; 5579 Label retry; 5580 5581 // Iterate until update with incremented value succeeds. 5582 __ z_lg(Rdst, $mem$$Address); // current contents 5583 __ bind(retry); 5584 // Calculate incremented value. 5585 __ z_lgr(Rtmp, Rdst); 5586 __ z_agfi(Rtmp, Isrc); 5587 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5588 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5589 %} 5590 ins_pipe(pipe_class_dummy); 5591%} 5592 5593instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{ 5594 match(Set dst (GetAndAddL mem src)); 5595 effect(KILL cr, TEMP_DEF dst, TEMP tmp); 5596 ins_cost(MEMORY_REF_COST+100*DEFAULT_COST); 5597 format %{ "BEGIN ATOMIC {\n\t" 5598 " LG $dst,[$mem]\n\t" 5599 " AGRK $tmp,$dst,$src\n\t" 5600 " CSG $dst,$tmp,$mem\n\t" 5601 " retry if failed\n\t" 5602 "} END ATOMIC" 5603 %} 5604 ins_encode %{ 5605 Register Rsrc = $src$$Register; 5606 Register Rdst = $dst$$Register; 5607 Register Rtmp = $tmp$$Register; 5608 Label retry; 5609 5610 // Iterate until update with incremented value succeeds. 5611 __ z_lg(Rdst, $mem$$Address); // current contents 5612 __ bind(retry); 5613 // Calculate incremented value. 5614 if (VM_Version::has_DistinctOpnds()) { 5615 __ z_agrk(Rtmp, Rdst, Rsrc); 5616 } else { 5617 __ z_lgr(Rtmp, Rdst); 5618 __ z_agr(Rtmp, Rsrc); 5619 } 5620 __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value. 5621 __ z_brne(retry); // Yikes, concurrent update, need to retry. 5622 %} 5623 ins_pipe(pipe_class_dummy); 5624%} 5625 5626// Increment value in memory, save old value in dst. 5627instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{ 5628 match(Set dst (GetAndAddI mem src)); 5629 predicate(VM_Version::has_LoadAndALUAtomicV1()); 5630 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5631 size(6); 5632 format %{ "LAA $dst,$src,[$mem]" %} 5633 ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %} 5634 ins_pipe(pipe_class_dummy); 5635%} 5636 5637// Increment value in memory, save old value in dst. 5638instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{ 5639 match(Set dst (GetAndAddL mem src)); 5640 predicate(VM_Version::has_LoadAndALUAtomicV1()); 5641 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5642 size(6); 5643 format %{ "LAAG $dst,$src,[$mem]" %} 5644 ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %} 5645 ins_pipe(pipe_class_dummy); 5646%} 5647 5648 5649instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{ 5650 match(Set dst (GetAndSetI mem dst)); 5651 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5652 format %{ "XCHGI $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %} 5653 ins_encode(z_enc_SwapI(mem, dst, tmp)); 5654 ins_pipe(pipe_class_dummy); 5655%} 5656 5657instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{ 5658 match(Set dst (GetAndSetL mem dst)); 5659 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5660 format %{ "XCHGL $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %} 5661 ins_encode(z_enc_SwapL(mem, dst, tmp)); 5662 ins_pipe(pipe_class_dummy); 5663%} 5664 5665instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{ 5666 match(Set dst (GetAndSetN mem dst)); 5667 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5668 format %{ "XCHGN $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %} 5669 ins_encode(z_enc_SwapI(mem, dst, tmp)); 5670 ins_pipe(pipe_class_dummy); 5671%} 5672 5673instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{ 5674 match(Set dst (GetAndSetP mem dst)); 5675 effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule. 5676 format %{ "XCHGP $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %} 5677 ins_encode(z_enc_SwapL(mem, dst, tmp)); 5678 ins_pipe(pipe_class_dummy); 5679%} 5680 5681 5682//----------Arithmetic Instructions-------------------------------------------- 5683 5684// The rules are sorted by right operand type and operand length. Please keep 5685// it that way. 5686// Left operand type is always reg. Left operand len is I, L, P 5687// Right operand type is reg, imm, mem. Right operand len is S, I, L, P 5688// Special instruction formats, e.g. multi-operand, are inserted at the end. 5689 5690// ADD 5691 5692// REG = REG + REG 5693 5694// Register Addition 5695instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{ 5696 match(Set dst (AddI dst src)); 5697 effect(KILL cr); 5698 // TODO: s390 port size(FIXED_SIZE); 5699 format %{ "AR $dst,$src\t # int CISC ALU" %} 5700 opcode(AR_ZOPC); 5701 ins_encode(z_rrform(dst, src)); 5702 ins_pipe(pipe_class_dummy); 5703%} 5704 5705// Avoid use of LA(Y) for general ALU operation. 5706instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 5707 match(Set dst (AddI src1 src2)); 5708 effect(KILL cr); 5709 predicate(VM_Version::has_DistinctOpnds()); 5710 ins_cost(DEFAULT_COST); 5711 size(4); 5712 format %{ "ARK $dst,$src1,$src2\t # int RISC ALU" %} 5713 opcode(ARK_ZOPC); 5714 ins_encode(z_rrfform(dst, src1, src2)); 5715 ins_pipe(pipe_class_dummy); 5716%} 5717 5718// REG = REG + IMM 5719 5720// Avoid use of LA(Y) for general ALU operation. 5721// Immediate Addition 5722instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{ 5723 match(Set dst (AddI dst con)); 5724 effect(KILL cr); 5725 ins_cost(DEFAULT_COST); 5726 // TODO: s390 port size(FIXED_SIZE); 5727 format %{ "AHI $dst,$con\t # int CISC ALU" %} 5728 opcode(AHI_ZOPC); 5729 ins_encode(z_riform_signed(dst, con)); 5730 ins_pipe(pipe_class_dummy); 5731%} 5732 5733// Avoid use of LA(Y) for general ALU operation. 5734// Immediate Addition 5735instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{ 5736 match(Set dst (AddI src con)); 5737 effect(KILL cr); 5738 predicate( VM_Version::has_DistinctOpnds()); 5739 ins_cost(DEFAULT_COST); 5740 // TODO: s390 port size(FIXED_SIZE); 5741 format %{ "AHIK $dst,$src,$con\t # int RISC ALU" %} 5742 opcode(AHIK_ZOPC); 5743 ins_encode(z_rieform_d(dst, src, con)); 5744 ins_pipe(pipe_class_dummy); 5745%} 5746 5747// Immediate Addition 5748instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{ 5749 match(Set dst (AddI dst src)); 5750 effect(KILL cr); 5751 ins_cost(DEFAULT_COST_HIGH); 5752 size(6); 5753 format %{ "AFI $dst,$src" %} 5754 opcode(AFI_ZOPC); 5755 ins_encode(z_rilform_signed(dst, src)); 5756 ins_pipe(pipe_class_dummy); 5757%} 5758 5759// Immediate Addition 5760instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{ 5761 match(Set dst (AddI src con)); 5762 predicate(PreferLAoverADD); 5763 ins_cost(DEFAULT_COST_LOW); 5764 size(4); 5765 format %{ "LA $dst,$con(,$src)\t # int d12(,b)" %} 5766 opcode(LA_ZOPC); 5767 ins_encode(z_rxform_imm_reg(dst, con, src)); 5768 ins_pipe(pipe_class_dummy); 5769%} 5770 5771// Immediate Addition 5772instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{ 5773 match(Set dst (AddI src con)); 5774 predicate(PreferLAoverADD); 5775 ins_cost(DEFAULT_COST); 5776 size(6); 5777 format %{ "LAY $dst,$con(,$src)\t # int d20(,b)" %} 5778 opcode(LAY_ZOPC); 5779 ins_encode(z_rxyform_imm_reg(dst, con, src)); 5780 ins_pipe(pipe_class_dummy); 5781%} 5782 5783instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{ 5784 match(Set dst (AddI (AddI src1 src2) con)); 5785 predicate( PreferLAoverADD); 5786 ins_cost(DEFAULT_COST_LOW); 5787 size(4); 5788 format %{ "LA $dst,$con($src1,$src2)\t # int d12(x,b)" %} 5789 opcode(LA_ZOPC); 5790 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 5791 ins_pipe(pipe_class_dummy); 5792%} 5793 5794instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{ 5795 match(Set dst (AddI (AddI src1 src2) con)); 5796 predicate(PreferLAoverADD); 5797 ins_cost(DEFAULT_COST); 5798 size(6); 5799 format %{ "LAY $dst,$con($src1,$src2)\t # int d20(x,b)" %} 5800 opcode(LAY_ZOPC); 5801 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 5802 ins_pipe(pipe_class_dummy); 5803%} 5804 5805// REG = REG + MEM 5806 5807instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 5808 match(Set dst (AddI dst (LoadI src))); 5809 effect(KILL cr); 5810 ins_cost(MEMORY_REF_COST); 5811 // TODO: s390 port size(VARIABLE_SIZE); 5812 format %{ "A(Y) $dst, $src\t # int" %} 5813 opcode(AY_ZOPC, A_ZOPC); 5814 ins_encode(z_form_rt_mem_opt(dst, src)); 5815 ins_pipe(pipe_class_dummy); 5816%} 5817 5818// MEM = MEM + IMM 5819 5820// Add Immediate to 4-byte memory operand and result 5821instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{ 5822 match(Set mem (StoreI mem (AddI (LoadI mem) src))); 5823 effect(KILL cr); 5824 predicate(VM_Version::has_MemWithImmALUOps()); 5825 ins_cost(MEMORY_REF_COST); 5826 size(6); 5827 format %{ "ASI $mem,$src\t # direct mem add 4" %} 5828 opcode(ASI_ZOPC); 5829 ins_encode(z_siyform(mem, src)); 5830 ins_pipe(pipe_class_dummy); 5831%} 5832 5833 5834// 5835 5836// REG = REG + REG 5837 5838instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{ 5839 match(Set dst (AddL dst (ConvI2L src))); 5840 effect(KILL cr); 5841 size(4); 5842 format %{ "AGFR $dst,$src\t # long<-int CISC ALU" %} 5843 opcode(AGFR_ZOPC); 5844 ins_encode(z_rreform(dst, src)); 5845 ins_pipe(pipe_class_dummy); 5846%} 5847 5848instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{ 5849 match(Set dst (AddL dst src)); 5850 effect(KILL cr); 5851 // TODO: s390 port size(FIXED_SIZE); 5852 format %{ "AGR $dst, $src\t # long CISC ALU" %} 5853 opcode(AGR_ZOPC); 5854 ins_encode(z_rreform(dst, src)); 5855 ins_pipe(pipe_class_dummy); 5856%} 5857 5858// Avoid use of LA(Y) for general ALU operation. 5859instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 5860 match(Set dst (AddL src1 src2)); 5861 effect(KILL cr); 5862 predicate(VM_Version::has_DistinctOpnds()); 5863 ins_cost(DEFAULT_COST); 5864 size(4); 5865 format %{ "AGRK $dst,$src1,$src2\t # long RISC ALU" %} 5866 opcode(AGRK_ZOPC); 5867 ins_encode(z_rrfform(dst, src1, src2)); 5868 ins_pipe(pipe_class_dummy); 5869%} 5870 5871// REG = REG + IMM 5872 5873instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{ 5874 match(Set dst (AddL src con)); 5875 predicate( PreferLAoverADD); 5876 ins_cost(DEFAULT_COST_LOW); 5877 size(4); 5878 format %{ "LA $dst,$con(,$src)\t # long d12(,b)" %} 5879 opcode(LA_ZOPC); 5880 ins_encode(z_rxform_imm_reg(dst, con, src)); 5881 ins_pipe(pipe_class_dummy); 5882%} 5883 5884instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{ 5885 match(Set dst (AddL src con)); 5886 predicate(PreferLAoverADD); 5887 ins_cost(DEFAULT_COST); 5888 size(6); 5889 format %{ "LAY $dst,$con(,$src)\t # long d20(,b)" %} 5890 opcode(LAY_ZOPC); 5891 ins_encode(z_rxyform_imm_reg(dst, con, src)); 5892 ins_pipe(pipe_class_dummy); 5893%} 5894 5895instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{ 5896 match(Set dst (AddL dst con)); 5897 effect(KILL cr); 5898 ins_cost(DEFAULT_COST_HIGH); 5899 size(6); 5900 format %{ "AGFI $dst,$con\t # long CISC ALU" %} 5901 opcode(AGFI_ZOPC); 5902 ins_encode(z_rilform_signed(dst, con)); 5903 ins_pipe(pipe_class_dummy); 5904%} 5905 5906// Avoid use of LA(Y) for general ALU operation. 5907instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{ 5908 match(Set dst (AddL dst con)); 5909 effect(KILL cr); 5910 ins_cost(DEFAULT_COST); 5911 // TODO: s390 port size(FIXED_SIZE); 5912 format %{ "AGHI $dst,$con\t # long CISC ALU" %} 5913 opcode(AGHI_ZOPC); 5914 ins_encode(z_riform_signed(dst, con)); 5915 ins_pipe(pipe_class_dummy); 5916%} 5917 5918// Avoid use of LA(Y) for general ALU operation. 5919instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{ 5920 match(Set dst (AddL src con)); 5921 effect(KILL cr); 5922 predicate( VM_Version::has_DistinctOpnds()); 5923 ins_cost(DEFAULT_COST); 5924 size(6); 5925 format %{ "AGHIK $dst,$src,$con\t # long RISC ALU" %} 5926 opcode(AGHIK_ZOPC); 5927 ins_encode(z_rieform_d(dst, src, con)); 5928 ins_pipe(pipe_class_dummy); 5929%} 5930 5931// REG = REG + MEM 5932 5933instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{ 5934 match(Set dst (AddL dst (ConvI2L (LoadI src)))); 5935 effect(KILL cr); 5936 ins_cost(MEMORY_REF_COST); 5937 size(Z_DISP3_SIZE); 5938 format %{ "AGF $dst, $src\t # long/int" %} 5939 opcode(AGF_ZOPC, AGF_ZOPC); 5940 ins_encode(z_form_rt_mem_opt(dst, src)); 5941 ins_pipe(pipe_class_dummy); 5942%} 5943 5944instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 5945 match(Set dst (AddL dst (LoadL src))); 5946 effect(KILL cr); 5947 ins_cost(MEMORY_REF_COST); 5948 size(Z_DISP3_SIZE); 5949 format %{ "AG $dst, $src\t # long" %} 5950 opcode(AG_ZOPC, AG_ZOPC); 5951 ins_encode(z_form_rt_mem_opt(dst, src)); 5952 ins_pipe(pipe_class_dummy); 5953%} 5954 5955instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{ 5956 match(Set dst (AddL (AddL src1 src2) con)); 5957 predicate( PreferLAoverADD); 5958 ins_cost(DEFAULT_COST_LOW); 5959 size(4); 5960 format %{ "LA $dst,$con($src1,$src2)\t # long d12(x,b)" %} 5961 opcode(LA_ZOPC); 5962 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 5963 ins_pipe(pipe_class_dummy); 5964%} 5965 5966instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{ 5967 match(Set dst (AddL (AddL src1 src2) con)); 5968 predicate(PreferLAoverADD); 5969 ins_cost(DEFAULT_COST); 5970 size(6); 5971 format %{ "LAY $dst,$con($src1,$src2)\t # long d20(x,b)" %} 5972 opcode(LAY_ZOPC); 5973 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 5974 ins_pipe(pipe_class_dummy); 5975%} 5976 5977// MEM = MEM + IMM 5978 5979// Add Immediate to 8-byte memory operand and result. 5980instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{ 5981 match(Set mem (StoreL mem (AddL (LoadL mem) src))); 5982 effect(KILL cr); 5983 predicate(VM_Version::has_MemWithImmALUOps()); 5984 ins_cost(MEMORY_REF_COST); 5985 size(6); 5986 format %{ "AGSI $mem,$src\t # direct mem add 8" %} 5987 opcode(AGSI_ZOPC); 5988 ins_encode(z_siyform(mem, src)); 5989 ins_pipe(pipe_class_dummy); 5990%} 5991 5992 5993// REG = REG + REG 5994 5995// Ptr Addition 5996instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{ 5997 match(Set dst (AddP src1 src2)); 5998 predicate( PreferLAoverADD); 5999 ins_cost(DEFAULT_COST); 6000 size(4); 6001 format %{ "LA $dst,#0($src1,$src2)\t # ptr 0(x,b)" %} 6002 opcode(LA_ZOPC); 6003 ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2)); 6004 ins_pipe(pipe_class_dummy); 6005%} 6006 6007// Ptr Addition 6008// Avoid use of LA(Y) for general ALU operation. 6009instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{ 6010 match(Set dst (AddP dst src)); 6011 effect(KILL cr); 6012 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); 6013 ins_cost(DEFAULT_COST); 6014 // TODO: s390 port size(FIXED_SIZE); 6015 format %{ "ALGR $dst,$src\t # ptr CICS ALU" %} 6016 opcode(ALGR_ZOPC); 6017 ins_encode(z_rreform(dst, src)); 6018 ins_pipe(pipe_class_dummy); 6019%} 6020 6021// Ptr Addition 6022// Avoid use of LA(Y) for general ALU operation. 6023instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{ 6024 match(Set dst (AddP src1 src2)); 6025 effect(KILL cr); 6026 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); 6027 ins_cost(DEFAULT_COST); 6028 // TODO: s390 port size(FIXED_SIZE); 6029 format %{ "ALGRK $dst,$src1,$src2\t # ptr RISC ALU" %} 6030 opcode(ALGRK_ZOPC); 6031 ins_encode(z_rrfform(dst, src1, src2)); 6032 ins_pipe(pipe_class_dummy); 6033%} 6034 6035// REG = REG + IMM 6036 6037instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{ 6038 match(Set dst (AddP src con)); 6039 predicate( PreferLAoverADD); 6040 ins_cost(DEFAULT_COST_LOW); 6041 size(4); 6042 format %{ "LA $dst,$con(,$src)\t # ptr d12(,b)" %} 6043 opcode(LA_ZOPC); 6044 ins_encode(z_rxform_imm_reg(dst, con, src)); 6045 ins_pipe(pipe_class_dummy); 6046%} 6047 6048// Avoid use of LA(Y) for general ALU operation. 6049instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{ 6050 match(Set dst (AddP dst src)); 6051 effect(KILL cr); 6052 predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds()); 6053 ins_cost(DEFAULT_COST); 6054 // TODO: s390 port size(FIXED_SIZE); 6055 format %{ "AGHI $dst,$src\t # ptr CISC ALU" %} 6056 opcode(AGHI_ZOPC); 6057 ins_encode(z_riform_signed(dst, src)); 6058 ins_pipe(pipe_class_dummy); 6059%} 6060 6061// Avoid use of LA(Y) for general ALU operation. 6062instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{ 6063 match(Set dst (AddP src con)); 6064 effect(KILL cr); 6065 predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds()); 6066 ins_cost(DEFAULT_COST); 6067 // TODO: s390 port size(FIXED_SIZE); 6068 format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %} 6069 opcode(ALGHSIK_ZOPC); 6070 ins_encode(z_rieform_d(dst, src, con)); 6071 ins_pipe(pipe_class_dummy); 6072%} 6073 6074instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{ 6075 match(Set dst (AddP src con)); 6076 predicate(PreferLAoverADD); 6077 ins_cost(DEFAULT_COST); 6078 size(6); 6079 format %{ "LAY $dst,$con(,$src)\t # ptr d20(,b)" %} 6080 opcode(LAY_ZOPC); 6081 ins_encode(z_rxyform_imm_reg(dst, con, src)); 6082 ins_pipe(pipe_class_dummy); 6083%} 6084 6085// Pointer Immediate Addition 6086instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{ 6087 match(Set dst (AddP dst src)); 6088 effect(KILL cr); 6089 ins_cost(DEFAULT_COST_HIGH); 6090 // TODO: s390 port size(FIXED_SIZE); 6091 format %{ "AGFI $dst,$src\t # ptr" %} 6092 opcode(AGFI_ZOPC); 6093 ins_encode(z_rilform_signed(dst, src)); 6094 ins_pipe(pipe_class_dummy); 6095%} 6096 6097// REG = REG1 + REG2 + IMM 6098 6099instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{ 6100 match(Set dst (AddP (AddP src1 src2) con)); 6101 predicate( PreferLAoverADD); 6102 ins_cost(DEFAULT_COST_LOW); 6103 size(4); 6104 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} 6105 opcode(LA_ZOPC); 6106 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6107 ins_pipe(pipe_class_dummy); 6108%} 6109 6110instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{ 6111 match(Set dst (AddP (AddP src1 src2) con)); 6112 predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0); 6113 ins_cost(DEFAULT_COST_LOW); 6114 size(4); 6115 format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} 6116 opcode(LA_ZOPC); 6117 ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); 6118 ins_pipe(pipe_class_dummy); 6119%} 6120 6121instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{ 6122 match(Set dst (AddP (AddP src1 src2) con)); 6123 predicate(PreferLAoverADD); 6124 ins_cost(DEFAULT_COST); 6125 // TODO: s390 port size(FIXED_SIZE); 6126 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} 6127 opcode(LAY_ZOPC); 6128 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6129 ins_pipe(pipe_class_dummy); 6130%} 6131 6132instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{ 6133 match(Set dst (AddP (AddP src1 src2) con)); 6134 predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0); 6135 ins_cost(DEFAULT_COST); 6136 // TODO: s390 port size(FIXED_SIZE); 6137 format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} 6138 opcode(LAY_ZOPC); 6139 ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); 6140 ins_pipe(pipe_class_dummy); 6141%} 6142 6143// MEM = MEM + IMM 6144 6145// Add Immediate to 8-byte memory operand and result 6146instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{ 6147 match(Set mem (StoreP mem (AddP (LoadP mem) src))); 6148 effect(KILL cr); 6149 predicate(VM_Version::has_MemWithImmALUOps()); 6150 ins_cost(MEMORY_REF_COST); 6151 size(6); 6152 format %{ "AGSI $mem,$src\t # direct mem add 8 (ptr)" %} 6153 opcode(AGSI_ZOPC); 6154 ins_encode(z_siyform(mem, src)); 6155 ins_pipe(pipe_class_dummy); 6156%} 6157 6158// SUB 6159 6160// Register Subtraction 6161instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{ 6162 match(Set dst (SubI dst src)); 6163 effect(KILL cr); 6164 // TODO: s390 port size(FIXED_SIZE); 6165 format %{ "SR $dst,$src\t # int CISC ALU" %} 6166 opcode(SR_ZOPC); 6167 ins_encode(z_rrform(dst, src)); 6168 ins_pipe(pipe_class_dummy); 6169%} 6170 6171instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 6172 match(Set dst (SubI src1 src2)); 6173 effect(KILL cr); 6174 predicate(VM_Version::has_DistinctOpnds()); 6175 ins_cost(DEFAULT_COST); 6176 size(4); 6177 format %{ "SRK $dst,$src1,$src2\t # int RISC ALU" %} 6178 opcode(SRK_ZOPC); 6179 ins_encode(z_rrfform(dst, src1, src2)); 6180 ins_pipe(pipe_class_dummy); 6181%} 6182 6183instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 6184 match(Set dst (SubI dst (LoadI src))); 6185 effect(KILL cr); 6186 ins_cost(MEMORY_REF_COST); 6187 // TODO: s390 port size(VARIABLE_SIZE); 6188 format %{ "S(Y) $dst, $src\t # int" %} 6189 opcode(SY_ZOPC, S_ZOPC); 6190 ins_encode(z_form_rt_mem_opt(dst, src)); 6191 ins_pipe(pipe_class_dummy); 6192%} 6193 6194instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{ 6195 match(Set dst (SubI zero src)); 6196 effect(KILL cr); 6197 size(2); 6198 format %{ "NEG $dst, $src" %} 6199 ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %} 6200 ins_pipe(pipe_class_dummy); 6201%} 6202 6203// 6204 6205// Long subtraction 6206instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{ 6207 match(Set dst (SubL dst src)); 6208 effect(KILL cr); 6209 // TODO: s390 port size(FIXED_SIZE); 6210 format %{ "SGR $dst,$src\t # int CISC ALU" %} 6211 opcode(SGR_ZOPC); 6212 ins_encode(z_rreform(dst, src)); 6213 ins_pipe(pipe_class_dummy); 6214%} 6215 6216// Avoid use of LA(Y) for general ALU operation. 6217instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 6218 match(Set dst (SubL src1 src2)); 6219 effect(KILL cr); 6220 predicate(VM_Version::has_DistinctOpnds()); 6221 ins_cost(DEFAULT_COST); 6222 size(4); 6223 format %{ "SGRK $dst,$src1,$src2\t # int RISC ALU" %} 6224 opcode(SGRK_ZOPC); 6225 ins_encode(z_rrfform(dst, src1, src2)); 6226 ins_pipe(pipe_class_dummy); 6227%} 6228 6229instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{ 6230 match(Set dst (SubL dst (ConvI2L src))); 6231 effect(KILL cr); 6232 size(4); 6233 format %{ "SGFR $dst, $src\t # int CISC ALU" %} 6234 opcode(SGFR_ZOPC); 6235 ins_encode(z_rreform(dst, src)); 6236 ins_pipe(pipe_class_dummy); 6237%} 6238 6239instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{ 6240 match(Set dst (SubL dst (ConvI2L (LoadI src)))); 6241 effect(KILL cr); 6242 ins_cost(MEMORY_REF_COST); 6243 size(Z_DISP3_SIZE); 6244 format %{ "SGF $dst, $src\t # long/int" %} 6245 opcode(SGF_ZOPC, SGF_ZOPC); 6246 ins_encode(z_form_rt_mem_opt(dst, src)); 6247 ins_pipe(pipe_class_dummy); 6248%} 6249 6250instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 6251 match(Set dst (SubL dst (LoadL src))); 6252 effect(KILL cr); 6253 ins_cost(MEMORY_REF_COST); 6254 size(Z_DISP3_SIZE); 6255 format %{ "SG $dst, $src\t # long" %} 6256 opcode(SG_ZOPC, SG_ZOPC); 6257 ins_encode(z_form_rt_mem_opt(dst, src)); 6258 ins_pipe(pipe_class_dummy); 6259%} 6260 6261// Moved declaration of negL_reg_reg before encode nodes, where it is used. 6262 6263// MUL 6264 6265// Register Multiplication 6266instruct mulI_reg_reg(iRegI dst, iRegI src) %{ 6267 match(Set dst (MulI dst src)); 6268 ins_cost(DEFAULT_COST); 6269 size(4); 6270 format %{ "MSR $dst, $src" %} 6271 opcode(MSR_ZOPC); 6272 ins_encode(z_rreform(dst, src)); 6273 ins_pipe(pipe_class_dummy); 6274%} 6275 6276// Immediate Multiplication 6277instruct mulI_reg_imm16(iRegI dst, immI16 con) %{ 6278 match(Set dst (MulI dst con)); 6279 ins_cost(DEFAULT_COST); 6280 // TODO: s390 port size(FIXED_SIZE); 6281 format %{ "MHI $dst,$con" %} 6282 opcode(MHI_ZOPC); 6283 ins_encode(z_riform_signed(dst,con)); 6284 ins_pipe(pipe_class_dummy); 6285%} 6286 6287// Immediate (32bit) Multiplication 6288instruct mulI_reg_imm32(iRegI dst, immI con) %{ 6289 match(Set dst (MulI dst con)); 6290 ins_cost(DEFAULT_COST); 6291 size(6); 6292 format %{ "MSFI $dst,$con" %} 6293 opcode(MSFI_ZOPC); 6294 ins_encode(z_rilform_signed(dst,con)); 6295 ins_pipe(pipe_class_dummy); 6296%} 6297 6298instruct mulI_Reg_mem(iRegI dst, memory src)%{ 6299 match(Set dst (MulI dst (LoadI src))); 6300 ins_cost(MEMORY_REF_COST); 6301 // TODO: s390 port size(VARIABLE_SIZE); 6302 format %{ "MS(Y) $dst, $src\t # int" %} 6303 opcode(MSY_ZOPC, MS_ZOPC); 6304 ins_encode(z_form_rt_mem_opt(dst, src)); 6305 ins_pipe(pipe_class_dummy); 6306%} 6307 6308// 6309 6310instruct mulL_reg_regI(iRegL dst, iRegI src) %{ 6311 match(Set dst (MulL dst (ConvI2L src))); 6312 ins_cost(DEFAULT_COST); 6313 // TODO: s390 port size(FIXED_SIZE); 6314 format %{ "MSGFR $dst $src\t # long/int" %} 6315 opcode(MSGFR_ZOPC); 6316 ins_encode(z_rreform(dst, src)); 6317 ins_pipe(pipe_class_dummy); 6318%} 6319 6320instruct mulL_reg_reg(iRegL dst, iRegL src) %{ 6321 match(Set dst (MulL dst src)); 6322 ins_cost(DEFAULT_COST); 6323 size(4); 6324 format %{ "MSGR $dst $src\t # long" %} 6325 opcode(MSGR_ZOPC); 6326 ins_encode(z_rreform(dst, src)); 6327 ins_pipe(pipe_class_dummy); 6328%} 6329 6330// Immediate Multiplication 6331instruct mulL_reg_imm16(iRegL dst, immL16 src) %{ 6332 match(Set dst (MulL dst src)); 6333 ins_cost(DEFAULT_COST); 6334 // TODO: s390 port size(FIXED_SIZE); 6335 format %{ "MGHI $dst,$src\t # long" %} 6336 opcode(MGHI_ZOPC); 6337 ins_encode(z_riform_signed(dst, src)); 6338 ins_pipe(pipe_class_dummy); 6339%} 6340 6341// Immediate (32bit) Multiplication 6342instruct mulL_reg_imm32(iRegL dst, immL32 con) %{ 6343 match(Set dst (MulL dst con)); 6344 ins_cost(DEFAULT_COST); 6345 size(6); 6346 format %{ "MSGFI $dst,$con" %} 6347 opcode(MSGFI_ZOPC); 6348 ins_encode(z_rilform_signed(dst,con)); 6349 ins_pipe(pipe_class_dummy); 6350%} 6351 6352instruct mulL_Reg_memI(iRegL dst, memory src)%{ 6353 match(Set dst (MulL dst (ConvI2L (LoadI src)))); 6354 ins_cost(MEMORY_REF_COST); 6355 size(Z_DISP3_SIZE); 6356 format %{ "MSGF $dst, $src\t # long" %} 6357 opcode(MSGF_ZOPC, MSGF_ZOPC); 6358 ins_encode(z_form_rt_mem_opt(dst, src)); 6359 ins_pipe(pipe_class_dummy); 6360%} 6361 6362instruct mulL_Reg_mem(iRegL dst, memory src)%{ 6363 match(Set dst (MulL dst (LoadL src))); 6364 ins_cost(MEMORY_REF_COST); 6365 size(Z_DISP3_SIZE); 6366 format %{ "MSG $dst, $src\t # long" %} 6367 opcode(MSG_ZOPC, MSG_ZOPC); 6368 ins_encode(z_form_rt_mem_opt(dst, src)); 6369 ins_pipe(pipe_class_dummy); 6370%} 6371 6372instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{ 6373 match(Set Rdst (MulHiL Rsrc1 Rsrc2)); 6374 effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr); 6375 ins_cost(7*DEFAULT_COST); 6376 // TODO: s390 port size(VARIABLE_SIZE); 6377 format %{ "MulHiL $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %} 6378 ins_encode%{ 6379 Register dst = $Rdst$$Register; 6380 Register src1 = $Rsrc1$$Register; 6381 Register src2 = $Rsrc2$$Register; 6382 Register tmp1 = $Rtmp1$$Register; 6383 Register tmp2 = $Rdst$$Register; 6384 // z/Architecture has only unsigned multiply (64 * 64 -> 128). 6385 // implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63)) 6386 __ z_srag(tmp2, src1, 63); // a>>63 6387 __ z_srag(tmp1, src2, 63); // b>>63 6388 __ z_ngr(tmp2, src2); // b & (a>>63) 6389 __ z_ngr(tmp1, src1); // a & (b>>63) 6390 __ z_agr(tmp1, tmp2); // ((a & (b>>63)) + (b & (a>>63))) 6391 __ z_mlgr(dst, src2); // tricky: 128-bit product is written to even/odd pair (dst,src1), 6392 // multiplicand is taken from oddReg (src1), multiplier in src2. 6393 __ z_sgr(dst, tmp1); 6394 %} 6395 ins_pipe(pipe_class_dummy); 6396%} 6397 6398// DIV 6399 6400// Integer DIVMOD with Register, both quotient and mod results 6401instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{ 6402 match(DivModI dst1src1 src2); 6403 effect(KILL cr); 6404 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6405 size((VM_Version::has_CompareBranch() ? 24 : 26)); 6406 format %{ "DIVMODI ($dst1src1, $dst2) $src2" %} 6407 ins_encode %{ 6408 Register d1s1 = $dst1src1$$Register; 6409 Register d2 = $dst2$$Register; 6410 Register s2 = $src2$$Register; 6411 6412 assert_different_registers(d1s1, s2); 6413 6414 Label do_div, done_div; 6415 if (VM_Version::has_CompareBranch()) { 6416 __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div); 6417 } else { 6418 __ z_chi(s2, -1); 6419 __ z_brne(do_div); 6420 } 6421 __ z_lcr(d1s1, d1s1); 6422 __ clear_reg(d2, false, false); 6423 __ z_bru(done_div); 6424 __ bind(do_div); 6425 __ z_lgfr(d1s1, d1s1); 6426 __ z_dsgfr(d2, s2); 6427 __ bind(done_div); 6428 %} 6429 ins_pipe(pipe_class_dummy); 6430%} 6431 6432 6433// Register Division 6434instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{ 6435 match(Set dst (DivI src1 src2)); 6436 effect(KILL tmp, KILL cr); 6437 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6438 size((VM_Version::has_CompareBranch() ? 20 : 22)); 6439 format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %} 6440 ins_encode %{ 6441 Register a = $src1$$Register; 6442 Register b = $src2$$Register; 6443 Register t = $dst$$Register; 6444 6445 assert_different_registers(t, b); 6446 6447 Label do_div, done_div; 6448 if (VM_Version::has_CompareBranch()) { 6449 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div); 6450 } else { 6451 __ z_chi(b, -1); 6452 __ z_brne(do_div); 6453 } 6454 __ z_lcr(t, a); 6455 __ z_bru(done_div); 6456 __ bind(do_div); 6457 __ z_lgfr(t, a); 6458 __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b); 6459 __ bind(done_div); 6460 %} 6461 ins_pipe(pipe_class_dummy); 6462%} 6463 6464// Immediate Division 6465instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{ 6466 match(Set dst (DivI src1 src2)); 6467 effect(KILL tmp, KILL cr); // R0 is killed, too. 6468 ins_cost(2 * DEFAULT_COST); 6469 // TODO: s390 port size(VARIABLE_SIZE); 6470 format %{ "DIV_const $dst,$src1,$src2" %} 6471 ins_encode %{ 6472 // No sign extension of Rdividend needed here. 6473 if ($src2$$constant != -1) { 6474 __ z_lghi(Z_R0_scratch, $src2$$constant); 6475 __ z_lgfr($dst$$Register, $src1$$Register); 6476 __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); 6477 } else { 6478 __ z_lcr($dst$$Register, $src1$$Register); 6479 } 6480 %} 6481 ins_pipe(pipe_class_dummy); 6482%} 6483 6484// Long DIVMOD with Register, both quotient and mod results 6485instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{ 6486 match(DivModL dst1src1 src2); 6487 effect(KILL cr); 6488 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6489 size((VM_Version::has_CompareBranch() ? 22 : 24)); 6490 format %{ "DIVMODL ($dst1src1, $dst2) $src2" %} 6491 ins_encode %{ 6492 Register d1s1 = $dst1src1$$Register; 6493 Register d2 = $dst2$$Register; 6494 Register s2 = $src2$$Register; 6495 6496 Label do_div, done_div; 6497 if (VM_Version::has_CompareBranch()) { 6498 __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div); 6499 } else { 6500 __ z_cghi(s2, -1); 6501 __ z_brne(do_div); 6502 } 6503 __ z_lcgr(d1s1, d1s1); 6504 // indicate unused result 6505 (void) __ clear_reg(d2, true, false); 6506 __ z_bru(done_div); 6507 __ bind(do_div); 6508 __ z_dsgr(d2, s2); 6509 __ bind(done_div); 6510 %} 6511 ins_pipe(pipe_class_dummy); 6512%} 6513 6514// Register Long Division 6515instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{ 6516 match(Set dst (DivL dst src)); 6517 effect(KILL tmp, KILL cr); 6518 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6519 size((VM_Version::has_CompareBranch() ? 18 : 20)); 6520 format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %} 6521 ins_encode %{ 6522 Register b = $src$$Register; 6523 Register t = $dst$$Register; 6524 6525 Label done_div; 6526 __ z_lcgr(t, t); // Does no harm. divisor is in other register. 6527 if (VM_Version::has_CompareBranch()) { 6528 __ z_cgij(b, -1, Assembler::bcondEqual, done_div); 6529 } else { 6530 __ z_cghi(b, -1); 6531 __ z_bre(done_div); 6532 } 6533 __ z_lcgr(t, t); // Restore sign. 6534 __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b); 6535 __ bind(done_div); 6536 %} 6537 ins_pipe(pipe_class_dummy); 6538%} 6539 6540// Immediate Long Division 6541instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{ 6542 match(Set dst (DivL src1 src2)); 6543 effect(KILL tmp, KILL cr); // R0 is killed, too. 6544 ins_cost(2 * DEFAULT_COST); 6545 // TODO: s390 port size(VARIABLE_SIZE); 6546 format %{ "DIVG_const $dst,$src1,$src2\t # long" %} 6547 ins_encode %{ 6548 if ($src2$$constant != -1) { 6549 __ z_lghi(Z_R0_scratch, $src2$$constant); 6550 __ lgr_if_needed($dst$$Register, $src1$$Register); 6551 __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch); 6552 } else { 6553 __ z_lcgr($dst$$Register, $src1$$Register); 6554 } 6555 %} 6556 ins_pipe(pipe_class_dummy); 6557%} 6558 6559// REM 6560 6561// Integer Remainder 6562// Register Remainder 6563instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{ 6564 match(Set dst (ModI src1 src2)); 6565 effect(KILL tmp, KILL cr); 6566 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6567 // TODO: s390 port size(VARIABLE_SIZE); 6568 format %{ "MOD_checked $dst,$src1,$src2" %} 6569 ins_encode %{ 6570 Register a = $src1$$Register; 6571 Register b = $src2$$Register; 6572 Register t = $dst$$Register; 6573 assert_different_registers(t->successor(), b); 6574 6575 Label do_div, done_div; 6576 6577 if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) { 6578 (void) __ clear_reg(t, true, false); // Does no harm. Operands are in other regs. 6579 if (VM_Version::has_CompareBranch()) { 6580 __ z_cij(b, -1, Assembler::bcondEqual, done_div); 6581 } else { 6582 __ z_chi(b, -1); 6583 __ z_bre(done_div); 6584 } 6585 __ z_lgfr(t->successor(), a); 6586 __ z_dsgfr(t/* t is even part of a register pair. */, b); 6587 } else { 6588 if (VM_Version::has_CompareBranch()) { 6589 __ z_cij(b, -1, Assembler::bcondNotEqual, do_div); 6590 } else { 6591 __ z_chi(b, -1); 6592 __ z_brne(do_div); 6593 } 6594 __ clear_reg(t, true, false); 6595 __ z_bru(done_div); 6596 __ bind(do_div); 6597 __ z_lgfr(t->successor(), a); 6598 __ z_dsgfr(t/* t is even part of a register pair. */, b); 6599 } 6600 __ bind(done_div); 6601 %} 6602 ins_pipe(pipe_class_dummy); 6603%} 6604 6605// Immediate Remainder 6606instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{ 6607 match(Set dst (ModI src1 src2)); 6608 effect(KILL tmp, KILL cr); // R0 is killed, too. 6609 ins_cost(3 * DEFAULT_COST); 6610 // TODO: s390 port size(VARIABLE_SIZE); 6611 format %{ "MOD_const $dst,src1,$src2" %} 6612 ins_encode %{ 6613 assert_different_registers($dst$$Register, $src1$$Register); 6614 assert_different_registers($dst$$Register->successor(), $src1$$Register); 6615 int divisor = $src2$$constant; 6616 6617 if (divisor != -1) { 6618 __ z_lghi(Z_R0_scratch, divisor); 6619 __ z_lgfr($dst$$Register->successor(), $src1$$Register); 6620 __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. 6621 } else { 6622 __ clear_reg($dst$$Register, true, false); 6623 } 6624 %} 6625 ins_pipe(pipe_class_dummy); 6626%} 6627 6628// Register Long Remainder 6629instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{ 6630 match(Set dst (ModL src1 src2)); 6631 effect(KILL src1, KILL cr); // R0 is killed, too. 6632 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 6633 // TODO: s390 port size(VARIABLE_SIZE); 6634 format %{ "MODG_checked $dst,$src1,$src2" %} 6635 ins_encode %{ 6636 Register a = $src1$$Register; 6637 Register b = $src2$$Register; 6638 Register t = $dst$$Register; 6639 assert(t->successor() == a, "(t,a) is an even-odd pair" ); 6640 6641 Label do_div, done_div; 6642 if (t->encoding() != b->encoding()) { 6643 (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor. 6644 if (VM_Version::has_CompareBranch()) { 6645 __ z_cgij(b, -1, Assembler::bcondEqual, done_div); 6646 } else { 6647 __ z_cghi(b, -1); 6648 __ z_bre(done_div); 6649 } 6650 __ z_dsgr(t, b); 6651 } else { 6652 if (VM_Version::has_CompareBranch()) { 6653 __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div); 6654 } else { 6655 __ z_cghi(b, -1); 6656 __ z_brne(do_div); 6657 } 6658 __ clear_reg(t, true, false); 6659 __ z_bru(done_div); 6660 __ bind(do_div); 6661 __ z_dsgr(t, b); 6662 } 6663 __ bind(done_div); 6664 %} 6665 ins_pipe(pipe_class_dummy); 6666%} 6667 6668// Register Long Remainder 6669instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{ 6670 match(Set dst (ModL src1 src2)); 6671 effect(KILL tmp, KILL cr); // R0 is killed, too. 6672 ins_cost(3 * DEFAULT_COST); 6673 // TODO: s390 port size(VARIABLE_SIZE); 6674 format %{ "MODG_const $dst,src1,$src2\t # long" %} 6675 ins_encode %{ 6676 int divisor = $src2$$constant; 6677 if (divisor != -1) { 6678 __ z_lghi(Z_R0_scratch, divisor); 6679 __ z_lgr($dst$$Register->successor(), $src1$$Register); 6680 __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp. 6681 } else { 6682 __ clear_reg($dst$$Register, true, false); 6683 } 6684 %} 6685 ins_pipe(pipe_class_dummy); 6686%} 6687 6688// SHIFT 6689 6690// Shift left logical 6691 6692// Register Shift Left variable 6693instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{ 6694 match(Set dst (LShiftI src nbits)); 6695 effect(KILL cr); // R1 is killed, too. 6696 ins_cost(3 * DEFAULT_COST); 6697 size(14); 6698 format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %} 6699 ins_encode %{ 6700 __ z_lgr(Z_R1_scratch, $nbits$$Register); 6701 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6702 __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch); 6703 %} 6704 ins_pipe(pipe_class_dummy); 6705%} 6706 6707// Register Shift Left Immediate 6708// Constant shift count is masked in ideal graph already. 6709instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{ 6710 match(Set dst (LShiftI src nbits)); 6711 size(6); 6712 format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %} 6713 ins_encode %{ 6714 int Nbit = $nbits$$constant; 6715 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6716 __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6717 %} 6718 ins_pipe(pipe_class_dummy); 6719%} 6720 6721// Register Shift Left Immediate by 1bit 6722instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{ 6723 match(Set dst (LShiftI src nbits)); 6724 predicate(PreferLAoverADD); 6725 ins_cost(DEFAULT_COST_LOW); 6726 size(4); 6727 format %{ "LA $dst,#0($src,$src)\t # SLL by 1 (int)" %} 6728 ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %} 6729 ins_pipe(pipe_class_dummy); 6730%} 6731 6732// Register Shift Left Long 6733instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{ 6734 match(Set dst (LShiftL src1 nbits)); 6735 size(6); 6736 format %{ "SLLG $dst,$src1,[$nbits]" %} 6737 opcode(SLLG_ZOPC); 6738 ins_encode(z_rsyform_reg_reg(dst, src1, nbits)); 6739 ins_pipe(pipe_class_dummy); 6740%} 6741 6742// Register Shift Left Long Immediate 6743instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{ 6744 match(Set dst (LShiftL src1 nbits)); 6745 size(6); 6746 format %{ "SLLG $dst,$src1,$nbits" %} 6747 opcode(SLLG_ZOPC); 6748 ins_encode(z_rsyform_const(dst, src1, nbits)); 6749 ins_pipe(pipe_class_dummy); 6750%} 6751 6752// Register Shift Left Long Immediate by 1bit 6753instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{ 6754 match(Set dst (LShiftL src1 nbits)); 6755 predicate(PreferLAoverADD); 6756 ins_cost(DEFAULT_COST_LOW); 6757 size(4); 6758 format %{ "LA $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %} 6759 ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %} 6760 ins_pipe(pipe_class_dummy); 6761%} 6762 6763// Shift right arithmetic 6764 6765// Register Arithmetic Shift Right 6766instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 6767 match(Set dst (RShiftI dst src)); 6768 effect(KILL cr); // R1 is killed, too. 6769 ins_cost(3 * DEFAULT_COST); 6770 size(12); 6771 format %{ "SRA $dst,[$src] & 31" %} 6772 ins_encode %{ 6773 __ z_lgr(Z_R1_scratch, $src$$Register); 6774 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6775 __ z_sra($dst$$Register, 0, Z_R1_scratch); 6776 %} 6777 ins_pipe(pipe_class_dummy); 6778%} 6779 6780// Register Arithmetic Shift Right Immediate 6781// Constant shift count is masked in ideal graph already. 6782instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{ 6783 match(Set dst (RShiftI dst src)); 6784 effect(KILL cr); 6785 size(4); 6786 format %{ "SRA $dst,$src" %} 6787 ins_encode %{ 6788 int Nbit = $src$$constant; 6789 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6790 __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6791 %} 6792 ins_pipe(pipe_class_dummy); 6793%} 6794 6795// Register Arithmetic Shift Right Long 6796instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{ 6797 match(Set dst (RShiftL src1 src2)); 6798 effect(KILL cr); 6799 size(6); 6800 format %{ "SRAG $dst,$src1,[$src2]" %} 6801 opcode(SRAG_ZOPC); 6802 ins_encode(z_rsyform_reg_reg(dst, src1, src2)); 6803 ins_pipe(pipe_class_dummy); 6804%} 6805 6806// Register Arithmetic Shift Right Long Immediate 6807instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{ 6808 match(Set dst (RShiftL src1 src2)); 6809 effect(KILL cr); 6810 size(6); 6811 format %{ "SRAG $dst,$src1,$src2" %} 6812 opcode(SRAG_ZOPC); 6813 ins_encode(z_rsyform_const(dst, src1, src2)); 6814 ins_pipe(pipe_class_dummy); 6815%} 6816 6817// Shift right logical 6818 6819// Register Shift Right 6820instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 6821 match(Set dst (URShiftI dst src)); 6822 effect(KILL cr); // R1 is killed, too. 6823 ins_cost(3 * DEFAULT_COST); 6824 size(12); 6825 format %{ "SRL $dst,[$src] & 31" %} 6826 ins_encode %{ 6827 __ z_lgr(Z_R1_scratch, $src$$Register); 6828 __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); 6829 __ z_srl($dst$$Register, 0, Z_R1_scratch); 6830 %} 6831 ins_pipe(pipe_class_dummy); 6832%} 6833 6834// Register Shift Right Immediate 6835// Constant shift count is masked in ideal graph already. 6836instruct srlI_reg_imm(iRegI dst, immI src) %{ 6837 match(Set dst (URShiftI dst src)); 6838 size(4); 6839 format %{ "SRL $dst,$src" %} 6840 ins_encode %{ 6841 int Nbit = $src$$constant; 6842 assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); 6843 __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); 6844 %} 6845 ins_pipe(pipe_class_dummy); 6846%} 6847 6848// Register Shift Right Long 6849instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 6850 match(Set dst (URShiftL src1 src2)); 6851 size(6); 6852 format %{ "SRLG $dst,$src1,[$src2]" %} 6853 opcode(SRLG_ZOPC); 6854 ins_encode(z_rsyform_reg_reg(dst, src1, src2)); 6855 ins_pipe(pipe_class_dummy); 6856%} 6857 6858// Register Shift Right Long Immediate 6859instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{ 6860 match(Set dst (URShiftL src1 src2)); 6861 size(6); 6862 format %{ "SRLG $dst,$src1,$src2" %} 6863 opcode(SRLG_ZOPC); 6864 ins_encode(z_rsyform_const(dst, src1, src2)); 6865 ins_pipe(pipe_class_dummy); 6866%} 6867 6868// Register Shift Right Immediate with a CastP2X 6869instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{ 6870 match(Set dst (URShiftL (CastP2X src1) src2)); 6871 size(6); 6872 format %{ "SRLG $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %} 6873 opcode(SRLG_ZOPC); 6874 ins_encode(z_rsyform_const(dst, src1, src2)); 6875 ins_pipe(pipe_class_dummy); 6876%} 6877 6878//----------Rotate Instructions------------------------------------------------ 6879 6880// Rotate left 32bit. 6881instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{ 6882 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 6883 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 6884 size(6); 6885 format %{ "RLL $dst,$src,$lshift\t # ROTL32" %} 6886 opcode(RLL_ZOPC); 6887 ins_encode(z_rsyform_const(dst, src, lshift)); 6888 ins_pipe(pipe_class_dummy); 6889%} 6890 6891// Rotate left 64bit. 6892instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{ 6893 match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift))); 6894 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 6895 size(6); 6896 format %{ "RLLG $dst,$src,$lshift\t # ROTL64" %} 6897 opcode(RLLG_ZOPC); 6898 ins_encode(z_rsyform_const(dst, src, lshift)); 6899 ins_pipe(pipe_class_dummy); 6900%} 6901 6902// Rotate right 32bit. 6903instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{ 6904 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 6905 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 6906 // TODO: s390 port size(FIXED_SIZE); 6907 format %{ "RLL $dst,$src,$rshift\t # ROTR32" %} 6908 opcode(RLL_ZOPC); 6909 ins_encode(z_rsyform_const(dst, src, rshift)); 6910 ins_pipe(pipe_class_dummy); 6911%} 6912 6913// Rotate right 64bit. 6914instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{ 6915 match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift))); 6916 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); 6917 // TODO: s390 port size(FIXED_SIZE); 6918 format %{ "RLLG $dst,$src,$rshift\t # ROTR64" %} 6919 opcode(RLLG_ZOPC); 6920 ins_encode(z_rsyform_const(dst, src, rshift)); 6921 ins_pipe(pipe_class_dummy); 6922%} 6923 6924 6925//----------Overflow Math Instructions----------------------------------------- 6926 6927instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 6928 match(Set cr (OverflowAddI op1 op2)); 6929 effect(DEF cr, USE op1, USE op2); 6930 // TODO: s390 port size(FIXED_SIZE); 6931 format %{ "AR $op1,$op2\t # overflow check int" %} 6932 ins_encode %{ 6933 __ z_lr(Z_R0_scratch, $op1$$Register); 6934 __ z_ar(Z_R0_scratch, $op2$$Register); 6935 %} 6936 ins_pipe(pipe_class_dummy); 6937%} 6938 6939instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 6940 match(Set cr (OverflowAddI op1 op2)); 6941 effect(DEF cr, USE op1, USE op2); 6942 // TODO: s390 port size(VARIABLE_SIZE); 6943 format %{ "AR $op1,$op2\t # overflow check int" %} 6944 ins_encode %{ 6945 __ load_const_optimized(Z_R0_scratch, $op2$$constant); 6946 __ z_ar(Z_R0_scratch, $op1$$Register); 6947 %} 6948 ins_pipe(pipe_class_dummy); 6949%} 6950 6951instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 6952 match(Set cr (OverflowAddL op1 op2)); 6953 effect(DEF cr, USE op1, USE op2); 6954 // TODO: s390 port size(FIXED_SIZE); 6955 format %{ "AGR $op1,$op2\t # overflow check long" %} 6956 ins_encode %{ 6957 __ z_lgr(Z_R0_scratch, $op1$$Register); 6958 __ z_agr(Z_R0_scratch, $op2$$Register); 6959 %} 6960 ins_pipe(pipe_class_dummy); 6961%} 6962 6963instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{ 6964 match(Set cr (OverflowAddL op1 op2)); 6965 effect(DEF cr, USE op1, USE op2); 6966 // TODO: s390 port size(VARIABLE_SIZE); 6967 format %{ "AGR $op1,$op2\t # overflow check long" %} 6968 ins_encode %{ 6969 __ load_const_optimized(Z_R0_scratch, $op2$$constant); 6970 __ z_agr(Z_R0_scratch, $op1$$Register); 6971 %} 6972 ins_pipe(pipe_class_dummy); 6973%} 6974 6975instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 6976 match(Set cr (OverflowSubI op1 op2)); 6977 effect(DEF cr, USE op1, USE op2); 6978 // TODO: s390 port size(FIXED_SIZE); 6979 format %{ "SR $op1,$op2\t # overflow check int" %} 6980 ins_encode %{ 6981 __ z_lr(Z_R0_scratch, $op1$$Register); 6982 __ z_sr(Z_R0_scratch, $op2$$Register); 6983 %} 6984 ins_pipe(pipe_class_dummy); 6985%} 6986 6987instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 6988 match(Set cr (OverflowSubI op1 op2)); 6989 effect(DEF cr, USE op1, USE op2); 6990 // TODO: s390 port size(VARIABLE_SIZE); 6991 format %{ "SR $op1,$op2\t # overflow check int" %} 6992 ins_encode %{ 6993 __ load_const_optimized(Z_R1_scratch, $op2$$constant); 6994 __ z_lr(Z_R0_scratch, $op1$$Register); 6995 __ z_sr(Z_R0_scratch, Z_R1_scratch); 6996 %} 6997 ins_pipe(pipe_class_dummy); 6998%} 6999 7000instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 7001 match(Set cr (OverflowSubL op1 op2)); 7002 effect(DEF cr, USE op1, USE op2); 7003 // TODO: s390 port size(FIXED_SIZE); 7004 format %{ "SGR $op1,$op2\t # overflow check long" %} 7005 ins_encode %{ 7006 __ z_lgr(Z_R0_scratch, $op1$$Register); 7007 __ z_sgr(Z_R0_scratch, $op2$$Register); 7008 %} 7009 ins_pipe(pipe_class_dummy); 7010%} 7011 7012instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{ 7013 match(Set cr (OverflowSubL op1 op2)); 7014 effect(DEF cr, USE op1, USE op2); 7015 // TODO: s390 port size(VARIABLE_SIZE); 7016 format %{ "SGR $op1,$op2\t # overflow check long" %} 7017 ins_encode %{ 7018 __ load_const_optimized(Z_R1_scratch, $op2$$constant); 7019 __ z_lgr(Z_R0_scratch, $op1$$Register); 7020 __ z_sgr(Z_R0_scratch, Z_R1_scratch); 7021 %} 7022 ins_pipe(pipe_class_dummy); 7023%} 7024 7025instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{ 7026 match(Set cr (OverflowSubI zero op2)); 7027 effect(DEF cr, USE op2); 7028 format %{ "NEG $op2\t # overflow check int" %} 7029 ins_encode %{ 7030 __ clear_reg(Z_R0_scratch, false, false); 7031 __ z_sr(Z_R0_scratch, $op2$$Register); 7032 %} 7033 ins_pipe(pipe_class_dummy); 7034%} 7035 7036instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{ 7037 match(Set cr (OverflowSubL zero op2)); 7038 effect(DEF cr, USE op2); 7039 format %{ "NEGG $op2\t # overflow check long" %} 7040 ins_encode %{ 7041 __ clear_reg(Z_R0_scratch, true, false); 7042 __ z_sgr(Z_R0_scratch, $op2$$Register); 7043 %} 7044 ins_pipe(pipe_class_dummy); 7045%} 7046 7047// No intrinsics for multiplication, since there is no easy way 7048// to check for overflow. 7049 7050 7051//----------Floating Point Arithmetic Instructions----------------------------- 7052 7053// ADD 7054 7055// Add float single precision 7056instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{ 7057 match(Set dst (AddF dst src)); 7058 effect(KILL cr); 7059 ins_cost(ALU_REG_COST); 7060 size(4); 7061 format %{ "AEBR $dst,$src" %} 7062 opcode(AEBR_ZOPC); 7063 ins_encode(z_rreform(dst, src)); 7064 ins_pipe(pipe_class_dummy); 7065%} 7066 7067instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{ 7068 match(Set dst (AddF dst (LoadF src))); 7069 effect(KILL cr); 7070 ins_cost(ALU_MEMORY_COST); 7071 size(6); 7072 format %{ "AEB $dst,$src\t # floatMemory" %} 7073 opcode(AEB_ZOPC); 7074 ins_encode(z_form_rt_memFP(dst, src)); 7075 ins_pipe(pipe_class_dummy); 7076%} 7077 7078// Add float double precision 7079instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{ 7080 match(Set dst (AddD dst src)); 7081 effect(KILL cr); 7082 ins_cost(ALU_REG_COST); 7083 size(4); 7084 format %{ "ADBR $dst,$src" %} 7085 opcode(ADBR_ZOPC); 7086 ins_encode(z_rreform(dst, src)); 7087 ins_pipe(pipe_class_dummy); 7088%} 7089 7090instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{ 7091 match(Set dst (AddD dst (LoadD src))); 7092 effect(KILL cr); 7093 ins_cost(ALU_MEMORY_COST); 7094 size(6); 7095 format %{ "ADB $dst,$src\t # doubleMemory" %} 7096 opcode(ADB_ZOPC); 7097 ins_encode(z_form_rt_memFP(dst, src)); 7098 ins_pipe(pipe_class_dummy); 7099%} 7100 7101// SUB 7102 7103// Sub float single precision 7104instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{ 7105 match(Set dst (SubF dst src)); 7106 effect(KILL cr); 7107 ins_cost(ALU_REG_COST); 7108 size(4); 7109 format %{ "SEBR $dst,$src" %} 7110 opcode(SEBR_ZOPC); 7111 ins_encode(z_rreform(dst, src)); 7112 ins_pipe(pipe_class_dummy); 7113%} 7114 7115instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{ 7116 match(Set dst (SubF dst (LoadF src))); 7117 effect(KILL cr); 7118 ins_cost(ALU_MEMORY_COST); 7119 size(6); 7120 format %{ "SEB $dst,$src\t # floatMemory" %} 7121 opcode(SEB_ZOPC); 7122 ins_encode(z_form_rt_memFP(dst, src)); 7123 ins_pipe(pipe_class_dummy); 7124%} 7125 7126// Sub float double precision 7127instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{ 7128 match(Set dst (SubD dst src)); 7129 effect(KILL cr); 7130 ins_cost(ALU_REG_COST); 7131 size(4); 7132 format %{ "SDBR $dst,$src" %} 7133 opcode(SDBR_ZOPC); 7134 ins_encode(z_rreform(dst, src)); 7135 ins_pipe(pipe_class_dummy); 7136%} 7137 7138instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{ 7139 match(Set dst (SubD dst (LoadD src))); 7140 effect(KILL cr); 7141 ins_cost(ALU_MEMORY_COST); 7142 size(6); 7143 format %{ "SDB $dst,$src\t # doubleMemory" %} 7144 opcode(SDB_ZOPC); 7145 ins_encode(z_form_rt_memFP(dst, src)); 7146 ins_pipe(pipe_class_dummy); 7147%} 7148 7149// MUL 7150 7151// Mul float single precision 7152instruct mulF_reg_reg(regF dst, regF src) %{ 7153 match(Set dst (MulF dst src)); 7154 // CC unchanged by MUL. 7155 ins_cost(ALU_REG_COST); 7156 size(4); 7157 format %{ "MEEBR $dst,$src" %} 7158 opcode(MEEBR_ZOPC); 7159 ins_encode(z_rreform(dst, src)); 7160 ins_pipe(pipe_class_dummy); 7161%} 7162 7163instruct mulF_reg_mem(regF dst, memoryRX src)%{ 7164 match(Set dst (MulF dst (LoadF src))); 7165 // CC unchanged by MUL. 7166 ins_cost(ALU_MEMORY_COST); 7167 size(6); 7168 format %{ "MEEB $dst,$src\t # floatMemory" %} 7169 opcode(MEEB_ZOPC); 7170 ins_encode(z_form_rt_memFP(dst, src)); 7171 ins_pipe(pipe_class_dummy); 7172%} 7173 7174// Mul float double precision 7175instruct mulD_reg_reg(regD dst, regD src) %{ 7176 match(Set dst (MulD dst src)); 7177 // CC unchanged by MUL. 7178 ins_cost(ALU_REG_COST); 7179 size(4); 7180 format %{ "MDBR $dst,$src" %} 7181 opcode(MDBR_ZOPC); 7182 ins_encode(z_rreform(dst, src)); 7183 ins_pipe(pipe_class_dummy); 7184%} 7185 7186instruct mulD_reg_mem(regD dst, memoryRX src)%{ 7187 match(Set dst (MulD dst (LoadD src))); 7188 // CC unchanged by MUL. 7189 ins_cost(ALU_MEMORY_COST); 7190 size(6); 7191 format %{ "MDB $dst,$src\t # doubleMemory" %} 7192 opcode(MDB_ZOPC); 7193 ins_encode(z_form_rt_memFP(dst, src)); 7194 ins_pipe(pipe_class_dummy); 7195%} 7196 7197// Multiply-Accumulate 7198// src1 * src2 + dst 7199instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{ 7200 match(Set dst (FmaF dst (Binary src1 src2))); 7201 // CC unchanged by MUL-ADD. 7202 ins_cost(ALU_REG_COST); 7203 size(4); 7204 format %{ "MAEBR $dst, $src1, $src2" %} 7205 ins_encode %{ 7206 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7207 %} 7208 ins_pipe(pipe_class_dummy); 7209%} 7210 7211// src1 * src2 + dst 7212instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{ 7213 match(Set dst (FmaD dst (Binary src1 src2))); 7214 // CC unchanged by MUL-ADD. 7215 ins_cost(ALU_REG_COST); 7216 size(4); 7217 format %{ "MADBR $dst, $src1, $src2" %} 7218 ins_encode %{ 7219 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7220 %} 7221 ins_pipe(pipe_class_dummy); 7222%} 7223 7224// src1 * src2 - dst 7225instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{ 7226 match(Set dst (FmaF (NegF dst) (Binary src1 src2))); 7227 // CC unchanged by MUL-SUB. 7228 ins_cost(ALU_REG_COST); 7229 size(4); 7230 format %{ "MSEBR $dst, $src1, $src2" %} 7231 ins_encode %{ 7232 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7233 %} 7234 ins_pipe(pipe_class_dummy); 7235%} 7236 7237// src1 * src2 - dst 7238instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{ 7239 match(Set dst (FmaD (NegD dst) (Binary src1 src2))); 7240 // CC unchanged by MUL-SUB. 7241 ins_cost(ALU_REG_COST); 7242 size(4); 7243 format %{ "MSDBR $dst, $src1, $src2" %} 7244 ins_encode %{ 7245 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 7246 %} 7247 ins_pipe(pipe_class_dummy); 7248%} 7249 7250// src1 * src2 + dst 7251instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{ 7252 match(Set dst (FmaF dst (Binary src1 (LoadF src2)))); 7253 // CC unchanged by MUL-ADD. 7254 ins_cost(ALU_MEMORY_COST); 7255 size(6); 7256 format %{ "MAEB $dst, $src1, $src2" %} 7257 ins_encode %{ 7258 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister, 7259 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7260 %} 7261 ins_pipe(pipe_class_dummy); 7262%} 7263 7264// src1 * src2 + dst 7265instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{ 7266 match(Set dst (FmaD dst (Binary src1 (LoadD src2)))); 7267 // CC unchanged by MUL-ADD. 7268 ins_cost(ALU_MEMORY_COST); 7269 size(6); 7270 format %{ "MADB $dst, $src1, $src2" %} 7271 ins_encode %{ 7272 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister, 7273 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7274 %} 7275 ins_pipe(pipe_class_dummy); 7276%} 7277 7278// src1 * src2 - dst 7279instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{ 7280 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2)))); 7281 // CC unchanged by MUL-SUB. 7282 ins_cost(ALU_MEMORY_COST); 7283 size(6); 7284 format %{ "MSEB $dst, $src1, $src2" %} 7285 ins_encode %{ 7286 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister, 7287 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7288 %} 7289 ins_pipe(pipe_class_dummy); 7290%} 7291 7292// src1 * src2 - dst 7293instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{ 7294 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2)))); 7295 // CC unchanged by MUL-SUB. 7296 ins_cost(ALU_MEMORY_COST); 7297 size(6); 7298 format %{ "MSDB $dst, $src1, $src2" %} 7299 ins_encode %{ 7300 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister, 7301 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp)); 7302 %} 7303 ins_pipe(pipe_class_dummy); 7304%} 7305 7306// src1 * src2 + dst 7307instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{ 7308 match(Set dst (FmaF dst (Binary (LoadF src1) src2))); 7309 // CC unchanged by MUL-ADD. 7310 ins_cost(ALU_MEMORY_COST); 7311 size(6); 7312 format %{ "MAEB $dst, $src1, $src2" %} 7313 ins_encode %{ 7314 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister, 7315 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7316 %} 7317 ins_pipe(pipe_class_dummy); 7318%} 7319 7320// src1 * src2 + dst 7321instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{ 7322 match(Set dst (FmaD dst (Binary (LoadD src1) src2))); 7323 // CC unchanged by MUL-ADD. 7324 ins_cost(ALU_MEMORY_COST); 7325 size(6); 7326 format %{ "MADB $dst, $src1, $src2" %} 7327 ins_encode %{ 7328 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister, 7329 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7330 %} 7331 ins_pipe(pipe_class_dummy); 7332%} 7333 7334// src1 * src2 - dst 7335instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{ 7336 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2))); 7337 // CC unchanged by MUL-SUB. 7338 ins_cost(ALU_MEMORY_COST); 7339 size(6); 7340 format %{ "MSEB $dst, $src1, $src2" %} 7341 ins_encode %{ 7342 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister, 7343 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7344 %} 7345 ins_pipe(pipe_class_dummy); 7346%} 7347 7348// src1 * src2 - dst 7349instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{ 7350 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2))); 7351 // CC unchanged by MUL-SUB. 7352 ins_cost(ALU_MEMORY_COST); 7353 size(6); 7354 format %{ "MSDB $dst, $src1, $src2" %} 7355 ins_encode %{ 7356 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister, 7357 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp)); 7358 %} 7359 ins_pipe(pipe_class_dummy); 7360%} 7361 7362// DIV 7363 7364// Div float single precision 7365instruct divF_reg_reg(regF dst, regF src) %{ 7366 match(Set dst (DivF dst src)); 7367 // CC unchanged by DIV. 7368 ins_cost(ALU_REG_COST); 7369 size(4); 7370 format %{ "DEBR $dst,$src" %} 7371 opcode(DEBR_ZOPC); 7372 ins_encode(z_rreform(dst, src)); 7373 ins_pipe(pipe_class_dummy); 7374%} 7375 7376instruct divF_reg_mem(regF dst, memoryRX src)%{ 7377 match(Set dst (DivF dst (LoadF src))); 7378 // CC unchanged by DIV. 7379 ins_cost(ALU_MEMORY_COST); 7380 size(6); 7381 format %{ "DEB $dst,$src\t # floatMemory" %} 7382 opcode(DEB_ZOPC); 7383 ins_encode(z_form_rt_memFP(dst, src)); 7384 ins_pipe(pipe_class_dummy); 7385%} 7386 7387// Div float double precision 7388instruct divD_reg_reg(regD dst, regD src) %{ 7389 match(Set dst (DivD dst src)); 7390 // CC unchanged by DIV. 7391 ins_cost(ALU_REG_COST); 7392 size(4); 7393 format %{ "DDBR $dst,$src" %} 7394 opcode(DDBR_ZOPC); 7395 ins_encode(z_rreform(dst, src)); 7396 ins_pipe(pipe_class_dummy); 7397%} 7398 7399instruct divD_reg_mem(regD dst, memoryRX src)%{ 7400 match(Set dst (DivD dst (LoadD src))); 7401 // CC unchanged by DIV. 7402 ins_cost(ALU_MEMORY_COST); 7403 size(6); 7404 format %{ "DDB $dst,$src\t # doubleMemory" %} 7405 opcode(DDB_ZOPC); 7406 ins_encode(z_form_rt_memFP(dst, src)); 7407 ins_pipe(pipe_class_dummy); 7408%} 7409 7410// ABS 7411 7412// Absolute float single precision 7413instruct absF_reg(regF dst, regF src, flagsReg cr) %{ 7414 match(Set dst (AbsF src)); 7415 effect(KILL cr); 7416 size(4); 7417 format %{ "LPEBR $dst,$src\t float" %} 7418 opcode(LPEBR_ZOPC); 7419 ins_encode(z_rreform(dst, src)); 7420 ins_pipe(pipe_class_dummy); 7421%} 7422 7423// Absolute float double precision 7424instruct absD_reg(regD dst, regD src, flagsReg cr) %{ 7425 match(Set dst (AbsD src)); 7426 effect(KILL cr); 7427 size(4); 7428 format %{ "LPDBR $dst,$src\t double" %} 7429 opcode(LPDBR_ZOPC); 7430 ins_encode(z_rreform(dst, src)); 7431 ins_pipe(pipe_class_dummy); 7432%} 7433 7434// NEG(ABS) 7435 7436// Negative absolute float single precision 7437instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{ 7438 match(Set dst (NegF (AbsF src))); 7439 effect(KILL cr); 7440 size(4); 7441 format %{ "LNEBR $dst,$src\t float" %} 7442 opcode(LNEBR_ZOPC); 7443 ins_encode(z_rreform(dst, src)); 7444 ins_pipe(pipe_class_dummy); 7445%} 7446 7447// Negative absolute float double precision 7448instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{ 7449 match(Set dst (NegD (AbsD src))); 7450 effect(KILL cr); 7451 size(4); 7452 format %{ "LNDBR $dst,$src\t double" %} 7453 opcode(LNDBR_ZOPC); 7454 ins_encode(z_rreform(dst, src)); 7455 ins_pipe(pipe_class_dummy); 7456%} 7457 7458// NEG 7459 7460instruct negF_reg(regF dst, regF src, flagsReg cr) %{ 7461 match(Set dst (NegF src)); 7462 effect(KILL cr); 7463 size(4); 7464 format %{ "NegF $dst,$src\t float" %} 7465 ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %} 7466 ins_pipe(pipe_class_dummy); 7467%} 7468 7469instruct negD_reg(regD dst, regD src, flagsReg cr) %{ 7470 match(Set dst (NegD src)); 7471 effect(KILL cr); 7472 size(4); 7473 format %{ "NegD $dst,$src\t double" %} 7474 ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %} 7475 ins_pipe(pipe_class_dummy); 7476%} 7477 7478// SQRT 7479 7480// Sqrt float precision 7481instruct sqrtF_reg(regF dst, regF src) %{ 7482 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7483 // CC remains unchanged. 7484 ins_cost(ALU_REG_COST); 7485 size(4); 7486 format %{ "SQEBR $dst,$src" %} 7487 opcode(SQEBR_ZOPC); 7488 ins_encode(z_rreform(dst, src)); 7489 ins_pipe(pipe_class_dummy); 7490%} 7491 7492// Sqrt double precision 7493instruct sqrtD_reg(regD dst, regD src) %{ 7494 match(Set dst (SqrtD src)); 7495 // CC remains unchanged. 7496 ins_cost(ALU_REG_COST); 7497 size(4); 7498 format %{ "SQDBR $dst,$src" %} 7499 opcode(SQDBR_ZOPC); 7500 ins_encode(z_rreform(dst, src)); 7501 ins_pipe(pipe_class_dummy); 7502%} 7503 7504instruct sqrtF_mem(regF dst, memoryRX src) %{ 7505 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7506 // CC remains unchanged. 7507 ins_cost(ALU_MEMORY_COST); 7508 size(6); 7509 format %{ "SQEB $dst,$src\t # floatMemory" %} 7510 opcode(SQEB_ZOPC); 7511 ins_encode(z_form_rt_memFP(dst, src)); 7512 ins_pipe(pipe_class_dummy); 7513%} 7514 7515instruct sqrtD_mem(regD dst, memoryRX src) %{ 7516 match(Set dst (SqrtD src)); 7517 // CC remains unchanged. 7518 ins_cost(ALU_MEMORY_COST); 7519 // TODO: s390 port size(FIXED_SIZE); 7520 format %{ "SQDB $dst,$src\t # doubleMemory" %} 7521 opcode(SQDB_ZOPC); 7522 ins_encode(z_form_rt_memFP(dst, src)); 7523 ins_pipe(pipe_class_dummy); 7524%} 7525 7526//----------Logical Instructions----------------------------------------------- 7527 7528// Register And 7529instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7530 match(Set dst (AndI dst src)); 7531 effect(KILL cr); 7532 ins_cost(DEFAULT_COST_LOW); 7533 size(2); 7534 format %{ "NR $dst,$src\t # int" %} 7535 opcode(NR_ZOPC); 7536 ins_encode(z_rrform(dst, src)); 7537 ins_pipe(pipe_class_dummy); 7538%} 7539 7540instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7541 match(Set dst (AndI dst (LoadI src))); 7542 effect(KILL cr); 7543 ins_cost(MEMORY_REF_COST); 7544 // TODO: s390 port size(VARIABLE_SIZE); 7545 format %{ "N(Y) $dst, $src\t # int" %} 7546 opcode(NY_ZOPC, N_ZOPC); 7547 ins_encode(z_form_rt_mem_opt(dst, src)); 7548 ins_pipe(pipe_class_dummy); 7549%} 7550 7551// Immediate And 7552instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{ 7553 match(Set dst (AndI dst src)); 7554 effect(KILL cr); 7555 ins_cost(DEFAULT_COST_HIGH); 7556 size(6); 7557 format %{ "NILF $dst,$src" %} 7558 opcode(NILF_ZOPC); 7559 ins_encode(z_rilform_unsigned(dst, src)); 7560 ins_pipe(pipe_class_dummy); 7561%} 7562 7563instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{ 7564 match(Set dst (AndI dst src)); 7565 effect(KILL cr); 7566 ins_cost(DEFAULT_COST); 7567 size(4); 7568 format %{ "NILH $dst,$src" %} 7569 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %} 7570 ins_pipe(pipe_class_dummy); 7571%} 7572 7573instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{ 7574 match(Set dst (AndI dst src)); 7575 effect(KILL cr); 7576 ins_cost(DEFAULT_COST); 7577 size(4); 7578 format %{ "NILL $dst,$src" %} 7579 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %} 7580 ins_pipe(pipe_class_dummy); 7581%} 7582 7583// Register And Long 7584instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7585 match(Set dst (AndL dst src)); 7586 effect(KILL cr); 7587 ins_cost(DEFAULT_COST); 7588 size(4); 7589 format %{ "NGR $dst,$src\t # long" %} 7590 opcode(NGR_ZOPC); 7591 ins_encode(z_rreform(dst, src)); 7592 ins_pipe(pipe_class_dummy); 7593%} 7594 7595instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7596 match(Set dst (AndL dst (LoadL src))); 7597 effect(KILL cr); 7598 ins_cost(MEMORY_REF_COST); 7599 size(Z_DISP3_SIZE); 7600 format %{ "NG $dst, $src\t # long" %} 7601 opcode(NG_ZOPC, NG_ZOPC); 7602 ins_encode(z_form_rt_mem_opt(dst, src)); 7603 ins_pipe(pipe_class_dummy); 7604%} 7605 7606instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{ 7607 match(Set dst (AndL dst src)); 7608 effect(KILL cr); 7609 ins_cost(DEFAULT_COST); 7610 size(4); 7611 format %{ "NILL $dst,$src\t # long" %} 7612 ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %} 7613 ins_pipe(pipe_class_dummy); 7614%} 7615 7616instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{ 7617 match(Set dst (AndL dst src)); 7618 effect(KILL cr); 7619 ins_cost(DEFAULT_COST); 7620 size(4); 7621 format %{ "NILH $dst,$src\t # long" %} 7622 ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %} 7623 ins_pipe(pipe_class_dummy); 7624%} 7625 7626instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{ 7627 match(Set dst (AndL dst src)); 7628 effect(KILL cr); 7629 ins_cost(DEFAULT_COST); 7630 size(4); 7631 format %{ "NIHL $dst,$src\t # long" %} 7632 ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %} 7633 ins_pipe(pipe_class_dummy); 7634%} 7635 7636instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{ 7637 match(Set dst (AndL dst src)); 7638 effect(KILL cr); 7639 ins_cost(DEFAULT_COST); 7640 size(4); 7641 format %{ "NIHH $dst,$src\t # long" %} 7642 ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %} 7643 ins_pipe(pipe_class_dummy); 7644%} 7645 7646// OR 7647 7648// Or Instructions 7649// Register Or 7650instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7651 match(Set dst (OrI dst src)); 7652 effect(KILL cr); 7653 size(2); 7654 format %{ "OR $dst,$src" %} 7655 opcode(OR_ZOPC); 7656 ins_encode(z_rrform(dst, src)); 7657 ins_pipe(pipe_class_dummy); 7658%} 7659 7660instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7661 match(Set dst (OrI dst (LoadI src))); 7662 effect(KILL cr); 7663 ins_cost(MEMORY_REF_COST); 7664 // TODO: s390 port size(VARIABLE_SIZE); 7665 format %{ "O(Y) $dst, $src\t # int" %} 7666 opcode(OY_ZOPC, O_ZOPC); 7667 ins_encode(z_form_rt_mem_opt(dst, src)); 7668 ins_pipe(pipe_class_dummy); 7669%} 7670 7671// Immediate Or 7672instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{ 7673 match(Set dst (OrI dst con)); 7674 effect(KILL cr); 7675 size(4); 7676 format %{ "OILL $dst,$con" %} 7677 opcode(OILL_ZOPC); 7678 ins_encode(z_riform_unsigned(dst,con)); 7679 ins_pipe(pipe_class_dummy); 7680%} 7681 7682instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{ 7683 match(Set dst (OrI dst con)); 7684 effect(KILL cr); 7685 ins_cost(DEFAULT_COST_HIGH); 7686 size(6); 7687 format %{ "OILF $dst,$con" %} 7688 opcode(OILF_ZOPC); 7689 ins_encode(z_rilform_unsigned(dst,con)); 7690 ins_pipe(pipe_class_dummy); 7691%} 7692 7693// Register Or Long 7694instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7695 match(Set dst (OrL dst src)); 7696 effect(KILL cr); 7697 ins_cost(DEFAULT_COST); 7698 size(4); 7699 format %{ "OGR $dst,$src\t # long" %} 7700 opcode(OGR_ZOPC); 7701 ins_encode(z_rreform(dst, src)); 7702 ins_pipe(pipe_class_dummy); 7703%} 7704 7705instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7706 match(Set dst (OrL dst (LoadL src))); 7707 effect(KILL cr); 7708 ins_cost(MEMORY_REF_COST); 7709 size(Z_DISP3_SIZE); 7710 format %{ "OG $dst, $src\t # long" %} 7711 opcode(OG_ZOPC, OG_ZOPC); 7712 ins_encode(z_form_rt_mem_opt(dst, src)); 7713 ins_pipe(pipe_class_dummy); 7714%} 7715 7716// Immediate Or long 7717instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{ 7718 match(Set dst (OrL dst con)); 7719 effect(KILL cr); 7720 ins_cost(DEFAULT_COST); 7721 size(4); 7722 format %{ "OILL $dst,$con\t # long" %} 7723 opcode(OILL_ZOPC); 7724 ins_encode(z_riform_unsigned(dst,con)); 7725 ins_pipe(pipe_class_dummy); 7726%} 7727 7728instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{ 7729 match(Set dst (OrI dst con)); 7730 effect(KILL cr); 7731 ins_cost(DEFAULT_COST_HIGH); 7732 // TODO: s390 port size(FIXED_SIZE); 7733 format %{ "OILF $dst,$con\t # long" %} 7734 opcode(OILF_ZOPC); 7735 ins_encode(z_rilform_unsigned(dst,con)); 7736 ins_pipe(pipe_class_dummy); 7737%} 7738 7739// XOR 7740 7741// Register Xor 7742instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7743 match(Set dst (XorI dst src)); 7744 effect(KILL cr); 7745 size(2); 7746 format %{ "XR $dst,$src" %} 7747 opcode(XR_ZOPC); 7748 ins_encode(z_rrform(dst, src)); 7749 ins_pipe(pipe_class_dummy); 7750%} 7751 7752instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{ 7753 match(Set dst (XorI dst (LoadI src))); 7754 effect(KILL cr); 7755 ins_cost(MEMORY_REF_COST); 7756 // TODO: s390 port size(VARIABLE_SIZE); 7757 format %{ "X(Y) $dst, $src\t # int" %} 7758 opcode(XY_ZOPC, X_ZOPC); 7759 ins_encode(z_form_rt_mem_opt(dst, src)); 7760 ins_pipe(pipe_class_dummy); 7761%} 7762 7763// Immediate Xor 7764instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{ 7765 match(Set dst (XorI dst src)); 7766 effect(KILL cr); 7767 ins_cost(DEFAULT_COST_HIGH); 7768 size(6); 7769 format %{ "XILF $dst,$src" %} 7770 opcode(XILF_ZOPC); 7771 ins_encode(z_rilform_unsigned(dst, src)); 7772 ins_pipe(pipe_class_dummy); 7773%} 7774 7775// Register Xor Long 7776instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{ 7777 match(Set dst (XorL dst src)); 7778 effect(KILL cr); 7779 ins_cost(DEFAULT_COST); 7780 size(4); 7781 format %{ "XGR $dst,$src\t # long" %} 7782 opcode(XGR_ZOPC); 7783 ins_encode(z_rreform(dst, src)); 7784 ins_pipe(pipe_class_dummy); 7785%} 7786 7787instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{ 7788 match(Set dst (XorL dst (LoadL src))); 7789 effect(KILL cr); 7790 ins_cost(MEMORY_REF_COST); 7791 size(Z_DISP3_SIZE); 7792 format %{ "XG $dst, $src\t # long" %} 7793 opcode(XG_ZOPC, XG_ZOPC); 7794 ins_encode(z_form_rt_mem_opt(dst, src)); 7795 ins_pipe(pipe_class_dummy); 7796%} 7797 7798// Immediate Xor Long 7799instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{ 7800 match(Set dst (XorL dst con)); 7801 effect(KILL cr); 7802 ins_cost(DEFAULT_COST_HIGH); 7803 size(6); 7804 format %{ "XILF $dst,$con\t # long" %} 7805 opcode(XILF_ZOPC); 7806 ins_encode(z_rilform_unsigned(dst,con)); 7807 ins_pipe(pipe_class_dummy); 7808%} 7809 7810//----------Convert to Boolean------------------------------------------------- 7811 7812// Convert integer to boolean. 7813instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{ 7814 match(Set dst (Conv2B src)); 7815 effect(KILL cr); 7816 ins_cost(3 * DEFAULT_COST); 7817 size(6); 7818 format %{ "convI2B $dst,$src" %} 7819 ins_encode %{ 7820 __ z_lnr($dst$$Register, $src$$Register); // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0 7821 __ z_srl($dst$$Register, 31); // Rdst := sign(Rdest) 7822 %} 7823 ins_pipe(pipe_class_dummy); 7824%} 7825 7826instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{ 7827 match(Set dst (Conv2B src)); 7828 effect(KILL cr); 7829 ins_cost(3 * DEFAULT_COST); 7830 size(10); 7831 format %{ "convP2B $dst,$src" %} 7832 ins_encode %{ 7833 __ z_lngr($dst$$Register, $src$$Register); // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0 7834 __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest) 7835 %} 7836 ins_pipe(pipe_class_dummy); 7837%} 7838 7839instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{ 7840 match(Set dst (CmpLTMask dst src)); 7841 effect(KILL cr); 7842 ins_cost(2 * DEFAULT_COST); 7843 size(18); 7844 format %{ "Set $dst CmpLTMask $dst,$src" %} 7845 ins_encode %{ 7846 // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit. 7847 __ z_lgfr(Z_R0_scratch, $src$$Register); 7848 __ z_lgfr($dst$$Register, $dst$$Register); 7849 __ z_sgr($dst$$Register, Z_R0_scratch); 7850 __ z_srag($dst$$Register, $dst$$Register, 63); 7851 %} 7852 ins_pipe(pipe_class_dummy); 7853%} 7854 7855instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{ 7856 match(Set dst (CmpLTMask dst zero)); 7857 effect(KILL cr); 7858 ins_cost(DEFAULT_COST); 7859 size(4); 7860 format %{ "Set $dst CmpLTMask $dst,$zero" %} 7861 ins_encode %{ __ z_sra($dst$$Register, 31); %} 7862 ins_pipe(pipe_class_dummy); 7863%} 7864 7865 7866//----------Arithmetic Conversion Instructions--------------------------------- 7867// The conversions operations are all Alpha sorted. Please keep it that way! 7868 7869instruct convD2F_reg(regF dst, regD src) %{ 7870 match(Set dst (ConvD2F src)); 7871 // CC remains unchanged. 7872 size(4); 7873 format %{ "LEDBR $dst,$src" %} 7874 opcode(LEDBR_ZOPC); 7875 ins_encode(z_rreform(dst, src)); 7876 ins_pipe(pipe_class_dummy); 7877%} 7878 7879instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{ 7880 match(Set dst (ConvF2I src)); 7881 effect(KILL cr); 7882 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7883 size(16); 7884 format %{ "convF2I $dst,$src" %} 7885 ins_encode %{ 7886 Label done; 7887 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. 7888 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. 7889 __ z_brno(done); // Result is zero if unordered argument. 7890 __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7891 __ bind(done); 7892 %} 7893 ins_pipe(pipe_class_dummy); 7894%} 7895 7896instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{ 7897 match(Set dst (ConvD2I src)); 7898 effect(KILL cr); 7899 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7900 size(16); 7901 format %{ "convD2I $dst,$src" %} 7902 ins_encode %{ 7903 Label done; 7904 __ clear_reg($dst$$Register, false, false); // Initialize with result for unordered: 0. 7905 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. 7906 __ z_brno(done); // Result is zero if unordered argument. 7907 __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7908 __ bind(done); 7909 %} 7910 ins_pipe(pipe_class_dummy); 7911%} 7912 7913instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{ 7914 match(Set dst (ConvF2L src)); 7915 effect(KILL cr); 7916 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7917 size(16); 7918 format %{ "convF2L $dst,$src" %} 7919 ins_encode %{ 7920 Label done; 7921 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. 7922 __ z_cebr($src$$FloatRegister, $src$$FloatRegister); // Round. 7923 __ z_brno(done); // Result is zero if unordered argument. 7924 __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7925 __ bind(done); 7926 %} 7927 ins_pipe(pipe_class_dummy); 7928%} 7929 7930instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{ 7931 match(Set dst (ConvD2L src)); 7932 effect(KILL cr); 7933 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 7934 size(16); 7935 format %{ "convD2L $dst,$src" %} 7936 ins_encode %{ 7937 Label done; 7938 __ clear_reg($dst$$Register, true, false); // Initialize with result for unordered: 0. 7939 __ z_cdbr($src$$FloatRegister, $src$$FloatRegister); // Round. 7940 __ z_brno(done); // Result is zero if unordered argument. 7941 __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero); 7942 __ bind(done); 7943 %} 7944 ins_pipe(pipe_class_dummy); 7945%} 7946 7947instruct convF2D_reg(regD dst, regF src) %{ 7948 match(Set dst (ConvF2D src)); 7949 // CC remains unchanged. 7950 size(4); 7951 format %{ "LDEBR $dst,$src" %} 7952 opcode(LDEBR_ZOPC); 7953 ins_encode(z_rreform(dst, src)); 7954 ins_pipe(pipe_class_dummy); 7955%} 7956 7957instruct convF2D_mem(regD dst, memoryRX src) %{ 7958 match(Set dst (ConvF2D src)); 7959 // CC remains unchanged. 7960 size(6); 7961 format %{ "LDEB $dst,$src" %} 7962 opcode(LDEB_ZOPC); 7963 ins_encode(z_form_rt_memFP(dst, src)); 7964 ins_pipe(pipe_class_dummy); 7965%} 7966 7967instruct convI2D_reg(regD dst, iRegI src) %{ 7968 match(Set dst (ConvI2D src)); 7969 // CC remains unchanged. 7970 ins_cost(DEFAULT_COST); 7971 size(4); 7972 format %{ "CDFBR $dst,$src" %} 7973 opcode(CDFBR_ZOPC); 7974 ins_encode(z_rreform(dst, src)); 7975 ins_pipe(pipe_class_dummy); 7976%} 7977 7978// Optimization that saves up to two memory operations for each conversion. 7979instruct convI2F_ireg(regF dst, iRegI src) %{ 7980 match(Set dst (ConvI2F src)); 7981 // CC remains unchanged. 7982 ins_cost(DEFAULT_COST); 7983 size(4); 7984 format %{ "CEFBR $dst,$src\t # convert int to float" %} 7985 opcode(CEFBR_ZOPC); 7986 ins_encode(z_rreform(dst, src)); 7987 ins_pipe(pipe_class_dummy); 7988%} 7989 7990instruct convI2L_reg(iRegL dst, iRegI src) %{ 7991 match(Set dst (ConvI2L src)); 7992 size(4); 7993 format %{ "LGFR $dst,$src\t # int->long" %} 7994 opcode(LGFR_ZOPC); 7995 ins_encode(z_rreform(dst, src)); 7996 ins_pipe(pipe_class_dummy); 7997%} 7998 7999// Zero-extend convert int to long. 8000instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{ 8001 match(Set dst (AndL (ConvI2L src) mask)); 8002 size(4); 8003 format %{ "LLGFR $dst, $src \t # zero-extend int to long" %} 8004 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %} 8005 ins_pipe(pipe_class_dummy); 8006%} 8007 8008// Zero-extend convert int to long. 8009instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{ 8010 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); 8011 // Uses load_const_optmized, so size can vary. 8012 // TODO: s390 port size(VARIABLE_SIZE); 8013 format %{ "LLGF $dst, $src \t # zero-extend int to long" %} 8014 opcode(LLGF_ZOPC, LLGF_ZOPC); 8015 ins_encode(z_form_rt_mem_opt(dst, src)); 8016 ins_pipe(pipe_class_dummy); 8017%} 8018 8019// Zero-extend long 8020instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{ 8021 match(Set dst (AndL src mask)); 8022 size(4); 8023 format %{ "LLGFR $dst, $src \t # zero-extend long to long" %} 8024 ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %} 8025 ins_pipe(pipe_class_dummy); 8026%} 8027 8028instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{ 8029 match(Set dst (RShiftI (LShiftI src amount) amount)); 8030 size(4); 8031 format %{ "LHR $dst,$src\t short->int" %} 8032 opcode(LHR_ZOPC); 8033 ins_encode(z_rreform(dst, src)); 8034 ins_pipe(pipe_class_dummy); 8035%} 8036 8037instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{ 8038 match(Set dst (RShiftI (LShiftI src amount) amount)); 8039 size(4); 8040 format %{ "LBR $dst,$src\t byte->int" %} 8041 opcode(LBR_ZOPC); 8042 ins_encode(z_rreform(dst, src)); 8043 ins_pipe(pipe_class_dummy); 8044%} 8045 8046instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8047 match(Set dst (MoveF2I src)); 8048 ins_cost(MEMORY_REF_COST); 8049 size(4); 8050 format %{ "L $dst,$src\t # MoveF2I" %} 8051 opcode(L_ZOPC); 8052 ins_encode(z_form_rt_mem(dst, src)); 8053 ins_pipe(pipe_class_dummy); 8054%} 8055 8056// javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII) 8057instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8058 match(Set dst (MoveI2F src)); 8059 ins_cost(MEMORY_REF_COST); 8060 // TODO: s390 port size(FIXED_SIZE); 8061 format %{ "LE $dst,$src\t # MoveI2F" %} 8062 opcode(LE_ZOPC); 8063 ins_encode(z_form_rt_mem(dst, src)); 8064 ins_pipe(pipe_class_dummy); 8065%} 8066 8067instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8068 match(Set dst (MoveD2L src)); 8069 ins_cost(MEMORY_REF_COST); 8070 size(6); 8071 format %{ "LG $src,$dst\t # MoveD2L" %} 8072 opcode(LG_ZOPC); 8073 ins_encode(z_form_rt_mem(dst, src)); 8074 ins_pipe(pipe_class_dummy); 8075%} 8076 8077instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8078 match(Set dst (MoveL2D src)); 8079 ins_cost(MEMORY_REF_COST); 8080 size(4); 8081 format %{ "LD $dst,$src\t # MoveL2D" %} 8082 opcode(LD_ZOPC); 8083 ins_encode(z_form_rt_mem(dst, src)); 8084 ins_pipe(pipe_class_dummy); 8085%} 8086 8087instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8088 match(Set dst (MoveI2F src)); 8089 ins_cost(MEMORY_REF_COST); 8090 size(4); 8091 format %{ "ST $src,$dst\t # MoveI2F" %} 8092 opcode(ST_ZOPC); 8093 ins_encode(z_form_rt_mem(src, dst)); 8094 ins_pipe(pipe_class_dummy); 8095%} 8096 8097instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8098 match(Set dst (MoveD2L src)); 8099 effect(DEF dst, USE src); 8100 ins_cost(MEMORY_REF_COST); 8101 size(4); 8102 format %{ "STD $src,$dst\t # MoveD2L" %} 8103 opcode(STD_ZOPC); 8104 ins_encode(z_form_rt_mem(src,dst)); 8105 ins_pipe(pipe_class_dummy); 8106%} 8107 8108instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8109 match(Set dst (MoveL2D src)); 8110 ins_cost(MEMORY_REF_COST); 8111 size(6); 8112 format %{ "STG $src,$dst\t # MoveL2D" %} 8113 opcode(STG_ZOPC); 8114 ins_encode(z_form_rt_mem(src,dst)); 8115 ins_pipe(pipe_class_dummy); 8116%} 8117 8118instruct convL2F_reg(regF dst, iRegL src) %{ 8119 match(Set dst (ConvL2F src)); 8120 // CC remains unchanged. 8121 ins_cost(DEFAULT_COST); 8122 size(4); 8123 format %{ "CEGBR $dst,$src" %} 8124 opcode(CEGBR_ZOPC); 8125 ins_encode(z_rreform(dst, src)); 8126 ins_pipe(pipe_class_dummy); 8127%} 8128 8129instruct convL2D_reg(regD dst, iRegL src) %{ 8130 match(Set dst (ConvL2D src)); 8131 // CC remains unchanged. 8132 ins_cost(DEFAULT_COST); 8133 size(4); 8134 format %{ "CDGBR $dst,$src" %} 8135 opcode(CDGBR_ZOPC); 8136 ins_encode(z_rreform(dst, src)); 8137 ins_pipe(pipe_class_dummy); 8138%} 8139 8140instruct convL2I_reg(iRegI dst, iRegL src) %{ 8141 match(Set dst (ConvL2I src)); 8142 // TODO: s390 port size(VARIABLE_SIZE); 8143 format %{ "LR $dst,$src\t # long->int (if needed)" %} 8144 ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %} 8145 ins_pipe(pipe_class_dummy); 8146%} 8147 8148// Register Shift Right Immediate 8149instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{ 8150 match(Set dst (ConvL2I (RShiftL src cnt))); 8151 effect(KILL cr); 8152 size(6); 8153 format %{ "SRAG $dst,$src,$cnt" %} 8154 opcode(SRAG_ZOPC); 8155 ins_encode(z_rsyform_const(dst, src, cnt)); 8156 ins_pipe(pipe_class_dummy); 8157%} 8158 8159//----------TRAP based zero checks and range checks---------------------------- 8160 8161// SIGTRAP based implicit range checks in compiled code. 8162// A range check in the ideal world has one of the following shapes: 8163// - (If le (CmpU length index)), (IfTrue throw exception) 8164// - (If lt (CmpU index length)), (IfFalse throw exception) 8165// 8166// Match range check 'If le (CmpU length index)' 8167instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{ 8168 match(If cmp (CmpU length index)); 8169 effect(USE labl); 8170 predicate(TrapBasedRangeChecks && 8171 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 8172 PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS && 8173 Matcher::branches_to_uncommon_trap(_leaf)); 8174 ins_cost(1); 8175 // TODO: s390 port size(FIXED_SIZE); 8176 8177 ins_is_TrapBasedCheckNode(true); 8178 8179 format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %} 8180 ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %} 8181 ins_pipe(pipe_class_trap); 8182%} 8183 8184// Match range check 'If lt (CmpU index length)' 8185instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{ 8186 match(If cmp (CmpU index length)); 8187 effect(USE labl, KILL cr); 8188 predicate(TrapBasedRangeChecks && 8189 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 8190 _leaf->as_If ()->_prob >= PROB_ALWAYS && 8191 Matcher::branches_to_uncommon_trap(_leaf)); 8192 ins_cost(1); 8193 // TODO: s390 port size(FIXED_SIZE); 8194 8195 ins_is_TrapBasedCheckNode(true); 8196 8197 format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %} 8198 ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %} 8199 ins_pipe(pipe_class_trap); 8200%} 8201 8202// Match range check 'If lt (CmpU index length)' 8203instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{ 8204 match(If cmp (CmpU index length)); 8205 effect(USE labl); 8206 predicate(TrapBasedRangeChecks && 8207 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 8208 _leaf->as_If ()->_prob >= PROB_ALWAYS && 8209 Matcher::branches_to_uncommon_trap(_leaf)); 8210 ins_cost(1); 8211 // TODO: s390 port size(FIXED_SIZE); 8212 8213 ins_is_TrapBasedCheckNode(true); 8214 8215 format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %} 8216 ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %} 8217 ins_pipe(pipe_class_trap); 8218%} 8219 8220// Implicit zero checks (more implicit null checks). 8221instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{ 8222 match(If cmp (CmpP value zero)); 8223 effect(USE labl); 8224 predicate(TrapBasedNullChecks && 8225 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 8226 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && 8227 Matcher::branches_to_uncommon_trap(_leaf)); 8228 size(6); 8229 8230 ins_is_TrapBasedCheckNode(true); 8231 8232 format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %} 8233 ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %} 8234 ins_pipe(pipe_class_trap); 8235%} 8236 8237// Implicit zero checks (more implicit null checks). 8238instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{ 8239 match(If cmp (CmpN value zero)); 8240 effect(USE labl); 8241 predicate(TrapBasedNullChecks && 8242 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 8243 _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) && 8244 Matcher::branches_to_uncommon_trap(_leaf)); 8245 size(6); 8246 8247 ins_is_TrapBasedCheckNode(true); 8248 8249 format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %} 8250 ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %} 8251 ins_pipe(pipe_class_trap); 8252%} 8253 8254//----------Compare instructions----------------------------------------------- 8255 8256// INT signed 8257 8258// Compare Integers 8259instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 8260 match(Set cr (CmpI op1 op2)); 8261 size(2); 8262 format %{ "CR $op1,$op2" %} 8263 opcode(CR_ZOPC); 8264 ins_encode(z_rrform(op1, op2)); 8265 ins_pipe(pipe_class_dummy); 8266%} 8267 8268instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{ 8269 match(Set cr (CmpI op1 op2)); 8270 size(6); 8271 format %{ "CFI $op1,$op2" %} 8272 opcode(CFI_ZOPC); 8273 ins_encode(z_rilform_signed(op1, op2)); 8274 ins_pipe(pipe_class_dummy); 8275%} 8276 8277instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{ 8278 match(Set cr (CmpI op1 op2)); 8279 size(4); 8280 format %{ "CHI $op1,$op2" %} 8281 opcode(CHI_ZOPC); 8282 ins_encode(z_riform_signed(op1, op2)); 8283 ins_pipe(pipe_class_dummy); 8284%} 8285 8286instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{ 8287 match(Set cr (CmpI op1 zero)); 8288 ins_cost(DEFAULT_COST_LOW); 8289 size(2); 8290 format %{ "LTR $op1,$op1" %} 8291 opcode(LTR_ZOPC); 8292 ins_encode(z_rrform(op1, op1)); 8293 ins_pipe(pipe_class_dummy); 8294%} 8295 8296instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{ 8297 match(Set cr (CmpI op1 (LoadI op2))); 8298 ins_cost(MEMORY_REF_COST); 8299 // TODO: s390 port size(VARIABLE_SIZE); 8300 format %{ "C(Y) $op1, $op2\t # int" %} 8301 opcode(CY_ZOPC, C_ZOPC); 8302 ins_encode(z_form_rt_mem_opt(op1, op2)); 8303 ins_pipe(pipe_class_dummy); 8304%} 8305 8306// INT unsigned 8307 8308instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{ 8309 match(Set cr (CmpU op1 op2)); 8310 size(2); 8311 format %{ "CLR $op1,$op2\t # unsigned" %} 8312 opcode(CLR_ZOPC); 8313 ins_encode(z_rrform(op1, op2)); 8314 ins_pipe(pipe_class_dummy); 8315%} 8316 8317instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{ 8318 match(Set cr (CmpU op1 op2)); 8319 size(6); 8320 format %{ "CLFI $op1,$op2\t # unsigned" %} 8321 opcode(CLFI_ZOPC); 8322 ins_encode(z_rilform_unsigned(op1, op2)); 8323 ins_pipe(pipe_class_dummy); 8324%} 8325 8326instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{ 8327 match(Set cr (CmpU op1 (LoadI op2))); 8328 ins_cost(MEMORY_REF_COST); 8329 // TODO: s390 port size(VARIABLE_SIZE); 8330 format %{ "CL(Y) $op1, $op2\t # unsigned" %} 8331 opcode(CLY_ZOPC, CL_ZOPC); 8332 ins_encode(z_form_rt_mem_opt(op1, op2)); 8333 ins_pipe(pipe_class_dummy); 8334%} 8335 8336// LONG signed 8337 8338instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 8339 match(Set cr (CmpL op1 op2)); 8340 size(4); 8341 format %{ "CGR $op1,$op2\t # long" %} 8342 opcode(CGR_ZOPC); 8343 ins_encode(z_rreform(op1, op2)); 8344 ins_pipe(pipe_class_dummy); 8345%} 8346 8347instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{ 8348 match(Set cr (CmpL op1 (ConvI2L op2))); 8349 size(4); 8350 format %{ "CGFR $op1,$op2\t # long/int" %} 8351 opcode(CGFR_ZOPC); 8352 ins_encode(z_rreform(op1, op2)); 8353 ins_pipe(pipe_class_dummy); 8354%} 8355 8356instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{ 8357 match(Set cr (CmpL op1 con)); 8358 size(6); 8359 format %{ "CGFI $op1,$con" %} 8360 opcode(CGFI_ZOPC); 8361 ins_encode(z_rilform_signed(op1, con)); 8362 ins_pipe(pipe_class_dummy); 8363%} 8364 8365instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{ 8366 match(Set cr (CmpL op1 con)); 8367 size(4); 8368 format %{ "CGHI $op1,$con" %} 8369 opcode(CGHI_ZOPC); 8370 ins_encode(z_riform_signed(op1, con)); 8371 ins_pipe(pipe_class_dummy); 8372%} 8373 8374instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{ 8375 match(Set cr (CmpL op1 con)); 8376 ins_cost(DEFAULT_COST_LOW); 8377 size(4); 8378 format %{ "LTGR $op1,$op1" %} 8379 opcode(LTGR_ZOPC); 8380 ins_encode(z_rreform(op1, op1)); 8381 ins_pipe(pipe_class_dummy); 8382%} 8383 8384instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{ 8385 match(Set cr (CmpL (ConvI2L op1) con)); 8386 ins_cost(DEFAULT_COST_LOW); 8387 size(4); 8388 format %{ "LTGFR $op1,$op1" %} 8389 opcode(LTGFR_ZOPC); 8390 ins_encode(z_rreform(op1, op1)); 8391 ins_pipe(pipe_class_dummy); 8392%} 8393 8394instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{ 8395 match(Set cr (CmpL dst (LoadL src))); 8396 ins_cost(MEMORY_REF_COST); 8397 size(Z_DISP3_SIZE); 8398 format %{ "CG $dst, $src\t # long" %} 8399 opcode(CG_ZOPC, CG_ZOPC); 8400 ins_encode(z_form_rt_mem_opt(dst, src)); 8401 ins_pipe(pipe_class_dummy); 8402%} 8403 8404instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{ 8405 match(Set cr (CmpL dst (ConvI2L (LoadI src)))); 8406 ins_cost(MEMORY_REF_COST); 8407 size(Z_DISP3_SIZE); 8408 format %{ "CGF $dst, $src\t # long/int" %} 8409 opcode(CGF_ZOPC, CGF_ZOPC); 8410 ins_encode(z_form_rt_mem_opt(dst, src)); 8411 ins_pipe(pipe_class_dummy); 8412%} 8413 8414// LONG unsigned 8415// Added CmpUL for LoopPredicate. 8416instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{ 8417 match(Set cr (CmpUL op1 op2)); 8418 size(4); 8419 format %{ "CLGR $op1,$op2\t # long" %} 8420 opcode(CLGR_ZOPC); 8421 ins_encode(z_rreform(op1, op2)); 8422 ins_pipe(pipe_class_dummy); 8423%} 8424 8425instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{ 8426 match(Set cr (CmpUL op1 con)); 8427 size(6); 8428 format %{ "CLGFI $op1,$con" %} 8429 opcode(CLGFI_ZOPC); 8430 ins_encode(z_rilform_unsigned(op1, con)); 8431 ins_pipe(pipe_class_dummy); 8432%} 8433 8434// PTR unsigned 8435 8436instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{ 8437 match(Set cr (CmpP op1 op2)); 8438 size(4); 8439 format %{ "CLGR $op1,$op2\t # ptr" %} 8440 opcode(CLGR_ZOPC); 8441 ins_encode(z_rreform(op1, op2)); 8442 ins_pipe(pipe_class_dummy); 8443%} 8444 8445instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{ 8446 match(Set cr (CmpP op1 op2)); 8447 ins_cost(DEFAULT_COST_LOW); 8448 size(4); 8449 format %{ "LTGR $op1, $op1\t # ptr" %} 8450 opcode(LTGR_ZOPC); 8451 ins_encode(z_rreform(op1, op1)); 8452 ins_pipe(pipe_class_dummy); 8453%} 8454 8455// Don't use LTGFR which performs sign extend. 8456instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{ 8457 match(Set cr (CmpP (DecodeN op1) op2)); 8458 predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0); 8459 ins_cost(DEFAULT_COST_LOW); 8460 size(2); 8461 format %{ "LTR $op1, $op1\t # ptr" %} 8462 opcode(LTR_ZOPC); 8463 ins_encode(z_rrform(op1, op1)); 8464 ins_pipe(pipe_class_dummy); 8465%} 8466 8467instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{ 8468 match(Set cr (CmpP dst (LoadP src))); 8469 ins_cost(MEMORY_REF_COST); 8470 size(Z_DISP3_SIZE); 8471 format %{ "CLG $dst, $src\t # ptr" %} 8472 opcode(CLG_ZOPC, CLG_ZOPC); 8473 ins_encode(z_form_rt_mem_opt(dst, src)); 8474 ins_pipe(pipe_class_dummy); 8475%} 8476 8477//----------Max and Min-------------------------------------------------------- 8478 8479// Max Register with Register 8480instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8481 match(Set dst (MinI src1 src2)); 8482 effect(KILL cr); 8483 predicate(VM_Version::has_LoadStoreConditional()); 8484 ins_cost(3 * DEFAULT_COST); 8485 // TODO: s390 port size(VARIABLE_SIZE); 8486 format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %} 8487 ins_encode %{ 8488 Register Rdst = $dst$$Register; 8489 Register Rsrc1 = $src1$$Register; 8490 Register Rsrc2 = $src2$$Register; 8491 8492 if (Rsrc1 == Rsrc2) { 8493 if (Rdst != Rsrc1) { 8494 __ z_lgfr(Rdst, Rsrc1); 8495 } 8496 } else if (Rdst == Rsrc1) { // Rdst preset with src1. 8497 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotLow. 8498 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); 8499 } else if (Rdst == Rsrc2) { // Rdst preset with src2. 8500 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotLow. 8501 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow); 8502 } else { 8503 // Rdst is disjoint from operands, move in either case. 8504 __ z_cr(Rsrc1, Rsrc2); 8505 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow); 8506 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8507 } 8508 %} 8509 ins_pipe(pipe_class_dummy); 8510%} 8511 8512// Min Register with Register. 8513instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8514 match(Set dst (MinI src1 src2)); 8515 effect(KILL cr); 8516 predicate(VM_Version::has_CompareBranch()); 8517 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8518 // TODO: s390 port size(VARIABLE_SIZE); 8519 format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %} 8520 ins_encode %{ 8521 Register Rdst = $dst$$Register; 8522 Register Rsrc1 = $src1$$Register; 8523 Register Rsrc2 = $src2$$Register; 8524 Label done; 8525 8526 if (Rsrc1 == Rsrc2) { 8527 if (Rdst != Rsrc1) { 8528 __ z_lgfr(Rdst, Rsrc1); 8529 } 8530 } else if (Rdst == Rsrc1) { 8531 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); 8532 __ z_lgfr(Rdst, Rsrc2); 8533 } else if (Rdst == Rsrc2) { 8534 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done); 8535 __ z_lgfr(Rdst, Rsrc1); 8536 } else { 8537 __ z_lgfr(Rdst, Rsrc1); 8538 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done); 8539 __ z_lgfr(Rdst, Rsrc2); 8540 } 8541 __ bind(done); 8542 %} 8543 ins_pipe(pipe_class_dummy); 8544%} 8545 8546instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8547 match(Set dst (MinI src1 src2)); 8548 effect(KILL cr); 8549 predicate(!VM_Version::has_CompareBranch()); 8550 ins_cost(3 * DEFAULT_COST + BRANCH_COST); 8551 // TODO: s390 port size(VARIABLE_SIZE); 8552 format %{ "MinI $dst $src1,$src2\t MinI" %} 8553 ins_encode %{ 8554 Register Rdst = $dst$$Register; 8555 Register Rsrc1 = $src1$$Register; 8556 Register Rsrc2 = $src2$$Register; 8557 Label done; 8558 8559 if (Rsrc1 == Rsrc2) { 8560 if (Rdst != Rsrc1) { 8561 __ z_lgfr(Rdst, Rsrc1); 8562 } 8563 } else if (Rdst == Rsrc1) { 8564 __ z_cr(Rsrc1, Rsrc2); 8565 __ z_brl(done); 8566 __ z_lgfr(Rdst, Rsrc2); 8567 } else if (Rdst == Rsrc2) { 8568 __ z_cr(Rsrc2, Rsrc1); 8569 __ z_brl(done); 8570 __ z_lgfr(Rdst, Rsrc1); 8571 } else { 8572 __ z_lgfr(Rdst, Rsrc1); 8573 __ z_cr(Rsrc1, Rsrc2); 8574 __ z_brl(done); 8575 __ z_lgfr(Rdst, Rsrc2); 8576 } 8577 __ bind(done); 8578 %} 8579 ins_pipe(pipe_class_dummy); 8580%} 8581 8582instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8583 match(Set dst (MinI src1 src2)); 8584 effect(KILL cr); 8585 predicate(VM_Version::has_LoadStoreConditional()); 8586 ins_cost(3 * DEFAULT_COST); 8587 // TODO: s390 port size(VARIABLE_SIZE); 8588 format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %} 8589 ins_encode %{ 8590 Register Rdst = $dst$$Register; 8591 Register Rsrc1 = $src1$$Register; 8592 int Isrc2 = $src2$$constant; 8593 8594 if (Rdst == Rsrc1) { 8595 __ load_const_optimized(Z_R0_scratch, Isrc2); 8596 __ z_cfi(Rsrc1, Isrc2); 8597 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); 8598 } else { 8599 __ load_const_optimized(Rdst, Isrc2); 8600 __ z_cfi(Rsrc1, Isrc2); 8601 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8602 } 8603 %} 8604 ins_pipe(pipe_class_dummy); 8605%} 8606 8607instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8608 match(Set dst (MinI src1 src2)); 8609 effect(KILL cr); 8610 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8611 // TODO: s390 port size(VARIABLE_SIZE); 8612 format %{ "MinI $dst $src1,$src2\t MinI const32" %} 8613 ins_encode %{ 8614 Label done; 8615 if ($dst$$Register != $src1$$Register) { 8616 __ z_lgfr($dst$$Register, $src1$$Register); 8617 } 8618 __ z_cfi($src1$$Register, $src2$$constant); 8619 __ z_brl(done); 8620 __ z_lgfi($dst$$Register, $src2$$constant); 8621 __ bind(done); 8622 %} 8623 ins_pipe(pipe_class_dummy); 8624%} 8625 8626instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8627 match(Set dst (MinI src1 src2)); 8628 effect(KILL cr); 8629 predicate(VM_Version::has_LoadStoreConditional()); 8630 ins_cost(3 * DEFAULT_COST); 8631 // TODO: s390 port size(VARIABLE_SIZE); 8632 format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %} 8633 ins_encode %{ 8634 Register Rdst = $dst$$Register; 8635 Register Rsrc1 = $src1$$Register; 8636 int Isrc2 = $src2$$constant; 8637 8638 if (Rdst == Rsrc1) { 8639 __ load_const_optimized(Z_R0_scratch, Isrc2); 8640 __ z_chi(Rsrc1, Isrc2); 8641 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow); 8642 } else { 8643 __ load_const_optimized(Rdst, Isrc2); 8644 __ z_chi(Rsrc1, Isrc2); 8645 __ z_locr(Rdst, Rsrc1, Assembler::bcondLow); 8646 } 8647 %} 8648 ins_pipe(pipe_class_dummy); 8649%} 8650 8651instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8652 match(Set dst (MinI src1 src2)); 8653 effect(KILL cr); 8654 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8655 // TODO: s390 port size(VARIABLE_SIZE); 8656 format %{ "MinI $dst $src1,$src2\t MinI const16" %} 8657 ins_encode %{ 8658 Label done; 8659 if ($dst$$Register != $src1$$Register) { 8660 __ z_lgfr($dst$$Register, $src1$$Register); 8661 } 8662 __ z_chi($src1$$Register, $src2$$constant); 8663 __ z_brl(done); 8664 __ z_lghi($dst$$Register, $src2$$constant); 8665 __ bind(done); 8666 %} 8667 ins_pipe(pipe_class_dummy); 8668%} 8669 8670instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{ 8671 match(Set dst (MinI src1 src2)); 8672 effect(KILL cr); 8673 predicate(VM_Version::has_CompareBranch()); 8674 ins_cost(DEFAULT_COST + BRANCH_COST); 8675 // TODO: s390 port size(VARIABLE_SIZE); 8676 format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %} 8677 ins_encode %{ 8678 Label done; 8679 if ($dst$$Register != $src1$$Register) { 8680 __ z_lgfr($dst$$Register, $src1$$Register); 8681 } 8682 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done); 8683 __ z_lghi($dst$$Register, $src2$$constant); 8684 __ bind(done); 8685 %} 8686 ins_pipe(pipe_class_dummy); 8687%} 8688 8689// Max Register with Register 8690instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8691 match(Set dst (MaxI src1 src2)); 8692 effect(KILL cr); 8693 predicate(VM_Version::has_LoadStoreConditional()); 8694 ins_cost(3 * DEFAULT_COST); 8695 // TODO: s390 port size(VARIABLE_SIZE); 8696 format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %} 8697 ins_encode %{ 8698 Register Rdst = $dst$$Register; 8699 Register Rsrc1 = $src1$$Register; 8700 Register Rsrc2 = $src2$$Register; 8701 8702 if (Rsrc1 == Rsrc2) { 8703 if (Rdst != Rsrc1) { 8704 __ z_lgfr(Rdst, Rsrc1); 8705 } 8706 } else if (Rdst == Rsrc1) { // Rdst preset with src1. 8707 __ z_cr(Rsrc1, Rsrc2); // Move src2 only if src1 is NotHigh. 8708 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); 8709 } else if (Rdst == Rsrc2) { // Rdst preset with src2. 8710 __ z_cr(Rsrc2, Rsrc1); // Move src1 only if src2 is NotHigh. 8711 __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh); 8712 } else { // Rdst is disjoint from operands, move in either case. 8713 __ z_cr(Rsrc1, Rsrc2); 8714 __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh); 8715 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8716 } 8717 %} 8718 ins_pipe(pipe_class_dummy); 8719%} 8720 8721// Max Register with Register 8722instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8723 match(Set dst (MaxI src1 src2)); 8724 effect(KILL cr); 8725 predicate(VM_Version::has_CompareBranch()); 8726 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8727 // TODO: s390 port size(VARIABLE_SIZE); 8728 format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %} 8729 ins_encode %{ 8730 Register Rdst = $dst$$Register; 8731 Register Rsrc1 = $src1$$Register; 8732 Register Rsrc2 = $src2$$Register; 8733 Label done; 8734 8735 if (Rsrc1 == Rsrc2) { 8736 if (Rdst != Rsrc1) { 8737 __ z_lgfr(Rdst, Rsrc1); 8738 } 8739 } else if (Rdst == Rsrc1) { 8740 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); 8741 __ z_lgfr(Rdst, Rsrc2); 8742 } else if (Rdst == Rsrc2) { 8743 __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done); 8744 __ z_lgfr(Rdst, Rsrc1); 8745 } else { 8746 __ z_lgfr(Rdst, Rsrc1); 8747 __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done); 8748 __ z_lgfr(Rdst, Rsrc2); 8749 } 8750 __ bind(done); 8751 %} 8752 ins_pipe(pipe_class_dummy); 8753%} 8754 8755instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 8756 match(Set dst (MaxI src1 src2)); 8757 effect(KILL cr); 8758 predicate(!VM_Version::has_CompareBranch()); 8759 ins_cost(3 * DEFAULT_COST + BRANCH_COST); 8760 // TODO: s390 port size(VARIABLE_SIZE); 8761 format %{ "MaxI $dst $src1,$src2\t MaxI" %} 8762 ins_encode %{ 8763 Register Rdst = $dst$$Register; 8764 Register Rsrc1 = $src1$$Register; 8765 Register Rsrc2 = $src2$$Register; 8766 Label done; 8767 8768 if (Rsrc1 == Rsrc2) { 8769 if (Rdst != Rsrc1) { 8770 __ z_lgfr(Rdst, Rsrc1); 8771 } 8772 } else if (Rdst == Rsrc1) { 8773 __ z_cr(Rsrc1, Rsrc2); 8774 __ z_brh(done); 8775 __ z_lgfr(Rdst, Rsrc2); 8776 } else if (Rdst == Rsrc2) { 8777 __ z_cr(Rsrc2, Rsrc1); 8778 __ z_brh(done); 8779 __ z_lgfr(Rdst, Rsrc1); 8780 } else { 8781 __ z_lgfr(Rdst, Rsrc1); 8782 __ z_cr(Rsrc1, Rsrc2); 8783 __ z_brh(done); 8784 __ z_lgfr(Rdst, Rsrc2); 8785 } 8786 8787 __ bind(done); 8788 %} 8789 8790 ins_pipe(pipe_class_dummy); 8791%} 8792 8793instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8794 match(Set dst (MaxI src1 src2)); 8795 effect(KILL cr); 8796 predicate(VM_Version::has_LoadStoreConditional()); 8797 ins_cost(3 * DEFAULT_COST); 8798 // TODO: s390 port size(VARIABLE_SIZE); 8799 format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %} 8800 ins_encode %{ 8801 Register Rdst = $dst$$Register; 8802 Register Rsrc1 = $src1$$Register; 8803 int Isrc2 = $src2$$constant; 8804 8805 if (Rdst == Rsrc1) { 8806 __ load_const_optimized(Z_R0_scratch, Isrc2); 8807 __ z_cfi(Rsrc1, Isrc2); 8808 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); 8809 } else { 8810 __ load_const_optimized(Rdst, Isrc2); 8811 __ z_cfi(Rsrc1, Isrc2); 8812 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8813 } 8814 %} 8815 ins_pipe(pipe_class_dummy); 8816%} 8817 8818instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{ 8819 match(Set dst (MaxI src1 src2)); 8820 effect(KILL cr); 8821 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8822 // TODO: s390 port size(VARIABLE_SIZE); 8823 format %{ "MaxI $dst $src1,$src2\t MaxI const32" %} 8824 ins_encode %{ 8825 Label done; 8826 if ($dst$$Register != $src1$$Register) { 8827 __ z_lgfr($dst$$Register, $src1$$Register); 8828 } 8829 __ z_cfi($src1$$Register, $src2$$constant); 8830 __ z_brh(done); 8831 __ z_lgfi($dst$$Register, $src2$$constant); 8832 __ bind(done); 8833 %} 8834 ins_pipe(pipe_class_dummy); 8835%} 8836 8837instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8838 match(Set dst (MaxI src1 src2)); 8839 effect(KILL cr); 8840 predicate(VM_Version::has_LoadStoreConditional()); 8841 ins_cost(3 * DEFAULT_COST); 8842 // TODO: s390 port size(VARIABLE_SIZE); 8843 format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %} 8844 ins_encode %{ 8845 Register Rdst = $dst$$Register; 8846 Register Rsrc1 = $src1$$Register; 8847 int Isrc2 = $src2$$constant; 8848 if (Rdst == Rsrc1) { 8849 __ load_const_optimized(Z_R0_scratch, Isrc2); 8850 __ z_chi(Rsrc1, Isrc2); 8851 __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh); 8852 } else { 8853 __ load_const_optimized(Rdst, Isrc2); 8854 __ z_chi(Rsrc1, Isrc2); 8855 __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh); 8856 } 8857 %} 8858 ins_pipe(pipe_class_dummy); 8859%} 8860 8861instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{ 8862 match(Set dst (MaxI src1 src2)); 8863 effect(KILL cr); 8864 ins_cost(2 * DEFAULT_COST + BRANCH_COST); 8865 // TODO: s390 port size(VARIABLE_SIZE); 8866 format %{ "MaxI $dst $src1,$src2\t MaxI const16" %} 8867 ins_encode %{ 8868 Label done; 8869 if ($dst$$Register != $src1$$Register) { 8870 __ z_lgfr($dst$$Register, $src1$$Register); 8871 } 8872 __ z_chi($src1$$Register, $src2$$constant); 8873 __ z_brh(done); 8874 __ z_lghi($dst$$Register, $src2$$constant); 8875 __ bind(done); 8876 %} 8877 ins_pipe(pipe_class_dummy); 8878%} 8879 8880instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{ 8881 match(Set dst (MaxI src1 src2)); 8882 effect(KILL cr); 8883 predicate(VM_Version::has_CompareBranch()); 8884 ins_cost(DEFAULT_COST + BRANCH_COST); 8885 // TODO: s390 port size(VARIABLE_SIZE); 8886 format %{ "MaxI $dst $src1,$src2\t MaxI const8" %} 8887 ins_encode %{ 8888 Label done; 8889 if ($dst$$Register != $src1$$Register) { 8890 __ z_lgfr($dst$$Register, $src1$$Register); 8891 } 8892 __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done); 8893 __ z_lghi($dst$$Register, $src2$$constant); 8894 __ bind(done); 8895 %} 8896 ins_pipe(pipe_class_dummy); 8897%} 8898 8899//----------Abs--------------------------------------------------------------- 8900 8901instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{ 8902 match(Set dst (AbsI src)); 8903 effect(KILL cr); 8904 ins_cost(DEFAULT_COST_LOW); 8905 // TODO: s390 port size(FIXED_SIZE); 8906 format %{ "LPR $dst, $src" %} 8907 opcode(LPR_ZOPC); 8908 ins_encode(z_rrform(dst, src)); 8909 ins_pipe(pipe_class_dummy); 8910%} 8911 8912instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{ 8913 match(Set dst (AbsL src)); 8914 effect(KILL cr); 8915 ins_cost(DEFAULT_COST_LOW); 8916 // TODO: s390 port size(FIXED_SIZE); 8917 format %{ "LPGR $dst, $src" %} 8918 opcode(LPGR_ZOPC); 8919 ins_encode(z_rreform(dst, src)); 8920 ins_pipe(pipe_class_dummy); 8921%} 8922 8923instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{ 8924 match(Set dst (SubI zero (AbsI src))); 8925 effect(KILL cr); 8926 ins_cost(DEFAULT_COST_LOW); 8927 // TODO: s390 port size(FIXED_SIZE); 8928 format %{ "LNR $dst, $src" %} 8929 opcode(LNR_ZOPC); 8930 ins_encode(z_rrform(dst, src)); 8931 ins_pipe(pipe_class_dummy); 8932%} 8933 8934//----------Float Compares---------------------------------------------------- 8935 8936// Compare floating, generate condition code. 8937instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{ 8938 match(Set cr (CmpF src1 src2)); 8939 ins_cost(ALU_REG_COST); 8940 size(4); 8941 format %{ "FCMPcc $src1,$src2\t # float" %} 8942 ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %} 8943 ins_pipe(pipe_class_dummy); 8944%} 8945 8946instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{ 8947 match(Set cr (CmpD src1 src2)); 8948 ins_cost(ALU_REG_COST); 8949 size(4); 8950 format %{ "FCMPcc $src1,$src2 \t # double" %} 8951 ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %} 8952 ins_pipe(pipe_class_dummy); 8953%} 8954 8955instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{ 8956 match(Set cr (CmpF src1 (LoadF src2))); 8957 ins_cost(ALU_MEMORY_COST); 8958 size(6); 8959 format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %} 8960 opcode(CEB_ZOPC); 8961 ins_encode(z_form_rt_memFP(src1, src2)); 8962 ins_pipe(pipe_class_dummy); 8963%} 8964 8965instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{ 8966 match(Set cr (CmpD src1 (LoadD src2))); 8967 ins_cost(ALU_MEMORY_COST); 8968 size(6); 8969 format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %} 8970 opcode(CDB_ZOPC); 8971 ins_encode(z_form_rt_memFP(src1, src2)); 8972 ins_pipe(pipe_class_dummy); 8973%} 8974 8975// Compare floating, generate condition code 8976instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{ 8977 match(Set cr (CmpF src1 src2)); 8978 ins_cost(DEFAULT_COST); 8979 size(4); 8980 format %{ "LTEBR $src1,$src1\t # float" %} 8981 opcode(LTEBR_ZOPC); 8982 ins_encode(z_rreform(src1, src1)); 8983 ins_pipe(pipe_class_dummy); 8984%} 8985 8986instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{ 8987 match(Set cr (CmpD src1 src2)); 8988 ins_cost(DEFAULT_COST); 8989 size(4); 8990 format %{ "LTDBR $src1,$src1 \t # double" %} 8991 opcode(LTDBR_ZOPC); 8992 ins_encode(z_rreform(src1, src1)); 8993 ins_pipe(pipe_class_dummy); 8994%} 8995 8996// Compare floating, generate -1,0,1 8997instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{ 8998 match(Set dst (CmpF3 src1 src2)); 8999 effect(KILL cr); 9000 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9001 size(24); 9002 format %{ "CmpF3 $dst,$src1,$src2" %} 9003 ins_encode %{ 9004 // compare registers 9005 __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); 9006 // Convert condition code into -1,0,1, where 9007 // -1 means unordered or less 9008 // 0 means equal 9009 // 1 means greater. 9010 if (VM_Version::has_LoadStoreConditional()) { 9011 Register one = Z_R0_scratch; 9012 Register minus_one = Z_R1_scratch; 9013 __ z_lghi(minus_one, -1); 9014 __ z_lghi(one, 1); 9015 __ z_lghi( $dst$$Register, 0); 9016 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9017 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); 9018 } else { 9019 Label done; 9020 __ clear_reg($dst$$Register, true, false); 9021 __ z_bre(done); 9022 __ z_lhi($dst$$Register, 1); 9023 __ z_brh(done); 9024 __ z_lhi($dst$$Register, -1); 9025 __ bind(done); 9026 } 9027 %} 9028 ins_pipe(pipe_class_dummy); 9029%} 9030 9031instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{ 9032 match(Set dst (CmpD3 src1 src2)); 9033 effect(KILL cr); 9034 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9035 size(24); 9036 format %{ "CmpD3 $dst,$src1,$src2" %} 9037 ins_encode %{ 9038 // compare registers 9039 __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); 9040 // Convert condition code into -1,0,1, where 9041 // -1 means unordered or less 9042 // 0 means equal 9043 // 1 means greater. 9044 if (VM_Version::has_LoadStoreConditional()) { 9045 Register one = Z_R0_scratch; 9046 Register minus_one = Z_R1_scratch; 9047 __ z_lghi(minus_one, -1); 9048 __ z_lghi(one, 1); 9049 __ z_lghi( $dst$$Register, 0); 9050 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9051 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered); 9052 } else { 9053 Label done; 9054 // indicate unused result 9055 (void) __ clear_reg($dst$$Register, true, false); 9056 __ z_bre(done); 9057 __ z_lhi($dst$$Register, 1); 9058 __ z_brh(done); 9059 __ z_lhi($dst$$Register, -1); 9060 __ bind(done); 9061 } 9062 %} 9063 ins_pipe(pipe_class_dummy); 9064%} 9065 9066//----------Branches--------------------------------------------------------- 9067// Jump 9068 9069// Direct Branch. 9070instruct branch(label labl) %{ 9071 match(Goto); 9072 effect(USE labl); 9073 ins_cost(BRANCH_COST); 9074 size(4); 9075 format %{ "BRU $labl" %} 9076 ins_encode(z_enc_bru(labl)); 9077 ins_pipe(pipe_class_dummy); 9078 // If set to 1 this indicates that the current instruction is a 9079 // short variant of a long branch. This avoids using this 9080 // instruction in first-pass matching. It will then only be used in 9081 // the `Shorten_branches' pass. 9082 ins_short_branch(1); 9083%} 9084 9085// Direct Branch. 9086instruct branchFar(label labl) %{ 9087 match(Goto); 9088 effect(USE labl); 9089 ins_cost(BRANCH_COST); 9090 size(6); 9091 format %{ "BRUL $labl" %} 9092 ins_encode(z_enc_brul(labl)); 9093 ins_pipe(pipe_class_dummy); 9094 // This is not a short variant of a branch, but the long variant. 9095 ins_short_branch(0); 9096%} 9097 9098// Conditional Near Branch 9099instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{ 9100 // Same match rule as `branchConFar'. 9101 match(If cmp cr); 9102 effect(USE lbl); 9103 ins_cost(BRANCH_COST); 9104 size(4); 9105 format %{ "branch_con_short,$cmp $lbl" %} 9106 ins_encode(z_enc_branch_con_short(cmp, lbl)); 9107 ins_pipe(pipe_class_dummy); 9108 // If set to 1 this indicates that the current instruction is a 9109 // short variant of a long branch. This avoids using this 9110 // instruction in first-pass matching. It will then only be used in 9111 // the `Shorten_branches' pass. 9112 ins_short_branch(1); 9113%} 9114 9115// This is for cases when the z/Architecture conditional branch instruction 9116// does not reach far enough. So we emit a far branch here, which is 9117// more expensive. 9118// 9119// Conditional Far Branch 9120instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{ 9121 // Same match rule as `branchCon'. 9122 match(If cmp cr); 9123 effect(USE cr, USE lbl); 9124 // Make more expensive to prefer compare_and_branch over separate instructions. 9125 ins_cost(2 * BRANCH_COST); 9126 size(6); 9127 format %{ "branch_con_far,$cmp $lbl" %} 9128 ins_encode(z_enc_branch_con_far(cmp, lbl)); 9129 ins_pipe(pipe_class_dummy); 9130 // This is not a short variant of a branch, but the long variant.. 9131 ins_short_branch(0); 9132%} 9133 9134instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{ 9135 match(CountedLoopEnd cmp cr); 9136 effect(USE labl); 9137 ins_cost(BRANCH_COST); 9138 size(4); 9139 format %{ "branch_con_short,$cmp $labl\t # counted loop end" %} 9140 ins_encode(z_enc_branch_con_short(cmp, labl)); 9141 ins_pipe(pipe_class_dummy); 9142 // If set to 1 this indicates that the current instruction is a 9143 // short variant of a long branch. This avoids using this 9144 // instruction in first-pass matching. It will then only be used in 9145 // the `Shorten_branches' pass. 9146 ins_short_branch(1); 9147%} 9148 9149instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{ 9150 match(CountedLoopEnd cmp cr); 9151 effect(USE labl); 9152 ins_cost(BRANCH_COST); 9153 size(6); 9154 format %{ "branch_con_far,$cmp $labl\t # counted loop end" %} 9155 ins_encode(z_enc_branch_con_far(cmp, labl)); 9156 ins_pipe(pipe_class_dummy); 9157 // This is not a short variant of a branch, but the long variant. 9158 ins_short_branch(0); 9159%} 9160 9161//----------Compare and Branch (short distance)------------------------------ 9162 9163// INT REG operands for loop counter processing. 9164instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9165 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9166 effect(USE labl, KILL cr); 9167 predicate(VM_Version::has_CompareBranch()); 9168 ins_cost(BRANCH_COST); 9169 // TODO: s390 port size(FIXED_SIZE); 9170 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %} 9171 opcode(CRJ_ZOPC); 9172 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9173 ins_pipe(pipe_class_dummy); 9174 ins_short_branch(1); 9175%} 9176 9177// INT REG operands. 9178instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9179 match(If boolnode (CmpI src1 src2)); 9180 effect(USE labl, KILL cr); 9181 predicate(VM_Version::has_CompareBranch()); 9182 ins_cost(BRANCH_COST); 9183 // TODO: s390 port size(FIXED_SIZE); 9184 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9185 opcode(CRJ_ZOPC); 9186 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9187 ins_pipe(pipe_class_dummy); 9188 ins_short_branch(1); 9189%} 9190 9191// Unsigned INT REG operands 9192instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9193 match(If boolnode (CmpU src1 src2)); 9194 effect(USE labl, KILL cr); 9195 predicate(VM_Version::has_CompareBranch()); 9196 ins_cost(BRANCH_COST); 9197 // TODO: s390 port size(FIXED_SIZE); 9198 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9199 opcode(CLRJ_ZOPC); 9200 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9201 ins_pipe(pipe_class_dummy); 9202 ins_short_branch(1); 9203%} 9204 9205// LONG REG operands 9206instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{ 9207 match(If boolnode (CmpL src1 src2)); 9208 effect(USE labl, KILL cr); 9209 predicate(VM_Version::has_CompareBranch()); 9210 ins_cost(BRANCH_COST); 9211 // TODO: s390 port size(FIXED_SIZE); 9212 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9213 opcode(CGRJ_ZOPC); 9214 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9215 ins_pipe(pipe_class_dummy); 9216 ins_short_branch(1); 9217%} 9218 9219// PTR REG operands 9220 9221// Separate rules for regular and narrow oops. ADLC can't recognize 9222// rules with polymorphic operands to be sisters -> shorten_branches 9223// will not shorten. 9224 9225instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{ 9226 match(If boolnode (CmpP src1 src2)); 9227 effect(USE labl, KILL cr); 9228 predicate(VM_Version::has_CompareBranch()); 9229 ins_cost(BRANCH_COST); 9230 // TODO: s390 port size(FIXED_SIZE); 9231 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9232 opcode(CLGRJ_ZOPC); 9233 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9234 ins_pipe(pipe_class_dummy); 9235 ins_short_branch(1); 9236%} 9237 9238instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{ 9239 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9240 effect(USE labl, KILL cr); 9241 predicate(VM_Version::has_CompareBranch()); 9242 ins_cost(BRANCH_COST); 9243 // TODO: s390 port size(FIXED_SIZE); 9244 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9245 opcode(CLGRJ_ZOPC); 9246 ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode)); 9247 ins_pipe(pipe_class_dummy); 9248 ins_short_branch(1); 9249%} 9250 9251// INT REG/IMM operands for loop counter processing 9252instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9253 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9254 effect(USE labl, KILL cr); 9255 predicate(VM_Version::has_CompareBranch()); 9256 ins_cost(BRANCH_COST); 9257 // TODO: s390 port size(FIXED_SIZE); 9258 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end SHORT" %} 9259 opcode(CIJ_ZOPC); 9260 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9261 ins_pipe(pipe_class_dummy); 9262 ins_short_branch(1); 9263%} 9264 9265// INT REG/IMM operands 9266instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9267 match(If boolnode (CmpI src1 src2)); 9268 effect(USE labl, KILL cr); 9269 predicate(VM_Version::has_CompareBranch()); 9270 ins_cost(BRANCH_COST); 9271 // TODO: s390 port size(FIXED_SIZE); 9272 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9273 opcode(CIJ_ZOPC); 9274 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9275 ins_pipe(pipe_class_dummy); 9276 ins_short_branch(1); 9277%} 9278 9279// INT REG/IMM operands 9280instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{ 9281 match(If boolnode (CmpU src1 src2)); 9282 effect(USE labl, KILL cr); 9283 predicate(VM_Version::has_CompareBranch()); 9284 ins_cost(BRANCH_COST); 9285 // TODO: s390 port size(FIXED_SIZE); 9286 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9287 opcode(CLIJ_ZOPC); 9288 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9289 ins_pipe(pipe_class_dummy); 9290 ins_short_branch(1); 9291%} 9292 9293// LONG REG/IMM operands 9294instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{ 9295 match(If boolnode (CmpL src1 src2)); 9296 effect(USE labl, KILL cr); 9297 predicate(VM_Version::has_CompareBranch()); 9298 ins_cost(BRANCH_COST); 9299 // TODO: s390 port size(FIXED_SIZE); 9300 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9301 opcode(CGIJ_ZOPC); 9302 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9303 ins_pipe(pipe_class_dummy); 9304 ins_short_branch(1); 9305%} 9306 9307// PTR REG-imm operands 9308 9309// Separate rules for regular and narrow oops. ADLC can't recognize 9310// rules with polymorphic operands to be sisters -> shorten_branches 9311// will not shorten. 9312 9313instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{ 9314 match(If boolnode (CmpP src1 src2)); 9315 effect(USE labl, KILL cr); 9316 predicate(VM_Version::has_CompareBranch()); 9317 ins_cost(BRANCH_COST); 9318 // TODO: s390 port size(FIXED_SIZE); 9319 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9320 opcode(CLGIJ_ZOPC); 9321 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9322 ins_pipe(pipe_class_dummy); 9323 ins_short_branch(1); 9324%} 9325 9326// Compare against zero only, do not mix N and P oops (encode/decode required). 9327instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{ 9328 match(If boolnode (CmpP (DecodeN src1) src2)); 9329 effect(USE labl, KILL cr); 9330 predicate(VM_Version::has_CompareBranch()); 9331 ins_cost(BRANCH_COST); 9332 // TODO: s390 port size(FIXED_SIZE); 9333 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9334 opcode(CLGIJ_ZOPC); 9335 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9336 ins_pipe(pipe_class_dummy); 9337 ins_short_branch(1); 9338%} 9339 9340instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{ 9341 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9342 effect(USE labl, KILL cr); 9343 predicate(VM_Version::has_CompareBranch()); 9344 ins_cost(BRANCH_COST); 9345 // TODO: s390 port size(FIXED_SIZE); 9346 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %} 9347 opcode(CLGIJ_ZOPC); 9348 ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode)); 9349 ins_pipe(pipe_class_dummy); 9350 ins_short_branch(1); 9351%} 9352 9353 9354//----------Compare and Branch (far distance)------------------------------ 9355 9356// INT REG operands for loop counter processing 9357instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9358 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9359 effect(USE labl, KILL cr); 9360 predicate(VM_Version::has_CompareBranch()); 9361 ins_cost(BRANCH_COST+DEFAULT_COST); 9362 // TODO: s390 port size(FIXED_SIZE); 9363 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %} 9364 opcode(CR_ZOPC, BRCL_ZOPC); 9365 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9366 ins_pipe(pipe_class_dummy); 9367 ins_short_branch(0); 9368%} 9369 9370// INT REG operands 9371instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9372 match(If boolnode (CmpI src1 src2)); 9373 effect(USE labl, KILL cr); 9374 predicate(VM_Version::has_CompareBranch()); 9375 ins_cost(BRANCH_COST+DEFAULT_COST); 9376 // TODO: s390 port size(FIXED_SIZE); 9377 format %{ "CRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9378 opcode(CR_ZOPC, BRCL_ZOPC); 9379 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9380 ins_pipe(pipe_class_dummy); 9381 ins_short_branch(0); 9382%} 9383 9384// INT REG operands 9385instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 9386 match(If boolnode (CmpU src1 src2)); 9387 effect(USE labl, KILL cr); 9388 predicate(VM_Version::has_CompareBranch()); 9389 ins_cost(BRANCH_COST+DEFAULT_COST); 9390 // TODO: s390 port size(FIXED_SIZE); 9391 format %{ "CLRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9392 opcode(CLR_ZOPC, BRCL_ZOPC); 9393 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9394 ins_pipe(pipe_class_dummy); 9395 ins_short_branch(0); 9396%} 9397 9398// LONG REG operands 9399instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{ 9400 match(If boolnode (CmpL src1 src2)); 9401 effect(USE labl, KILL cr); 9402 predicate(VM_Version::has_CompareBranch()); 9403 ins_cost(BRANCH_COST+DEFAULT_COST); 9404 // TODO: s390 port size(FIXED_SIZE); 9405 format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9406 opcode(CGR_ZOPC, BRCL_ZOPC); 9407 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9408 ins_pipe(pipe_class_dummy); 9409 ins_short_branch(0); 9410%} 9411 9412// PTR REG operands 9413 9414// Separate rules for regular and narrow oops. ADLC can't recognize 9415// rules with polymorphic operands to be sisters -> shorten_branches 9416// will not shorten. 9417 9418instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{ 9419 match(If boolnode (CmpP src1 src2)); 9420 effect(USE labl, KILL cr); 9421 predicate(VM_Version::has_CompareBranch()); 9422 ins_cost(BRANCH_COST+DEFAULT_COST); 9423 // TODO: s390 port size(FIXED_SIZE); 9424 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9425 opcode(CLGR_ZOPC, BRCL_ZOPC); 9426 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9427 ins_pipe(pipe_class_dummy); 9428 ins_short_branch(0); 9429%} 9430 9431instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{ 9432 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9433 effect(USE labl, KILL cr); 9434 predicate(VM_Version::has_CompareBranch()); 9435 ins_cost(BRANCH_COST+DEFAULT_COST); 9436 // TODO: s390 port size(FIXED_SIZE); 9437 format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9438 opcode(CLGR_ZOPC, BRCL_ZOPC); 9439 ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode)); 9440 ins_pipe(pipe_class_dummy); 9441 ins_short_branch(0); 9442%} 9443 9444// INT REG/IMM operands for loop counter processing 9445instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9446 match(CountedLoopEnd boolnode (CmpI src1 src2)); 9447 effect(USE labl, KILL cr); 9448 predicate(VM_Version::has_CompareBranch()); 9449 ins_cost(BRANCH_COST+DEFAULT_COST); 9450 // TODO: s390 port size(FIXED_SIZE); 9451 format %{ "test_and_branch_loop_end,$boolnode $src1,$src2,$labl\t # counted loop end FAR" %} 9452 opcode(CHI_ZOPC, BRCL_ZOPC); 9453 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9454 ins_pipe(pipe_class_dummy); 9455 ins_short_branch(0); 9456%} 9457 9458// INT REG/IMM operands 9459instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{ 9460 match(If boolnode (CmpI src1 src2)); 9461 effect(USE labl, KILL cr); 9462 predicate(VM_Version::has_CompareBranch()); 9463 ins_cost(BRANCH_COST+DEFAULT_COST); 9464 // TODO: s390 port size(FIXED_SIZE); 9465 format %{ "CIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9466 opcode(CHI_ZOPC, BRCL_ZOPC); 9467 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9468 ins_pipe(pipe_class_dummy); 9469 ins_short_branch(0); 9470%} 9471 9472// INT REG/IMM operands 9473instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{ 9474 match(If boolnode (CmpU src1 src2)); 9475 effect(USE labl, KILL cr); 9476 predicate(VM_Version::has_CompareBranch()); 9477 ins_cost(BRANCH_COST+DEFAULT_COST); 9478 // TODO: s390 port size(FIXED_SIZE); 9479 format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9480 opcode(CLFI_ZOPC, BRCL_ZOPC); 9481 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9482 ins_pipe(pipe_class_dummy); 9483 ins_short_branch(0); 9484%} 9485 9486// LONG REG/IMM operands 9487instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{ 9488 match(If boolnode (CmpL src1 src2)); 9489 effect(USE labl, KILL cr); 9490 predicate(VM_Version::has_CompareBranch()); 9491 ins_cost(BRANCH_COST+DEFAULT_COST); 9492 // TODO: s390 port size(FIXED_SIZE); 9493 format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9494 opcode(CGHI_ZOPC, BRCL_ZOPC); 9495 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9496 ins_pipe(pipe_class_dummy); 9497 ins_short_branch(0); 9498%} 9499 9500// PTR REG-imm operands 9501 9502// Separate rules for regular and narrow oops. ADLC can't recognize 9503// rules with polymorphic operands to be sisters -> shorten_branches 9504// will not shorten. 9505 9506instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{ 9507 match(If boolnode (CmpP src1 src2)); 9508 effect(USE labl, KILL cr); 9509 predicate(VM_Version::has_CompareBranch()); 9510 ins_cost(BRANCH_COST+DEFAULT_COST); 9511 // TODO: s390 port size(FIXED_SIZE); 9512 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9513 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9514 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9515 ins_pipe(pipe_class_dummy); 9516 ins_short_branch(0); 9517%} 9518 9519// Compare against zero only, do not mix N and P oops (encode/decode required). 9520instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{ 9521 match(If boolnode (CmpP (DecodeN src1) src2)); 9522 effect(USE labl, KILL cr); 9523 predicate(VM_Version::has_CompareBranch()); 9524 ins_cost(BRANCH_COST+DEFAULT_COST); 9525 // TODO: s390 port size(FIXED_SIZE); 9526 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9527 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9528 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9529 ins_pipe(pipe_class_dummy); 9530 ins_short_branch(0); 9531%} 9532 9533instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{ 9534 match(If boolnode (CmpP (DecodeN src1) (DecodeN src2))); 9535 effect(USE labl, KILL cr); 9536 predicate(VM_Version::has_CompareBranch()); 9537 ins_cost(BRANCH_COST+DEFAULT_COST); 9538 // TODO: s390 port size(FIXED_SIZE); 9539 format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # FAR(substituted)" %} 9540 opcode(CLGFI_ZOPC, BRCL_ZOPC); 9541 ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode)); 9542 ins_pipe(pipe_class_dummy); 9543 ins_short_branch(0); 9544%} 9545 9546// ============================================================================ 9547// Long Compare 9548 9549// Due to a shortcoming in the ADLC, it mixes up expressions like: 9550// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9551// difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9552// are collapsed internally in the ADLC's dfa-gen code. The match for 9553// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9554// foo match ends up with the wrong leaf. One fix is to not match both 9555// reg-reg and reg-zero forms of long-compare. This is unfortunate because 9556// both forms beat the trinary form of long-compare and both are very useful 9557// on platforms which have few registers. 9558 9559// Manifest a CmpL3 result in an integer register. Very painful. 9560// This is the test to avoid. 9561instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{ 9562 match(Set dst (CmpL3 src1 src2)); 9563 effect(KILL cr); 9564 ins_cost(DEFAULT_COST * 5 + BRANCH_COST); 9565 size(24); 9566 format %{ "CmpL3 $dst,$src1,$src2" %} 9567 ins_encode %{ 9568 Label done; 9569 // compare registers 9570 __ z_cgr($src1$$Register, $src2$$Register); 9571 // Convert condition code into -1,0,1, where 9572 // -1 means less 9573 // 0 means equal 9574 // 1 means greater. 9575 if (VM_Version::has_LoadStoreConditional()) { 9576 Register one = Z_R0_scratch; 9577 Register minus_one = Z_R1_scratch; 9578 __ z_lghi(minus_one, -1); 9579 __ z_lghi(one, 1); 9580 __ z_lghi( $dst$$Register, 0); 9581 __ z_locgr($dst$$Register, one, Assembler::bcondHigh); 9582 __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow); 9583 } else { 9584 __ clear_reg($dst$$Register, true, false); 9585 __ z_bre(done); 9586 __ z_lhi($dst$$Register, 1); 9587 __ z_brh(done); 9588 __ z_lhi($dst$$Register, -1); 9589 } 9590 __ bind(done); 9591 %} 9592 ins_pipe(pipe_class_dummy); 9593%} 9594 9595// ============================================================================ 9596// Safepoint Instruction 9597 9598instruct safePoint() %{ 9599 match(SafePoint); 9600 predicate(false); 9601 // TODO: s390 port size(FIXED_SIZE); 9602 format %{ "UNIMPLEMENTED Safepoint_ " %} 9603 ins_encode(enc_unimplemented()); 9604 ins_pipe(pipe_class_dummy); 9605%} 9606 9607instruct safePoint_poll(iRegP poll, flagsReg cr) %{ 9608 match(SafePoint poll); 9609 effect(USE poll, KILL cr); // R0 is killed, too. 9610 // TODO: s390 port size(FIXED_SIZE); 9611 format %{ "TM #0[,$poll],#111\t # Safepoint: poll for GC" %} 9612 ins_encode %{ 9613 // Mark the code position where the load from the safepoint 9614 // polling page was emitted as relocInfo::poll_type. 9615 __ relocate(relocInfo::poll_type); 9616 __ load_from_polling_page($poll$$Register); 9617 %} 9618 ins_pipe(pipe_class_dummy); 9619%} 9620 9621// ============================================================================ 9622 9623// Call Instructions 9624 9625// Call Java Static Instruction 9626instruct CallStaticJavaDirect_dynTOC(method meth) %{ 9627 match(CallStaticJava); 9628 effect(USE meth); 9629 ins_cost(CALL_COST); 9630 // TODO: s390 port size(VARIABLE_SIZE); 9631 format %{ "CALL,static dynTOC $meth; ==> " %} 9632 ins_encode( z_enc_java_static_call(meth) ); 9633 ins_pipe(pipe_class_dummy); 9634 ins_alignment(2); 9635%} 9636 9637// Call Java Dynamic Instruction 9638instruct CallDynamicJavaDirect_dynTOC(method meth) %{ 9639 match(CallDynamicJava); 9640 effect(USE meth); 9641 ins_cost(CALL_COST); 9642 // TODO: s390 port size(VARIABLE_SIZE); 9643 format %{ "CALL,dynamic dynTOC $meth; ==> " %} 9644 ins_encode(z_enc_java_dynamic_call(meth)); 9645 ins_pipe(pipe_class_dummy); 9646 ins_alignment(2); 9647%} 9648 9649// Call Runtime Instruction 9650instruct CallRuntimeDirect(method meth) %{ 9651 match(CallRuntime); 9652 effect(USE meth); 9653 ins_cost(CALL_COST); 9654 // TODO: s390 port size(VARIABLE_SIZE); 9655 ins_num_consts(1); 9656 ins_alignment(2); 9657 format %{ "CALL,runtime" %} 9658 ins_encode( z_enc_java_to_runtime_call(meth) ); 9659 ins_pipe(pipe_class_dummy); 9660%} 9661 9662// Call runtime without safepoint - same as CallRuntime 9663instruct CallLeafDirect(method meth) %{ 9664 match(CallLeaf); 9665 effect(USE meth); 9666 ins_cost(CALL_COST); 9667 // TODO: s390 port size(VARIABLE_SIZE); 9668 ins_num_consts(1); 9669 ins_alignment(2); 9670 format %{ "CALL,runtime leaf $meth" %} 9671 ins_encode( z_enc_java_to_runtime_call(meth) ); 9672 ins_pipe(pipe_class_dummy); 9673%} 9674 9675// Call runtime without safepoint - same as CallLeaf 9676instruct CallLeafNoFPDirect(method meth) %{ 9677 match(CallLeafNoFP); 9678 effect(USE meth); 9679 ins_cost(CALL_COST); 9680 // TODO: s390 port size(VARIABLE_SIZE); 9681 ins_num_consts(1); 9682 format %{ "CALL,runtime leaf nofp $meth" %} 9683 ins_encode( z_enc_java_to_runtime_call(meth) ); 9684 ins_pipe(pipe_class_dummy); 9685 ins_alignment(2); 9686%} 9687 9688// Tail Call; Jump from runtime stub to Java code. 9689// Also known as an 'interprocedural jump'. 9690// Target of jump will eventually return to caller. 9691// TailJump below removes the return address. 9692instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_ptr) %{ 9693 match(TailCall jump_target method_ptr); 9694 ins_cost(CALL_COST); 9695 size(2); 9696 format %{ "Jmp $jump_target\t # $method_ptr holds method" %} 9697 ins_encode %{ __ z_br($jump_target$$Register); %} 9698 ins_pipe(pipe_class_dummy); 9699%} 9700 9701// Return Instruction 9702instruct Ret() %{ 9703 match(Return); 9704 size(2); 9705 format %{ "BR(Z_R14) // branch to link register" %} 9706 ins_encode %{ __ z_br(Z_R14); %} 9707 ins_pipe(pipe_class_dummy); 9708%} 9709 9710// Tail Jump; remove the return address; jump to target. 9711// TailCall above leaves the return address around. 9712// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9713// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9714// "restore" before this instruction (in Epilogue), we need to materialize it 9715// in %i0. 9716instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{ 9717 match(TailJump jump_target ex_oop); 9718 ins_cost(CALL_COST); 9719 size(8); 9720 format %{ "TailJump $jump_target" %} 9721 ins_encode %{ 9722 __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP); 9723 __ z_br($jump_target$$Register); 9724 %} 9725 ins_pipe(pipe_class_dummy); 9726%} 9727 9728// Create exception oop: created by stack-crawling runtime code. 9729// Created exception is now available to this handler, and is setup 9730// just prior to jumping to this handler. No code emitted. 9731instruct CreateException(rarg1RegP ex_oop) %{ 9732 match(Set ex_oop (CreateEx)); 9733 ins_cost(0); 9734 size(0); 9735 format %{ "# exception oop; no code emitted" %} 9736 ins_encode(/*empty*/); 9737 ins_pipe(pipe_class_dummy); 9738%} 9739 9740// Rethrow exception: The exception oop will come in the first 9741// argument position. Then JUMP (not call) to the rethrow stub code. 9742instruct RethrowException() %{ 9743 match(Rethrow); 9744 ins_cost(CALL_COST); 9745 // TODO: s390 port size(VARIABLE_SIZE); 9746 format %{ "Jmp rethrow_stub" %} 9747 ins_encode %{ 9748 cbuf.set_insts_mark(); 9749 __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub()); 9750 __ z_br(Z_R1_scratch); 9751 %} 9752 ins_pipe(pipe_class_dummy); 9753%} 9754 9755// Die now. 9756instruct ShouldNotReachHere() %{ 9757 match(Halt); 9758 ins_cost(CALL_COST); 9759 format %{ "ILLTRAP; ShouldNotReachHere" %} 9760 ins_encode %{ 9761 if (is_reachable()) { 9762 __ stop(_halt_reason); 9763 } 9764 %} 9765 ins_pipe(pipe_class_dummy); 9766%} 9767 9768// ============================================================================ 9769// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9770// array for an instance of the superklass. Set a hidden internal cache on a 9771// hit (cache is checked with exposed code in gen_subtype_check()). Return 9772// not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9773instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc, 9774 rarg4RegP scratch1, rarg5RegP scratch2) %{ 9775 match(Set index (PartialSubtypeCheck sub super)); 9776 effect(KILL pcc, KILL scratch1, KILL scratch2); 9777 ins_cost(10 * DEFAULT_COST); 9778 // TODO: s390 port size(FIXED_SIZE); 9779 format %{ " CALL PartialSubtypeCheck\n" %} 9780 ins_encode %{ 9781 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); 9782 __ load_const_optimized(Z_ARG4, stub_address); 9783 __ z_basr(Z_R14, Z_ARG4); 9784 %} 9785 ins_pipe(pipe_class_dummy); 9786%} 9787 9788instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero, 9789 rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{ 9790 match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero)); 9791 effect(KILL scratch1, KILL scratch2, KILL index); 9792 ins_cost(10 * DEFAULT_COST); 9793 // TODO: s390 port size(FIXED_SIZE); 9794 format %{ "CALL PartialSubtypeCheck_vs_zero\n" %} 9795 ins_encode %{ 9796 AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check()); 9797 __ load_const_optimized(Z_ARG4, stub_address); 9798 __ z_basr(Z_R14, Z_ARG4); 9799 %} 9800 ins_pipe(pipe_class_dummy); 9801%} 9802 9803// ============================================================================ 9804// inlined locking and unlocking 9805 9806instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{ 9807 match(Set pcc (FastLock oop box)); 9808 effect(TEMP tmp1, TEMP tmp2); 9809 ins_cost(100); 9810 // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized. 9811 format %{ "FASTLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %} 9812 ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register, 9813 UseBiasedLocking && !UseOptoBiasInlining); %} 9814 ins_pipe(pipe_class_dummy); 9815%} 9816 9817instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{ 9818 match(Set pcc (FastUnlock oop box)); 9819 effect(TEMP tmp1, TEMP tmp2); 9820 ins_cost(100); 9821 // TODO: s390 port size(FIXED_SIZE); // emitted code depends on UseBiasedLocking being on/off. 9822 format %{ "FASTUNLOCK $oop, $box; KILL Z_ARG4, Z_ARG5" %} 9823 ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register, 9824 UseBiasedLocking && !UseOptoBiasInlining); %} 9825 ins_pipe(pipe_class_dummy); 9826%} 9827 9828instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{ 9829 match(Set dummy (ClearArray cnt base)); 9830 effect(KILL cr); 9831 ins_cost(100); 9832 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to varying #instructions. 9833 format %{ "ClearArrayConst $cnt,$base" %} 9834 ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %} 9835 ins_pipe(pipe_class_dummy); 9836%} 9837 9838instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{ 9839 match(Set dummy (ClearArray cnt base)); 9840 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too. 9841 ins_cost(200); 9842 // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader. 9843 format %{ "ClearArrayConstBig $cnt,$base" %} 9844 ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %} 9845 ins_pipe(pipe_class_dummy); 9846%} 9847 9848instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{ 9849 match(Set dummy (ClearArray cnt base)); 9850 effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too. 9851 ins_cost(300); 9852 // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off. 9853 format %{ "ClearArrayVar $cnt,$base" %} 9854 ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %} 9855 ins_pipe(pipe_class_dummy); 9856%} 9857 9858// ============================================================================ 9859// CompactStrings 9860 9861// String equals 9862instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9863 match(Set result (StrEquals (Binary str1 str2) cnt)); 9864 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9865 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 9866 ins_cost(300); 9867 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %} 9868 ins_encode %{ 9869 __ array_equals(false, $str1$$Register, $str2$$Register, 9870 $cnt$$Register, $oddReg$$Register, $evenReg$$Register, 9871 $result$$Register, true /* byte */); 9872 %} 9873 ins_pipe(pipe_class_dummy); 9874%} 9875 9876instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9877 match(Set result (StrEquals (Binary str1 str2) cnt)); 9878 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9879 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); 9880 ins_cost(300); 9881 format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %} 9882 ins_encode %{ 9883 __ array_equals(false, $str1$$Register, $str2$$Register, 9884 $cnt$$Register, $oddReg$$Register, $evenReg$$Register, 9885 $result$$Register, false /* byte */); 9886 %} 9887 ins_pipe(pipe_class_dummy); 9888%} 9889 9890instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{ 9891 match(Set result (StrEquals (Binary str1 str2) cnt)); 9892 effect(KILL cr); // R0 is killed, too. 9893 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 9894 ins_cost(100); 9895 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %} 9896 ins_encode %{ 9897 const int cnt_imm = $cnt$$constant; 9898 if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); } 9899 __ z_lhi($result$$Register, 1); 9900 if (cnt_imm) { 9901 if (VM_Version::has_LoadStoreConditional()) { 9902 __ z_lhi(Z_R0_scratch, 0); 9903 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); 9904 } else { 9905 Label Lskip; 9906 __ z_bre(Lskip); 9907 __ clear_reg($result$$Register); 9908 __ bind(Lskip); 9909 } 9910 } 9911 %} 9912 ins_pipe(pipe_class_dummy); 9913%} 9914 9915instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{ 9916 match(Set result (StrEquals (Binary str1 str2) cnt)); 9917 effect(KILL cr); // R0 is killed, too. 9918 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none); 9919 ins_cost(100); 9920 format %{ "String Equals $str1,$str2,$cnt -> $result" %} 9921 ins_encode %{ 9922 const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used) 9923 if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); } 9924 __ z_lhi($result$$Register, 1); 9925 if (cnt_imm) { 9926 if (VM_Version::has_LoadStoreConditional()) { 9927 __ z_lhi(Z_R0_scratch, 0); 9928 __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual); 9929 } else { 9930 Label Lskip; 9931 __ z_bre(Lskip); 9932 __ clear_reg($result$$Register); 9933 __ bind(Lskip); 9934 } 9935 } 9936 %} 9937 ins_pipe(pipe_class_dummy); 9938%} 9939 9940// Array equals 9941instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9942 match(Set result (AryEq ary1 ary2)); 9943 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9944 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 9945 ins_cost(300); 9946 format %{ "Array Equals $ary1,$ary2 -> $result" %} 9947 ins_encode %{ 9948 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9949 noreg, $oddReg$$Register, $evenReg$$Register, 9950 $result$$Register, true /* byte */); 9951 %} 9952 ins_pipe(pipe_class_dummy); 9953%} 9954 9955instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9956 match(Set result (AryEq ary1 ary2)); 9957 effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9958 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 9959 ins_cost(300); 9960 format %{ "Array Equals $ary1,$ary2 -> $result" %} 9961 ins_encode %{ 9962 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9963 noreg, $oddReg$$Register, $evenReg$$Register, 9964 $result$$Register, false /* byte */); 9965 %} 9966 ins_pipe(pipe_class_dummy); 9967%} 9968 9969// String CompareTo 9970instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9971 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9972 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9973 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 9974 ins_cost(300); 9975 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 9976 ins_encode %{ 9977 __ string_compare($str1$$Register, $str2$$Register, 9978 $cnt1$$Register, $cnt2$$Register, 9979 $oddReg$$Register, $evenReg$$Register, 9980 $result$$Register, StrIntrinsicNode::LL); 9981 %} 9982 ins_pipe(pipe_class_dummy); 9983%} 9984 9985instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 9986 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9987 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 9988 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none); 9989 ins_cost(300); 9990 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 9991 ins_encode %{ 9992 __ string_compare($str1$$Register, $str2$$Register, 9993 $cnt1$$Register, $cnt2$$Register, 9994 $oddReg$$Register, $evenReg$$Register, 9995 $result$$Register, StrIntrinsicNode::UU); 9996 %} 9997 ins_pipe(pipe_class_dummy); 9998%} 9999 10000instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10001 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10002 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10003 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 10004 ins_cost(300); 10005 format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10006 ins_encode %{ 10007 __ string_compare($str1$$Register, $str2$$Register, 10008 $cnt1$$Register, $cnt2$$Register, 10009 $oddReg$$Register, $evenReg$$Register, 10010 $result$$Register, StrIntrinsicNode::LU); 10011 %} 10012 ins_pipe(pipe_class_dummy); 10013%} 10014 10015instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10016 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10017 effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10018 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 10019 ins_cost(300); 10020 format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %} 10021 ins_encode %{ 10022 __ string_compare($str2$$Register, $str1$$Register, 10023 $cnt2$$Register, $cnt1$$Register, 10024 $oddReg$$Register, $evenReg$$Register, 10025 $result$$Register, StrIntrinsicNode::UL); 10026 %} 10027 ins_pipe(pipe_class_dummy); 10028%} 10029 10030// String IndexOfChar 10031instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10032 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); 10033 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10034 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U); 10035 ins_cost(200); 10036 format %{ "StringUTF16 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %} 10037 ins_encode %{ 10038 __ string_indexof_char($result$$Register, 10039 $haystack$$Register, $haycnt$$Register, 10040 $ch$$Register, 0 /* unused, ch is in register */, 10041 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10042 %} 10043 ins_pipe(pipe_class_dummy); 10044%} 10045 10046instruct indexOfChar_L(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10047 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); 10048 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10049 predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L); 10050 ins_cost(200); 10051 format %{ "StringLatin1 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %} 10052 ins_encode %{ 10053 __ string_indexof_char($result$$Register, 10054 $haystack$$Register, $haycnt$$Register, 10055 $ch$$Register, 0 /* unused, ch is in register */, 10056 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/); 10057 %} 10058 ins_pipe(pipe_class_dummy); 10059%} 10060 10061instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10062 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10063 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10064 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10065 ins_cost(200); 10066 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10067 ins_encode %{ 10068 immPOper *needleOper = (immPOper *)$needle; 10069 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10070 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10071 jchar chr; 10072#ifdef VM_LITTLE_ENDIAN 10073 Unimplemented(); 10074#else 10075 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | 10076 ((jchar)(unsigned char)needle_values->element_value(1).as_byte()); 10077#endif 10078 __ string_indexof_char($result$$Register, 10079 $haystack$$Register, $haycnt$$Register, 10080 noreg, chr, 10081 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10082 %} 10083 ins_pipe(pipe_class_dummy); 10084%} 10085 10086instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10087 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10088 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10089 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10090 ins_cost(200); 10091 format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10092 ins_encode %{ 10093 immPOper *needleOper = (immPOper *)$needle; 10094 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10095 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10096 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 10097 __ string_indexof_char($result$$Register, 10098 $haystack$$Register, $haycnt$$Register, 10099 noreg, chr, 10100 $oddReg$$Register, $evenReg$$Register, true /*is_byte*/); 10101 %} 10102 ins_pipe(pipe_class_dummy); 10103%} 10104 10105instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10106 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10107 effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too. 10108 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10109 ins_cost(200); 10110 format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %} 10111 ins_encode %{ 10112 immPOper *needleOper = (immPOper *)$needle; 10113 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 10114 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 10115 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 10116 __ string_indexof_char($result$$Register, 10117 $haystack$$Register, $haycnt$$Register, 10118 noreg, chr, 10119 $oddReg$$Register, $evenReg$$Register, false /*is_byte*/); 10120 %} 10121 ins_pipe(pipe_class_dummy); 10122%} 10123 10124// String IndexOf 10125instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10126 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10127 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10128 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10129 ins_cost(250); 10130 format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10131 ins_encode %{ 10132 __ string_indexof($result$$Register, 10133 $haystack$$Register, $haycnt$$Register, 10134 $needle$$Register, noreg, $needlecntImm$$constant, 10135 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); 10136 %} 10137 ins_pipe(pipe_class_dummy); 10138%} 10139 10140instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10141 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10142 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10143 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10144 ins_cost(250); 10145 format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10146 ins_encode %{ 10147 __ string_indexof($result$$Register, 10148 $haystack$$Register, $haycnt$$Register, 10149 $needle$$Register, noreg, $needlecntImm$$constant, 10150 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); 10151 %} 10152 ins_pipe(pipe_class_dummy); 10153%} 10154 10155instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10156 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 10157 effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10158 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10159 ins_cost(250); 10160 format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10161 ins_encode %{ 10162 __ string_indexof($result$$Register, 10163 $haystack$$Register, $haycnt$$Register, 10164 $needle$$Register, noreg, $needlecntImm$$constant, 10165 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); 10166 %} 10167 ins_pipe(pipe_class_dummy); 10168%} 10169 10170instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10171 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10172 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10173 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none); 10174 ins_cost(300); 10175 format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10176 ins_encode %{ 10177 __ string_indexof($result$$Register, 10178 $haystack$$Register, $haycnt$$Register, 10179 $needle$$Register, $needlecnt$$Register, 0, 10180 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU); 10181 %} 10182 ins_pipe(pipe_class_dummy); 10183%} 10184 10185instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10186 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10187 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10188 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 10189 ins_cost(300); 10190 format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10191 ins_encode %{ 10192 __ string_indexof($result$$Register, 10193 $haystack$$Register, $haycnt$$Register, 10194 $needle$$Register, $needlecnt$$Register, 0, 10195 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL); 10196 %} 10197 ins_pipe(pipe_class_dummy); 10198%} 10199 10200instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{ 10201 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 10202 effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too. 10203 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 10204 ins_cost(300); 10205 format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %} 10206 ins_encode %{ 10207 __ string_indexof($result$$Register, 10208 $haystack$$Register, $haycnt$$Register, 10209 $needle$$Register, $needlecnt$$Register, 0, 10210 $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL); 10211 %} 10212 ins_pipe(pipe_class_dummy); 10213%} 10214 10215// char[] to byte[] compression 10216instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{ 10217 match(Set result (StrCompressedCopy src (Binary dst len))); 10218 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10219 ins_cost(300); 10220 format %{ "String Compress $src->$dst($len) -> $result" %} 10221 ins_encode %{ 10222 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, 10223 $tmp$$Register, false); 10224 %} 10225 ins_pipe(pipe_class_dummy); 10226%} 10227 10228// byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop. 10229//instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{ 10230// match(Set dummy (StrInflatedCopy src (Binary dst len))); 10231// effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10232// predicate(VM_Version::has_ETF2Enhancements()); 10233// ins_cost(300); 10234// format %{ "String Inflate (trot) $dst,$src($len)" %} 10235// ins_encode %{ 10236// __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); 10237// %} 10238// ins_pipe(pipe_class_dummy); 10239//%} 10240 10241// byte[] to char[] inflation 10242instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{ 10243 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10244 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too. 10245 ins_cost(300); 10246 format %{ "String Inflate $src->$dst($len)" %} 10247 ins_encode %{ 10248 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register); 10249 %} 10250 ins_pipe(pipe_class_dummy); 10251%} 10252 10253// byte[] to char[] inflation 10254instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{ 10255 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10256 effect(TEMP tmp, KILL cr); // R0, R1 are killed, too. 10257 ins_cost(300); 10258 format %{ "String Inflate (constLen) $src->$dst($len)" %} 10259 ins_encode %{ 10260 __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant); 10261 %} 10262 ins_pipe(pipe_class_dummy); 10263%} 10264 10265// StringCoding.java intrinsics 10266instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{ 10267 match(Set result (HasNegatives ary1 len)); 10268 effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10269 ins_cost(300); 10270 format %{ "has negatives byte[] $ary1($len) -> $result" %} 10271 ins_encode %{ 10272 __ has_negatives($result$$Register, $ary1$$Register, $len$$Register, 10273 $oddReg$$Register, $evenReg$$Register, $tmp$$Register); 10274 %} 10275 ins_pipe(pipe_class_dummy); 10276%} 10277 10278// encode char[] to byte[] in ISO_8859_1 10279instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{ 10280 match(Set result (EncodeISOArray src (Binary dst len))); 10281 effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too. 10282 ins_cost(300); 10283 format %{ "Encode array $src->$dst($len) -> $result" %} 10284 ins_encode %{ 10285 __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register, 10286 $tmp$$Register, true); 10287 %} 10288 ins_pipe(pipe_class_dummy); 10289%} 10290 10291 10292//----------PEEPHOLE RULES----------------------------------------------------- 10293// These must follow all instruction definitions as they use the names 10294// defined in the instructions definitions. 10295// 10296// peepmatch (root_instr_name [preceeding_instruction]*); 10297// 10298// peepconstraint %{ 10299// (instruction_number.operand_name relational_op instruction_number.operand_name 10300// [, ...]); 10301// // instruction numbers are zero-based using left to right order in peepmatch 10302// 10303// peepreplace (instr_name([instruction_number.operand_name]*)); 10304// // provide an instruction_number.operand_name for each operand that appears 10305// // in the replacement instruction's match rule 10306// 10307// ---------VM FLAGS--------------------------------------------------------- 10308// 10309// All peephole optimizations can be turned off using -XX:-OptoPeephole 10310// 10311// Each peephole rule is given an identifying number starting with zero and 10312// increasing by one in the order seen by the parser. An individual peephole 10313// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10314// on the command-line. 10315// 10316// ---------CURRENT LIMITATIONS---------------------------------------------- 10317// 10318// Only match adjacent instructions in same basic block 10319// Only equality constraints 10320// Only constraints between operands, not (0.dest_reg == EAX_enc) 10321// Only one replacement instruction 10322// 10323// ---------EXAMPLE---------------------------------------------------------- 10324// 10325// // pertinent parts of existing instructions in architecture description 10326// instruct movI(eRegI dst, eRegI src) %{ 10327// match(Set dst (CopyI src)); 10328// %} 10329// 10330// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10331// match(Set dst (AddI dst src)); 10332// effect(KILL cr); 10333// %} 10334// 10335// // Change (inc mov) to lea 10336// peephole %{ 10337// // increment preceeded by register-register move 10338// peepmatch (incI_eReg movI); 10339// // require that the destination register of the increment 10340// // match the destination register of the move 10341// peepconstraint (0.dst == 1.dst); 10342// // construct a replacement instruction that sets 10343// // the destination to (move's source register + one) 10344// peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10345// %} 10346// 10347// Implementation no longer uses movX instructions since 10348// machine-independent system no longer uses CopyX nodes. 10349// 10350// peephole %{ 10351// peepmatch (incI_eReg movI); 10352// peepconstraint (0.dst == 1.dst); 10353// peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10354// %} 10355// 10356// peephole %{ 10357// peepmatch (decI_eReg movI); 10358// peepconstraint (0.dst == 1.dst); 10359// peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10360// %} 10361// 10362// peephole %{ 10363// peepmatch (addI_eReg_imm movI); 10364// peepconstraint (0.dst == 1.dst); 10365// peepreplace (leaI_eReg_immI(0.dst 1.src 0.src)); 10366// %} 10367// 10368// peephole %{ 10369// peepmatch (addP_eReg_imm movP); 10370// peepconstraint (0.dst == 1.dst); 10371// peepreplace (leaP_eReg_immI(0.dst 1.src 0.src)); 10372// %} 10373 10374 10375// This peephole rule does not work, probably because ADLC can't handle two effects: 10376// Effect 1 is defining 0.op1 and effect 2 is setting CC 10377// condense a load from memory and subsequent test for zero 10378// into a single, more efficient ICM instruction. 10379// peephole %{ 10380// peepmatch (compI_iReg_imm0 loadI); 10381// peepconstraint (1.dst == 0.op1); 10382// peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem)); 10383// %} 10384 10385// // Change load of spilled value to only a spill 10386// instruct storeI(memory mem, eRegI src) %{ 10387// match(Set mem (StoreI mem src)); 10388// %} 10389// 10390// instruct loadI(eRegI dst, memory mem) %{ 10391// match(Set dst (LoadI mem)); 10392// %} 10393// 10394peephole %{ 10395 peepmatch (loadI storeI); 10396 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 10397 peepreplace (storeI(1.mem 1.mem 1.src)); 10398%} 10399 10400peephole %{ 10401 peepmatch (loadL storeL); 10402 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); 10403 peepreplace (storeL(1.mem 1.mem 1.src)); 10404%} 10405 10406peephole %{ 10407 peepmatch (loadP storeP); 10408 peepconstraint (1.src == 0.dst, 1.dst == 0.mem); 10409 peepreplace (storeP(1.dst 1.dst 1.src)); 10410%} 10411 10412//----------SUPERWORD RULES--------------------------------------------------- 10413 10414// Expand rules for special cases 10415 10416instruct expand_storeF(stackSlotF mem, regF src) %{ 10417 // No match rule, false predicate, for expand only. 10418 effect(DEF mem, USE src); 10419 predicate(false); 10420 ins_cost(MEMORY_REF_COST); 10421 // TODO: s390 port size(FIXED_SIZE); 10422 format %{ "STE $src,$mem\t # replicate(float2stack)" %} 10423 opcode(STE_ZOPC, STE_ZOPC); 10424 ins_encode(z_form_rt_mem(src, mem)); 10425 ins_pipe(pipe_class_dummy); 10426%} 10427 10428instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{ 10429 // No match rule, false predicate, for expand only. 10430 effect(DEF dst, USE mem); 10431 predicate(false); 10432 ins_cost(MEMORY_REF_COST); 10433 // TODO: s390 port size(FIXED_SIZE); 10434 format %{ "LLGF $dst,$mem\t # replicate(stack2reg(unsigned))" %} 10435 opcode(LLGF_ZOPC, LLGF_ZOPC); 10436 ins_encode(z_form_rt_mem(dst, mem)); 10437 ins_pipe(pipe_class_dummy); 10438%} 10439 10440// Replicate scalar int to packed int values (8 Bytes) 10441instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{ 10442 // Dummy match rule, false predicate, for expand only. 10443 match(Set dst (ConvI2L src)); 10444 predicate(false); 10445 ins_cost(DEFAULT_COST); 10446 // TODO: s390 port size(FIXED_SIZE); 10447 format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %} 10448 ins_encode %{ 10449 if ($dst$$Register == $src$$Register) { 10450 __ z_sllg(Z_R0_scratch, $src$$Register, 64-32); 10451 __ z_ogr($dst$$Register, Z_R0_scratch); 10452 } else { 10453 __ z_sllg($dst$$Register, $src$$Register, 64-32); 10454 __ z_ogr( $dst$$Register, $src$$Register); 10455 } 10456 %} 10457 ins_pipe(pipe_class_dummy); 10458%} 10459 10460// Replication 10461 10462// Exploit rotate_then_insert, if available 10463// Replicate scalar byte to packed byte values (8 Bytes). 10464instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10465 match(Set dst (ReplicateB src)); 10466 effect(KILL cr); 10467 predicate((n->as_Vector()->length() == 8)); 10468 format %{ "REPLIC8B $dst,$src\t # pack8B" %} 10469 ins_encode %{ 10470 if ($dst$$Register != $src$$Register) { 10471 __ z_lgr($dst$$Register, $src$$Register); 10472 } 10473 __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55, 8, false); 10474 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); 10475 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10476 %} 10477 ins_pipe(pipe_class_dummy); 10478%} 10479 10480// Replicate scalar byte to packed byte values (8 Bytes). 10481instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{ 10482 match(Set dst (ReplicateB src)); 10483 predicate(n->as_Vector()->length() == 8); 10484 ins_should_rematerialize(true); 10485 format %{ "REPLIC8B $dst,$src\t # pack8B imm" %} 10486 ins_encode %{ 10487 int64_t Isrc8 = $src$$constant & 0x000000ff; 10488 int64_t Isrc16 = Isrc8 << 8 | Isrc8; 10489 int64_t Isrc32 = Isrc16 << 16 | Isrc16; 10490 assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules."); 10491 10492 __ z_llilf($dst$$Register, Isrc32); 10493 __ z_iihf($dst$$Register, Isrc32); 10494 %} 10495 ins_pipe(pipe_class_dummy); 10496%} 10497 10498// Replicate scalar byte to packed byte values (8 Bytes). 10499instruct Repl8B_imm0(iRegL dst, immI_0 src) %{ 10500 match(Set dst (ReplicateB src)); 10501 predicate(n->as_Vector()->length() == 8); 10502 ins_should_rematerialize(true); 10503 format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %} 10504 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10505 ins_pipe(pipe_class_dummy); 10506%} 10507 10508// Replicate scalar byte to packed byte values (8 Bytes). 10509instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{ 10510 match(Set dst (ReplicateB src)); 10511 predicate(n->as_Vector()->length() == 8); 10512 ins_should_rematerialize(true); 10513 format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %} 10514 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10515 ins_pipe(pipe_class_dummy); 10516%} 10517 10518// Exploit rotate_then_insert, if available 10519// Replicate scalar short to packed short values (8 Bytes). 10520instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10521 match(Set dst (ReplicateS src)); 10522 effect(KILL cr); 10523 predicate((n->as_Vector()->length() == 4)); 10524 format %{ "REPLIC4S $dst,$src\t # pack4S" %} 10525 ins_encode %{ 10526 if ($dst$$Register != $src$$Register) { 10527 __ z_lgr($dst$$Register, $src$$Register); 10528 } 10529 __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false); 10530 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10531 %} 10532 ins_pipe(pipe_class_dummy); 10533%} 10534 10535// Replicate scalar short to packed short values (8 Bytes). 10536instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{ 10537 match(Set dst (ReplicateS src)); 10538 predicate(n->as_Vector()->length() == 4); 10539 ins_should_rematerialize(true); 10540 format %{ "REPLIC4S $dst,$src\t # pack4S imm" %} 10541 ins_encode %{ 10542 int64_t Isrc16 = $src$$constant & 0x0000ffff; 10543 int64_t Isrc32 = Isrc16 << 16 | Isrc16; 10544 assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT 10545 ") should be handled by other match rules.", $src$$constant); 10546 10547 __ z_llilf($dst$$Register, Isrc32); 10548 __ z_iihf($dst$$Register, Isrc32); 10549 %} 10550 ins_pipe(pipe_class_dummy); 10551%} 10552 10553// Replicate scalar short to packed short values (8 Bytes). 10554instruct Repl4S_imm0(iRegL dst, immI_0 src) %{ 10555 match(Set dst (ReplicateS src)); 10556 predicate(n->as_Vector()->length() == 4); 10557 ins_should_rematerialize(true); 10558 format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %} 10559 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10560 ins_pipe(pipe_class_dummy); 10561%} 10562 10563// Replicate scalar short to packed short values (8 Bytes). 10564instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{ 10565 match(Set dst (ReplicateS src)); 10566 predicate(n->as_Vector()->length() == 4); 10567 ins_should_rematerialize(true); 10568 format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %} 10569 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10570 ins_pipe(pipe_class_dummy); 10571%} 10572 10573// Exploit rotate_then_insert, if available. 10574// Replicate scalar int to packed int values (8 Bytes). 10575instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{ 10576 match(Set dst (ReplicateI src)); 10577 effect(KILL cr); 10578 predicate((n->as_Vector()->length() == 2)); 10579 format %{ "REPLIC2I $dst,$src\t # pack2I" %} 10580 ins_encode %{ 10581 if ($dst$$Register != $src$$Register) { 10582 __ z_lgr($dst$$Register, $src$$Register); 10583 } 10584 __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false); 10585 %} 10586 ins_pipe(pipe_class_dummy); 10587%} 10588 10589// Replicate scalar int to packed int values (8 Bytes). 10590instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{ 10591 match(Set dst (ReplicateI src)); 10592 predicate(n->as_Vector()->length() == 2); 10593 ins_should_rematerialize(true); 10594 format %{ "REPLIC2I $dst,$src\t # pack2I imm" %} 10595 ins_encode %{ 10596 int64_t Isrc32 = $src$$constant; 10597 assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules."); 10598 10599 __ z_llilf($dst$$Register, Isrc32); 10600 __ z_iihf($dst$$Register, Isrc32); 10601 %} 10602 ins_pipe(pipe_class_dummy); 10603%} 10604 10605// Replicate scalar int to packed int values (8 Bytes). 10606instruct Repl2I_imm0(iRegL dst, immI_0 src) %{ 10607 match(Set dst (ReplicateI src)); 10608 predicate(n->as_Vector()->length() == 2); 10609 ins_should_rematerialize(true); 10610 format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %} 10611 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10612 ins_pipe(pipe_class_dummy); 10613%} 10614 10615// Replicate scalar int to packed int values (8 Bytes). 10616instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{ 10617 match(Set dst (ReplicateI src)); 10618 predicate(n->as_Vector()->length() == 2); 10619 ins_should_rematerialize(true); 10620 format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %} 10621 ins_encode %{ __ z_lghi($dst$$Register, -1); %} 10622 ins_pipe(pipe_class_dummy); 10623%} 10624 10625// 10626 10627instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{ 10628 match(Set dst (ReplicateF src)); 10629 effect(KILL cr); 10630 predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); 10631 format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %} 10632 expand %{ 10633 stackSlotF tmp; 10634 iRegL tmp2; 10635 expand_storeF(tmp, src); 10636 expand_LoadLogical_I2L(tmp2, tmp); 10637 expand_Repl2I_reg(dst, tmp2); 10638 %} 10639%} 10640 10641// Replicate scalar float to packed float values in GREG (8 Bytes). 10642instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{ 10643 match(Set dst (ReplicateF src)); 10644 effect(KILL cr); 10645 predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2); 10646 format %{ "REPLIC2F $dst,$src\t # pack2F direct" %} 10647 ins_encode %{ 10648 assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W"); 10649 __ z_lgdr($dst$$Register, $src$$FloatRegister); 10650 10651 __ z_srlg(Z_R0_scratch, $dst$$Register, 32); // Floats are left-justified in 64bit reg. 10652 __ z_iilf($dst$$Register, 0); // Save a "result not ready" stall. 10653 __ z_ogr($dst$$Register, Z_R0_scratch); 10654 %} 10655 ins_pipe(pipe_class_dummy); 10656%} 10657 10658// Replicate scalar float immediate to packed float values in GREG (8 Bytes). 10659instruct Repl2F_imm(iRegL dst, immF src) %{ 10660 match(Set dst (ReplicateF src)); 10661 predicate(n->as_Vector()->length() == 2); 10662 ins_should_rematerialize(true); 10663 format %{ "REPLIC2F $dst,$src\t # pack2F imm" %} 10664 ins_encode %{ 10665 union { 10666 int Isrc32; 10667 float Fsrc32; 10668 }; 10669 Fsrc32 = $src$$constant; 10670 __ z_llilf($dst$$Register, Isrc32); 10671 __ z_iihf($dst$$Register, Isrc32); 10672 %} 10673 ins_pipe(pipe_class_dummy); 10674%} 10675 10676// Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes). 10677// Do this only for 'real' zeroes, especially don't loose sign of negative zeroes. 10678instruct Repl2F_imm0(iRegL dst, immFp0 src) %{ 10679 match(Set dst (ReplicateF src)); 10680 predicate(n->as_Vector()->length() == 2); 10681 ins_should_rematerialize(true); 10682 format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %} 10683 ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %} 10684 ins_pipe(pipe_class_dummy); 10685%} 10686 10687// Load/Store vector 10688 10689// Store Aligned Packed Byte register to memory (8 Bytes). 10690instruct storeA8B(memory mem, iRegL src) %{ 10691 match(Set mem (StoreVector mem src)); 10692 predicate(n->as_StoreVector()->memory_size() == 8); 10693 ins_cost(MEMORY_REF_COST); 10694 // TODO: s390 port size(VARIABLE_SIZE); 10695 format %{ "STG $src,$mem\t # ST(packed8B)" %} 10696 opcode(STG_ZOPC, STG_ZOPC); 10697 ins_encode(z_form_rt_mem_opt(src, mem)); 10698 ins_pipe(pipe_class_dummy); 10699%} 10700 10701instruct loadV8(iRegL dst, memory mem) %{ 10702 match(Set dst (LoadVector mem)); 10703 predicate(n->as_LoadVector()->memory_size() == 8); 10704 ins_cost(MEMORY_REF_COST); 10705 // TODO: s390 port size(VARIABLE_SIZE); 10706 format %{ "LG $dst,$mem\t # L(packed8B)" %} 10707 opcode(LG_ZOPC, LG_ZOPC); 10708 ins_encode(z_form_rt_mem_opt(dst, mem)); 10709 ins_pipe(pipe_class_dummy); 10710%} 10711 10712// Reinterpret: only one vector size used 10713instruct reinterpret(iRegL dst) %{ 10714 match(Set dst (VectorReinterpret dst)); 10715 ins_cost(0); 10716 format %{ "reinterpret $dst" %} 10717 ins_encode( /*empty*/ ); 10718 ins_pipe(pipe_class_dummy); 10719%} 10720 10721//----------POPULATION COUNT RULES-------------------------------------------- 10722 10723// Byte reverse 10724 10725instruct bytes_reverse_int(iRegI dst, iRegI src) %{ 10726 match(Set dst (ReverseBytesI src)); 10727 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported 10728 ins_cost(DEFAULT_COST); 10729 size(4); 10730 format %{ "LRVR $dst,$src\t # byte reverse int" %} 10731 opcode(LRVR_ZOPC); 10732 ins_encode(z_rreform(dst, src)); 10733 ins_pipe(pipe_class_dummy); 10734%} 10735 10736instruct bytes_reverse_long(iRegL dst, iRegL src) %{ 10737 match(Set dst (ReverseBytesL src)); 10738 predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported 10739 ins_cost(DEFAULT_COST); 10740 // TODO: s390 port size(FIXED_SIZE); 10741 format %{ "LRVGR $dst,$src\t # byte reverse long" %} 10742 opcode(LRVGR_ZOPC); 10743 ins_encode(z_rreform(dst, src)); 10744 ins_pipe(pipe_class_dummy); 10745%} 10746 10747// Leading zeroes 10748 10749// The instruction FLOGR (Find Leftmost One in Grande (64bit) Register) 10750// returns the bit position of the leftmost 1 in the 64bit source register. 10751// As the bits are numbered from left to right (0..63), the returned 10752// position index is equivalent to the number of leading zeroes. 10753// If no 1-bit is found (i.e. the regsiter contains zero), the instruction 10754// returns position 64. That's exactly what we need. 10755 10756instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ 10757 match(Set dst (CountLeadingZerosI src)); 10758 effect(KILL tmp, KILL cr); 10759 ins_cost(3 * DEFAULT_COST); 10760 size(14); 10761 format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t" 10762 "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t" 10763 "FLOGR $dst,$dst" 10764 %} 10765 ins_encode %{ 10766 // Performance experiments indicate that "FLOGR" is using some kind of 10767 // iteration to find the leftmost "1" bit. 10768 // 10769 // The prior implementation zero-extended the 32-bit argument to 64 bit, 10770 // thus forcing "FLOGR" to count 32 bits of which we know they are zero. 10771 // We could gain measurable speedup in micro benchmark: 10772 // 10773 // leading trailing 10774 // z10: int 2.04 1.68 10775 // long 1.00 1.02 10776 // z196: int 0.99 1.23 10777 // long 1.00 1.11 10778 // 10779 // By shifting the argument into the high-word instead of zero-extending it. 10780 // The add'l branch on condition (taken for a zero argument, very infrequent, 10781 // good prediction) is well compensated for by the savings. 10782 // 10783 // We leave the previous implementation in for some time in the future when 10784 // the "FLOGR" instruction may become less iterative. 10785 10786 // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original 10787 __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first. 10788 __ z_iilh($dst$$Register, 0x8000); // Insert "stop bit" to force result 32 for zero src. 10789 __ z_flogr($dst$$Register, $dst$$Register); 10790 %} 10791 ins_pipe(pipe_class_dummy); 10792%} 10793 10794instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{ 10795 match(Set dst (CountLeadingZerosL src)); 10796 effect(KILL tmp, KILL cr); 10797 ins_cost(DEFAULT_COST); 10798 size(4); 10799 format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %} 10800 ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %} 10801 ins_pipe(pipe_class_dummy); 10802%} 10803 10804// trailing zeroes 10805 10806// We transform the trailing zeroes problem to a leading zeroes problem 10807// such that can use the FLOGR instruction to our advantage. 10808 10809// With 10810// tmp1 = src - 1 10811// we flip all trailing zeroes to ones and the rightmost one to zero. 10812// All other bits remain unchanged. 10813// With the complement 10814// tmp2 = ~src 10815// we get all ones in the trailing zeroes positions. Thus, 10816// tmp3 = tmp1 & tmp2 10817// yields ones in the trailing zeroes positions and zeroes elsewhere. 10818// Now we can apply FLOGR and get 64-(trailing zeroes). 10819instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ 10820 match(Set dst (CountTrailingZerosI src)); 10821 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10822 ins_cost(8 * DEFAULT_COST); 10823 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. 10824 format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t" 10825 "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t" 10826 "AGHI $dst,-1 \t # tmp1 = src-1\n\t" 10827 "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t" 10828 "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t" 10829 "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t" 10830 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t" 10831 "LCR $dst,$dst \t # res = -tmp4" 10832 %} 10833 ins_encode %{ 10834 Register Rdst = $dst$$Register; 10835 Register Rsrc = $src$$Register; 10836 // Rtmp only needed for for zero-argument shortcut. With kill effect in 10837 // match rule Rsrc = roddReg would be possible, saving one register. 10838 Register Rtmp = $tmp$$Register; 10839 10840 assert_different_registers(Rdst, Rsrc, Rtmp); 10841 10842 // Algorithm: 10843 // - Isolate the least significant (rightmost) set bit using (src & (-src)). 10844 // All other bits in the result are zero. 10845 // - Find the "leftmost one" bit position in the single-bit result from previous step. 10846 // - 63-("leftmost one" bit position) gives the # of trailing zeros. 10847 10848 // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original. 10849 Label done; 10850 __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32. 10851 __ z_lcgfr(Rtmp, Rsrc); 10852 __ z_bre(done); // Taken very infrequently, good prediction, no BHT entry. 10853 10854 __ z_nr(Rtmp, Rsrc); // (src) & (-src) leaves nothing but least significant bit. 10855 __ z_ahi(Rtmp, -1); // Subtract one to fill all trailing zero positions with ones. 10856 // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000) 10857 // into upper half of reg. Not relevant with sllg below. 10858 __ z_sllg(Rdst, Rtmp, 32); // Shift interesting contents to upper half of register. 10859 __ z_bre(done); // Shortcut for argument = 1, result will be 0. 10860 // Depends on CC set by ahi above. 10861 // Taken very infrequently, good prediction, no BHT entry. 10862 // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit) 10863 // after SLLG Rdst == 0(64bit)). 10864 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. 10865 __ add2reg(Rdst, -32); // 32-pos(leftmost1) is #trailing zeros 10866 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. 10867 __ bind(done); 10868 %} 10869 ins_pipe(pipe_class_dummy); 10870%} 10871 10872instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{ 10873 match(Set dst (CountTrailingZerosL src)); 10874 effect(TEMP_DEF dst, KILL tmp, KILL cr); 10875 ins_cost(8 * DEFAULT_COST); 10876 // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. 10877 format %{ "LCGR $dst,$src \t # preserve src\n\t" 10878 "NGR $dst,$src \t #\n\t" 10879 "AGHI $dst,-1 \t # tmp1 = src-1\n\t" 10880 "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t" 10881 "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t" 10882 "LCR $dst,$dst \t #" 10883 %} 10884 ins_encode %{ 10885 Register Rdst = $dst$$Register; 10886 Register Rsrc = $src$$Register; 10887 assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed. 10888 10889 // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original. 10890 __ z_lcgr(Rdst, Rsrc); 10891 __ z_ngr(Rdst, Rsrc); 10892 __ add2reg(Rdst, -1); 10893 __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst. 10894 __ add2reg(Rdst, -64); 10895 __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost. 10896 %} 10897 ins_pipe(pipe_class_dummy); 10898%} 10899 10900 10901// bit count 10902 10903instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10904 match(Set dst (PopCountI src)); 10905 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10906 predicate(UsePopCountInstruction && VM_Version::has_PopCount()); 10907 ins_cost(DEFAULT_COST); 10908 size(24); 10909 format %{ "POPCNT $dst,$src\t # pop count int" %} 10910 ins_encode %{ 10911 Register Rdst = $dst$$Register; 10912 Register Rsrc = $src$$Register; 10913 Register Rtmp = $tmp$$Register; 10914 10915 // Prefer compile-time assertion over run-time SIGILL. 10916 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); 10917 assert_different_registers(Rdst, Rtmp); 10918 10919 // Version 2: shows 10%(z196) improvement over original. 10920 __ z_popcnt(Rdst, Rsrc); 10921 __ z_srlg(Rtmp, Rdst, 16); // calc byte4+byte6 and byte5+byte7 10922 __ z_alr(Rdst, Rtmp); // into byte6 and byte7 10923 __ z_srlg(Rtmp, Rdst, 8); // calc (byte4+byte6) + (byte5+byte7) 10924 __ z_alr(Rdst, Rtmp); // into byte7 10925 __ z_llgcr(Rdst, Rdst); // zero-extend sum 10926 %} 10927 ins_pipe(pipe_class_dummy); 10928%} 10929 10930instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10931 match(Set dst (PopCountL src)); 10932 effect(TEMP_DEF dst, TEMP tmp, KILL cr); 10933 predicate(UsePopCountInstruction && VM_Version::has_PopCount()); 10934 ins_cost(DEFAULT_COST); 10935 // TODO: s390 port size(FIXED_SIZE); 10936 format %{ "POPCNT $dst,$src\t # pop count long" %} 10937 ins_encode %{ 10938 Register Rdst = $dst$$Register; 10939 Register Rsrc = $src$$Register; 10940 Register Rtmp = $tmp$$Register; 10941 10942 // Prefer compile-time assertion over run-time SIGILL. 10943 assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI"); 10944 assert_different_registers(Rdst, Rtmp); 10945 10946 // Original version. Using LA instead of algr seems to be a really bad idea (-35%). 10947 __ z_popcnt(Rdst, Rsrc); 10948 __ z_ahhlr(Rdst, Rdst, Rdst); 10949 __ z_sllg(Rtmp, Rdst, 16); 10950 __ z_algr(Rdst, Rtmp); 10951 __ z_sllg(Rtmp, Rdst, 8); 10952 __ z_algr(Rdst, Rtmp); 10953 __ z_srlg(Rdst, Rdst, 56); 10954 %} 10955 ins_pipe(pipe_class_dummy); 10956%} 10957 10958//----------SMARTSPILL RULES--------------------------------------------------- 10959// These must follow all instruction definitions as they use the names 10960// defined in the instructions definitions. 10961 10962// ============================================================================ 10963// TYPE PROFILING RULES 10964